1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016 AmLogic, Inc. 4 * Michael Turquette <mturquette@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/init.h> 10 #include <linux/of_address.h> 11 #include <linux/of_device.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 16 #include "clkc.h" 17 #include "gxbb.h" 18 #include "clk-regmap.h" 19 20 static DEFINE_SPINLOCK(meson_clk_lock); 21 22 static const struct pll_rate_table gxbb_gp0_pll_rate_table[] = { 23 PLL_RATE(96000000, 32, 1, 3), 24 PLL_RATE(99000000, 33, 1, 3), 25 PLL_RATE(102000000, 34, 1, 3), 26 PLL_RATE(105000000, 35, 1, 3), 27 PLL_RATE(108000000, 36, 1, 3), 28 PLL_RATE(111000000, 37, 1, 3), 29 PLL_RATE(114000000, 38, 1, 3), 30 PLL_RATE(117000000, 39, 1, 3), 31 PLL_RATE(120000000, 40, 1, 3), 32 PLL_RATE(123000000, 41, 1, 3), 33 PLL_RATE(126000000, 42, 1, 3), 34 PLL_RATE(129000000, 43, 1, 3), 35 PLL_RATE(132000000, 44, 1, 3), 36 PLL_RATE(135000000, 45, 1, 3), 37 PLL_RATE(138000000, 46, 1, 3), 38 PLL_RATE(141000000, 47, 1, 3), 39 PLL_RATE(144000000, 48, 1, 3), 40 PLL_RATE(147000000, 49, 1, 3), 41 PLL_RATE(150000000, 50, 1, 3), 42 PLL_RATE(153000000, 51, 1, 3), 43 PLL_RATE(156000000, 52, 1, 3), 44 PLL_RATE(159000000, 53, 1, 3), 45 PLL_RATE(162000000, 54, 1, 3), 46 PLL_RATE(165000000, 55, 1, 3), 47 PLL_RATE(168000000, 56, 1, 3), 48 PLL_RATE(171000000, 57, 1, 3), 49 PLL_RATE(174000000, 58, 1, 3), 50 PLL_RATE(177000000, 59, 1, 3), 51 PLL_RATE(180000000, 60, 1, 3), 52 PLL_RATE(183000000, 61, 1, 3), 53 PLL_RATE(186000000, 62, 1, 3), 54 PLL_RATE(192000000, 32, 1, 2), 55 PLL_RATE(198000000, 33, 1, 2), 56 PLL_RATE(204000000, 34, 1, 2), 57 PLL_RATE(210000000, 35, 1, 2), 58 PLL_RATE(216000000, 36, 1, 2), 59 PLL_RATE(222000000, 37, 1, 2), 60 PLL_RATE(228000000, 38, 1, 2), 61 PLL_RATE(234000000, 39, 1, 2), 62 PLL_RATE(240000000, 40, 1, 2), 63 PLL_RATE(246000000, 41, 1, 2), 64 PLL_RATE(252000000, 42, 1, 2), 65 PLL_RATE(258000000, 43, 1, 2), 66 PLL_RATE(264000000, 44, 1, 2), 67 PLL_RATE(270000000, 45, 1, 2), 68 PLL_RATE(276000000, 46, 1, 2), 69 PLL_RATE(282000000, 47, 1, 2), 70 PLL_RATE(288000000, 48, 1, 2), 71 PLL_RATE(294000000, 49, 1, 2), 72 PLL_RATE(300000000, 50, 1, 2), 73 PLL_RATE(306000000, 51, 1, 2), 74 PLL_RATE(312000000, 52, 1, 2), 75 PLL_RATE(318000000, 53, 1, 2), 76 PLL_RATE(324000000, 54, 1, 2), 77 PLL_RATE(330000000, 55, 1, 2), 78 PLL_RATE(336000000, 56, 1, 2), 79 PLL_RATE(342000000, 57, 1, 2), 80 PLL_RATE(348000000, 58, 1, 2), 81 PLL_RATE(354000000, 59, 1, 2), 82 PLL_RATE(360000000, 60, 1, 2), 83 PLL_RATE(366000000, 61, 1, 2), 84 PLL_RATE(372000000, 62, 1, 2), 85 PLL_RATE(384000000, 32, 1, 1), 86 PLL_RATE(396000000, 33, 1, 1), 87 PLL_RATE(408000000, 34, 1, 1), 88 PLL_RATE(420000000, 35, 1, 1), 89 PLL_RATE(432000000, 36, 1, 1), 90 PLL_RATE(444000000, 37, 1, 1), 91 PLL_RATE(456000000, 38, 1, 1), 92 PLL_RATE(468000000, 39, 1, 1), 93 PLL_RATE(480000000, 40, 1, 1), 94 PLL_RATE(492000000, 41, 1, 1), 95 PLL_RATE(504000000, 42, 1, 1), 96 PLL_RATE(516000000, 43, 1, 1), 97 PLL_RATE(528000000, 44, 1, 1), 98 PLL_RATE(540000000, 45, 1, 1), 99 PLL_RATE(552000000, 46, 1, 1), 100 PLL_RATE(564000000, 47, 1, 1), 101 PLL_RATE(576000000, 48, 1, 1), 102 PLL_RATE(588000000, 49, 1, 1), 103 PLL_RATE(600000000, 50, 1, 1), 104 PLL_RATE(612000000, 51, 1, 1), 105 PLL_RATE(624000000, 52, 1, 1), 106 PLL_RATE(636000000, 53, 1, 1), 107 PLL_RATE(648000000, 54, 1, 1), 108 PLL_RATE(660000000, 55, 1, 1), 109 PLL_RATE(672000000, 56, 1, 1), 110 PLL_RATE(684000000, 57, 1, 1), 111 PLL_RATE(696000000, 58, 1, 1), 112 PLL_RATE(708000000, 59, 1, 1), 113 PLL_RATE(720000000, 60, 1, 1), 114 PLL_RATE(732000000, 61, 1, 1), 115 PLL_RATE(744000000, 62, 1, 1), 116 PLL_RATE(768000000, 32, 1, 0), 117 PLL_RATE(792000000, 33, 1, 0), 118 PLL_RATE(816000000, 34, 1, 0), 119 PLL_RATE(840000000, 35, 1, 0), 120 PLL_RATE(864000000, 36, 1, 0), 121 PLL_RATE(888000000, 37, 1, 0), 122 PLL_RATE(912000000, 38, 1, 0), 123 PLL_RATE(936000000, 39, 1, 0), 124 PLL_RATE(960000000, 40, 1, 0), 125 PLL_RATE(984000000, 41, 1, 0), 126 PLL_RATE(1008000000, 42, 1, 0), 127 PLL_RATE(1032000000, 43, 1, 0), 128 PLL_RATE(1056000000, 44, 1, 0), 129 PLL_RATE(1080000000, 45, 1, 0), 130 PLL_RATE(1104000000, 46, 1, 0), 131 PLL_RATE(1128000000, 47, 1, 0), 132 PLL_RATE(1152000000, 48, 1, 0), 133 PLL_RATE(1176000000, 49, 1, 0), 134 PLL_RATE(1200000000, 50, 1, 0), 135 PLL_RATE(1224000000, 51, 1, 0), 136 PLL_RATE(1248000000, 52, 1, 0), 137 PLL_RATE(1272000000, 53, 1, 0), 138 PLL_RATE(1296000000, 54, 1, 0), 139 PLL_RATE(1320000000, 55, 1, 0), 140 PLL_RATE(1344000000, 56, 1, 0), 141 PLL_RATE(1368000000, 57, 1, 0), 142 PLL_RATE(1392000000, 58, 1, 0), 143 PLL_RATE(1416000000, 59, 1, 0), 144 PLL_RATE(1440000000, 60, 1, 0), 145 PLL_RATE(1464000000, 61, 1, 0), 146 PLL_RATE(1488000000, 62, 1, 0), 147 { /* sentinel */ }, 148 }; 149 150 static const struct pll_rate_table gxl_gp0_pll_rate_table[] = { 151 PLL_RATE(504000000, 42, 1, 1), 152 PLL_RATE(516000000, 43, 1, 1), 153 PLL_RATE(528000000, 44, 1, 1), 154 PLL_RATE(540000000, 45, 1, 1), 155 PLL_RATE(552000000, 46, 1, 1), 156 PLL_RATE(564000000, 47, 1, 1), 157 PLL_RATE(576000000, 48, 1, 1), 158 PLL_RATE(588000000, 49, 1, 1), 159 PLL_RATE(600000000, 50, 1, 1), 160 PLL_RATE(612000000, 51, 1, 1), 161 PLL_RATE(624000000, 52, 1, 1), 162 PLL_RATE(636000000, 53, 1, 1), 163 PLL_RATE(648000000, 54, 1, 1), 164 PLL_RATE(660000000, 55, 1, 1), 165 PLL_RATE(672000000, 56, 1, 1), 166 PLL_RATE(684000000, 57, 1, 1), 167 PLL_RATE(696000000, 58, 1, 1), 168 PLL_RATE(708000000, 59, 1, 1), 169 PLL_RATE(720000000, 60, 1, 1), 170 PLL_RATE(732000000, 61, 1, 1), 171 PLL_RATE(744000000, 62, 1, 1), 172 PLL_RATE(756000000, 63, 1, 1), 173 PLL_RATE(768000000, 64, 1, 1), 174 PLL_RATE(780000000, 65, 1, 1), 175 PLL_RATE(792000000, 66, 1, 1), 176 { /* sentinel */ }, 177 }; 178 179 static struct clk_regmap gxbb_fixed_pll = { 180 .data = &(struct meson_clk_pll_data){ 181 .m = { 182 .reg_off = HHI_MPLL_CNTL, 183 .shift = 0, 184 .width = 9, 185 }, 186 .n = { 187 .reg_off = HHI_MPLL_CNTL, 188 .shift = 9, 189 .width = 5, 190 }, 191 .od = { 192 .reg_off = HHI_MPLL_CNTL, 193 .shift = 16, 194 .width = 2, 195 }, 196 .frac = { 197 .reg_off = HHI_MPLL_CNTL2, 198 .shift = 0, 199 .width = 12, 200 }, 201 .l = { 202 .reg_off = HHI_MPLL_CNTL, 203 .shift = 31, 204 .width = 1, 205 }, 206 .rst = { 207 .reg_off = HHI_MPLL_CNTL, 208 .shift = 29, 209 .width = 1, 210 }, 211 }, 212 .hw.init = &(struct clk_init_data){ 213 .name = "fixed_pll", 214 .ops = &meson_clk_pll_ro_ops, 215 .parent_names = (const char *[]){ "xtal" }, 216 .num_parents = 1, 217 .flags = CLK_GET_RATE_NOCACHE, 218 }, 219 }; 220 221 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = { 222 .mult = 2, 223 .div = 1, 224 .hw.init = &(struct clk_init_data){ 225 .name = "hdmi_pll_pre_mult", 226 .ops = &clk_fixed_factor_ops, 227 .parent_names = (const char *[]){ "xtal" }, 228 .num_parents = 1, 229 }, 230 }; 231 232 static struct clk_regmap gxbb_hdmi_pll = { 233 .data = &(struct meson_clk_pll_data){ 234 .m = { 235 .reg_off = HHI_HDMI_PLL_CNTL, 236 .shift = 0, 237 .width = 9, 238 }, 239 .n = { 240 .reg_off = HHI_HDMI_PLL_CNTL, 241 .shift = 9, 242 .width = 5, 243 }, 244 .frac = { 245 .reg_off = HHI_HDMI_PLL_CNTL2, 246 .shift = 0, 247 .width = 12, 248 }, 249 .od = { 250 .reg_off = HHI_HDMI_PLL_CNTL2, 251 .shift = 16, 252 .width = 2, 253 }, 254 .od2 = { 255 .reg_off = HHI_HDMI_PLL_CNTL2, 256 .shift = 22, 257 .width = 2, 258 }, 259 .od3 = { 260 .reg_off = HHI_HDMI_PLL_CNTL2, 261 .shift = 18, 262 .width = 2, 263 }, 264 .l = { 265 .reg_off = HHI_HDMI_PLL_CNTL, 266 .shift = 31, 267 .width = 1, 268 }, 269 .rst = { 270 .reg_off = HHI_HDMI_PLL_CNTL, 271 .shift = 28, 272 .width = 1, 273 }, 274 }, 275 .hw.init = &(struct clk_init_data){ 276 .name = "hdmi_pll", 277 .ops = &meson_clk_pll_ro_ops, 278 .parent_names = (const char *[]){ "hdmi_pll_pre_mult" }, 279 .num_parents = 1, 280 .flags = CLK_GET_RATE_NOCACHE, 281 }, 282 }; 283 284 static struct clk_regmap gxl_hdmi_pll = { 285 .data = &(struct meson_clk_pll_data){ 286 .m = { 287 .reg_off = HHI_HDMI_PLL_CNTL, 288 .shift = 0, 289 .width = 9, 290 }, 291 .n = { 292 .reg_off = HHI_HDMI_PLL_CNTL, 293 .shift = 9, 294 .width = 5, 295 }, 296 .frac = { 297 /* 298 * On gxl, there is a register shift due to 299 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb, 300 * so we compute the register offset based on the PLL 301 * base to get it right 302 */ 303 .reg_off = HHI_HDMI_PLL_CNTL + 4, 304 .shift = 0, 305 .width = 12, 306 }, 307 .od = { 308 .reg_off = HHI_HDMI_PLL_CNTL + 8, 309 .shift = 21, 310 .width = 2, 311 }, 312 .od2 = { 313 .reg_off = HHI_HDMI_PLL_CNTL + 8, 314 .shift = 23, 315 .width = 2, 316 }, 317 .od3 = { 318 .reg_off = HHI_HDMI_PLL_CNTL + 8, 319 .shift = 19, 320 .width = 2, 321 }, 322 .l = { 323 .reg_off = HHI_HDMI_PLL_CNTL, 324 .shift = 31, 325 .width = 1, 326 }, 327 .rst = { 328 .reg_off = HHI_HDMI_PLL_CNTL, 329 .shift = 29, 330 .width = 1, 331 }, 332 }, 333 .hw.init = &(struct clk_init_data){ 334 .name = "hdmi_pll", 335 .ops = &meson_clk_pll_ro_ops, 336 .parent_names = (const char *[]){ "xtal" }, 337 .num_parents = 1, 338 .flags = CLK_GET_RATE_NOCACHE, 339 }, 340 }; 341 342 static struct clk_regmap gxbb_sys_pll = { 343 .data = &(struct meson_clk_pll_data){ 344 .m = { 345 .reg_off = HHI_SYS_PLL_CNTL, 346 .shift = 0, 347 .width = 9, 348 }, 349 .n = { 350 .reg_off = HHI_SYS_PLL_CNTL, 351 .shift = 9, 352 .width = 5, 353 }, 354 .od = { 355 .reg_off = HHI_SYS_PLL_CNTL, 356 .shift = 10, 357 .width = 2, 358 }, 359 .l = { 360 .reg_off = HHI_SYS_PLL_CNTL, 361 .shift = 31, 362 .width = 1, 363 }, 364 .rst = { 365 .reg_off = HHI_SYS_PLL_CNTL, 366 .shift = 29, 367 .width = 1, 368 }, 369 }, 370 .hw.init = &(struct clk_init_data){ 371 .name = "sys_pll", 372 .ops = &meson_clk_pll_ro_ops, 373 .parent_names = (const char *[]){ "xtal" }, 374 .num_parents = 1, 375 .flags = CLK_GET_RATE_NOCACHE, 376 }, 377 }; 378 379 static const struct reg_sequence gxbb_gp0_init_regs[] = { 380 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 }, 381 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 }, 382 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d }, 383 { .reg = HHI_GP0_PLL_CNTL, .def = 0x4a000228 }, 384 }; 385 386 static struct clk_regmap gxbb_gp0_pll = { 387 .data = &(struct meson_clk_pll_data){ 388 .m = { 389 .reg_off = HHI_GP0_PLL_CNTL, 390 .shift = 0, 391 .width = 9, 392 }, 393 .n = { 394 .reg_off = HHI_GP0_PLL_CNTL, 395 .shift = 9, 396 .width = 5, 397 }, 398 .od = { 399 .reg_off = HHI_GP0_PLL_CNTL, 400 .shift = 16, 401 .width = 2, 402 }, 403 .l = { 404 .reg_off = HHI_GP0_PLL_CNTL, 405 .shift = 31, 406 .width = 1, 407 }, 408 .rst = { 409 .reg_off = HHI_GP0_PLL_CNTL, 410 .shift = 29, 411 .width = 1, 412 }, 413 .table = gxbb_gp0_pll_rate_table, 414 .init_regs = gxbb_gp0_init_regs, 415 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs), 416 }, 417 .hw.init = &(struct clk_init_data){ 418 .name = "gp0_pll", 419 .ops = &meson_clk_pll_ops, 420 .parent_names = (const char *[]){ "xtal" }, 421 .num_parents = 1, 422 .flags = CLK_GET_RATE_NOCACHE, 423 }, 424 }; 425 426 static const struct reg_sequence gxl_gp0_init_regs[] = { 427 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, 428 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, 429 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 430 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 431 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 432 { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 }, 433 }; 434 435 static struct clk_regmap gxl_gp0_pll = { 436 .data = &(struct meson_clk_pll_data){ 437 .m = { 438 .reg_off = HHI_GP0_PLL_CNTL, 439 .shift = 0, 440 .width = 9, 441 }, 442 .n = { 443 .reg_off = HHI_GP0_PLL_CNTL, 444 .shift = 9, 445 .width = 5, 446 }, 447 .od = { 448 .reg_off = HHI_GP0_PLL_CNTL, 449 .shift = 16, 450 .width = 2, 451 }, 452 .frac = { 453 .reg_off = HHI_GP0_PLL_CNTL1, 454 .shift = 0, 455 .width = 10, 456 }, 457 .l = { 458 .reg_off = HHI_GP0_PLL_CNTL, 459 .shift = 31, 460 .width = 1, 461 }, 462 .rst = { 463 .reg_off = HHI_GP0_PLL_CNTL, 464 .shift = 29, 465 .width = 1, 466 }, 467 .table = gxl_gp0_pll_rate_table, 468 .init_regs = gxl_gp0_init_regs, 469 .init_count = ARRAY_SIZE(gxl_gp0_init_regs), 470 }, 471 .hw.init = &(struct clk_init_data){ 472 .name = "gp0_pll", 473 .ops = &meson_clk_pll_ops, 474 .parent_names = (const char *[]){ "xtal" }, 475 .num_parents = 1, 476 .flags = CLK_GET_RATE_NOCACHE, 477 }, 478 }; 479 480 static struct clk_fixed_factor gxbb_fclk_div2_div = { 481 .mult = 1, 482 .div = 2, 483 .hw.init = &(struct clk_init_data){ 484 .name = "fclk_div2_div", 485 .ops = &clk_fixed_factor_ops, 486 .parent_names = (const char *[]){ "fixed_pll" }, 487 .num_parents = 1, 488 }, 489 }; 490 491 static struct clk_regmap gxbb_fclk_div2 = { 492 .data = &(struct clk_regmap_gate_data){ 493 .offset = HHI_MPLL_CNTL6, 494 .bit_idx = 27, 495 }, 496 .hw.init = &(struct clk_init_data){ 497 .name = "fclk_div2", 498 .ops = &clk_regmap_gate_ops, 499 .parent_names = (const char *[]){ "fclk_div2_div" }, 500 .num_parents = 1, 501 .flags = CLK_IS_CRITICAL, 502 }, 503 }; 504 505 static struct clk_fixed_factor gxbb_fclk_div3_div = { 506 .mult = 1, 507 .div = 3, 508 .hw.init = &(struct clk_init_data){ 509 .name = "fclk_div3_div", 510 .ops = &clk_fixed_factor_ops, 511 .parent_names = (const char *[]){ "fixed_pll" }, 512 .num_parents = 1, 513 }, 514 }; 515 516 static struct clk_regmap gxbb_fclk_div3 = { 517 .data = &(struct clk_regmap_gate_data){ 518 .offset = HHI_MPLL_CNTL6, 519 .bit_idx = 28, 520 }, 521 .hw.init = &(struct clk_init_data){ 522 .name = "fclk_div3", 523 .ops = &clk_regmap_gate_ops, 524 .parent_names = (const char *[]){ "fclk_div3_div" }, 525 .num_parents = 1, 526 }, 527 }; 528 529 static struct clk_fixed_factor gxbb_fclk_div4_div = { 530 .mult = 1, 531 .div = 4, 532 .hw.init = &(struct clk_init_data){ 533 .name = "fclk_div4_div", 534 .ops = &clk_fixed_factor_ops, 535 .parent_names = (const char *[]){ "fixed_pll" }, 536 .num_parents = 1, 537 }, 538 }; 539 540 static struct clk_regmap gxbb_fclk_div4 = { 541 .data = &(struct clk_regmap_gate_data){ 542 .offset = HHI_MPLL_CNTL6, 543 .bit_idx = 29, 544 }, 545 .hw.init = &(struct clk_init_data){ 546 .name = "fclk_div4", 547 .ops = &clk_regmap_gate_ops, 548 .parent_names = (const char *[]){ "fclk_div4_div" }, 549 .num_parents = 1, 550 }, 551 }; 552 553 static struct clk_fixed_factor gxbb_fclk_div5_div = { 554 .mult = 1, 555 .div = 5, 556 .hw.init = &(struct clk_init_data){ 557 .name = "fclk_div5_div", 558 .ops = &clk_fixed_factor_ops, 559 .parent_names = (const char *[]){ "fixed_pll" }, 560 .num_parents = 1, 561 }, 562 }; 563 564 static struct clk_regmap gxbb_fclk_div5 = { 565 .data = &(struct clk_regmap_gate_data){ 566 .offset = HHI_MPLL_CNTL6, 567 .bit_idx = 30, 568 }, 569 .hw.init = &(struct clk_init_data){ 570 .name = "fclk_div5", 571 .ops = &clk_regmap_gate_ops, 572 .parent_names = (const char *[]){ "fclk_div5_div" }, 573 .num_parents = 1, 574 }, 575 }; 576 577 static struct clk_fixed_factor gxbb_fclk_div7_div = { 578 .mult = 1, 579 .div = 7, 580 .hw.init = &(struct clk_init_data){ 581 .name = "fclk_div7_div", 582 .ops = &clk_fixed_factor_ops, 583 .parent_names = (const char *[]){ "fixed_pll" }, 584 .num_parents = 1, 585 }, 586 }; 587 588 static struct clk_regmap gxbb_fclk_div7 = { 589 .data = &(struct clk_regmap_gate_data){ 590 .offset = HHI_MPLL_CNTL6, 591 .bit_idx = 31, 592 }, 593 .hw.init = &(struct clk_init_data){ 594 .name = "fclk_div7", 595 .ops = &clk_regmap_gate_ops, 596 .parent_names = (const char *[]){ "fclk_div7_div" }, 597 .num_parents = 1, 598 }, 599 }; 600 601 static struct clk_regmap gxbb_mpll_prediv = { 602 .data = &(struct clk_regmap_div_data){ 603 .offset = HHI_MPLL_CNTL5, 604 .shift = 12, 605 .width = 1, 606 }, 607 .hw.init = &(struct clk_init_data){ 608 .name = "mpll_prediv", 609 .ops = &clk_regmap_divider_ro_ops, 610 .parent_names = (const char *[]){ "fixed_pll" }, 611 .num_parents = 1, 612 }, 613 }; 614 615 static struct clk_regmap gxbb_mpll0_div = { 616 .data = &(struct meson_clk_mpll_data){ 617 .sdm = { 618 .reg_off = HHI_MPLL_CNTL7, 619 .shift = 0, 620 .width = 14, 621 }, 622 .sdm_en = { 623 .reg_off = HHI_MPLL_CNTL7, 624 .shift = 15, 625 .width = 1, 626 }, 627 .n2 = { 628 .reg_off = HHI_MPLL_CNTL7, 629 .shift = 16, 630 .width = 9, 631 }, 632 .ssen = { 633 .reg_off = HHI_MPLL_CNTL, 634 .shift = 25, 635 .width = 1, 636 }, 637 .lock = &meson_clk_lock, 638 }, 639 .hw.init = &(struct clk_init_data){ 640 .name = "mpll0_div", 641 .ops = &meson_clk_mpll_ops, 642 .parent_names = (const char *[]){ "mpll_prediv" }, 643 .num_parents = 1, 644 }, 645 }; 646 647 static struct clk_regmap gxbb_mpll0 = { 648 .data = &(struct clk_regmap_gate_data){ 649 .offset = HHI_MPLL_CNTL7, 650 .bit_idx = 14, 651 }, 652 .hw.init = &(struct clk_init_data){ 653 .name = "mpll0", 654 .ops = &clk_regmap_gate_ops, 655 .parent_names = (const char *[]){ "mpll0_div" }, 656 .num_parents = 1, 657 .flags = CLK_SET_RATE_PARENT, 658 }, 659 }; 660 661 static struct clk_regmap gxbb_mpll1_div = { 662 .data = &(struct meson_clk_mpll_data){ 663 .sdm = { 664 .reg_off = HHI_MPLL_CNTL8, 665 .shift = 0, 666 .width = 14, 667 }, 668 .sdm_en = { 669 .reg_off = HHI_MPLL_CNTL8, 670 .shift = 15, 671 .width = 1, 672 }, 673 .n2 = { 674 .reg_off = HHI_MPLL_CNTL8, 675 .shift = 16, 676 .width = 9, 677 }, 678 .lock = &meson_clk_lock, 679 }, 680 .hw.init = &(struct clk_init_data){ 681 .name = "mpll1_div", 682 .ops = &meson_clk_mpll_ops, 683 .parent_names = (const char *[]){ "mpll_prediv" }, 684 .num_parents = 1, 685 }, 686 }; 687 688 static struct clk_regmap gxbb_mpll1 = { 689 .data = &(struct clk_regmap_gate_data){ 690 .offset = HHI_MPLL_CNTL8, 691 .bit_idx = 14, 692 }, 693 .hw.init = &(struct clk_init_data){ 694 .name = "mpll1", 695 .ops = &clk_regmap_gate_ops, 696 .parent_names = (const char *[]){ "mpll1_div" }, 697 .num_parents = 1, 698 .flags = CLK_SET_RATE_PARENT, 699 }, 700 }; 701 702 static struct clk_regmap gxbb_mpll2_div = { 703 .data = &(struct meson_clk_mpll_data){ 704 .sdm = { 705 .reg_off = HHI_MPLL_CNTL9, 706 .shift = 0, 707 .width = 14, 708 }, 709 .sdm_en = { 710 .reg_off = HHI_MPLL_CNTL9, 711 .shift = 15, 712 .width = 1, 713 }, 714 .n2 = { 715 .reg_off = HHI_MPLL_CNTL9, 716 .shift = 16, 717 .width = 9, 718 }, 719 .lock = &meson_clk_lock, 720 }, 721 .hw.init = &(struct clk_init_data){ 722 .name = "mpll2_div", 723 .ops = &meson_clk_mpll_ops, 724 .parent_names = (const char *[]){ "mpll_prediv" }, 725 .num_parents = 1, 726 }, 727 }; 728 729 static struct clk_regmap gxbb_mpll2 = { 730 .data = &(struct clk_regmap_gate_data){ 731 .offset = HHI_MPLL_CNTL9, 732 .bit_idx = 14, 733 }, 734 .hw.init = &(struct clk_init_data){ 735 .name = "mpll2", 736 .ops = &clk_regmap_gate_ops, 737 .parent_names = (const char *[]){ "mpll2_div" }, 738 .num_parents = 1, 739 .flags = CLK_SET_RATE_PARENT, 740 }, 741 }; 742 743 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 744 static const char * const clk81_parent_names[] = { 745 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", 746 "fclk_div3", "fclk_div5" 747 }; 748 749 static struct clk_regmap gxbb_mpeg_clk_sel = { 750 .data = &(struct clk_regmap_mux_data){ 751 .offset = HHI_MPEG_CLK_CNTL, 752 .mask = 0x7, 753 .shift = 12, 754 .table = mux_table_clk81, 755 }, 756 .hw.init = &(struct clk_init_data){ 757 .name = "mpeg_clk_sel", 758 .ops = &clk_regmap_mux_ro_ops, 759 /* 760 * bits 14:12 selects from 8 possible parents: 761 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 762 * fclk_div4, fclk_div3, fclk_div5 763 */ 764 .parent_names = clk81_parent_names, 765 .num_parents = ARRAY_SIZE(clk81_parent_names), 766 }, 767 }; 768 769 static struct clk_regmap gxbb_mpeg_clk_div = { 770 .data = &(struct clk_regmap_div_data){ 771 .offset = HHI_MPEG_CLK_CNTL, 772 .shift = 0, 773 .width = 7, 774 }, 775 .hw.init = &(struct clk_init_data){ 776 .name = "mpeg_clk_div", 777 .ops = &clk_regmap_divider_ro_ops, 778 .parent_names = (const char *[]){ "mpeg_clk_sel" }, 779 .num_parents = 1, 780 }, 781 }; 782 783 /* the mother of dragons gates */ 784 static struct clk_regmap gxbb_clk81 = { 785 .data = &(struct clk_regmap_gate_data){ 786 .offset = HHI_MPEG_CLK_CNTL, 787 .bit_idx = 7, 788 }, 789 .hw.init = &(struct clk_init_data){ 790 .name = "clk81", 791 .ops = &clk_regmap_gate_ops, 792 .parent_names = (const char *[]){ "mpeg_clk_div" }, 793 .num_parents = 1, 794 .flags = CLK_IS_CRITICAL, 795 }, 796 }; 797 798 static struct clk_regmap gxbb_sar_adc_clk_sel = { 799 .data = &(struct clk_regmap_mux_data){ 800 .offset = HHI_SAR_CLK_CNTL, 801 .mask = 0x3, 802 .shift = 9, 803 }, 804 .hw.init = &(struct clk_init_data){ 805 .name = "sar_adc_clk_sel", 806 .ops = &clk_regmap_mux_ops, 807 /* NOTE: The datasheet doesn't list the parents for bit 10 */ 808 .parent_names = (const char *[]){ "xtal", "clk81", }, 809 .num_parents = 2, 810 }, 811 }; 812 813 static struct clk_regmap gxbb_sar_adc_clk_div = { 814 .data = &(struct clk_regmap_div_data){ 815 .offset = HHI_SAR_CLK_CNTL, 816 .shift = 0, 817 .width = 8, 818 }, 819 .hw.init = &(struct clk_init_data){ 820 .name = "sar_adc_clk_div", 821 .ops = &clk_regmap_divider_ops, 822 .parent_names = (const char *[]){ "sar_adc_clk_sel" }, 823 .num_parents = 1, 824 }, 825 }; 826 827 static struct clk_regmap gxbb_sar_adc_clk = { 828 .data = &(struct clk_regmap_gate_data){ 829 .offset = HHI_SAR_CLK_CNTL, 830 .bit_idx = 8, 831 }, 832 .hw.init = &(struct clk_init_data){ 833 .name = "sar_adc_clk", 834 .ops = &clk_regmap_gate_ops, 835 .parent_names = (const char *[]){ "sar_adc_clk_div" }, 836 .num_parents = 1, 837 .flags = CLK_SET_RATE_PARENT, 838 }, 839 }; 840 841 /* 842 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 843 * muxed by a glitch-free switch. 844 */ 845 846 static const char * const gxbb_mali_0_1_parent_names[] = { 847 "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7", 848 "fclk_div4", "fclk_div3", "fclk_div5" 849 }; 850 851 static struct clk_regmap gxbb_mali_0_sel = { 852 .data = &(struct clk_regmap_mux_data){ 853 .offset = HHI_MALI_CLK_CNTL, 854 .mask = 0x7, 855 .shift = 9, 856 }, 857 .hw.init = &(struct clk_init_data){ 858 .name = "mali_0_sel", 859 .ops = &clk_regmap_mux_ops, 860 /* 861 * bits 10:9 selects from 8 possible parents: 862 * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 863 * fclk_div4, fclk_div3, fclk_div5 864 */ 865 .parent_names = gxbb_mali_0_1_parent_names, 866 .num_parents = 8, 867 .flags = CLK_SET_RATE_NO_REPARENT, 868 }, 869 }; 870 871 static struct clk_regmap gxbb_mali_0_div = { 872 .data = &(struct clk_regmap_div_data){ 873 .offset = HHI_MALI_CLK_CNTL, 874 .shift = 0, 875 .width = 7, 876 }, 877 .hw.init = &(struct clk_init_data){ 878 .name = "mali_0_div", 879 .ops = &clk_regmap_divider_ops, 880 .parent_names = (const char *[]){ "mali_0_sel" }, 881 .num_parents = 1, 882 .flags = CLK_SET_RATE_NO_REPARENT, 883 }, 884 }; 885 886 static struct clk_regmap gxbb_mali_0 = { 887 .data = &(struct clk_regmap_gate_data){ 888 .offset = HHI_MALI_CLK_CNTL, 889 .bit_idx = 8, 890 }, 891 .hw.init = &(struct clk_init_data){ 892 .name = "mali_0", 893 .ops = &clk_regmap_gate_ops, 894 .parent_names = (const char *[]){ "mali_0_div" }, 895 .num_parents = 1, 896 .flags = CLK_SET_RATE_PARENT, 897 }, 898 }; 899 900 static struct clk_regmap gxbb_mali_1_sel = { 901 .data = &(struct clk_regmap_mux_data){ 902 .offset = HHI_MALI_CLK_CNTL, 903 .mask = 0x7, 904 .shift = 25, 905 }, 906 .hw.init = &(struct clk_init_data){ 907 .name = "mali_1_sel", 908 .ops = &clk_regmap_mux_ops, 909 /* 910 * bits 10:9 selects from 8 possible parents: 911 * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 912 * fclk_div4, fclk_div3, fclk_div5 913 */ 914 .parent_names = gxbb_mali_0_1_parent_names, 915 .num_parents = 8, 916 .flags = CLK_SET_RATE_NO_REPARENT, 917 }, 918 }; 919 920 static struct clk_regmap gxbb_mali_1_div = { 921 .data = &(struct clk_regmap_div_data){ 922 .offset = HHI_MALI_CLK_CNTL, 923 .shift = 16, 924 .width = 7, 925 }, 926 .hw.init = &(struct clk_init_data){ 927 .name = "mali_1_div", 928 .ops = &clk_regmap_divider_ops, 929 .parent_names = (const char *[]){ "mali_1_sel" }, 930 .num_parents = 1, 931 .flags = CLK_SET_RATE_NO_REPARENT, 932 }, 933 }; 934 935 static struct clk_regmap gxbb_mali_1 = { 936 .data = &(struct clk_regmap_gate_data){ 937 .offset = HHI_MALI_CLK_CNTL, 938 .bit_idx = 24, 939 }, 940 .hw.init = &(struct clk_init_data){ 941 .name = "mali_1", 942 .ops = &clk_regmap_gate_ops, 943 .parent_names = (const char *[]){ "mali_1_div" }, 944 .num_parents = 1, 945 .flags = CLK_SET_RATE_PARENT, 946 }, 947 }; 948 949 static const char * const gxbb_mali_parent_names[] = { 950 "mali_0", "mali_1" 951 }; 952 953 static struct clk_regmap gxbb_mali = { 954 .data = &(struct clk_regmap_mux_data){ 955 .offset = HHI_MALI_CLK_CNTL, 956 .mask = 1, 957 .shift = 31, 958 }, 959 .hw.init = &(struct clk_init_data){ 960 .name = "mali", 961 .ops = &clk_regmap_mux_ops, 962 .parent_names = gxbb_mali_parent_names, 963 .num_parents = 2, 964 .flags = CLK_SET_RATE_NO_REPARENT, 965 }, 966 }; 967 968 static struct clk_regmap gxbb_cts_amclk_sel = { 969 .data = &(struct clk_regmap_mux_data){ 970 .offset = HHI_AUD_CLK_CNTL, 971 .mask = 0x3, 972 .shift = 9, 973 .table = (u32[]){ 1, 2, 3 }, 974 }, 975 .hw.init = &(struct clk_init_data){ 976 .name = "cts_amclk_sel", 977 .ops = &clk_regmap_mux_ops, 978 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 979 .num_parents = 3, 980 .flags = CLK_SET_RATE_PARENT, 981 }, 982 }; 983 984 static struct clk_regmap gxbb_cts_amclk_div = { 985 .data = &(struct meson_clk_audio_div_data){ 986 .div = { 987 .reg_off = HHI_AUD_CLK_CNTL, 988 .shift = 0, 989 .width = 8, 990 }, 991 .flags = CLK_DIVIDER_ROUND_CLOSEST, 992 }, 993 .hw.init = &(struct clk_init_data){ 994 .name = "cts_amclk_div", 995 .ops = &meson_clk_audio_divider_ops, 996 .parent_names = (const char *[]){ "cts_amclk_sel" }, 997 .num_parents = 1, 998 .flags = CLK_SET_RATE_PARENT, 999 }, 1000 }; 1001 1002 static struct clk_regmap gxbb_cts_amclk = { 1003 .data = &(struct clk_regmap_gate_data){ 1004 .offset = HHI_AUD_CLK_CNTL, 1005 .bit_idx = 8, 1006 }, 1007 .hw.init = &(struct clk_init_data){ 1008 .name = "cts_amclk", 1009 .ops = &clk_regmap_gate_ops, 1010 .parent_names = (const char *[]){ "cts_amclk_div" }, 1011 .num_parents = 1, 1012 .flags = CLK_SET_RATE_PARENT, 1013 }, 1014 }; 1015 1016 static struct clk_regmap gxbb_cts_mclk_i958_sel = { 1017 .data = &(struct clk_regmap_mux_data){ 1018 .offset = HHI_AUD_CLK_CNTL2, 1019 .mask = 0x3, 1020 .shift = 25, 1021 .table = (u32[]){ 1, 2, 3 }, 1022 }, 1023 .hw.init = &(struct clk_init_data) { 1024 .name = "cts_mclk_i958_sel", 1025 .ops = &clk_regmap_mux_ops, 1026 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 1027 .num_parents = 3, 1028 .flags = CLK_SET_RATE_PARENT, 1029 }, 1030 }; 1031 1032 static struct clk_regmap gxbb_cts_mclk_i958_div = { 1033 .data = &(struct clk_regmap_div_data){ 1034 .offset = HHI_AUD_CLK_CNTL2, 1035 .shift = 16, 1036 .width = 8, 1037 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1038 }, 1039 .hw.init = &(struct clk_init_data) { 1040 .name = "cts_mclk_i958_div", 1041 .ops = &clk_regmap_divider_ops, 1042 .parent_names = (const char *[]){ "cts_mclk_i958_sel" }, 1043 .num_parents = 1, 1044 .flags = CLK_SET_RATE_PARENT, 1045 }, 1046 }; 1047 1048 static struct clk_regmap gxbb_cts_mclk_i958 = { 1049 .data = &(struct clk_regmap_gate_data){ 1050 .offset = HHI_AUD_CLK_CNTL2, 1051 .bit_idx = 24, 1052 }, 1053 .hw.init = &(struct clk_init_data){ 1054 .name = "cts_mclk_i958", 1055 .ops = &clk_regmap_gate_ops, 1056 .parent_names = (const char *[]){ "cts_mclk_i958_div" }, 1057 .num_parents = 1, 1058 .flags = CLK_SET_RATE_PARENT, 1059 }, 1060 }; 1061 1062 static struct clk_regmap gxbb_cts_i958 = { 1063 .data = &(struct clk_regmap_mux_data){ 1064 .offset = HHI_AUD_CLK_CNTL2, 1065 .mask = 0x1, 1066 .shift = 27, 1067 }, 1068 .hw.init = &(struct clk_init_data){ 1069 .name = "cts_i958", 1070 .ops = &clk_regmap_mux_ops, 1071 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" }, 1072 .num_parents = 2, 1073 /* 1074 *The parent is specific to origin of the audio data. Let the 1075 * consumer choose the appropriate parent 1076 */ 1077 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 1078 }, 1079 }; 1080 1081 static struct clk_regmap gxbb_32k_clk_div = { 1082 .data = &(struct clk_regmap_div_data){ 1083 .offset = HHI_32K_CLK_CNTL, 1084 .shift = 0, 1085 .width = 14, 1086 }, 1087 .hw.init = &(struct clk_init_data){ 1088 .name = "32k_clk_div", 1089 .ops = &clk_regmap_divider_ops, 1090 .parent_names = (const char *[]){ "32k_clk_sel" }, 1091 .num_parents = 1, 1092 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, 1093 }, 1094 }; 1095 1096 static struct clk_regmap gxbb_32k_clk = { 1097 .data = &(struct clk_regmap_gate_data){ 1098 .offset = HHI_32K_CLK_CNTL, 1099 .bit_idx = 15, 1100 }, 1101 .hw.init = &(struct clk_init_data){ 1102 .name = "32k_clk", 1103 .ops = &clk_regmap_gate_ops, 1104 .parent_names = (const char *[]){ "32k_clk_div" }, 1105 .num_parents = 1, 1106 .flags = CLK_SET_RATE_PARENT, 1107 }, 1108 }; 1109 1110 static const char * const gxbb_32k_clk_parent_names[] = { 1111 "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5" 1112 }; 1113 1114 static struct clk_regmap gxbb_32k_clk_sel = { 1115 .data = &(struct clk_regmap_mux_data){ 1116 .offset = HHI_32K_CLK_CNTL, 1117 .mask = 0x3, 1118 .shift = 16, 1119 }, 1120 .hw.init = &(struct clk_init_data){ 1121 .name = "32k_clk_sel", 1122 .ops = &clk_regmap_mux_ops, 1123 .parent_names = gxbb_32k_clk_parent_names, 1124 .num_parents = 4, 1125 .flags = CLK_SET_RATE_PARENT, 1126 }, 1127 }; 1128 1129 static const char * const gxbb_sd_emmc_clk0_parent_names[] = { 1130 "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", 1131 1132 /* 1133 * Following these parent clocks, we should also have had mpll2, mpll3 1134 * and gp0_pll but these clocks are too precious to be used here. All 1135 * the necessary rates for MMC and NAND operation can be acheived using 1136 * xtal or fclk_div clocks 1137 */ 1138 }; 1139 1140 /* SDIO clock */ 1141 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = { 1142 .data = &(struct clk_regmap_mux_data){ 1143 .offset = HHI_SD_EMMC_CLK_CNTL, 1144 .mask = 0x7, 1145 .shift = 9, 1146 }, 1147 .hw.init = &(struct clk_init_data) { 1148 .name = "sd_emmc_a_clk0_sel", 1149 .ops = &clk_regmap_mux_ops, 1150 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1151 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1152 .flags = CLK_SET_RATE_PARENT, 1153 }, 1154 }; 1155 1156 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = { 1157 .data = &(struct clk_regmap_div_data){ 1158 .offset = HHI_SD_EMMC_CLK_CNTL, 1159 .shift = 0, 1160 .width = 7, 1161 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1162 }, 1163 .hw.init = &(struct clk_init_data) { 1164 .name = "sd_emmc_a_clk0_div", 1165 .ops = &clk_regmap_divider_ops, 1166 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" }, 1167 .num_parents = 1, 1168 .flags = CLK_SET_RATE_PARENT, 1169 }, 1170 }; 1171 1172 static struct clk_regmap gxbb_sd_emmc_a_clk0 = { 1173 .data = &(struct clk_regmap_gate_data){ 1174 .offset = HHI_SD_EMMC_CLK_CNTL, 1175 .bit_idx = 7, 1176 }, 1177 .hw.init = &(struct clk_init_data){ 1178 .name = "sd_emmc_a_clk0", 1179 .ops = &clk_regmap_gate_ops, 1180 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" }, 1181 .num_parents = 1, 1182 .flags = CLK_SET_RATE_PARENT, 1183 }, 1184 }; 1185 1186 /* SDcard clock */ 1187 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = { 1188 .data = &(struct clk_regmap_mux_data){ 1189 .offset = HHI_SD_EMMC_CLK_CNTL, 1190 .mask = 0x7, 1191 .shift = 25, 1192 }, 1193 .hw.init = &(struct clk_init_data) { 1194 .name = "sd_emmc_b_clk0_sel", 1195 .ops = &clk_regmap_mux_ops, 1196 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1197 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1198 .flags = CLK_SET_RATE_PARENT, 1199 }, 1200 }; 1201 1202 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = { 1203 .data = &(struct clk_regmap_div_data){ 1204 .offset = HHI_SD_EMMC_CLK_CNTL, 1205 .shift = 16, 1206 .width = 7, 1207 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1208 }, 1209 .hw.init = &(struct clk_init_data) { 1210 .name = "sd_emmc_b_clk0_div", 1211 .ops = &clk_regmap_divider_ops, 1212 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, 1213 .num_parents = 1, 1214 .flags = CLK_SET_RATE_PARENT, 1215 }, 1216 }; 1217 1218 static struct clk_regmap gxbb_sd_emmc_b_clk0 = { 1219 .data = &(struct clk_regmap_gate_data){ 1220 .offset = HHI_SD_EMMC_CLK_CNTL, 1221 .bit_idx = 23, 1222 }, 1223 .hw.init = &(struct clk_init_data){ 1224 .name = "sd_emmc_b_clk0", 1225 .ops = &clk_regmap_gate_ops, 1226 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, 1227 .num_parents = 1, 1228 .flags = CLK_SET_RATE_PARENT, 1229 }, 1230 }; 1231 1232 /* EMMC/NAND clock */ 1233 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = { 1234 .data = &(struct clk_regmap_mux_data){ 1235 .offset = HHI_NAND_CLK_CNTL, 1236 .mask = 0x7, 1237 .shift = 9, 1238 }, 1239 .hw.init = &(struct clk_init_data) { 1240 .name = "sd_emmc_c_clk0_sel", 1241 .ops = &clk_regmap_mux_ops, 1242 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1243 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1244 .flags = CLK_SET_RATE_PARENT, 1245 }, 1246 }; 1247 1248 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = { 1249 .data = &(struct clk_regmap_div_data){ 1250 .offset = HHI_NAND_CLK_CNTL, 1251 .shift = 0, 1252 .width = 7, 1253 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1254 }, 1255 .hw.init = &(struct clk_init_data) { 1256 .name = "sd_emmc_c_clk0_div", 1257 .ops = &clk_regmap_divider_ops, 1258 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, 1259 .num_parents = 1, 1260 .flags = CLK_SET_RATE_PARENT, 1261 }, 1262 }; 1263 1264 static struct clk_regmap gxbb_sd_emmc_c_clk0 = { 1265 .data = &(struct clk_regmap_gate_data){ 1266 .offset = HHI_NAND_CLK_CNTL, 1267 .bit_idx = 7, 1268 }, 1269 .hw.init = &(struct clk_init_data){ 1270 .name = "sd_emmc_c_clk0", 1271 .ops = &clk_regmap_gate_ops, 1272 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, 1273 .num_parents = 1, 1274 .flags = CLK_SET_RATE_PARENT, 1275 }, 1276 }; 1277 1278 /* VPU Clock */ 1279 1280 static const char * const gxbb_vpu_parent_names[] = { 1281 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1282 }; 1283 1284 static struct clk_regmap gxbb_vpu_0_sel = { 1285 .data = &(struct clk_regmap_mux_data){ 1286 .offset = HHI_VPU_CLK_CNTL, 1287 .mask = 0x3, 1288 .shift = 9, 1289 }, 1290 .hw.init = &(struct clk_init_data){ 1291 .name = "vpu_0_sel", 1292 .ops = &clk_regmap_mux_ops, 1293 /* 1294 * bits 9:10 selects from 4 possible parents: 1295 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1296 */ 1297 .parent_names = gxbb_vpu_parent_names, 1298 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names), 1299 .flags = CLK_SET_RATE_NO_REPARENT, 1300 }, 1301 }; 1302 1303 static struct clk_regmap gxbb_vpu_0_div = { 1304 .data = &(struct clk_regmap_div_data){ 1305 .offset = HHI_VPU_CLK_CNTL, 1306 .shift = 0, 1307 .width = 7, 1308 }, 1309 .hw.init = &(struct clk_init_data){ 1310 .name = "vpu_0_div", 1311 .ops = &clk_regmap_divider_ops, 1312 .parent_names = (const char *[]){ "vpu_0_sel" }, 1313 .num_parents = 1, 1314 .flags = CLK_SET_RATE_PARENT, 1315 }, 1316 }; 1317 1318 static struct clk_regmap gxbb_vpu_0 = { 1319 .data = &(struct clk_regmap_gate_data){ 1320 .offset = HHI_VPU_CLK_CNTL, 1321 .bit_idx = 8, 1322 }, 1323 .hw.init = &(struct clk_init_data) { 1324 .name = "vpu_0", 1325 .ops = &clk_regmap_gate_ops, 1326 .parent_names = (const char *[]){ "vpu_0_div" }, 1327 .num_parents = 1, 1328 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1329 }, 1330 }; 1331 1332 static struct clk_regmap gxbb_vpu_1_sel = { 1333 .data = &(struct clk_regmap_mux_data){ 1334 .offset = HHI_VPU_CLK_CNTL, 1335 .mask = 0x3, 1336 .shift = 25, 1337 }, 1338 .hw.init = &(struct clk_init_data){ 1339 .name = "vpu_1_sel", 1340 .ops = &clk_regmap_mux_ops, 1341 /* 1342 * bits 25:26 selects from 4 possible parents: 1343 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1344 */ 1345 .parent_names = gxbb_vpu_parent_names, 1346 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names), 1347 .flags = CLK_SET_RATE_NO_REPARENT, 1348 }, 1349 }; 1350 1351 static struct clk_regmap gxbb_vpu_1_div = { 1352 .data = &(struct clk_regmap_div_data){ 1353 .offset = HHI_VPU_CLK_CNTL, 1354 .shift = 16, 1355 .width = 7, 1356 }, 1357 .hw.init = &(struct clk_init_data){ 1358 .name = "vpu_1_div", 1359 .ops = &clk_regmap_divider_ops, 1360 .parent_names = (const char *[]){ "vpu_1_sel" }, 1361 .num_parents = 1, 1362 .flags = CLK_SET_RATE_PARENT, 1363 }, 1364 }; 1365 1366 static struct clk_regmap gxbb_vpu_1 = { 1367 .data = &(struct clk_regmap_gate_data){ 1368 .offset = HHI_VPU_CLK_CNTL, 1369 .bit_idx = 24, 1370 }, 1371 .hw.init = &(struct clk_init_data) { 1372 .name = "vpu_1", 1373 .ops = &clk_regmap_gate_ops, 1374 .parent_names = (const char *[]){ "vpu_1_div" }, 1375 .num_parents = 1, 1376 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1377 }, 1378 }; 1379 1380 static struct clk_regmap gxbb_vpu = { 1381 .data = &(struct clk_regmap_mux_data){ 1382 .offset = HHI_VPU_CLK_CNTL, 1383 .mask = 1, 1384 .shift = 31, 1385 }, 1386 .hw.init = &(struct clk_init_data){ 1387 .name = "vpu", 1388 .ops = &clk_regmap_mux_ops, 1389 /* 1390 * bit 31 selects from 2 possible parents: 1391 * vpu_0 or vpu_1 1392 */ 1393 .parent_names = (const char *[]){ "vpu_0", "vpu_1" }, 1394 .num_parents = 2, 1395 .flags = CLK_SET_RATE_NO_REPARENT, 1396 }, 1397 }; 1398 1399 /* VAPB Clock */ 1400 1401 static const char * const gxbb_vapb_parent_names[] = { 1402 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1403 }; 1404 1405 static struct clk_regmap gxbb_vapb_0_sel = { 1406 .data = &(struct clk_regmap_mux_data){ 1407 .offset = HHI_VAPBCLK_CNTL, 1408 .mask = 0x3, 1409 .shift = 9, 1410 }, 1411 .hw.init = &(struct clk_init_data){ 1412 .name = "vapb_0_sel", 1413 .ops = &clk_regmap_mux_ops, 1414 /* 1415 * bits 9:10 selects from 4 possible parents: 1416 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1417 */ 1418 .parent_names = gxbb_vapb_parent_names, 1419 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names), 1420 .flags = CLK_SET_RATE_NO_REPARENT, 1421 }, 1422 }; 1423 1424 static struct clk_regmap gxbb_vapb_0_div = { 1425 .data = &(struct clk_regmap_div_data){ 1426 .offset = HHI_VAPBCLK_CNTL, 1427 .shift = 0, 1428 .width = 7, 1429 }, 1430 .hw.init = &(struct clk_init_data){ 1431 .name = "vapb_0_div", 1432 .ops = &clk_regmap_divider_ops, 1433 .parent_names = (const char *[]){ "vapb_0_sel" }, 1434 .num_parents = 1, 1435 .flags = CLK_SET_RATE_PARENT, 1436 }, 1437 }; 1438 1439 static struct clk_regmap gxbb_vapb_0 = { 1440 .data = &(struct clk_regmap_gate_data){ 1441 .offset = HHI_VAPBCLK_CNTL, 1442 .bit_idx = 8, 1443 }, 1444 .hw.init = &(struct clk_init_data) { 1445 .name = "vapb_0", 1446 .ops = &clk_regmap_gate_ops, 1447 .parent_names = (const char *[]){ "vapb_0_div" }, 1448 .num_parents = 1, 1449 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1450 }, 1451 }; 1452 1453 static struct clk_regmap gxbb_vapb_1_sel = { 1454 .data = &(struct clk_regmap_mux_data){ 1455 .offset = HHI_VAPBCLK_CNTL, 1456 .mask = 0x3, 1457 .shift = 25, 1458 }, 1459 .hw.init = &(struct clk_init_data){ 1460 .name = "vapb_1_sel", 1461 .ops = &clk_regmap_mux_ops, 1462 /* 1463 * bits 25:26 selects from 4 possible parents: 1464 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1465 */ 1466 .parent_names = gxbb_vapb_parent_names, 1467 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names), 1468 .flags = CLK_SET_RATE_NO_REPARENT, 1469 }, 1470 }; 1471 1472 static struct clk_regmap gxbb_vapb_1_div = { 1473 .data = &(struct clk_regmap_div_data){ 1474 .offset = HHI_VAPBCLK_CNTL, 1475 .shift = 16, 1476 .width = 7, 1477 }, 1478 .hw.init = &(struct clk_init_data){ 1479 .name = "vapb_1_div", 1480 .ops = &clk_regmap_divider_ops, 1481 .parent_names = (const char *[]){ "vapb_1_sel" }, 1482 .num_parents = 1, 1483 .flags = CLK_SET_RATE_PARENT, 1484 }, 1485 }; 1486 1487 static struct clk_regmap gxbb_vapb_1 = { 1488 .data = &(struct clk_regmap_gate_data){ 1489 .offset = HHI_VAPBCLK_CNTL, 1490 .bit_idx = 24, 1491 }, 1492 .hw.init = &(struct clk_init_data) { 1493 .name = "vapb_1", 1494 .ops = &clk_regmap_gate_ops, 1495 .parent_names = (const char *[]){ "vapb_1_div" }, 1496 .num_parents = 1, 1497 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1498 }, 1499 }; 1500 1501 static struct clk_regmap gxbb_vapb_sel = { 1502 .data = &(struct clk_regmap_mux_data){ 1503 .offset = HHI_VAPBCLK_CNTL, 1504 .mask = 1, 1505 .shift = 31, 1506 }, 1507 .hw.init = &(struct clk_init_data){ 1508 .name = "vapb_sel", 1509 .ops = &clk_regmap_mux_ops, 1510 /* 1511 * bit 31 selects from 2 possible parents: 1512 * vapb_0 or vapb_1 1513 */ 1514 .parent_names = (const char *[]){ "vapb_0", "vapb_1" }, 1515 .num_parents = 2, 1516 .flags = CLK_SET_RATE_NO_REPARENT, 1517 }, 1518 }; 1519 1520 static struct clk_regmap gxbb_vapb = { 1521 .data = &(struct clk_regmap_gate_data){ 1522 .offset = HHI_VAPBCLK_CNTL, 1523 .bit_idx = 30, 1524 }, 1525 .hw.init = &(struct clk_init_data) { 1526 .name = "vapb", 1527 .ops = &clk_regmap_gate_ops, 1528 .parent_names = (const char *[]){ "vapb_sel" }, 1529 .num_parents = 1, 1530 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1531 }, 1532 }; 1533 1534 /* VDEC clocks */ 1535 1536 static const char * const gxbb_vdec_parent_names[] = { 1537 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1538 }; 1539 1540 static struct clk_regmap gxbb_vdec_1_sel = { 1541 .data = &(struct clk_regmap_mux_data){ 1542 .offset = HHI_VDEC_CLK_CNTL, 1543 .mask = 0x3, 1544 .shift = 9, 1545 .flags = CLK_MUX_ROUND_CLOSEST, 1546 }, 1547 .hw.init = &(struct clk_init_data){ 1548 .name = "vdec_1_sel", 1549 .ops = &clk_regmap_mux_ops, 1550 .parent_names = gxbb_vdec_parent_names, 1551 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names), 1552 .flags = CLK_SET_RATE_PARENT, 1553 }, 1554 }; 1555 1556 static struct clk_regmap gxbb_vdec_1_div = { 1557 .data = &(struct clk_regmap_div_data){ 1558 .offset = HHI_VDEC_CLK_CNTL, 1559 .shift = 0, 1560 .width = 7, 1561 }, 1562 .hw.init = &(struct clk_init_data){ 1563 .name = "vdec_1_div", 1564 .ops = &clk_regmap_divider_ops, 1565 .parent_names = (const char *[]){ "vdec_1_sel" }, 1566 .num_parents = 1, 1567 .flags = CLK_SET_RATE_PARENT, 1568 }, 1569 }; 1570 1571 static struct clk_regmap gxbb_vdec_1 = { 1572 .data = &(struct clk_regmap_gate_data){ 1573 .offset = HHI_VDEC_CLK_CNTL, 1574 .bit_idx = 8, 1575 }, 1576 .hw.init = &(struct clk_init_data) { 1577 .name = "vdec_1", 1578 .ops = &clk_regmap_gate_ops, 1579 .parent_names = (const char *[]){ "vdec_1_div" }, 1580 .num_parents = 1, 1581 .flags = CLK_SET_RATE_PARENT, 1582 }, 1583 }; 1584 1585 static struct clk_regmap gxbb_vdec_hevc_sel = { 1586 .data = &(struct clk_regmap_mux_data){ 1587 .offset = HHI_VDEC2_CLK_CNTL, 1588 .mask = 0x3, 1589 .shift = 25, 1590 .flags = CLK_MUX_ROUND_CLOSEST, 1591 }, 1592 .hw.init = &(struct clk_init_data){ 1593 .name = "vdec_hevc_sel", 1594 .ops = &clk_regmap_mux_ops, 1595 .parent_names = gxbb_vdec_parent_names, 1596 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names), 1597 .flags = CLK_SET_RATE_PARENT, 1598 }, 1599 }; 1600 1601 static struct clk_regmap gxbb_vdec_hevc_div = { 1602 .data = &(struct clk_regmap_div_data){ 1603 .offset = HHI_VDEC2_CLK_CNTL, 1604 .shift = 16, 1605 .width = 7, 1606 }, 1607 .hw.init = &(struct clk_init_data){ 1608 .name = "vdec_hevc_div", 1609 .ops = &clk_regmap_divider_ops, 1610 .parent_names = (const char *[]){ "vdec_hevc_sel" }, 1611 .num_parents = 1, 1612 .flags = CLK_SET_RATE_PARENT, 1613 }, 1614 }; 1615 1616 static struct clk_regmap gxbb_vdec_hevc = { 1617 .data = &(struct clk_regmap_gate_data){ 1618 .offset = HHI_VDEC2_CLK_CNTL, 1619 .bit_idx = 24, 1620 }, 1621 .hw.init = &(struct clk_init_data) { 1622 .name = "vdec_hevc", 1623 .ops = &clk_regmap_gate_ops, 1624 .parent_names = (const char *[]){ "vdec_hevc_div" }, 1625 .num_parents = 1, 1626 .flags = CLK_SET_RATE_PARENT, 1627 }, 1628 }; 1629 1630 /* Everything Else (EE) domain gates */ 1631 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 1632 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); 1633 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5); 1634 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6); 1635 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7); 1636 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8); 1637 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9); 1638 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10); 1639 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11); 1640 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12); 1641 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13); 1642 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14); 1643 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15); 1644 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16); 1645 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17); 1646 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18); 1647 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19); 1648 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); 1649 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24); 1650 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25); 1651 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26); 1652 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30); 1653 1654 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2); 1655 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3); 1656 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4); 1657 static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6); 1658 static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7); 1659 static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8); 1660 static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9); 1661 static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10); 1662 static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11); 1663 static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12); 1664 static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13); 1665 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14); 1666 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15); 1667 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16); 1668 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20); 1669 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21); 1670 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22); 1671 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23); 1672 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24); 1673 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25); 1674 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26); 1675 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28); 1676 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29); 1677 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30); 1678 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31); 1679 1680 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1); 1681 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 1682 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); 1683 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4); 1684 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); 1685 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); 1686 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); 1687 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12); 1688 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15); 1689 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22); 1690 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); 1691 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 1692 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); 1693 1694 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1); 1695 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2); 1696 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3); 1697 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4); 1698 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8); 1699 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9); 1700 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10); 1701 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14); 1702 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16); 1703 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20); 1704 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21); 1705 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22); 1706 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24); 1707 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25); 1708 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26); 1709 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31); 1710 1711 /* Always On (AO) domain gates */ 1712 1713 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0); 1714 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1); 1715 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2); 1716 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3); 1717 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4); 1718 1719 /* Array of all clocks provided by this provider */ 1720 1721 static struct clk_hw_onecell_data gxbb_hw_onecell_data = { 1722 .hws = { 1723 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 1724 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 1725 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 1726 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 1727 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 1728 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 1729 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 1730 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 1731 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 1732 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 1733 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 1734 [CLKID_CLK81] = &gxbb_clk81.hw, 1735 [CLKID_MPLL0] = &gxbb_mpll0.hw, 1736 [CLKID_MPLL1] = &gxbb_mpll1.hw, 1737 [CLKID_MPLL2] = &gxbb_mpll2.hw, 1738 [CLKID_DDR] = &gxbb_ddr.hw, 1739 [CLKID_DOS] = &gxbb_dos.hw, 1740 [CLKID_ISA] = &gxbb_isa.hw, 1741 [CLKID_PL301] = &gxbb_pl301.hw, 1742 [CLKID_PERIPHS] = &gxbb_periphs.hw, 1743 [CLKID_SPICC] = &gxbb_spicc.hw, 1744 [CLKID_I2C] = &gxbb_i2c.hw, 1745 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 1746 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 1747 [CLKID_RNG0] = &gxbb_rng0.hw, 1748 [CLKID_UART0] = &gxbb_uart0.hw, 1749 [CLKID_SDHC] = &gxbb_sdhc.hw, 1750 [CLKID_STREAM] = &gxbb_stream.hw, 1751 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 1752 [CLKID_SDIO] = &gxbb_sdio.hw, 1753 [CLKID_ABUF] = &gxbb_abuf.hw, 1754 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 1755 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 1756 [CLKID_SPI] = &gxbb_spi.hw, 1757 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 1758 [CLKID_ETH] = &gxbb_eth.hw, 1759 [CLKID_DEMUX] = &gxbb_demux.hw, 1760 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 1761 [CLKID_IEC958] = &gxbb_iec958.hw, 1762 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 1763 [CLKID_AMCLK] = &gxbb_amclk.hw, 1764 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 1765 [CLKID_MIXER] = &gxbb_mixer.hw, 1766 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 1767 [CLKID_ADC] = &gxbb_adc.hw, 1768 [CLKID_BLKMV] = &gxbb_blkmv.hw, 1769 [CLKID_AIU] = &gxbb_aiu.hw, 1770 [CLKID_UART1] = &gxbb_uart1.hw, 1771 [CLKID_G2D] = &gxbb_g2d.hw, 1772 [CLKID_USB0] = &gxbb_usb0.hw, 1773 [CLKID_USB1] = &gxbb_usb1.hw, 1774 [CLKID_RESET] = &gxbb_reset.hw, 1775 [CLKID_NAND] = &gxbb_nand.hw, 1776 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 1777 [CLKID_USB] = &gxbb_usb.hw, 1778 [CLKID_VDIN1] = &gxbb_vdin1.hw, 1779 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 1780 [CLKID_EFUSE] = &gxbb_efuse.hw, 1781 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 1782 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 1783 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 1784 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 1785 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 1786 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 1787 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 1788 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 1789 [CLKID_DVIN] = &gxbb_dvin.hw, 1790 [CLKID_UART2] = &gxbb_uart2.hw, 1791 [CLKID_SANA] = &gxbb_sana.hw, 1792 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 1793 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 1794 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 1795 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 1796 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 1797 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 1798 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 1799 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 1800 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 1801 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 1802 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 1803 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 1804 [CLKID_ENC480P] = &gxbb_enc480p.hw, 1805 [CLKID_RNG1] = &gxbb_rng1.hw, 1806 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 1807 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 1808 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 1809 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 1810 [CLKID_EDP] = &gxbb_edp.hw, 1811 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 1812 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 1813 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 1814 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 1815 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 1816 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 1817 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 1818 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 1819 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 1820 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 1821 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 1822 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 1823 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 1824 [CLKID_MALI_0] = &gxbb_mali_0.hw, 1825 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 1826 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 1827 [CLKID_MALI_1] = &gxbb_mali_1.hw, 1828 [CLKID_MALI] = &gxbb_mali.hw, 1829 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 1830 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 1831 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 1832 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 1833 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 1834 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 1835 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 1836 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 1837 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 1838 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 1839 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 1840 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 1841 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 1842 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 1843 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 1844 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 1845 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 1846 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 1847 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 1848 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 1849 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 1850 [CLKID_VPU_0] = &gxbb_vpu_0.hw, 1851 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 1852 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 1853 [CLKID_VPU_1] = &gxbb_vpu_1.hw, 1854 [CLKID_VPU] = &gxbb_vpu.hw, 1855 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 1856 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 1857 [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 1858 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 1859 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 1860 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 1861 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 1862 [CLKID_VAPB] = &gxbb_vapb.hw, 1863 [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw, 1864 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 1865 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 1866 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 1867 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 1868 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 1869 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 1870 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 1871 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 1872 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 1873 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 1874 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 1875 [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 1876 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 1877 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 1878 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 1879 [NR_CLKS] = NULL, 1880 }, 1881 .num = NR_CLKS, 1882 }; 1883 1884 static struct clk_hw_onecell_data gxl_hw_onecell_data = { 1885 .hws = { 1886 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 1887 [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw, 1888 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 1889 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 1890 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 1891 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 1892 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 1893 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 1894 [CLKID_GP0_PLL] = &gxl_gp0_pll.hw, 1895 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 1896 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 1897 [CLKID_CLK81] = &gxbb_clk81.hw, 1898 [CLKID_MPLL0] = &gxbb_mpll0.hw, 1899 [CLKID_MPLL1] = &gxbb_mpll1.hw, 1900 [CLKID_MPLL2] = &gxbb_mpll2.hw, 1901 [CLKID_DDR] = &gxbb_ddr.hw, 1902 [CLKID_DOS] = &gxbb_dos.hw, 1903 [CLKID_ISA] = &gxbb_isa.hw, 1904 [CLKID_PL301] = &gxbb_pl301.hw, 1905 [CLKID_PERIPHS] = &gxbb_periphs.hw, 1906 [CLKID_SPICC] = &gxbb_spicc.hw, 1907 [CLKID_I2C] = &gxbb_i2c.hw, 1908 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 1909 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 1910 [CLKID_RNG0] = &gxbb_rng0.hw, 1911 [CLKID_UART0] = &gxbb_uart0.hw, 1912 [CLKID_SDHC] = &gxbb_sdhc.hw, 1913 [CLKID_STREAM] = &gxbb_stream.hw, 1914 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 1915 [CLKID_SDIO] = &gxbb_sdio.hw, 1916 [CLKID_ABUF] = &gxbb_abuf.hw, 1917 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 1918 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 1919 [CLKID_SPI] = &gxbb_spi.hw, 1920 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 1921 [CLKID_ETH] = &gxbb_eth.hw, 1922 [CLKID_DEMUX] = &gxbb_demux.hw, 1923 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 1924 [CLKID_IEC958] = &gxbb_iec958.hw, 1925 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 1926 [CLKID_AMCLK] = &gxbb_amclk.hw, 1927 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 1928 [CLKID_MIXER] = &gxbb_mixer.hw, 1929 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 1930 [CLKID_ADC] = &gxbb_adc.hw, 1931 [CLKID_BLKMV] = &gxbb_blkmv.hw, 1932 [CLKID_AIU] = &gxbb_aiu.hw, 1933 [CLKID_UART1] = &gxbb_uart1.hw, 1934 [CLKID_G2D] = &gxbb_g2d.hw, 1935 [CLKID_USB0] = &gxbb_usb0.hw, 1936 [CLKID_USB1] = &gxbb_usb1.hw, 1937 [CLKID_RESET] = &gxbb_reset.hw, 1938 [CLKID_NAND] = &gxbb_nand.hw, 1939 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 1940 [CLKID_USB] = &gxbb_usb.hw, 1941 [CLKID_VDIN1] = &gxbb_vdin1.hw, 1942 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 1943 [CLKID_EFUSE] = &gxbb_efuse.hw, 1944 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 1945 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 1946 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 1947 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 1948 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 1949 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 1950 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 1951 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 1952 [CLKID_DVIN] = &gxbb_dvin.hw, 1953 [CLKID_UART2] = &gxbb_uart2.hw, 1954 [CLKID_SANA] = &gxbb_sana.hw, 1955 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 1956 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 1957 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 1958 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 1959 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 1960 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 1961 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 1962 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 1963 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 1964 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 1965 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 1966 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 1967 [CLKID_ENC480P] = &gxbb_enc480p.hw, 1968 [CLKID_RNG1] = &gxbb_rng1.hw, 1969 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 1970 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 1971 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 1972 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 1973 [CLKID_EDP] = &gxbb_edp.hw, 1974 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 1975 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 1976 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 1977 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 1978 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 1979 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 1980 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 1981 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 1982 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 1983 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 1984 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 1985 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 1986 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 1987 [CLKID_MALI_0] = &gxbb_mali_0.hw, 1988 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 1989 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 1990 [CLKID_MALI_1] = &gxbb_mali_1.hw, 1991 [CLKID_MALI] = &gxbb_mali.hw, 1992 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 1993 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 1994 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 1995 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 1996 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 1997 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 1998 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 1999 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 2000 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 2001 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 2002 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 2003 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 2004 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 2005 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 2006 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 2007 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 2008 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 2009 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 2010 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 2011 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 2012 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 2013 [CLKID_VPU_0] = &gxbb_vpu_0.hw, 2014 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 2015 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 2016 [CLKID_VPU_1] = &gxbb_vpu_1.hw, 2017 [CLKID_VPU] = &gxbb_vpu.hw, 2018 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 2019 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 2020 [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 2021 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 2022 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 2023 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 2024 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 2025 [CLKID_VAPB] = &gxbb_vapb.hw, 2026 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 2027 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 2028 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 2029 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 2030 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 2031 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 2032 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 2033 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 2034 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 2035 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 2036 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 2037 [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 2038 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 2039 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 2040 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 2041 [NR_CLKS] = NULL, 2042 }, 2043 .num = NR_CLKS, 2044 }; 2045 2046 static struct clk_regmap *const gxbb_clk_regmaps[] = { 2047 &gxbb_gp0_pll, 2048 &gxbb_hdmi_pll, 2049 }; 2050 2051 static struct clk_regmap *const gxl_clk_regmaps[] = { 2052 &gxl_gp0_pll, 2053 &gxl_hdmi_pll, 2054 }; 2055 2056 static struct clk_regmap *const gx_clk_regmaps[] = { 2057 &gxbb_clk81, 2058 &gxbb_ddr, 2059 &gxbb_dos, 2060 &gxbb_isa, 2061 &gxbb_pl301, 2062 &gxbb_periphs, 2063 &gxbb_spicc, 2064 &gxbb_i2c, 2065 &gxbb_sar_adc, 2066 &gxbb_smart_card, 2067 &gxbb_rng0, 2068 &gxbb_uart0, 2069 &gxbb_sdhc, 2070 &gxbb_stream, 2071 &gxbb_async_fifo, 2072 &gxbb_sdio, 2073 &gxbb_abuf, 2074 &gxbb_hiu_iface, 2075 &gxbb_assist_misc, 2076 &gxbb_spi, 2077 &gxbb_i2s_spdif, 2078 &gxbb_eth, 2079 &gxbb_demux, 2080 &gxbb_aiu_glue, 2081 &gxbb_iec958, 2082 &gxbb_i2s_out, 2083 &gxbb_amclk, 2084 &gxbb_aififo2, 2085 &gxbb_mixer, 2086 &gxbb_mixer_iface, 2087 &gxbb_adc, 2088 &gxbb_blkmv, 2089 &gxbb_aiu, 2090 &gxbb_uart1, 2091 &gxbb_g2d, 2092 &gxbb_usb0, 2093 &gxbb_usb1, 2094 &gxbb_reset, 2095 &gxbb_nand, 2096 &gxbb_dos_parser, 2097 &gxbb_usb, 2098 &gxbb_vdin1, 2099 &gxbb_ahb_arb0, 2100 &gxbb_efuse, 2101 &gxbb_boot_rom, 2102 &gxbb_ahb_data_bus, 2103 &gxbb_ahb_ctrl_bus, 2104 &gxbb_hdmi_intr_sync, 2105 &gxbb_hdmi_pclk, 2106 &gxbb_usb1_ddr_bridge, 2107 &gxbb_usb0_ddr_bridge, 2108 &gxbb_mmc_pclk, 2109 &gxbb_dvin, 2110 &gxbb_uart2, 2111 &gxbb_sana, 2112 &gxbb_vpu_intr, 2113 &gxbb_sec_ahb_ahb3_bridge, 2114 &gxbb_clk81_a53, 2115 &gxbb_vclk2_venci0, 2116 &gxbb_vclk2_venci1, 2117 &gxbb_vclk2_vencp0, 2118 &gxbb_vclk2_vencp1, 2119 &gxbb_gclk_venci_int0, 2120 &gxbb_gclk_vencp_int, 2121 &gxbb_dac_clk, 2122 &gxbb_aoclk_gate, 2123 &gxbb_iec958_gate, 2124 &gxbb_enc480p, 2125 &gxbb_rng1, 2126 &gxbb_gclk_venci_int1, 2127 &gxbb_vclk2_venclmcc, 2128 &gxbb_vclk2_vencl, 2129 &gxbb_vclk_other, 2130 &gxbb_edp, 2131 &gxbb_ao_media_cpu, 2132 &gxbb_ao_ahb_sram, 2133 &gxbb_ao_ahb_bus, 2134 &gxbb_ao_iface, 2135 &gxbb_ao_i2c, 2136 &gxbb_emmc_a, 2137 &gxbb_emmc_b, 2138 &gxbb_emmc_c, 2139 &gxbb_sar_adc_clk, 2140 &gxbb_mali_0, 2141 &gxbb_mali_1, 2142 &gxbb_cts_amclk, 2143 &gxbb_cts_mclk_i958, 2144 &gxbb_32k_clk, 2145 &gxbb_sd_emmc_a_clk0, 2146 &gxbb_sd_emmc_b_clk0, 2147 &gxbb_sd_emmc_c_clk0, 2148 &gxbb_vpu_0, 2149 &gxbb_vpu_1, 2150 &gxbb_vapb_0, 2151 &gxbb_vapb_1, 2152 &gxbb_vapb, 2153 &gxbb_mpeg_clk_div, 2154 &gxbb_sar_adc_clk_div, 2155 &gxbb_mali_0_div, 2156 &gxbb_mali_1_div, 2157 &gxbb_cts_mclk_i958_div, 2158 &gxbb_32k_clk_div, 2159 &gxbb_sd_emmc_a_clk0_div, 2160 &gxbb_sd_emmc_b_clk0_div, 2161 &gxbb_sd_emmc_c_clk0_div, 2162 &gxbb_vpu_0_div, 2163 &gxbb_vpu_1_div, 2164 &gxbb_vapb_0_div, 2165 &gxbb_vapb_1_div, 2166 &gxbb_mpeg_clk_sel, 2167 &gxbb_sar_adc_clk_sel, 2168 &gxbb_mali_0_sel, 2169 &gxbb_mali_1_sel, 2170 &gxbb_mali, 2171 &gxbb_cts_amclk_sel, 2172 &gxbb_cts_mclk_i958_sel, 2173 &gxbb_cts_i958, 2174 &gxbb_32k_clk_sel, 2175 &gxbb_sd_emmc_a_clk0_sel, 2176 &gxbb_sd_emmc_b_clk0_sel, 2177 &gxbb_sd_emmc_c_clk0_sel, 2178 &gxbb_vpu_0_sel, 2179 &gxbb_vpu_1_sel, 2180 &gxbb_vpu, 2181 &gxbb_vapb_0_sel, 2182 &gxbb_vapb_1_sel, 2183 &gxbb_vapb_sel, 2184 &gxbb_mpll0, 2185 &gxbb_mpll1, 2186 &gxbb_mpll2, 2187 &gxbb_mpll0_div, 2188 &gxbb_mpll1_div, 2189 &gxbb_mpll2_div, 2190 &gxbb_cts_amclk_div, 2191 &gxbb_fixed_pll, 2192 &gxbb_sys_pll, 2193 &gxbb_mpll_prediv, 2194 &gxbb_fclk_div2, 2195 &gxbb_fclk_div3, 2196 &gxbb_fclk_div4, 2197 &gxbb_fclk_div5, 2198 &gxbb_fclk_div7, 2199 &gxbb_vdec_1_sel, 2200 &gxbb_vdec_1_div, 2201 &gxbb_vdec_1, 2202 &gxbb_vdec_hevc_sel, 2203 &gxbb_vdec_hevc_div, 2204 &gxbb_vdec_hevc, 2205 }; 2206 2207 struct clkc_data { 2208 struct clk_regmap *const *regmap_clks; 2209 unsigned int regmap_clks_count; 2210 struct clk_hw_onecell_data *hw_onecell_data; 2211 }; 2212 2213 static const struct clkc_data gxbb_clkc_data = { 2214 .regmap_clks = gxbb_clk_regmaps, 2215 .regmap_clks_count = ARRAY_SIZE(gxbb_clk_regmaps), 2216 .hw_onecell_data = &gxbb_hw_onecell_data, 2217 }; 2218 2219 static const struct clkc_data gxl_clkc_data = { 2220 .regmap_clks = gxl_clk_regmaps, 2221 .regmap_clks_count = ARRAY_SIZE(gxl_clk_regmaps), 2222 .hw_onecell_data = &gxl_hw_onecell_data, 2223 }; 2224 2225 static const struct of_device_id clkc_match_table[] = { 2226 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data }, 2227 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data }, 2228 {}, 2229 }; 2230 2231 static const struct regmap_config clkc_regmap_config = { 2232 .reg_bits = 32, 2233 .val_bits = 32, 2234 .reg_stride = 4, 2235 }; 2236 2237 static int gxbb_clkc_probe(struct platform_device *pdev) 2238 { 2239 const struct clkc_data *clkc_data; 2240 struct resource *res; 2241 void __iomem *clk_base; 2242 struct regmap *map; 2243 int ret, i; 2244 struct device *dev = &pdev->dev; 2245 2246 clkc_data = of_device_get_match_data(dev); 2247 if (!clkc_data) 2248 return -EINVAL; 2249 2250 /* Get the hhi system controller node if available */ 2251 map = syscon_node_to_regmap(of_get_parent(dev->of_node)); 2252 if (IS_ERR(map)) { 2253 dev_err(dev, 2254 "failed to get HHI regmap - Trying obsolete regs\n"); 2255 2256 /* 2257 * FIXME: HHI registers should be accessed through 2258 * the appropriate system controller. This is required because 2259 * there is more than just clocks in this register space 2260 * 2261 * This fallback method is only provided temporarily until 2262 * all the platform DTs are properly using the syscon node 2263 */ 2264 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2265 if (!res) 2266 return -EINVAL; 2267 2268 clk_base = devm_ioremap(dev, res->start, resource_size(res)); 2269 if (!clk_base) { 2270 dev_err(dev, "Unable to map clk base\n"); 2271 return -ENXIO; 2272 } 2273 2274 map = devm_regmap_init_mmio(dev, clk_base, 2275 &clkc_regmap_config); 2276 if (IS_ERR(map)) 2277 return PTR_ERR(map); 2278 } 2279 2280 /* Populate regmap for the common regmap backed clocks */ 2281 for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++) 2282 gx_clk_regmaps[i]->map = map; 2283 2284 /* Populate regmap for soc specific clocks */ 2285 for (i = 0; i < clkc_data->regmap_clks_count; i++) 2286 clkc_data->regmap_clks[i]->map = map; 2287 2288 /* Register all clks */ 2289 for (i = 0; i < clkc_data->hw_onecell_data->num; i++) { 2290 /* array might be sparse */ 2291 if (!clkc_data->hw_onecell_data->hws[i]) 2292 continue; 2293 2294 ret = devm_clk_hw_register(dev, 2295 clkc_data->hw_onecell_data->hws[i]); 2296 if (ret) { 2297 dev_err(dev, "Clock registration failed\n"); 2298 return ret; 2299 } 2300 } 2301 2302 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 2303 clkc_data->hw_onecell_data); 2304 } 2305 2306 static struct platform_driver gxbb_driver = { 2307 .probe = gxbb_clkc_probe, 2308 .driver = { 2309 .name = "gxbb-clkc", 2310 .of_match_table = clkc_match_table, 2311 }, 2312 }; 2313 2314 builtin_platform_driver(gxbb_driver); 2315