1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016 AmLogic, Inc. 4 * Michael Turquette <mturquette@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/init.h> 10 #include <linux/of_device.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 15 #include "clkc.h" 16 #include "gxbb.h" 17 #include "clk-regmap.h" 18 19 static DEFINE_SPINLOCK(meson_clk_lock); 20 21 static const struct pll_rate_table gxbb_gp0_pll_rate_table[] = { 22 PLL_RATE(96000000, 32, 1, 3), 23 PLL_RATE(99000000, 33, 1, 3), 24 PLL_RATE(102000000, 34, 1, 3), 25 PLL_RATE(105000000, 35, 1, 3), 26 PLL_RATE(108000000, 36, 1, 3), 27 PLL_RATE(111000000, 37, 1, 3), 28 PLL_RATE(114000000, 38, 1, 3), 29 PLL_RATE(117000000, 39, 1, 3), 30 PLL_RATE(120000000, 40, 1, 3), 31 PLL_RATE(123000000, 41, 1, 3), 32 PLL_RATE(126000000, 42, 1, 3), 33 PLL_RATE(129000000, 43, 1, 3), 34 PLL_RATE(132000000, 44, 1, 3), 35 PLL_RATE(135000000, 45, 1, 3), 36 PLL_RATE(138000000, 46, 1, 3), 37 PLL_RATE(141000000, 47, 1, 3), 38 PLL_RATE(144000000, 48, 1, 3), 39 PLL_RATE(147000000, 49, 1, 3), 40 PLL_RATE(150000000, 50, 1, 3), 41 PLL_RATE(153000000, 51, 1, 3), 42 PLL_RATE(156000000, 52, 1, 3), 43 PLL_RATE(159000000, 53, 1, 3), 44 PLL_RATE(162000000, 54, 1, 3), 45 PLL_RATE(165000000, 55, 1, 3), 46 PLL_RATE(168000000, 56, 1, 3), 47 PLL_RATE(171000000, 57, 1, 3), 48 PLL_RATE(174000000, 58, 1, 3), 49 PLL_RATE(177000000, 59, 1, 3), 50 PLL_RATE(180000000, 60, 1, 3), 51 PLL_RATE(183000000, 61, 1, 3), 52 PLL_RATE(186000000, 62, 1, 3), 53 PLL_RATE(192000000, 32, 1, 2), 54 PLL_RATE(198000000, 33, 1, 2), 55 PLL_RATE(204000000, 34, 1, 2), 56 PLL_RATE(210000000, 35, 1, 2), 57 PLL_RATE(216000000, 36, 1, 2), 58 PLL_RATE(222000000, 37, 1, 2), 59 PLL_RATE(228000000, 38, 1, 2), 60 PLL_RATE(234000000, 39, 1, 2), 61 PLL_RATE(240000000, 40, 1, 2), 62 PLL_RATE(246000000, 41, 1, 2), 63 PLL_RATE(252000000, 42, 1, 2), 64 PLL_RATE(258000000, 43, 1, 2), 65 PLL_RATE(264000000, 44, 1, 2), 66 PLL_RATE(270000000, 45, 1, 2), 67 PLL_RATE(276000000, 46, 1, 2), 68 PLL_RATE(282000000, 47, 1, 2), 69 PLL_RATE(288000000, 48, 1, 2), 70 PLL_RATE(294000000, 49, 1, 2), 71 PLL_RATE(300000000, 50, 1, 2), 72 PLL_RATE(306000000, 51, 1, 2), 73 PLL_RATE(312000000, 52, 1, 2), 74 PLL_RATE(318000000, 53, 1, 2), 75 PLL_RATE(324000000, 54, 1, 2), 76 PLL_RATE(330000000, 55, 1, 2), 77 PLL_RATE(336000000, 56, 1, 2), 78 PLL_RATE(342000000, 57, 1, 2), 79 PLL_RATE(348000000, 58, 1, 2), 80 PLL_RATE(354000000, 59, 1, 2), 81 PLL_RATE(360000000, 60, 1, 2), 82 PLL_RATE(366000000, 61, 1, 2), 83 PLL_RATE(372000000, 62, 1, 2), 84 PLL_RATE(384000000, 32, 1, 1), 85 PLL_RATE(396000000, 33, 1, 1), 86 PLL_RATE(408000000, 34, 1, 1), 87 PLL_RATE(420000000, 35, 1, 1), 88 PLL_RATE(432000000, 36, 1, 1), 89 PLL_RATE(444000000, 37, 1, 1), 90 PLL_RATE(456000000, 38, 1, 1), 91 PLL_RATE(468000000, 39, 1, 1), 92 PLL_RATE(480000000, 40, 1, 1), 93 PLL_RATE(492000000, 41, 1, 1), 94 PLL_RATE(504000000, 42, 1, 1), 95 PLL_RATE(516000000, 43, 1, 1), 96 PLL_RATE(528000000, 44, 1, 1), 97 PLL_RATE(540000000, 45, 1, 1), 98 PLL_RATE(552000000, 46, 1, 1), 99 PLL_RATE(564000000, 47, 1, 1), 100 PLL_RATE(576000000, 48, 1, 1), 101 PLL_RATE(588000000, 49, 1, 1), 102 PLL_RATE(600000000, 50, 1, 1), 103 PLL_RATE(612000000, 51, 1, 1), 104 PLL_RATE(624000000, 52, 1, 1), 105 PLL_RATE(636000000, 53, 1, 1), 106 PLL_RATE(648000000, 54, 1, 1), 107 PLL_RATE(660000000, 55, 1, 1), 108 PLL_RATE(672000000, 56, 1, 1), 109 PLL_RATE(684000000, 57, 1, 1), 110 PLL_RATE(696000000, 58, 1, 1), 111 PLL_RATE(708000000, 59, 1, 1), 112 PLL_RATE(720000000, 60, 1, 1), 113 PLL_RATE(732000000, 61, 1, 1), 114 PLL_RATE(744000000, 62, 1, 1), 115 PLL_RATE(768000000, 32, 1, 0), 116 PLL_RATE(792000000, 33, 1, 0), 117 PLL_RATE(816000000, 34, 1, 0), 118 PLL_RATE(840000000, 35, 1, 0), 119 PLL_RATE(864000000, 36, 1, 0), 120 PLL_RATE(888000000, 37, 1, 0), 121 PLL_RATE(912000000, 38, 1, 0), 122 PLL_RATE(936000000, 39, 1, 0), 123 PLL_RATE(960000000, 40, 1, 0), 124 PLL_RATE(984000000, 41, 1, 0), 125 PLL_RATE(1008000000, 42, 1, 0), 126 PLL_RATE(1032000000, 43, 1, 0), 127 PLL_RATE(1056000000, 44, 1, 0), 128 PLL_RATE(1080000000, 45, 1, 0), 129 PLL_RATE(1104000000, 46, 1, 0), 130 PLL_RATE(1128000000, 47, 1, 0), 131 PLL_RATE(1152000000, 48, 1, 0), 132 PLL_RATE(1176000000, 49, 1, 0), 133 PLL_RATE(1200000000, 50, 1, 0), 134 PLL_RATE(1224000000, 51, 1, 0), 135 PLL_RATE(1248000000, 52, 1, 0), 136 PLL_RATE(1272000000, 53, 1, 0), 137 PLL_RATE(1296000000, 54, 1, 0), 138 PLL_RATE(1320000000, 55, 1, 0), 139 PLL_RATE(1344000000, 56, 1, 0), 140 PLL_RATE(1368000000, 57, 1, 0), 141 PLL_RATE(1392000000, 58, 1, 0), 142 PLL_RATE(1416000000, 59, 1, 0), 143 PLL_RATE(1440000000, 60, 1, 0), 144 PLL_RATE(1464000000, 61, 1, 0), 145 PLL_RATE(1488000000, 62, 1, 0), 146 { /* sentinel */ }, 147 }; 148 149 static const struct pll_rate_table gxl_gp0_pll_rate_table[] = { 150 PLL_RATE(504000000, 42, 1, 1), 151 PLL_RATE(516000000, 43, 1, 1), 152 PLL_RATE(528000000, 44, 1, 1), 153 PLL_RATE(540000000, 45, 1, 1), 154 PLL_RATE(552000000, 46, 1, 1), 155 PLL_RATE(564000000, 47, 1, 1), 156 PLL_RATE(576000000, 48, 1, 1), 157 PLL_RATE(588000000, 49, 1, 1), 158 PLL_RATE(600000000, 50, 1, 1), 159 PLL_RATE(612000000, 51, 1, 1), 160 PLL_RATE(624000000, 52, 1, 1), 161 PLL_RATE(636000000, 53, 1, 1), 162 PLL_RATE(648000000, 54, 1, 1), 163 PLL_RATE(660000000, 55, 1, 1), 164 PLL_RATE(672000000, 56, 1, 1), 165 PLL_RATE(684000000, 57, 1, 1), 166 PLL_RATE(696000000, 58, 1, 1), 167 PLL_RATE(708000000, 59, 1, 1), 168 PLL_RATE(720000000, 60, 1, 1), 169 PLL_RATE(732000000, 61, 1, 1), 170 PLL_RATE(744000000, 62, 1, 1), 171 PLL_RATE(756000000, 63, 1, 1), 172 PLL_RATE(768000000, 64, 1, 1), 173 PLL_RATE(780000000, 65, 1, 1), 174 PLL_RATE(792000000, 66, 1, 1), 175 { /* sentinel */ }, 176 }; 177 178 static struct clk_regmap gxbb_fixed_pll = { 179 .data = &(struct meson_clk_pll_data){ 180 .m = { 181 .reg_off = HHI_MPLL_CNTL, 182 .shift = 0, 183 .width = 9, 184 }, 185 .n = { 186 .reg_off = HHI_MPLL_CNTL, 187 .shift = 9, 188 .width = 5, 189 }, 190 .od = { 191 .reg_off = HHI_MPLL_CNTL, 192 .shift = 16, 193 .width = 2, 194 }, 195 .frac = { 196 .reg_off = HHI_MPLL_CNTL2, 197 .shift = 0, 198 .width = 12, 199 }, 200 .l = { 201 .reg_off = HHI_MPLL_CNTL, 202 .shift = 31, 203 .width = 1, 204 }, 205 .rst = { 206 .reg_off = HHI_MPLL_CNTL, 207 .shift = 29, 208 .width = 1, 209 }, 210 }, 211 .hw.init = &(struct clk_init_data){ 212 .name = "fixed_pll", 213 .ops = &meson_clk_pll_ro_ops, 214 .parent_names = (const char *[]){ "xtal" }, 215 .num_parents = 1, 216 .flags = CLK_GET_RATE_NOCACHE, 217 }, 218 }; 219 220 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = { 221 .mult = 2, 222 .div = 1, 223 .hw.init = &(struct clk_init_data){ 224 .name = "hdmi_pll_pre_mult", 225 .ops = &clk_fixed_factor_ops, 226 .parent_names = (const char *[]){ "xtal" }, 227 .num_parents = 1, 228 }, 229 }; 230 231 static struct clk_regmap gxbb_hdmi_pll = { 232 .data = &(struct meson_clk_pll_data){ 233 .m = { 234 .reg_off = HHI_HDMI_PLL_CNTL, 235 .shift = 0, 236 .width = 9, 237 }, 238 .n = { 239 .reg_off = HHI_HDMI_PLL_CNTL, 240 .shift = 9, 241 .width = 5, 242 }, 243 .frac = { 244 .reg_off = HHI_HDMI_PLL_CNTL2, 245 .shift = 0, 246 .width = 12, 247 }, 248 .od = { 249 .reg_off = HHI_HDMI_PLL_CNTL2, 250 .shift = 16, 251 .width = 2, 252 }, 253 .od2 = { 254 .reg_off = HHI_HDMI_PLL_CNTL2, 255 .shift = 22, 256 .width = 2, 257 }, 258 .od3 = { 259 .reg_off = HHI_HDMI_PLL_CNTL2, 260 .shift = 18, 261 .width = 2, 262 }, 263 .l = { 264 .reg_off = HHI_HDMI_PLL_CNTL, 265 .shift = 31, 266 .width = 1, 267 }, 268 .rst = { 269 .reg_off = HHI_HDMI_PLL_CNTL, 270 .shift = 28, 271 .width = 1, 272 }, 273 }, 274 .hw.init = &(struct clk_init_data){ 275 .name = "hdmi_pll", 276 .ops = &meson_clk_pll_ro_ops, 277 .parent_names = (const char *[]){ "hdmi_pll_pre_mult" }, 278 .num_parents = 1, 279 .flags = CLK_GET_RATE_NOCACHE, 280 }, 281 }; 282 283 static struct clk_regmap gxl_hdmi_pll = { 284 .data = &(struct meson_clk_pll_data){ 285 .m = { 286 .reg_off = HHI_HDMI_PLL_CNTL, 287 .shift = 0, 288 .width = 9, 289 }, 290 .n = { 291 .reg_off = HHI_HDMI_PLL_CNTL, 292 .shift = 9, 293 .width = 5, 294 }, 295 .frac = { 296 /* 297 * On gxl, there is a register shift due to 298 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb, 299 * so we compute the register offset based on the PLL 300 * base to get it right 301 */ 302 .reg_off = HHI_HDMI_PLL_CNTL + 4, 303 .shift = 0, 304 .width = 12, 305 }, 306 .od = { 307 .reg_off = HHI_HDMI_PLL_CNTL + 8, 308 .shift = 21, 309 .width = 2, 310 }, 311 .od2 = { 312 .reg_off = HHI_HDMI_PLL_CNTL + 8, 313 .shift = 23, 314 .width = 2, 315 }, 316 .od3 = { 317 .reg_off = HHI_HDMI_PLL_CNTL + 8, 318 .shift = 19, 319 .width = 2, 320 }, 321 .l = { 322 .reg_off = HHI_HDMI_PLL_CNTL, 323 .shift = 31, 324 .width = 1, 325 }, 326 .rst = { 327 .reg_off = HHI_HDMI_PLL_CNTL, 328 .shift = 29, 329 .width = 1, 330 }, 331 }, 332 .hw.init = &(struct clk_init_data){ 333 .name = "hdmi_pll", 334 .ops = &meson_clk_pll_ro_ops, 335 .parent_names = (const char *[]){ "xtal" }, 336 .num_parents = 1, 337 .flags = CLK_GET_RATE_NOCACHE, 338 }, 339 }; 340 341 static struct clk_regmap gxbb_sys_pll = { 342 .data = &(struct meson_clk_pll_data){ 343 .m = { 344 .reg_off = HHI_SYS_PLL_CNTL, 345 .shift = 0, 346 .width = 9, 347 }, 348 .n = { 349 .reg_off = HHI_SYS_PLL_CNTL, 350 .shift = 9, 351 .width = 5, 352 }, 353 .od = { 354 .reg_off = HHI_SYS_PLL_CNTL, 355 .shift = 10, 356 .width = 2, 357 }, 358 .l = { 359 .reg_off = HHI_SYS_PLL_CNTL, 360 .shift = 31, 361 .width = 1, 362 }, 363 .rst = { 364 .reg_off = HHI_SYS_PLL_CNTL, 365 .shift = 29, 366 .width = 1, 367 }, 368 }, 369 .hw.init = &(struct clk_init_data){ 370 .name = "sys_pll", 371 .ops = &meson_clk_pll_ro_ops, 372 .parent_names = (const char *[]){ "xtal" }, 373 .num_parents = 1, 374 .flags = CLK_GET_RATE_NOCACHE, 375 }, 376 }; 377 378 static const struct reg_sequence gxbb_gp0_init_regs[] = { 379 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 }, 380 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 }, 381 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d }, 382 { .reg = HHI_GP0_PLL_CNTL, .def = 0x4a000228 }, 383 }; 384 385 static struct clk_regmap gxbb_gp0_pll = { 386 .data = &(struct meson_clk_pll_data){ 387 .m = { 388 .reg_off = HHI_GP0_PLL_CNTL, 389 .shift = 0, 390 .width = 9, 391 }, 392 .n = { 393 .reg_off = HHI_GP0_PLL_CNTL, 394 .shift = 9, 395 .width = 5, 396 }, 397 .od = { 398 .reg_off = HHI_GP0_PLL_CNTL, 399 .shift = 16, 400 .width = 2, 401 }, 402 .l = { 403 .reg_off = HHI_GP0_PLL_CNTL, 404 .shift = 31, 405 .width = 1, 406 }, 407 .rst = { 408 .reg_off = HHI_GP0_PLL_CNTL, 409 .shift = 29, 410 .width = 1, 411 }, 412 .table = gxbb_gp0_pll_rate_table, 413 .init_regs = gxbb_gp0_init_regs, 414 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs), 415 }, 416 .hw.init = &(struct clk_init_data){ 417 .name = "gp0_pll", 418 .ops = &meson_clk_pll_ops, 419 .parent_names = (const char *[]){ "xtal" }, 420 .num_parents = 1, 421 .flags = CLK_GET_RATE_NOCACHE, 422 }, 423 }; 424 425 static const struct reg_sequence gxl_gp0_init_regs[] = { 426 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, 427 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, 428 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 429 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 430 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 431 { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 }, 432 }; 433 434 static struct clk_regmap gxl_gp0_pll = { 435 .data = &(struct meson_clk_pll_data){ 436 .m = { 437 .reg_off = HHI_GP0_PLL_CNTL, 438 .shift = 0, 439 .width = 9, 440 }, 441 .n = { 442 .reg_off = HHI_GP0_PLL_CNTL, 443 .shift = 9, 444 .width = 5, 445 }, 446 .od = { 447 .reg_off = HHI_GP0_PLL_CNTL, 448 .shift = 16, 449 .width = 2, 450 }, 451 .frac = { 452 .reg_off = HHI_GP0_PLL_CNTL1, 453 .shift = 0, 454 .width = 10, 455 }, 456 .l = { 457 .reg_off = HHI_GP0_PLL_CNTL, 458 .shift = 31, 459 .width = 1, 460 }, 461 .rst = { 462 .reg_off = HHI_GP0_PLL_CNTL, 463 .shift = 29, 464 .width = 1, 465 }, 466 .table = gxl_gp0_pll_rate_table, 467 .init_regs = gxl_gp0_init_regs, 468 .init_count = ARRAY_SIZE(gxl_gp0_init_regs), 469 }, 470 .hw.init = &(struct clk_init_data){ 471 .name = "gp0_pll", 472 .ops = &meson_clk_pll_ops, 473 .parent_names = (const char *[]){ "xtal" }, 474 .num_parents = 1, 475 .flags = CLK_GET_RATE_NOCACHE, 476 }, 477 }; 478 479 static struct clk_fixed_factor gxbb_fclk_div2_div = { 480 .mult = 1, 481 .div = 2, 482 .hw.init = &(struct clk_init_data){ 483 .name = "fclk_div2_div", 484 .ops = &clk_fixed_factor_ops, 485 .parent_names = (const char *[]){ "fixed_pll" }, 486 .num_parents = 1, 487 }, 488 }; 489 490 static struct clk_regmap gxbb_fclk_div2 = { 491 .data = &(struct clk_regmap_gate_data){ 492 .offset = HHI_MPLL_CNTL6, 493 .bit_idx = 27, 494 }, 495 .hw.init = &(struct clk_init_data){ 496 .name = "fclk_div2", 497 .ops = &clk_regmap_gate_ops, 498 .parent_names = (const char *[]){ "fclk_div2_div" }, 499 .num_parents = 1, 500 .flags = CLK_IS_CRITICAL, 501 }, 502 }; 503 504 static struct clk_fixed_factor gxbb_fclk_div3_div = { 505 .mult = 1, 506 .div = 3, 507 .hw.init = &(struct clk_init_data){ 508 .name = "fclk_div3_div", 509 .ops = &clk_fixed_factor_ops, 510 .parent_names = (const char *[]){ "fixed_pll" }, 511 .num_parents = 1, 512 }, 513 }; 514 515 static struct clk_regmap gxbb_fclk_div3 = { 516 .data = &(struct clk_regmap_gate_data){ 517 .offset = HHI_MPLL_CNTL6, 518 .bit_idx = 28, 519 }, 520 .hw.init = &(struct clk_init_data){ 521 .name = "fclk_div3", 522 .ops = &clk_regmap_gate_ops, 523 .parent_names = (const char *[]){ "fclk_div3_div" }, 524 .num_parents = 1, 525 }, 526 }; 527 528 static struct clk_fixed_factor gxbb_fclk_div4_div = { 529 .mult = 1, 530 .div = 4, 531 .hw.init = &(struct clk_init_data){ 532 .name = "fclk_div4_div", 533 .ops = &clk_fixed_factor_ops, 534 .parent_names = (const char *[]){ "fixed_pll" }, 535 .num_parents = 1, 536 }, 537 }; 538 539 static struct clk_regmap gxbb_fclk_div4 = { 540 .data = &(struct clk_regmap_gate_data){ 541 .offset = HHI_MPLL_CNTL6, 542 .bit_idx = 29, 543 }, 544 .hw.init = &(struct clk_init_data){ 545 .name = "fclk_div4", 546 .ops = &clk_regmap_gate_ops, 547 .parent_names = (const char *[]){ "fclk_div4_div" }, 548 .num_parents = 1, 549 }, 550 }; 551 552 static struct clk_fixed_factor gxbb_fclk_div5_div = { 553 .mult = 1, 554 .div = 5, 555 .hw.init = &(struct clk_init_data){ 556 .name = "fclk_div5_div", 557 .ops = &clk_fixed_factor_ops, 558 .parent_names = (const char *[]){ "fixed_pll" }, 559 .num_parents = 1, 560 }, 561 }; 562 563 static struct clk_regmap gxbb_fclk_div5 = { 564 .data = &(struct clk_regmap_gate_data){ 565 .offset = HHI_MPLL_CNTL6, 566 .bit_idx = 30, 567 }, 568 .hw.init = &(struct clk_init_data){ 569 .name = "fclk_div5", 570 .ops = &clk_regmap_gate_ops, 571 .parent_names = (const char *[]){ "fclk_div5_div" }, 572 .num_parents = 1, 573 }, 574 }; 575 576 static struct clk_fixed_factor gxbb_fclk_div7_div = { 577 .mult = 1, 578 .div = 7, 579 .hw.init = &(struct clk_init_data){ 580 .name = "fclk_div7_div", 581 .ops = &clk_fixed_factor_ops, 582 .parent_names = (const char *[]){ "fixed_pll" }, 583 .num_parents = 1, 584 }, 585 }; 586 587 static struct clk_regmap gxbb_fclk_div7 = { 588 .data = &(struct clk_regmap_gate_data){ 589 .offset = HHI_MPLL_CNTL6, 590 .bit_idx = 31, 591 }, 592 .hw.init = &(struct clk_init_data){ 593 .name = "fclk_div7", 594 .ops = &clk_regmap_gate_ops, 595 .parent_names = (const char *[]){ "fclk_div7_div" }, 596 .num_parents = 1, 597 }, 598 }; 599 600 static struct clk_regmap gxbb_mpll_prediv = { 601 .data = &(struct clk_regmap_div_data){ 602 .offset = HHI_MPLL_CNTL5, 603 .shift = 12, 604 .width = 1, 605 }, 606 .hw.init = &(struct clk_init_data){ 607 .name = "mpll_prediv", 608 .ops = &clk_regmap_divider_ro_ops, 609 .parent_names = (const char *[]){ "fixed_pll" }, 610 .num_parents = 1, 611 }, 612 }; 613 614 static struct clk_regmap gxbb_mpll0_div = { 615 .data = &(struct meson_clk_mpll_data){ 616 .sdm = { 617 .reg_off = HHI_MPLL_CNTL7, 618 .shift = 0, 619 .width = 14, 620 }, 621 .sdm_en = { 622 .reg_off = HHI_MPLL_CNTL7, 623 .shift = 15, 624 .width = 1, 625 }, 626 .n2 = { 627 .reg_off = HHI_MPLL_CNTL7, 628 .shift = 16, 629 .width = 9, 630 }, 631 .ssen = { 632 .reg_off = HHI_MPLL_CNTL, 633 .shift = 25, 634 .width = 1, 635 }, 636 .lock = &meson_clk_lock, 637 }, 638 .hw.init = &(struct clk_init_data){ 639 .name = "mpll0_div", 640 .ops = &meson_clk_mpll_ops, 641 .parent_names = (const char *[]){ "mpll_prediv" }, 642 .num_parents = 1, 643 }, 644 }; 645 646 static struct clk_regmap gxbb_mpll0 = { 647 .data = &(struct clk_regmap_gate_data){ 648 .offset = HHI_MPLL_CNTL7, 649 .bit_idx = 14, 650 }, 651 .hw.init = &(struct clk_init_data){ 652 .name = "mpll0", 653 .ops = &clk_regmap_gate_ops, 654 .parent_names = (const char *[]){ "mpll0_div" }, 655 .num_parents = 1, 656 .flags = CLK_SET_RATE_PARENT, 657 }, 658 }; 659 660 static struct clk_regmap gxbb_mpll1_div = { 661 .data = &(struct meson_clk_mpll_data){ 662 .sdm = { 663 .reg_off = HHI_MPLL_CNTL8, 664 .shift = 0, 665 .width = 14, 666 }, 667 .sdm_en = { 668 .reg_off = HHI_MPLL_CNTL8, 669 .shift = 15, 670 .width = 1, 671 }, 672 .n2 = { 673 .reg_off = HHI_MPLL_CNTL8, 674 .shift = 16, 675 .width = 9, 676 }, 677 .lock = &meson_clk_lock, 678 }, 679 .hw.init = &(struct clk_init_data){ 680 .name = "mpll1_div", 681 .ops = &meson_clk_mpll_ops, 682 .parent_names = (const char *[]){ "mpll_prediv" }, 683 .num_parents = 1, 684 }, 685 }; 686 687 static struct clk_regmap gxbb_mpll1 = { 688 .data = &(struct clk_regmap_gate_data){ 689 .offset = HHI_MPLL_CNTL8, 690 .bit_idx = 14, 691 }, 692 .hw.init = &(struct clk_init_data){ 693 .name = "mpll1", 694 .ops = &clk_regmap_gate_ops, 695 .parent_names = (const char *[]){ "mpll1_div" }, 696 .num_parents = 1, 697 .flags = CLK_SET_RATE_PARENT, 698 }, 699 }; 700 701 static struct clk_regmap gxbb_mpll2_div = { 702 .data = &(struct meson_clk_mpll_data){ 703 .sdm = { 704 .reg_off = HHI_MPLL_CNTL9, 705 .shift = 0, 706 .width = 14, 707 }, 708 .sdm_en = { 709 .reg_off = HHI_MPLL_CNTL9, 710 .shift = 15, 711 .width = 1, 712 }, 713 .n2 = { 714 .reg_off = HHI_MPLL_CNTL9, 715 .shift = 16, 716 .width = 9, 717 }, 718 .lock = &meson_clk_lock, 719 }, 720 .hw.init = &(struct clk_init_data){ 721 .name = "mpll2_div", 722 .ops = &meson_clk_mpll_ops, 723 .parent_names = (const char *[]){ "mpll_prediv" }, 724 .num_parents = 1, 725 }, 726 }; 727 728 static struct clk_regmap gxbb_mpll2 = { 729 .data = &(struct clk_regmap_gate_data){ 730 .offset = HHI_MPLL_CNTL9, 731 .bit_idx = 14, 732 }, 733 .hw.init = &(struct clk_init_data){ 734 .name = "mpll2", 735 .ops = &clk_regmap_gate_ops, 736 .parent_names = (const char *[]){ "mpll2_div" }, 737 .num_parents = 1, 738 .flags = CLK_SET_RATE_PARENT, 739 }, 740 }; 741 742 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 743 static const char * const clk81_parent_names[] = { 744 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", 745 "fclk_div3", "fclk_div5" 746 }; 747 748 static struct clk_regmap gxbb_mpeg_clk_sel = { 749 .data = &(struct clk_regmap_mux_data){ 750 .offset = HHI_MPEG_CLK_CNTL, 751 .mask = 0x7, 752 .shift = 12, 753 .table = mux_table_clk81, 754 }, 755 .hw.init = &(struct clk_init_data){ 756 .name = "mpeg_clk_sel", 757 .ops = &clk_regmap_mux_ro_ops, 758 /* 759 * bits 14:12 selects from 8 possible parents: 760 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 761 * fclk_div4, fclk_div3, fclk_div5 762 */ 763 .parent_names = clk81_parent_names, 764 .num_parents = ARRAY_SIZE(clk81_parent_names), 765 }, 766 }; 767 768 static struct clk_regmap gxbb_mpeg_clk_div = { 769 .data = &(struct clk_regmap_div_data){ 770 .offset = HHI_MPEG_CLK_CNTL, 771 .shift = 0, 772 .width = 7, 773 }, 774 .hw.init = &(struct clk_init_data){ 775 .name = "mpeg_clk_div", 776 .ops = &clk_regmap_divider_ro_ops, 777 .parent_names = (const char *[]){ "mpeg_clk_sel" }, 778 .num_parents = 1, 779 }, 780 }; 781 782 /* the mother of dragons gates */ 783 static struct clk_regmap gxbb_clk81 = { 784 .data = &(struct clk_regmap_gate_data){ 785 .offset = HHI_MPEG_CLK_CNTL, 786 .bit_idx = 7, 787 }, 788 .hw.init = &(struct clk_init_data){ 789 .name = "clk81", 790 .ops = &clk_regmap_gate_ops, 791 .parent_names = (const char *[]){ "mpeg_clk_div" }, 792 .num_parents = 1, 793 .flags = CLK_IS_CRITICAL, 794 }, 795 }; 796 797 static struct clk_regmap gxbb_sar_adc_clk_sel = { 798 .data = &(struct clk_regmap_mux_data){ 799 .offset = HHI_SAR_CLK_CNTL, 800 .mask = 0x3, 801 .shift = 9, 802 }, 803 .hw.init = &(struct clk_init_data){ 804 .name = "sar_adc_clk_sel", 805 .ops = &clk_regmap_mux_ops, 806 /* NOTE: The datasheet doesn't list the parents for bit 10 */ 807 .parent_names = (const char *[]){ "xtal", "clk81", }, 808 .num_parents = 2, 809 }, 810 }; 811 812 static struct clk_regmap gxbb_sar_adc_clk_div = { 813 .data = &(struct clk_regmap_div_data){ 814 .offset = HHI_SAR_CLK_CNTL, 815 .shift = 0, 816 .width = 8, 817 }, 818 .hw.init = &(struct clk_init_data){ 819 .name = "sar_adc_clk_div", 820 .ops = &clk_regmap_divider_ops, 821 .parent_names = (const char *[]){ "sar_adc_clk_sel" }, 822 .num_parents = 1, 823 }, 824 }; 825 826 static struct clk_regmap gxbb_sar_adc_clk = { 827 .data = &(struct clk_regmap_gate_data){ 828 .offset = HHI_SAR_CLK_CNTL, 829 .bit_idx = 8, 830 }, 831 .hw.init = &(struct clk_init_data){ 832 .name = "sar_adc_clk", 833 .ops = &clk_regmap_gate_ops, 834 .parent_names = (const char *[]){ "sar_adc_clk_div" }, 835 .num_parents = 1, 836 .flags = CLK_SET_RATE_PARENT, 837 }, 838 }; 839 840 /* 841 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 842 * muxed by a glitch-free switch. 843 */ 844 845 static const char * const gxbb_mali_0_1_parent_names[] = { 846 "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7", 847 "fclk_div4", "fclk_div3", "fclk_div5" 848 }; 849 850 static struct clk_regmap gxbb_mali_0_sel = { 851 .data = &(struct clk_regmap_mux_data){ 852 .offset = HHI_MALI_CLK_CNTL, 853 .mask = 0x7, 854 .shift = 9, 855 }, 856 .hw.init = &(struct clk_init_data){ 857 .name = "mali_0_sel", 858 .ops = &clk_regmap_mux_ops, 859 /* 860 * bits 10:9 selects from 8 possible parents: 861 * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 862 * fclk_div4, fclk_div3, fclk_div5 863 */ 864 .parent_names = gxbb_mali_0_1_parent_names, 865 .num_parents = 8, 866 .flags = CLK_SET_RATE_NO_REPARENT, 867 }, 868 }; 869 870 static struct clk_regmap gxbb_mali_0_div = { 871 .data = &(struct clk_regmap_div_data){ 872 .offset = HHI_MALI_CLK_CNTL, 873 .shift = 0, 874 .width = 7, 875 }, 876 .hw.init = &(struct clk_init_data){ 877 .name = "mali_0_div", 878 .ops = &clk_regmap_divider_ops, 879 .parent_names = (const char *[]){ "mali_0_sel" }, 880 .num_parents = 1, 881 .flags = CLK_SET_RATE_NO_REPARENT, 882 }, 883 }; 884 885 static struct clk_regmap gxbb_mali_0 = { 886 .data = &(struct clk_regmap_gate_data){ 887 .offset = HHI_MALI_CLK_CNTL, 888 .bit_idx = 8, 889 }, 890 .hw.init = &(struct clk_init_data){ 891 .name = "mali_0", 892 .ops = &clk_regmap_gate_ops, 893 .parent_names = (const char *[]){ "mali_0_div" }, 894 .num_parents = 1, 895 .flags = CLK_SET_RATE_PARENT, 896 }, 897 }; 898 899 static struct clk_regmap gxbb_mali_1_sel = { 900 .data = &(struct clk_regmap_mux_data){ 901 .offset = HHI_MALI_CLK_CNTL, 902 .mask = 0x7, 903 .shift = 25, 904 }, 905 .hw.init = &(struct clk_init_data){ 906 .name = "mali_1_sel", 907 .ops = &clk_regmap_mux_ops, 908 /* 909 * bits 10:9 selects from 8 possible parents: 910 * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 911 * fclk_div4, fclk_div3, fclk_div5 912 */ 913 .parent_names = gxbb_mali_0_1_parent_names, 914 .num_parents = 8, 915 .flags = CLK_SET_RATE_NO_REPARENT, 916 }, 917 }; 918 919 static struct clk_regmap gxbb_mali_1_div = { 920 .data = &(struct clk_regmap_div_data){ 921 .offset = HHI_MALI_CLK_CNTL, 922 .shift = 16, 923 .width = 7, 924 }, 925 .hw.init = &(struct clk_init_data){ 926 .name = "mali_1_div", 927 .ops = &clk_regmap_divider_ops, 928 .parent_names = (const char *[]){ "mali_1_sel" }, 929 .num_parents = 1, 930 .flags = CLK_SET_RATE_NO_REPARENT, 931 }, 932 }; 933 934 static struct clk_regmap gxbb_mali_1 = { 935 .data = &(struct clk_regmap_gate_data){ 936 .offset = HHI_MALI_CLK_CNTL, 937 .bit_idx = 24, 938 }, 939 .hw.init = &(struct clk_init_data){ 940 .name = "mali_1", 941 .ops = &clk_regmap_gate_ops, 942 .parent_names = (const char *[]){ "mali_1_div" }, 943 .num_parents = 1, 944 .flags = CLK_SET_RATE_PARENT, 945 }, 946 }; 947 948 static const char * const gxbb_mali_parent_names[] = { 949 "mali_0", "mali_1" 950 }; 951 952 static struct clk_regmap gxbb_mali = { 953 .data = &(struct clk_regmap_mux_data){ 954 .offset = HHI_MALI_CLK_CNTL, 955 .mask = 1, 956 .shift = 31, 957 }, 958 .hw.init = &(struct clk_init_data){ 959 .name = "mali", 960 .ops = &clk_regmap_mux_ops, 961 .parent_names = gxbb_mali_parent_names, 962 .num_parents = 2, 963 .flags = CLK_SET_RATE_NO_REPARENT, 964 }, 965 }; 966 967 static struct clk_regmap gxbb_cts_amclk_sel = { 968 .data = &(struct clk_regmap_mux_data){ 969 .offset = HHI_AUD_CLK_CNTL, 970 .mask = 0x3, 971 .shift = 9, 972 .table = (u32[]){ 1, 2, 3 }, 973 .flags = CLK_MUX_ROUND_CLOSEST, 974 }, 975 .hw.init = &(struct clk_init_data){ 976 .name = "cts_amclk_sel", 977 .ops = &clk_regmap_mux_ops, 978 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 979 .num_parents = 3, 980 }, 981 }; 982 983 static struct clk_regmap gxbb_cts_amclk_div = { 984 .data = &(struct clk_regmap_div_data) { 985 .offset = HHI_AUD_CLK_CNTL, 986 .shift = 0, 987 .width = 8, 988 .flags = CLK_DIVIDER_ROUND_CLOSEST, 989 }, 990 .hw.init = &(struct clk_init_data){ 991 .name = "cts_amclk_div", 992 .ops = &clk_regmap_divider_ops, 993 .parent_names = (const char *[]){ "cts_amclk_sel" }, 994 .num_parents = 1, 995 .flags = CLK_SET_RATE_PARENT, 996 }, 997 }; 998 999 static struct clk_regmap gxbb_cts_amclk = { 1000 .data = &(struct clk_regmap_gate_data){ 1001 .offset = HHI_AUD_CLK_CNTL, 1002 .bit_idx = 8, 1003 }, 1004 .hw.init = &(struct clk_init_data){ 1005 .name = "cts_amclk", 1006 .ops = &clk_regmap_gate_ops, 1007 .parent_names = (const char *[]){ "cts_amclk_div" }, 1008 .num_parents = 1, 1009 .flags = CLK_SET_RATE_PARENT, 1010 }, 1011 }; 1012 1013 static struct clk_regmap gxbb_cts_mclk_i958_sel = { 1014 .data = &(struct clk_regmap_mux_data){ 1015 .offset = HHI_AUD_CLK_CNTL2, 1016 .mask = 0x3, 1017 .shift = 25, 1018 .table = (u32[]){ 1, 2, 3 }, 1019 .flags = CLK_MUX_ROUND_CLOSEST, 1020 }, 1021 .hw.init = &(struct clk_init_data) { 1022 .name = "cts_mclk_i958_sel", 1023 .ops = &clk_regmap_mux_ops, 1024 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 1025 .num_parents = 3, 1026 }, 1027 }; 1028 1029 static struct clk_regmap gxbb_cts_mclk_i958_div = { 1030 .data = &(struct clk_regmap_div_data){ 1031 .offset = HHI_AUD_CLK_CNTL2, 1032 .shift = 16, 1033 .width = 8, 1034 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1035 }, 1036 .hw.init = &(struct clk_init_data) { 1037 .name = "cts_mclk_i958_div", 1038 .ops = &clk_regmap_divider_ops, 1039 .parent_names = (const char *[]){ "cts_mclk_i958_sel" }, 1040 .num_parents = 1, 1041 .flags = CLK_SET_RATE_PARENT, 1042 }, 1043 }; 1044 1045 static struct clk_regmap gxbb_cts_mclk_i958 = { 1046 .data = &(struct clk_regmap_gate_data){ 1047 .offset = HHI_AUD_CLK_CNTL2, 1048 .bit_idx = 24, 1049 }, 1050 .hw.init = &(struct clk_init_data){ 1051 .name = "cts_mclk_i958", 1052 .ops = &clk_regmap_gate_ops, 1053 .parent_names = (const char *[]){ "cts_mclk_i958_div" }, 1054 .num_parents = 1, 1055 .flags = CLK_SET_RATE_PARENT, 1056 }, 1057 }; 1058 1059 static struct clk_regmap gxbb_cts_i958 = { 1060 .data = &(struct clk_regmap_mux_data){ 1061 .offset = HHI_AUD_CLK_CNTL2, 1062 .mask = 0x1, 1063 .shift = 27, 1064 }, 1065 .hw.init = &(struct clk_init_data){ 1066 .name = "cts_i958", 1067 .ops = &clk_regmap_mux_ops, 1068 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" }, 1069 .num_parents = 2, 1070 /* 1071 *The parent is specific to origin of the audio data. Let the 1072 * consumer choose the appropriate parent 1073 */ 1074 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 1075 }, 1076 }; 1077 1078 static struct clk_regmap gxbb_32k_clk_div = { 1079 .data = &(struct clk_regmap_div_data){ 1080 .offset = HHI_32K_CLK_CNTL, 1081 .shift = 0, 1082 .width = 14, 1083 }, 1084 .hw.init = &(struct clk_init_data){ 1085 .name = "32k_clk_div", 1086 .ops = &clk_regmap_divider_ops, 1087 .parent_names = (const char *[]){ "32k_clk_sel" }, 1088 .num_parents = 1, 1089 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, 1090 }, 1091 }; 1092 1093 static struct clk_regmap gxbb_32k_clk = { 1094 .data = &(struct clk_regmap_gate_data){ 1095 .offset = HHI_32K_CLK_CNTL, 1096 .bit_idx = 15, 1097 }, 1098 .hw.init = &(struct clk_init_data){ 1099 .name = "32k_clk", 1100 .ops = &clk_regmap_gate_ops, 1101 .parent_names = (const char *[]){ "32k_clk_div" }, 1102 .num_parents = 1, 1103 .flags = CLK_SET_RATE_PARENT, 1104 }, 1105 }; 1106 1107 static const char * const gxbb_32k_clk_parent_names[] = { 1108 "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5" 1109 }; 1110 1111 static struct clk_regmap gxbb_32k_clk_sel = { 1112 .data = &(struct clk_regmap_mux_data){ 1113 .offset = HHI_32K_CLK_CNTL, 1114 .mask = 0x3, 1115 .shift = 16, 1116 }, 1117 .hw.init = &(struct clk_init_data){ 1118 .name = "32k_clk_sel", 1119 .ops = &clk_regmap_mux_ops, 1120 .parent_names = gxbb_32k_clk_parent_names, 1121 .num_parents = 4, 1122 .flags = CLK_SET_RATE_PARENT, 1123 }, 1124 }; 1125 1126 static const char * const gxbb_sd_emmc_clk0_parent_names[] = { 1127 "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", 1128 1129 /* 1130 * Following these parent clocks, we should also have had mpll2, mpll3 1131 * and gp0_pll but these clocks are too precious to be used here. All 1132 * the necessary rates for MMC and NAND operation can be acheived using 1133 * xtal or fclk_div clocks 1134 */ 1135 }; 1136 1137 /* SDIO clock */ 1138 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = { 1139 .data = &(struct clk_regmap_mux_data){ 1140 .offset = HHI_SD_EMMC_CLK_CNTL, 1141 .mask = 0x7, 1142 .shift = 9, 1143 }, 1144 .hw.init = &(struct clk_init_data) { 1145 .name = "sd_emmc_a_clk0_sel", 1146 .ops = &clk_regmap_mux_ops, 1147 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1148 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1149 .flags = CLK_SET_RATE_PARENT, 1150 }, 1151 }; 1152 1153 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = { 1154 .data = &(struct clk_regmap_div_data){ 1155 .offset = HHI_SD_EMMC_CLK_CNTL, 1156 .shift = 0, 1157 .width = 7, 1158 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1159 }, 1160 .hw.init = &(struct clk_init_data) { 1161 .name = "sd_emmc_a_clk0_div", 1162 .ops = &clk_regmap_divider_ops, 1163 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" }, 1164 .num_parents = 1, 1165 .flags = CLK_SET_RATE_PARENT, 1166 }, 1167 }; 1168 1169 static struct clk_regmap gxbb_sd_emmc_a_clk0 = { 1170 .data = &(struct clk_regmap_gate_data){ 1171 .offset = HHI_SD_EMMC_CLK_CNTL, 1172 .bit_idx = 7, 1173 }, 1174 .hw.init = &(struct clk_init_data){ 1175 .name = "sd_emmc_a_clk0", 1176 .ops = &clk_regmap_gate_ops, 1177 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" }, 1178 .num_parents = 1, 1179 .flags = CLK_SET_RATE_PARENT, 1180 }, 1181 }; 1182 1183 /* SDcard clock */ 1184 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = { 1185 .data = &(struct clk_regmap_mux_data){ 1186 .offset = HHI_SD_EMMC_CLK_CNTL, 1187 .mask = 0x7, 1188 .shift = 25, 1189 }, 1190 .hw.init = &(struct clk_init_data) { 1191 .name = "sd_emmc_b_clk0_sel", 1192 .ops = &clk_regmap_mux_ops, 1193 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1194 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1195 .flags = CLK_SET_RATE_PARENT, 1196 }, 1197 }; 1198 1199 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = { 1200 .data = &(struct clk_regmap_div_data){ 1201 .offset = HHI_SD_EMMC_CLK_CNTL, 1202 .shift = 16, 1203 .width = 7, 1204 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1205 }, 1206 .hw.init = &(struct clk_init_data) { 1207 .name = "sd_emmc_b_clk0_div", 1208 .ops = &clk_regmap_divider_ops, 1209 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, 1210 .num_parents = 1, 1211 .flags = CLK_SET_RATE_PARENT, 1212 }, 1213 }; 1214 1215 static struct clk_regmap gxbb_sd_emmc_b_clk0 = { 1216 .data = &(struct clk_regmap_gate_data){ 1217 .offset = HHI_SD_EMMC_CLK_CNTL, 1218 .bit_idx = 23, 1219 }, 1220 .hw.init = &(struct clk_init_data){ 1221 .name = "sd_emmc_b_clk0", 1222 .ops = &clk_regmap_gate_ops, 1223 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, 1224 .num_parents = 1, 1225 .flags = CLK_SET_RATE_PARENT, 1226 }, 1227 }; 1228 1229 /* EMMC/NAND clock */ 1230 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = { 1231 .data = &(struct clk_regmap_mux_data){ 1232 .offset = HHI_NAND_CLK_CNTL, 1233 .mask = 0x7, 1234 .shift = 9, 1235 }, 1236 .hw.init = &(struct clk_init_data) { 1237 .name = "sd_emmc_c_clk0_sel", 1238 .ops = &clk_regmap_mux_ops, 1239 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1240 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1241 .flags = CLK_SET_RATE_PARENT, 1242 }, 1243 }; 1244 1245 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = { 1246 .data = &(struct clk_regmap_div_data){ 1247 .offset = HHI_NAND_CLK_CNTL, 1248 .shift = 0, 1249 .width = 7, 1250 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1251 }, 1252 .hw.init = &(struct clk_init_data) { 1253 .name = "sd_emmc_c_clk0_div", 1254 .ops = &clk_regmap_divider_ops, 1255 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, 1256 .num_parents = 1, 1257 .flags = CLK_SET_RATE_PARENT, 1258 }, 1259 }; 1260 1261 static struct clk_regmap gxbb_sd_emmc_c_clk0 = { 1262 .data = &(struct clk_regmap_gate_data){ 1263 .offset = HHI_NAND_CLK_CNTL, 1264 .bit_idx = 7, 1265 }, 1266 .hw.init = &(struct clk_init_data){ 1267 .name = "sd_emmc_c_clk0", 1268 .ops = &clk_regmap_gate_ops, 1269 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, 1270 .num_parents = 1, 1271 .flags = CLK_SET_RATE_PARENT, 1272 }, 1273 }; 1274 1275 /* VPU Clock */ 1276 1277 static const char * const gxbb_vpu_parent_names[] = { 1278 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1279 }; 1280 1281 static struct clk_regmap gxbb_vpu_0_sel = { 1282 .data = &(struct clk_regmap_mux_data){ 1283 .offset = HHI_VPU_CLK_CNTL, 1284 .mask = 0x3, 1285 .shift = 9, 1286 }, 1287 .hw.init = &(struct clk_init_data){ 1288 .name = "vpu_0_sel", 1289 .ops = &clk_regmap_mux_ops, 1290 /* 1291 * bits 9:10 selects from 4 possible parents: 1292 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1293 */ 1294 .parent_names = gxbb_vpu_parent_names, 1295 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names), 1296 .flags = CLK_SET_RATE_NO_REPARENT, 1297 }, 1298 }; 1299 1300 static struct clk_regmap gxbb_vpu_0_div = { 1301 .data = &(struct clk_regmap_div_data){ 1302 .offset = HHI_VPU_CLK_CNTL, 1303 .shift = 0, 1304 .width = 7, 1305 }, 1306 .hw.init = &(struct clk_init_data){ 1307 .name = "vpu_0_div", 1308 .ops = &clk_regmap_divider_ops, 1309 .parent_names = (const char *[]){ "vpu_0_sel" }, 1310 .num_parents = 1, 1311 .flags = CLK_SET_RATE_PARENT, 1312 }, 1313 }; 1314 1315 static struct clk_regmap gxbb_vpu_0 = { 1316 .data = &(struct clk_regmap_gate_data){ 1317 .offset = HHI_VPU_CLK_CNTL, 1318 .bit_idx = 8, 1319 }, 1320 .hw.init = &(struct clk_init_data) { 1321 .name = "vpu_0", 1322 .ops = &clk_regmap_gate_ops, 1323 .parent_names = (const char *[]){ "vpu_0_div" }, 1324 .num_parents = 1, 1325 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1326 }, 1327 }; 1328 1329 static struct clk_regmap gxbb_vpu_1_sel = { 1330 .data = &(struct clk_regmap_mux_data){ 1331 .offset = HHI_VPU_CLK_CNTL, 1332 .mask = 0x3, 1333 .shift = 25, 1334 }, 1335 .hw.init = &(struct clk_init_data){ 1336 .name = "vpu_1_sel", 1337 .ops = &clk_regmap_mux_ops, 1338 /* 1339 * bits 25:26 selects from 4 possible parents: 1340 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1341 */ 1342 .parent_names = gxbb_vpu_parent_names, 1343 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names), 1344 .flags = CLK_SET_RATE_NO_REPARENT, 1345 }, 1346 }; 1347 1348 static struct clk_regmap gxbb_vpu_1_div = { 1349 .data = &(struct clk_regmap_div_data){ 1350 .offset = HHI_VPU_CLK_CNTL, 1351 .shift = 16, 1352 .width = 7, 1353 }, 1354 .hw.init = &(struct clk_init_data){ 1355 .name = "vpu_1_div", 1356 .ops = &clk_regmap_divider_ops, 1357 .parent_names = (const char *[]){ "vpu_1_sel" }, 1358 .num_parents = 1, 1359 .flags = CLK_SET_RATE_PARENT, 1360 }, 1361 }; 1362 1363 static struct clk_regmap gxbb_vpu_1 = { 1364 .data = &(struct clk_regmap_gate_data){ 1365 .offset = HHI_VPU_CLK_CNTL, 1366 .bit_idx = 24, 1367 }, 1368 .hw.init = &(struct clk_init_data) { 1369 .name = "vpu_1", 1370 .ops = &clk_regmap_gate_ops, 1371 .parent_names = (const char *[]){ "vpu_1_div" }, 1372 .num_parents = 1, 1373 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1374 }, 1375 }; 1376 1377 static struct clk_regmap gxbb_vpu = { 1378 .data = &(struct clk_regmap_mux_data){ 1379 .offset = HHI_VPU_CLK_CNTL, 1380 .mask = 1, 1381 .shift = 31, 1382 }, 1383 .hw.init = &(struct clk_init_data){ 1384 .name = "vpu", 1385 .ops = &clk_regmap_mux_ops, 1386 /* 1387 * bit 31 selects from 2 possible parents: 1388 * vpu_0 or vpu_1 1389 */ 1390 .parent_names = (const char *[]){ "vpu_0", "vpu_1" }, 1391 .num_parents = 2, 1392 .flags = CLK_SET_RATE_NO_REPARENT, 1393 }, 1394 }; 1395 1396 /* VAPB Clock */ 1397 1398 static const char * const gxbb_vapb_parent_names[] = { 1399 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1400 }; 1401 1402 static struct clk_regmap gxbb_vapb_0_sel = { 1403 .data = &(struct clk_regmap_mux_data){ 1404 .offset = HHI_VAPBCLK_CNTL, 1405 .mask = 0x3, 1406 .shift = 9, 1407 }, 1408 .hw.init = &(struct clk_init_data){ 1409 .name = "vapb_0_sel", 1410 .ops = &clk_regmap_mux_ops, 1411 /* 1412 * bits 9:10 selects from 4 possible parents: 1413 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1414 */ 1415 .parent_names = gxbb_vapb_parent_names, 1416 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names), 1417 .flags = CLK_SET_RATE_NO_REPARENT, 1418 }, 1419 }; 1420 1421 static struct clk_regmap gxbb_vapb_0_div = { 1422 .data = &(struct clk_regmap_div_data){ 1423 .offset = HHI_VAPBCLK_CNTL, 1424 .shift = 0, 1425 .width = 7, 1426 }, 1427 .hw.init = &(struct clk_init_data){ 1428 .name = "vapb_0_div", 1429 .ops = &clk_regmap_divider_ops, 1430 .parent_names = (const char *[]){ "vapb_0_sel" }, 1431 .num_parents = 1, 1432 .flags = CLK_SET_RATE_PARENT, 1433 }, 1434 }; 1435 1436 static struct clk_regmap gxbb_vapb_0 = { 1437 .data = &(struct clk_regmap_gate_data){ 1438 .offset = HHI_VAPBCLK_CNTL, 1439 .bit_idx = 8, 1440 }, 1441 .hw.init = &(struct clk_init_data) { 1442 .name = "vapb_0", 1443 .ops = &clk_regmap_gate_ops, 1444 .parent_names = (const char *[]){ "vapb_0_div" }, 1445 .num_parents = 1, 1446 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1447 }, 1448 }; 1449 1450 static struct clk_regmap gxbb_vapb_1_sel = { 1451 .data = &(struct clk_regmap_mux_data){ 1452 .offset = HHI_VAPBCLK_CNTL, 1453 .mask = 0x3, 1454 .shift = 25, 1455 }, 1456 .hw.init = &(struct clk_init_data){ 1457 .name = "vapb_1_sel", 1458 .ops = &clk_regmap_mux_ops, 1459 /* 1460 * bits 25:26 selects from 4 possible parents: 1461 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1462 */ 1463 .parent_names = gxbb_vapb_parent_names, 1464 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names), 1465 .flags = CLK_SET_RATE_NO_REPARENT, 1466 }, 1467 }; 1468 1469 static struct clk_regmap gxbb_vapb_1_div = { 1470 .data = &(struct clk_regmap_div_data){ 1471 .offset = HHI_VAPBCLK_CNTL, 1472 .shift = 16, 1473 .width = 7, 1474 }, 1475 .hw.init = &(struct clk_init_data){ 1476 .name = "vapb_1_div", 1477 .ops = &clk_regmap_divider_ops, 1478 .parent_names = (const char *[]){ "vapb_1_sel" }, 1479 .num_parents = 1, 1480 .flags = CLK_SET_RATE_PARENT, 1481 }, 1482 }; 1483 1484 static struct clk_regmap gxbb_vapb_1 = { 1485 .data = &(struct clk_regmap_gate_data){ 1486 .offset = HHI_VAPBCLK_CNTL, 1487 .bit_idx = 24, 1488 }, 1489 .hw.init = &(struct clk_init_data) { 1490 .name = "vapb_1", 1491 .ops = &clk_regmap_gate_ops, 1492 .parent_names = (const char *[]){ "vapb_1_div" }, 1493 .num_parents = 1, 1494 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1495 }, 1496 }; 1497 1498 static struct clk_regmap gxbb_vapb_sel = { 1499 .data = &(struct clk_regmap_mux_data){ 1500 .offset = HHI_VAPBCLK_CNTL, 1501 .mask = 1, 1502 .shift = 31, 1503 }, 1504 .hw.init = &(struct clk_init_data){ 1505 .name = "vapb_sel", 1506 .ops = &clk_regmap_mux_ops, 1507 /* 1508 * bit 31 selects from 2 possible parents: 1509 * vapb_0 or vapb_1 1510 */ 1511 .parent_names = (const char *[]){ "vapb_0", "vapb_1" }, 1512 .num_parents = 2, 1513 .flags = CLK_SET_RATE_NO_REPARENT, 1514 }, 1515 }; 1516 1517 static struct clk_regmap gxbb_vapb = { 1518 .data = &(struct clk_regmap_gate_data){ 1519 .offset = HHI_VAPBCLK_CNTL, 1520 .bit_idx = 30, 1521 }, 1522 .hw.init = &(struct clk_init_data) { 1523 .name = "vapb", 1524 .ops = &clk_regmap_gate_ops, 1525 .parent_names = (const char *[]){ "vapb_sel" }, 1526 .num_parents = 1, 1527 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1528 }, 1529 }; 1530 1531 /* VDEC clocks */ 1532 1533 static const char * const gxbb_vdec_parent_names[] = { 1534 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1535 }; 1536 1537 static struct clk_regmap gxbb_vdec_1_sel = { 1538 .data = &(struct clk_regmap_mux_data){ 1539 .offset = HHI_VDEC_CLK_CNTL, 1540 .mask = 0x3, 1541 .shift = 9, 1542 .flags = CLK_MUX_ROUND_CLOSEST, 1543 }, 1544 .hw.init = &(struct clk_init_data){ 1545 .name = "vdec_1_sel", 1546 .ops = &clk_regmap_mux_ops, 1547 .parent_names = gxbb_vdec_parent_names, 1548 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names), 1549 .flags = CLK_SET_RATE_PARENT, 1550 }, 1551 }; 1552 1553 static struct clk_regmap gxbb_vdec_1_div = { 1554 .data = &(struct clk_regmap_div_data){ 1555 .offset = HHI_VDEC_CLK_CNTL, 1556 .shift = 0, 1557 .width = 7, 1558 }, 1559 .hw.init = &(struct clk_init_data){ 1560 .name = "vdec_1_div", 1561 .ops = &clk_regmap_divider_ops, 1562 .parent_names = (const char *[]){ "vdec_1_sel" }, 1563 .num_parents = 1, 1564 .flags = CLK_SET_RATE_PARENT, 1565 }, 1566 }; 1567 1568 static struct clk_regmap gxbb_vdec_1 = { 1569 .data = &(struct clk_regmap_gate_data){ 1570 .offset = HHI_VDEC_CLK_CNTL, 1571 .bit_idx = 8, 1572 }, 1573 .hw.init = &(struct clk_init_data) { 1574 .name = "vdec_1", 1575 .ops = &clk_regmap_gate_ops, 1576 .parent_names = (const char *[]){ "vdec_1_div" }, 1577 .num_parents = 1, 1578 .flags = CLK_SET_RATE_PARENT, 1579 }, 1580 }; 1581 1582 static struct clk_regmap gxbb_vdec_hevc_sel = { 1583 .data = &(struct clk_regmap_mux_data){ 1584 .offset = HHI_VDEC2_CLK_CNTL, 1585 .mask = 0x3, 1586 .shift = 25, 1587 .flags = CLK_MUX_ROUND_CLOSEST, 1588 }, 1589 .hw.init = &(struct clk_init_data){ 1590 .name = "vdec_hevc_sel", 1591 .ops = &clk_regmap_mux_ops, 1592 .parent_names = gxbb_vdec_parent_names, 1593 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names), 1594 .flags = CLK_SET_RATE_PARENT, 1595 }, 1596 }; 1597 1598 static struct clk_regmap gxbb_vdec_hevc_div = { 1599 .data = &(struct clk_regmap_div_data){ 1600 .offset = HHI_VDEC2_CLK_CNTL, 1601 .shift = 16, 1602 .width = 7, 1603 }, 1604 .hw.init = &(struct clk_init_data){ 1605 .name = "vdec_hevc_div", 1606 .ops = &clk_regmap_divider_ops, 1607 .parent_names = (const char *[]){ "vdec_hevc_sel" }, 1608 .num_parents = 1, 1609 .flags = CLK_SET_RATE_PARENT, 1610 }, 1611 }; 1612 1613 static struct clk_regmap gxbb_vdec_hevc = { 1614 .data = &(struct clk_regmap_gate_data){ 1615 .offset = HHI_VDEC2_CLK_CNTL, 1616 .bit_idx = 24, 1617 }, 1618 .hw.init = &(struct clk_init_data) { 1619 .name = "vdec_hevc", 1620 .ops = &clk_regmap_gate_ops, 1621 .parent_names = (const char *[]){ "vdec_hevc_div" }, 1622 .num_parents = 1, 1623 .flags = CLK_SET_RATE_PARENT, 1624 }, 1625 }; 1626 1627 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, 1628 9, 10, 11, 13, 14, }; 1629 static const char * const gen_clk_parent_names[] = { 1630 "xtal", "vdec_1", "vdec_hevc", "mpll0", "mpll1", "mpll2", 1631 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll", 1632 }; 1633 1634 static struct clk_regmap gxbb_gen_clk_sel = { 1635 .data = &(struct clk_regmap_mux_data){ 1636 .offset = HHI_GEN_CLK_CNTL, 1637 .mask = 0xf, 1638 .shift = 12, 1639 .table = mux_table_gen_clk, 1640 }, 1641 .hw.init = &(struct clk_init_data){ 1642 .name = "gen_clk_sel", 1643 .ops = &clk_regmap_mux_ops, 1644 /* 1645 * bits 15:12 selects from 14 possible parents: 1646 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt], 1647 * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4, 1648 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 1649 */ 1650 .parent_names = gen_clk_parent_names, 1651 .num_parents = ARRAY_SIZE(gen_clk_parent_names), 1652 }, 1653 }; 1654 1655 static struct clk_regmap gxbb_gen_clk_div = { 1656 .data = &(struct clk_regmap_div_data){ 1657 .offset = HHI_GEN_CLK_CNTL, 1658 .shift = 0, 1659 .width = 11, 1660 }, 1661 .hw.init = &(struct clk_init_data){ 1662 .name = "gen_clk_div", 1663 .ops = &clk_regmap_divider_ops, 1664 .parent_names = (const char *[]){ "gen_clk_sel" }, 1665 .num_parents = 1, 1666 .flags = CLK_SET_RATE_PARENT, 1667 }, 1668 }; 1669 1670 static struct clk_regmap gxbb_gen_clk = { 1671 .data = &(struct clk_regmap_gate_data){ 1672 .offset = HHI_GEN_CLK_CNTL, 1673 .bit_idx = 7, 1674 }, 1675 .hw.init = &(struct clk_init_data){ 1676 .name = "gen_clk", 1677 .ops = &clk_regmap_gate_ops, 1678 .parent_names = (const char *[]){ "gen_clk_div" }, 1679 .num_parents = 1, 1680 .flags = CLK_SET_RATE_PARENT, 1681 }, 1682 }; 1683 1684 /* Everything Else (EE) domain gates */ 1685 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 1686 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); 1687 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5); 1688 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6); 1689 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7); 1690 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8); 1691 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9); 1692 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10); 1693 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11); 1694 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12); 1695 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13); 1696 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14); 1697 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15); 1698 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16); 1699 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17); 1700 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18); 1701 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19); 1702 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); 1703 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24); 1704 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25); 1705 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26); 1706 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30); 1707 1708 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2); 1709 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3); 1710 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4); 1711 static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6); 1712 static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7); 1713 static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8); 1714 static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9); 1715 static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10); 1716 static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11); 1717 static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12); 1718 static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13); 1719 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14); 1720 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15); 1721 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16); 1722 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20); 1723 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21); 1724 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22); 1725 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23); 1726 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24); 1727 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25); 1728 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26); 1729 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28); 1730 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29); 1731 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30); 1732 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31); 1733 1734 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1); 1735 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 1736 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); 1737 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4); 1738 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); 1739 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); 1740 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); 1741 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12); 1742 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15); 1743 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22); 1744 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); 1745 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 1746 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); 1747 1748 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1); 1749 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2); 1750 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3); 1751 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4); 1752 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8); 1753 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9); 1754 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10); 1755 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14); 1756 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16); 1757 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20); 1758 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21); 1759 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22); 1760 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24); 1761 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25); 1762 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26); 1763 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31); 1764 1765 /* Always On (AO) domain gates */ 1766 1767 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0); 1768 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1); 1769 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2); 1770 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3); 1771 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4); 1772 1773 /* Array of all clocks provided by this provider */ 1774 1775 static struct clk_hw_onecell_data gxbb_hw_onecell_data = { 1776 .hws = { 1777 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 1778 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 1779 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 1780 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 1781 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 1782 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 1783 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 1784 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 1785 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 1786 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 1787 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 1788 [CLKID_CLK81] = &gxbb_clk81.hw, 1789 [CLKID_MPLL0] = &gxbb_mpll0.hw, 1790 [CLKID_MPLL1] = &gxbb_mpll1.hw, 1791 [CLKID_MPLL2] = &gxbb_mpll2.hw, 1792 [CLKID_DDR] = &gxbb_ddr.hw, 1793 [CLKID_DOS] = &gxbb_dos.hw, 1794 [CLKID_ISA] = &gxbb_isa.hw, 1795 [CLKID_PL301] = &gxbb_pl301.hw, 1796 [CLKID_PERIPHS] = &gxbb_periphs.hw, 1797 [CLKID_SPICC] = &gxbb_spicc.hw, 1798 [CLKID_I2C] = &gxbb_i2c.hw, 1799 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 1800 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 1801 [CLKID_RNG0] = &gxbb_rng0.hw, 1802 [CLKID_UART0] = &gxbb_uart0.hw, 1803 [CLKID_SDHC] = &gxbb_sdhc.hw, 1804 [CLKID_STREAM] = &gxbb_stream.hw, 1805 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 1806 [CLKID_SDIO] = &gxbb_sdio.hw, 1807 [CLKID_ABUF] = &gxbb_abuf.hw, 1808 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 1809 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 1810 [CLKID_SPI] = &gxbb_spi.hw, 1811 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 1812 [CLKID_ETH] = &gxbb_eth.hw, 1813 [CLKID_DEMUX] = &gxbb_demux.hw, 1814 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 1815 [CLKID_IEC958] = &gxbb_iec958.hw, 1816 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 1817 [CLKID_AMCLK] = &gxbb_amclk.hw, 1818 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 1819 [CLKID_MIXER] = &gxbb_mixer.hw, 1820 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 1821 [CLKID_ADC] = &gxbb_adc.hw, 1822 [CLKID_BLKMV] = &gxbb_blkmv.hw, 1823 [CLKID_AIU] = &gxbb_aiu.hw, 1824 [CLKID_UART1] = &gxbb_uart1.hw, 1825 [CLKID_G2D] = &gxbb_g2d.hw, 1826 [CLKID_USB0] = &gxbb_usb0.hw, 1827 [CLKID_USB1] = &gxbb_usb1.hw, 1828 [CLKID_RESET] = &gxbb_reset.hw, 1829 [CLKID_NAND] = &gxbb_nand.hw, 1830 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 1831 [CLKID_USB] = &gxbb_usb.hw, 1832 [CLKID_VDIN1] = &gxbb_vdin1.hw, 1833 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 1834 [CLKID_EFUSE] = &gxbb_efuse.hw, 1835 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 1836 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 1837 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 1838 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 1839 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 1840 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 1841 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 1842 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 1843 [CLKID_DVIN] = &gxbb_dvin.hw, 1844 [CLKID_UART2] = &gxbb_uart2.hw, 1845 [CLKID_SANA] = &gxbb_sana.hw, 1846 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 1847 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 1848 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 1849 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 1850 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 1851 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 1852 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 1853 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 1854 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 1855 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 1856 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 1857 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 1858 [CLKID_ENC480P] = &gxbb_enc480p.hw, 1859 [CLKID_RNG1] = &gxbb_rng1.hw, 1860 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 1861 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 1862 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 1863 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 1864 [CLKID_EDP] = &gxbb_edp.hw, 1865 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 1866 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 1867 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 1868 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 1869 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 1870 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 1871 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 1872 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 1873 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 1874 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 1875 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 1876 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 1877 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 1878 [CLKID_MALI_0] = &gxbb_mali_0.hw, 1879 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 1880 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 1881 [CLKID_MALI_1] = &gxbb_mali_1.hw, 1882 [CLKID_MALI] = &gxbb_mali.hw, 1883 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 1884 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 1885 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 1886 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 1887 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 1888 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 1889 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 1890 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 1891 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 1892 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 1893 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 1894 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 1895 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 1896 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 1897 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 1898 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 1899 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 1900 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 1901 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 1902 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 1903 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 1904 [CLKID_VPU_0] = &gxbb_vpu_0.hw, 1905 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 1906 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 1907 [CLKID_VPU_1] = &gxbb_vpu_1.hw, 1908 [CLKID_VPU] = &gxbb_vpu.hw, 1909 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 1910 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 1911 [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 1912 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 1913 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 1914 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 1915 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 1916 [CLKID_VAPB] = &gxbb_vapb.hw, 1917 [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw, 1918 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 1919 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 1920 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 1921 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 1922 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 1923 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 1924 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 1925 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 1926 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 1927 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 1928 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 1929 [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 1930 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 1931 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 1932 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 1933 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 1934 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 1935 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 1936 [NR_CLKS] = NULL, 1937 }, 1938 .num = NR_CLKS, 1939 }; 1940 1941 static struct clk_hw_onecell_data gxl_hw_onecell_data = { 1942 .hws = { 1943 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 1944 [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw, 1945 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 1946 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 1947 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 1948 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 1949 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 1950 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 1951 [CLKID_GP0_PLL] = &gxl_gp0_pll.hw, 1952 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 1953 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 1954 [CLKID_CLK81] = &gxbb_clk81.hw, 1955 [CLKID_MPLL0] = &gxbb_mpll0.hw, 1956 [CLKID_MPLL1] = &gxbb_mpll1.hw, 1957 [CLKID_MPLL2] = &gxbb_mpll2.hw, 1958 [CLKID_DDR] = &gxbb_ddr.hw, 1959 [CLKID_DOS] = &gxbb_dos.hw, 1960 [CLKID_ISA] = &gxbb_isa.hw, 1961 [CLKID_PL301] = &gxbb_pl301.hw, 1962 [CLKID_PERIPHS] = &gxbb_periphs.hw, 1963 [CLKID_SPICC] = &gxbb_spicc.hw, 1964 [CLKID_I2C] = &gxbb_i2c.hw, 1965 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 1966 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 1967 [CLKID_RNG0] = &gxbb_rng0.hw, 1968 [CLKID_UART0] = &gxbb_uart0.hw, 1969 [CLKID_SDHC] = &gxbb_sdhc.hw, 1970 [CLKID_STREAM] = &gxbb_stream.hw, 1971 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 1972 [CLKID_SDIO] = &gxbb_sdio.hw, 1973 [CLKID_ABUF] = &gxbb_abuf.hw, 1974 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 1975 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 1976 [CLKID_SPI] = &gxbb_spi.hw, 1977 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 1978 [CLKID_ETH] = &gxbb_eth.hw, 1979 [CLKID_DEMUX] = &gxbb_demux.hw, 1980 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 1981 [CLKID_IEC958] = &gxbb_iec958.hw, 1982 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 1983 [CLKID_AMCLK] = &gxbb_amclk.hw, 1984 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 1985 [CLKID_MIXER] = &gxbb_mixer.hw, 1986 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 1987 [CLKID_ADC] = &gxbb_adc.hw, 1988 [CLKID_BLKMV] = &gxbb_blkmv.hw, 1989 [CLKID_AIU] = &gxbb_aiu.hw, 1990 [CLKID_UART1] = &gxbb_uart1.hw, 1991 [CLKID_G2D] = &gxbb_g2d.hw, 1992 [CLKID_USB0] = &gxbb_usb0.hw, 1993 [CLKID_USB1] = &gxbb_usb1.hw, 1994 [CLKID_RESET] = &gxbb_reset.hw, 1995 [CLKID_NAND] = &gxbb_nand.hw, 1996 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 1997 [CLKID_USB] = &gxbb_usb.hw, 1998 [CLKID_VDIN1] = &gxbb_vdin1.hw, 1999 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 2000 [CLKID_EFUSE] = &gxbb_efuse.hw, 2001 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 2002 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 2003 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 2004 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 2005 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 2006 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 2007 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 2008 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 2009 [CLKID_DVIN] = &gxbb_dvin.hw, 2010 [CLKID_UART2] = &gxbb_uart2.hw, 2011 [CLKID_SANA] = &gxbb_sana.hw, 2012 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 2013 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 2014 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 2015 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 2016 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 2017 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 2018 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 2019 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 2020 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 2021 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 2022 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 2023 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 2024 [CLKID_ENC480P] = &gxbb_enc480p.hw, 2025 [CLKID_RNG1] = &gxbb_rng1.hw, 2026 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 2027 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 2028 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 2029 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 2030 [CLKID_EDP] = &gxbb_edp.hw, 2031 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 2032 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 2033 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 2034 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 2035 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 2036 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 2037 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 2038 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 2039 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 2040 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 2041 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 2042 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 2043 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 2044 [CLKID_MALI_0] = &gxbb_mali_0.hw, 2045 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 2046 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 2047 [CLKID_MALI_1] = &gxbb_mali_1.hw, 2048 [CLKID_MALI] = &gxbb_mali.hw, 2049 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 2050 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 2051 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 2052 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 2053 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 2054 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 2055 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 2056 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 2057 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 2058 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 2059 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 2060 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 2061 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 2062 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 2063 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 2064 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 2065 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 2066 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 2067 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 2068 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 2069 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 2070 [CLKID_VPU_0] = &gxbb_vpu_0.hw, 2071 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 2072 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 2073 [CLKID_VPU_1] = &gxbb_vpu_1.hw, 2074 [CLKID_VPU] = &gxbb_vpu.hw, 2075 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 2076 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 2077 [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 2078 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 2079 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 2080 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 2081 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 2082 [CLKID_VAPB] = &gxbb_vapb.hw, 2083 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 2084 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 2085 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 2086 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 2087 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 2088 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 2089 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 2090 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 2091 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 2092 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 2093 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 2094 [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 2095 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 2096 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 2097 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 2098 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 2099 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 2100 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 2101 [NR_CLKS] = NULL, 2102 }, 2103 .num = NR_CLKS, 2104 }; 2105 2106 static struct clk_regmap *const gxbb_clk_regmaps[] = { 2107 &gxbb_gp0_pll, 2108 &gxbb_hdmi_pll, 2109 }; 2110 2111 static struct clk_regmap *const gxl_clk_regmaps[] = { 2112 &gxl_gp0_pll, 2113 &gxl_hdmi_pll, 2114 }; 2115 2116 static struct clk_regmap *const gx_clk_regmaps[] = { 2117 &gxbb_clk81, 2118 &gxbb_ddr, 2119 &gxbb_dos, 2120 &gxbb_isa, 2121 &gxbb_pl301, 2122 &gxbb_periphs, 2123 &gxbb_spicc, 2124 &gxbb_i2c, 2125 &gxbb_sar_adc, 2126 &gxbb_smart_card, 2127 &gxbb_rng0, 2128 &gxbb_uart0, 2129 &gxbb_sdhc, 2130 &gxbb_stream, 2131 &gxbb_async_fifo, 2132 &gxbb_sdio, 2133 &gxbb_abuf, 2134 &gxbb_hiu_iface, 2135 &gxbb_assist_misc, 2136 &gxbb_spi, 2137 &gxbb_i2s_spdif, 2138 &gxbb_eth, 2139 &gxbb_demux, 2140 &gxbb_aiu_glue, 2141 &gxbb_iec958, 2142 &gxbb_i2s_out, 2143 &gxbb_amclk, 2144 &gxbb_aififo2, 2145 &gxbb_mixer, 2146 &gxbb_mixer_iface, 2147 &gxbb_adc, 2148 &gxbb_blkmv, 2149 &gxbb_aiu, 2150 &gxbb_uart1, 2151 &gxbb_g2d, 2152 &gxbb_usb0, 2153 &gxbb_usb1, 2154 &gxbb_reset, 2155 &gxbb_nand, 2156 &gxbb_dos_parser, 2157 &gxbb_usb, 2158 &gxbb_vdin1, 2159 &gxbb_ahb_arb0, 2160 &gxbb_efuse, 2161 &gxbb_boot_rom, 2162 &gxbb_ahb_data_bus, 2163 &gxbb_ahb_ctrl_bus, 2164 &gxbb_hdmi_intr_sync, 2165 &gxbb_hdmi_pclk, 2166 &gxbb_usb1_ddr_bridge, 2167 &gxbb_usb0_ddr_bridge, 2168 &gxbb_mmc_pclk, 2169 &gxbb_dvin, 2170 &gxbb_uart2, 2171 &gxbb_sana, 2172 &gxbb_vpu_intr, 2173 &gxbb_sec_ahb_ahb3_bridge, 2174 &gxbb_clk81_a53, 2175 &gxbb_vclk2_venci0, 2176 &gxbb_vclk2_venci1, 2177 &gxbb_vclk2_vencp0, 2178 &gxbb_vclk2_vencp1, 2179 &gxbb_gclk_venci_int0, 2180 &gxbb_gclk_vencp_int, 2181 &gxbb_dac_clk, 2182 &gxbb_aoclk_gate, 2183 &gxbb_iec958_gate, 2184 &gxbb_enc480p, 2185 &gxbb_rng1, 2186 &gxbb_gclk_venci_int1, 2187 &gxbb_vclk2_venclmcc, 2188 &gxbb_vclk2_vencl, 2189 &gxbb_vclk_other, 2190 &gxbb_edp, 2191 &gxbb_ao_media_cpu, 2192 &gxbb_ao_ahb_sram, 2193 &gxbb_ao_ahb_bus, 2194 &gxbb_ao_iface, 2195 &gxbb_ao_i2c, 2196 &gxbb_emmc_a, 2197 &gxbb_emmc_b, 2198 &gxbb_emmc_c, 2199 &gxbb_sar_adc_clk, 2200 &gxbb_mali_0, 2201 &gxbb_mali_1, 2202 &gxbb_cts_amclk, 2203 &gxbb_cts_mclk_i958, 2204 &gxbb_32k_clk, 2205 &gxbb_sd_emmc_a_clk0, 2206 &gxbb_sd_emmc_b_clk0, 2207 &gxbb_sd_emmc_c_clk0, 2208 &gxbb_vpu_0, 2209 &gxbb_vpu_1, 2210 &gxbb_vapb_0, 2211 &gxbb_vapb_1, 2212 &gxbb_vapb, 2213 &gxbb_mpeg_clk_div, 2214 &gxbb_sar_adc_clk_div, 2215 &gxbb_mali_0_div, 2216 &gxbb_mali_1_div, 2217 &gxbb_cts_mclk_i958_div, 2218 &gxbb_32k_clk_div, 2219 &gxbb_sd_emmc_a_clk0_div, 2220 &gxbb_sd_emmc_b_clk0_div, 2221 &gxbb_sd_emmc_c_clk0_div, 2222 &gxbb_vpu_0_div, 2223 &gxbb_vpu_1_div, 2224 &gxbb_vapb_0_div, 2225 &gxbb_vapb_1_div, 2226 &gxbb_mpeg_clk_sel, 2227 &gxbb_sar_adc_clk_sel, 2228 &gxbb_mali_0_sel, 2229 &gxbb_mali_1_sel, 2230 &gxbb_mali, 2231 &gxbb_cts_amclk_sel, 2232 &gxbb_cts_mclk_i958_sel, 2233 &gxbb_cts_i958, 2234 &gxbb_32k_clk_sel, 2235 &gxbb_sd_emmc_a_clk0_sel, 2236 &gxbb_sd_emmc_b_clk0_sel, 2237 &gxbb_sd_emmc_c_clk0_sel, 2238 &gxbb_vpu_0_sel, 2239 &gxbb_vpu_1_sel, 2240 &gxbb_vpu, 2241 &gxbb_vapb_0_sel, 2242 &gxbb_vapb_1_sel, 2243 &gxbb_vapb_sel, 2244 &gxbb_mpll0, 2245 &gxbb_mpll1, 2246 &gxbb_mpll2, 2247 &gxbb_mpll0_div, 2248 &gxbb_mpll1_div, 2249 &gxbb_mpll2_div, 2250 &gxbb_cts_amclk_div, 2251 &gxbb_fixed_pll, 2252 &gxbb_sys_pll, 2253 &gxbb_mpll_prediv, 2254 &gxbb_fclk_div2, 2255 &gxbb_fclk_div3, 2256 &gxbb_fclk_div4, 2257 &gxbb_fclk_div5, 2258 &gxbb_fclk_div7, 2259 &gxbb_vdec_1_sel, 2260 &gxbb_vdec_1_div, 2261 &gxbb_vdec_1, 2262 &gxbb_vdec_hevc_sel, 2263 &gxbb_vdec_hevc_div, 2264 &gxbb_vdec_hevc, 2265 &gxbb_gen_clk_sel, 2266 &gxbb_gen_clk_div, 2267 &gxbb_gen_clk, 2268 }; 2269 2270 struct clkc_data { 2271 struct clk_regmap *const *regmap_clks; 2272 unsigned int regmap_clks_count; 2273 struct clk_hw_onecell_data *hw_onecell_data; 2274 }; 2275 2276 static const struct clkc_data gxbb_clkc_data = { 2277 .regmap_clks = gxbb_clk_regmaps, 2278 .regmap_clks_count = ARRAY_SIZE(gxbb_clk_regmaps), 2279 .hw_onecell_data = &gxbb_hw_onecell_data, 2280 }; 2281 2282 static const struct clkc_data gxl_clkc_data = { 2283 .regmap_clks = gxl_clk_regmaps, 2284 .regmap_clks_count = ARRAY_SIZE(gxl_clk_regmaps), 2285 .hw_onecell_data = &gxl_hw_onecell_data, 2286 }; 2287 2288 static const struct of_device_id clkc_match_table[] = { 2289 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data }, 2290 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data }, 2291 {}, 2292 }; 2293 2294 static int gxbb_clkc_probe(struct platform_device *pdev) 2295 { 2296 const struct clkc_data *clkc_data; 2297 struct regmap *map; 2298 int ret, i; 2299 struct device *dev = &pdev->dev; 2300 2301 clkc_data = of_device_get_match_data(dev); 2302 if (!clkc_data) 2303 return -EINVAL; 2304 2305 /* Get the hhi system controller node if available */ 2306 map = syscon_node_to_regmap(of_get_parent(dev->of_node)); 2307 if (IS_ERR(map)) { 2308 dev_err(dev, "failed to get HHI regmap\n"); 2309 return PTR_ERR(map); 2310 } 2311 2312 /* Populate regmap for the common regmap backed clocks */ 2313 for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++) 2314 gx_clk_regmaps[i]->map = map; 2315 2316 /* Populate regmap for soc specific clocks */ 2317 for (i = 0; i < clkc_data->regmap_clks_count; i++) 2318 clkc_data->regmap_clks[i]->map = map; 2319 2320 /* Register all clks */ 2321 for (i = 0; i < clkc_data->hw_onecell_data->num; i++) { 2322 /* array might be sparse */ 2323 if (!clkc_data->hw_onecell_data->hws[i]) 2324 continue; 2325 2326 ret = devm_clk_hw_register(dev, 2327 clkc_data->hw_onecell_data->hws[i]); 2328 if (ret) { 2329 dev_err(dev, "Clock registration failed\n"); 2330 return ret; 2331 } 2332 } 2333 2334 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 2335 clkc_data->hw_onecell_data); 2336 } 2337 2338 static struct platform_driver gxbb_driver = { 2339 .probe = gxbb_clkc_probe, 2340 .driver = { 2341 .name = "gxbb-clkc", 2342 .of_match_table = clkc_match_table, 2343 }, 2344 }; 2345 2346 builtin_platform_driver(gxbb_driver); 2347