1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2016 AmLogic, Inc. 4 * Michael Turquette <mturquette@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/init.h> 10 #include <linux/of_device.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 15 #include "clkc.h" 16 #include "gxbb.h" 17 #include "clk-regmap.h" 18 19 static DEFINE_SPINLOCK(meson_clk_lock); 20 21 static const struct pll_params_table gxbb_gp0_pll_params_table[] = { 22 PLL_PARAMS(32, 1), 23 PLL_PARAMS(33, 1), 24 PLL_PARAMS(34, 1), 25 PLL_PARAMS(35, 1), 26 PLL_PARAMS(36, 1), 27 PLL_PARAMS(37, 1), 28 PLL_PARAMS(38, 1), 29 PLL_PARAMS(39, 1), 30 PLL_PARAMS(40, 1), 31 PLL_PARAMS(41, 1), 32 PLL_PARAMS(42, 1), 33 PLL_PARAMS(43, 1), 34 PLL_PARAMS(44, 1), 35 PLL_PARAMS(45, 1), 36 PLL_PARAMS(46, 1), 37 PLL_PARAMS(47, 1), 38 PLL_PARAMS(48, 1), 39 PLL_PARAMS(49, 1), 40 PLL_PARAMS(50, 1), 41 PLL_PARAMS(51, 1), 42 PLL_PARAMS(52, 1), 43 PLL_PARAMS(53, 1), 44 PLL_PARAMS(54, 1), 45 PLL_PARAMS(55, 1), 46 PLL_PARAMS(56, 1), 47 PLL_PARAMS(57, 1), 48 PLL_PARAMS(58, 1), 49 PLL_PARAMS(59, 1), 50 PLL_PARAMS(60, 1), 51 PLL_PARAMS(61, 1), 52 PLL_PARAMS(62, 1), 53 { /* sentinel */ }, 54 }; 55 56 static const struct pll_params_table gxl_gp0_pll_params_table[] = { 57 PLL_PARAMS(42, 1), 58 PLL_PARAMS(43, 1), 59 PLL_PARAMS(44, 1), 60 PLL_PARAMS(45, 1), 61 PLL_PARAMS(46, 1), 62 PLL_PARAMS(47, 1), 63 PLL_PARAMS(48, 1), 64 PLL_PARAMS(49, 1), 65 PLL_PARAMS(50, 1), 66 PLL_PARAMS(51, 1), 67 PLL_PARAMS(52, 1), 68 PLL_PARAMS(53, 1), 69 PLL_PARAMS(54, 1), 70 PLL_PARAMS(55, 1), 71 PLL_PARAMS(56, 1), 72 PLL_PARAMS(57, 1), 73 PLL_PARAMS(58, 1), 74 PLL_PARAMS(59, 1), 75 PLL_PARAMS(60, 1), 76 PLL_PARAMS(61, 1), 77 PLL_PARAMS(62, 1), 78 PLL_PARAMS(63, 1), 79 PLL_PARAMS(64, 1), 80 PLL_PARAMS(65, 1), 81 PLL_PARAMS(66, 1), 82 { /* sentinel */ }, 83 }; 84 85 static struct clk_regmap gxbb_fixed_pll_dco = { 86 .data = &(struct meson_clk_pll_data){ 87 .en = { 88 .reg_off = HHI_MPLL_CNTL, 89 .shift = 30, 90 .width = 1, 91 }, 92 .m = { 93 .reg_off = HHI_MPLL_CNTL, 94 .shift = 0, 95 .width = 9, 96 }, 97 .n = { 98 .reg_off = HHI_MPLL_CNTL, 99 .shift = 9, 100 .width = 5, 101 }, 102 .frac = { 103 .reg_off = HHI_MPLL_CNTL2, 104 .shift = 0, 105 .width = 12, 106 }, 107 .l = { 108 .reg_off = HHI_MPLL_CNTL, 109 .shift = 31, 110 .width = 1, 111 }, 112 .rst = { 113 .reg_off = HHI_MPLL_CNTL, 114 .shift = 29, 115 .width = 1, 116 }, 117 }, 118 .hw.init = &(struct clk_init_data){ 119 .name = "fixed_pll_dco", 120 .ops = &meson_clk_pll_ro_ops, 121 .parent_names = (const char *[]){ "xtal" }, 122 .num_parents = 1, 123 }, 124 }; 125 126 static struct clk_regmap gxbb_fixed_pll = { 127 .data = &(struct clk_regmap_div_data){ 128 .offset = HHI_MPLL_CNTL, 129 .shift = 16, 130 .width = 2, 131 .flags = CLK_DIVIDER_POWER_OF_TWO, 132 }, 133 .hw.init = &(struct clk_init_data){ 134 .name = "fixed_pll", 135 .ops = &clk_regmap_divider_ro_ops, 136 .parent_names = (const char *[]){ "fixed_pll_dco" }, 137 .num_parents = 1, 138 /* 139 * This clock won't ever change at runtime so 140 * CLK_SET_RATE_PARENT is not required 141 */ 142 }, 143 }; 144 145 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = { 146 .mult = 2, 147 .div = 1, 148 .hw.init = &(struct clk_init_data){ 149 .name = "hdmi_pll_pre_mult", 150 .ops = &clk_fixed_factor_ops, 151 .parent_names = (const char *[]){ "xtal" }, 152 .num_parents = 1, 153 }, 154 }; 155 156 static struct clk_regmap gxbb_hdmi_pll_dco = { 157 .data = &(struct meson_clk_pll_data){ 158 .en = { 159 .reg_off = HHI_HDMI_PLL_CNTL, 160 .shift = 30, 161 .width = 1, 162 }, 163 .m = { 164 .reg_off = HHI_HDMI_PLL_CNTL, 165 .shift = 0, 166 .width = 9, 167 }, 168 .n = { 169 .reg_off = HHI_HDMI_PLL_CNTL, 170 .shift = 9, 171 .width = 5, 172 }, 173 .frac = { 174 .reg_off = HHI_HDMI_PLL_CNTL2, 175 .shift = 0, 176 .width = 12, 177 }, 178 .l = { 179 .reg_off = HHI_HDMI_PLL_CNTL, 180 .shift = 31, 181 .width = 1, 182 }, 183 .rst = { 184 .reg_off = HHI_HDMI_PLL_CNTL, 185 .shift = 28, 186 .width = 1, 187 }, 188 }, 189 .hw.init = &(struct clk_init_data){ 190 .name = "hdmi_pll_dco", 191 .ops = &meson_clk_pll_ro_ops, 192 .parent_names = (const char *[]){ "hdmi_pll_pre_mult" }, 193 .num_parents = 1, 194 /* 195 * Display directly handle hdmi pll registers ATM, we need 196 * NOCACHE to keep our view of the clock as accurate as possible 197 */ 198 .flags = CLK_GET_RATE_NOCACHE, 199 }, 200 }; 201 202 static struct clk_regmap gxbb_hdmi_pll_od = { 203 .data = &(struct clk_regmap_div_data){ 204 .offset = HHI_HDMI_PLL_CNTL2, 205 .shift = 16, 206 .width = 2, 207 .flags = CLK_DIVIDER_POWER_OF_TWO, 208 }, 209 .hw.init = &(struct clk_init_data){ 210 .name = "hdmi_pll_od", 211 .ops = &clk_regmap_divider_ro_ops, 212 .parent_names = (const char *[]){ "hdmi_pll_dco" }, 213 .num_parents = 1, 214 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 215 }, 216 }; 217 218 static struct clk_regmap gxbb_hdmi_pll_od2 = { 219 .data = &(struct clk_regmap_div_data){ 220 .offset = HHI_HDMI_PLL_CNTL2, 221 .shift = 22, 222 .width = 2, 223 .flags = CLK_DIVIDER_POWER_OF_TWO, 224 }, 225 .hw.init = &(struct clk_init_data){ 226 .name = "hdmi_pll_od2", 227 .ops = &clk_regmap_divider_ro_ops, 228 .parent_names = (const char *[]){ "hdmi_pll_od" }, 229 .num_parents = 1, 230 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 231 }, 232 }; 233 234 static struct clk_regmap gxbb_hdmi_pll = { 235 .data = &(struct clk_regmap_div_data){ 236 .offset = HHI_HDMI_PLL_CNTL2, 237 .shift = 18, 238 .width = 2, 239 .flags = CLK_DIVIDER_POWER_OF_TWO, 240 }, 241 .hw.init = &(struct clk_init_data){ 242 .name = "hdmi_pll", 243 .ops = &clk_regmap_divider_ro_ops, 244 .parent_names = (const char *[]){ "hdmi_pll_od2" }, 245 .num_parents = 1, 246 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 247 }, 248 }; 249 250 static struct clk_regmap gxl_hdmi_pll_od = { 251 .data = &(struct clk_regmap_div_data){ 252 .offset = HHI_HDMI_PLL_CNTL + 8, 253 .shift = 21, 254 .width = 2, 255 .flags = CLK_DIVIDER_POWER_OF_TWO, 256 }, 257 .hw.init = &(struct clk_init_data){ 258 .name = "hdmi_pll_od", 259 .ops = &clk_regmap_divider_ro_ops, 260 .parent_names = (const char *[]){ "hdmi_pll_dco" }, 261 .num_parents = 1, 262 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 263 }, 264 }; 265 266 static struct clk_regmap gxl_hdmi_pll_od2 = { 267 .data = &(struct clk_regmap_div_data){ 268 .offset = HHI_HDMI_PLL_CNTL + 8, 269 .shift = 23, 270 .width = 2, 271 .flags = CLK_DIVIDER_POWER_OF_TWO, 272 }, 273 .hw.init = &(struct clk_init_data){ 274 .name = "hdmi_pll_od2", 275 .ops = &clk_regmap_divider_ro_ops, 276 .parent_names = (const char *[]){ "hdmi_pll_od" }, 277 .num_parents = 1, 278 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 279 }, 280 }; 281 282 static struct clk_regmap gxl_hdmi_pll = { 283 .data = &(struct clk_regmap_div_data){ 284 .offset = HHI_HDMI_PLL_CNTL + 8, 285 .shift = 19, 286 .width = 2, 287 .flags = CLK_DIVIDER_POWER_OF_TWO, 288 }, 289 .hw.init = &(struct clk_init_data){ 290 .name = "hdmi_pll", 291 .ops = &clk_regmap_divider_ro_ops, 292 .parent_names = (const char *[]){ "hdmi_pll_od2" }, 293 .num_parents = 1, 294 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 295 }, 296 }; 297 298 static struct clk_regmap gxbb_sys_pll_dco = { 299 .data = &(struct meson_clk_pll_data){ 300 .en = { 301 .reg_off = HHI_SYS_PLL_CNTL, 302 .shift = 30, 303 .width = 1, 304 }, 305 .m = { 306 .reg_off = HHI_SYS_PLL_CNTL, 307 .shift = 0, 308 .width = 9, 309 }, 310 .n = { 311 .reg_off = HHI_SYS_PLL_CNTL, 312 .shift = 9, 313 .width = 5, 314 }, 315 .l = { 316 .reg_off = HHI_SYS_PLL_CNTL, 317 .shift = 31, 318 .width = 1, 319 }, 320 .rst = { 321 .reg_off = HHI_SYS_PLL_CNTL, 322 .shift = 29, 323 .width = 1, 324 }, 325 }, 326 .hw.init = &(struct clk_init_data){ 327 .name = "sys_pll_dco", 328 .ops = &meson_clk_pll_ro_ops, 329 .parent_names = (const char *[]){ "xtal" }, 330 .num_parents = 1, 331 }, 332 }; 333 334 static struct clk_regmap gxbb_sys_pll = { 335 .data = &(struct clk_regmap_div_data){ 336 .offset = HHI_SYS_PLL_CNTL, 337 .shift = 10, 338 .width = 2, 339 .flags = CLK_DIVIDER_POWER_OF_TWO, 340 }, 341 .hw.init = &(struct clk_init_data){ 342 .name = "sys_pll", 343 .ops = &clk_regmap_divider_ro_ops, 344 .parent_names = (const char *[]){ "sys_pll_dco" }, 345 .num_parents = 1, 346 .flags = CLK_SET_RATE_PARENT, 347 }, 348 }; 349 350 static const struct reg_sequence gxbb_gp0_init_regs[] = { 351 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 }, 352 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 }, 353 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d }, 354 }; 355 356 static struct clk_regmap gxbb_gp0_pll_dco = { 357 .data = &(struct meson_clk_pll_data){ 358 .en = { 359 .reg_off = HHI_GP0_PLL_CNTL, 360 .shift = 30, 361 .width = 1, 362 }, 363 .m = { 364 .reg_off = HHI_GP0_PLL_CNTL, 365 .shift = 0, 366 .width = 9, 367 }, 368 .n = { 369 .reg_off = HHI_GP0_PLL_CNTL, 370 .shift = 9, 371 .width = 5, 372 }, 373 .l = { 374 .reg_off = HHI_GP0_PLL_CNTL, 375 .shift = 31, 376 .width = 1, 377 }, 378 .rst = { 379 .reg_off = HHI_GP0_PLL_CNTL, 380 .shift = 29, 381 .width = 1, 382 }, 383 .table = gxbb_gp0_pll_params_table, 384 .init_regs = gxbb_gp0_init_regs, 385 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs), 386 }, 387 .hw.init = &(struct clk_init_data){ 388 .name = "gp0_pll_dco", 389 .ops = &meson_clk_pll_ops, 390 .parent_names = (const char *[]){ "xtal" }, 391 .num_parents = 1, 392 }, 393 }; 394 395 static const struct reg_sequence gxl_gp0_init_regs[] = { 396 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, 397 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, 398 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 399 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 400 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 401 }; 402 403 static struct clk_regmap gxl_gp0_pll_dco = { 404 .data = &(struct meson_clk_pll_data){ 405 .en = { 406 .reg_off = HHI_GP0_PLL_CNTL, 407 .shift = 30, 408 .width = 1, 409 }, 410 .m = { 411 .reg_off = HHI_GP0_PLL_CNTL, 412 .shift = 0, 413 .width = 9, 414 }, 415 .n = { 416 .reg_off = HHI_GP0_PLL_CNTL, 417 .shift = 9, 418 .width = 5, 419 }, 420 .frac = { 421 .reg_off = HHI_GP0_PLL_CNTL1, 422 .shift = 0, 423 .width = 10, 424 }, 425 .l = { 426 .reg_off = HHI_GP0_PLL_CNTL, 427 .shift = 31, 428 .width = 1, 429 }, 430 .rst = { 431 .reg_off = HHI_GP0_PLL_CNTL, 432 .shift = 29, 433 .width = 1, 434 }, 435 .table = gxl_gp0_pll_params_table, 436 .init_regs = gxl_gp0_init_regs, 437 .init_count = ARRAY_SIZE(gxl_gp0_init_regs), 438 }, 439 .hw.init = &(struct clk_init_data){ 440 .name = "gp0_pll_dco", 441 .ops = &meson_clk_pll_ops, 442 .parent_names = (const char *[]){ "xtal" }, 443 .num_parents = 1, 444 }, 445 }; 446 447 static struct clk_regmap gxbb_gp0_pll = { 448 .data = &(struct clk_regmap_div_data){ 449 .offset = HHI_GP0_PLL_CNTL, 450 .shift = 16, 451 .width = 2, 452 .flags = CLK_DIVIDER_POWER_OF_TWO, 453 }, 454 .hw.init = &(struct clk_init_data){ 455 .name = "gp0_pll", 456 .ops = &clk_regmap_divider_ops, 457 .parent_names = (const char *[]){ "gp0_pll_dco" }, 458 .num_parents = 1, 459 .flags = CLK_SET_RATE_PARENT, 460 }, 461 }; 462 463 static struct clk_fixed_factor gxbb_fclk_div2_div = { 464 .mult = 1, 465 .div = 2, 466 .hw.init = &(struct clk_init_data){ 467 .name = "fclk_div2_div", 468 .ops = &clk_fixed_factor_ops, 469 .parent_names = (const char *[]){ "fixed_pll" }, 470 .num_parents = 1, 471 }, 472 }; 473 474 static struct clk_regmap gxbb_fclk_div2 = { 475 .data = &(struct clk_regmap_gate_data){ 476 .offset = HHI_MPLL_CNTL6, 477 .bit_idx = 27, 478 }, 479 .hw.init = &(struct clk_init_data){ 480 .name = "fclk_div2", 481 .ops = &clk_regmap_gate_ops, 482 .parent_names = (const char *[]){ "fclk_div2_div" }, 483 .num_parents = 1, 484 .flags = CLK_IS_CRITICAL, 485 }, 486 }; 487 488 static struct clk_fixed_factor gxbb_fclk_div3_div = { 489 .mult = 1, 490 .div = 3, 491 .hw.init = &(struct clk_init_data){ 492 .name = "fclk_div3_div", 493 .ops = &clk_fixed_factor_ops, 494 .parent_names = (const char *[]){ "fixed_pll" }, 495 .num_parents = 1, 496 }, 497 }; 498 499 static struct clk_regmap gxbb_fclk_div3 = { 500 .data = &(struct clk_regmap_gate_data){ 501 .offset = HHI_MPLL_CNTL6, 502 .bit_idx = 28, 503 }, 504 .hw.init = &(struct clk_init_data){ 505 .name = "fclk_div3", 506 .ops = &clk_regmap_gate_ops, 507 .parent_names = (const char *[]){ "fclk_div3_div" }, 508 .num_parents = 1, 509 /* 510 * FIXME: 511 * This clock, as fdiv2, is used by the SCPI FW and is required 512 * by the platform to operate correctly. 513 * Until the following condition are met, we need this clock to 514 * be marked as critical: 515 * a) The SCPI generic driver claims and enable all the clocks 516 * it needs 517 * b) CCF has a clock hand-off mechanism to make the sure the 518 * clock stays on until the proper driver comes along 519 */ 520 .flags = CLK_IS_CRITICAL, 521 }, 522 }; 523 524 static struct clk_fixed_factor gxbb_fclk_div4_div = { 525 .mult = 1, 526 .div = 4, 527 .hw.init = &(struct clk_init_data){ 528 .name = "fclk_div4_div", 529 .ops = &clk_fixed_factor_ops, 530 .parent_names = (const char *[]){ "fixed_pll" }, 531 .num_parents = 1, 532 }, 533 }; 534 535 static struct clk_regmap gxbb_fclk_div4 = { 536 .data = &(struct clk_regmap_gate_data){ 537 .offset = HHI_MPLL_CNTL6, 538 .bit_idx = 29, 539 }, 540 .hw.init = &(struct clk_init_data){ 541 .name = "fclk_div4", 542 .ops = &clk_regmap_gate_ops, 543 .parent_names = (const char *[]){ "fclk_div4_div" }, 544 .num_parents = 1, 545 }, 546 }; 547 548 static struct clk_fixed_factor gxbb_fclk_div5_div = { 549 .mult = 1, 550 .div = 5, 551 .hw.init = &(struct clk_init_data){ 552 .name = "fclk_div5_div", 553 .ops = &clk_fixed_factor_ops, 554 .parent_names = (const char *[]){ "fixed_pll" }, 555 .num_parents = 1, 556 }, 557 }; 558 559 static struct clk_regmap gxbb_fclk_div5 = { 560 .data = &(struct clk_regmap_gate_data){ 561 .offset = HHI_MPLL_CNTL6, 562 .bit_idx = 30, 563 }, 564 .hw.init = &(struct clk_init_data){ 565 .name = "fclk_div5", 566 .ops = &clk_regmap_gate_ops, 567 .parent_names = (const char *[]){ "fclk_div5_div" }, 568 .num_parents = 1, 569 }, 570 }; 571 572 static struct clk_fixed_factor gxbb_fclk_div7_div = { 573 .mult = 1, 574 .div = 7, 575 .hw.init = &(struct clk_init_data){ 576 .name = "fclk_div7_div", 577 .ops = &clk_fixed_factor_ops, 578 .parent_names = (const char *[]){ "fixed_pll" }, 579 .num_parents = 1, 580 }, 581 }; 582 583 static struct clk_regmap gxbb_fclk_div7 = { 584 .data = &(struct clk_regmap_gate_data){ 585 .offset = HHI_MPLL_CNTL6, 586 .bit_idx = 31, 587 }, 588 .hw.init = &(struct clk_init_data){ 589 .name = "fclk_div7", 590 .ops = &clk_regmap_gate_ops, 591 .parent_names = (const char *[]){ "fclk_div7_div" }, 592 .num_parents = 1, 593 }, 594 }; 595 596 static struct clk_regmap gxbb_mpll_prediv = { 597 .data = &(struct clk_regmap_div_data){ 598 .offset = HHI_MPLL_CNTL5, 599 .shift = 12, 600 .width = 1, 601 }, 602 .hw.init = &(struct clk_init_data){ 603 .name = "mpll_prediv", 604 .ops = &clk_regmap_divider_ro_ops, 605 .parent_names = (const char *[]){ "fixed_pll" }, 606 .num_parents = 1, 607 }, 608 }; 609 610 static struct clk_regmap gxbb_mpll0_div = { 611 .data = &(struct meson_clk_mpll_data){ 612 .sdm = { 613 .reg_off = HHI_MPLL_CNTL7, 614 .shift = 0, 615 .width = 14, 616 }, 617 .sdm_en = { 618 .reg_off = HHI_MPLL_CNTL7, 619 .shift = 15, 620 .width = 1, 621 }, 622 .n2 = { 623 .reg_off = HHI_MPLL_CNTL7, 624 .shift = 16, 625 .width = 9, 626 }, 627 .ssen = { 628 .reg_off = HHI_MPLL_CNTL, 629 .shift = 25, 630 .width = 1, 631 }, 632 .lock = &meson_clk_lock, 633 }, 634 .hw.init = &(struct clk_init_data){ 635 .name = "mpll0_div", 636 .ops = &meson_clk_mpll_ops, 637 .parent_names = (const char *[]){ "mpll_prediv" }, 638 .num_parents = 1, 639 }, 640 }; 641 642 static struct clk_regmap gxbb_mpll0 = { 643 .data = &(struct clk_regmap_gate_data){ 644 .offset = HHI_MPLL_CNTL7, 645 .bit_idx = 14, 646 }, 647 .hw.init = &(struct clk_init_data){ 648 .name = "mpll0", 649 .ops = &clk_regmap_gate_ops, 650 .parent_names = (const char *[]){ "mpll0_div" }, 651 .num_parents = 1, 652 .flags = CLK_SET_RATE_PARENT, 653 }, 654 }; 655 656 static struct clk_regmap gxbb_mpll1_div = { 657 .data = &(struct meson_clk_mpll_data){ 658 .sdm = { 659 .reg_off = HHI_MPLL_CNTL8, 660 .shift = 0, 661 .width = 14, 662 }, 663 .sdm_en = { 664 .reg_off = HHI_MPLL_CNTL8, 665 .shift = 15, 666 .width = 1, 667 }, 668 .n2 = { 669 .reg_off = HHI_MPLL_CNTL8, 670 .shift = 16, 671 .width = 9, 672 }, 673 .lock = &meson_clk_lock, 674 }, 675 .hw.init = &(struct clk_init_data){ 676 .name = "mpll1_div", 677 .ops = &meson_clk_mpll_ops, 678 .parent_names = (const char *[]){ "mpll_prediv" }, 679 .num_parents = 1, 680 }, 681 }; 682 683 static struct clk_regmap gxbb_mpll1 = { 684 .data = &(struct clk_regmap_gate_data){ 685 .offset = HHI_MPLL_CNTL8, 686 .bit_idx = 14, 687 }, 688 .hw.init = &(struct clk_init_data){ 689 .name = "mpll1", 690 .ops = &clk_regmap_gate_ops, 691 .parent_names = (const char *[]){ "mpll1_div" }, 692 .num_parents = 1, 693 .flags = CLK_SET_RATE_PARENT, 694 }, 695 }; 696 697 static struct clk_regmap gxbb_mpll2_div = { 698 .data = &(struct meson_clk_mpll_data){ 699 .sdm = { 700 .reg_off = HHI_MPLL_CNTL9, 701 .shift = 0, 702 .width = 14, 703 }, 704 .sdm_en = { 705 .reg_off = HHI_MPLL_CNTL9, 706 .shift = 15, 707 .width = 1, 708 }, 709 .n2 = { 710 .reg_off = HHI_MPLL_CNTL9, 711 .shift = 16, 712 .width = 9, 713 }, 714 .lock = &meson_clk_lock, 715 }, 716 .hw.init = &(struct clk_init_data){ 717 .name = "mpll2_div", 718 .ops = &meson_clk_mpll_ops, 719 .parent_names = (const char *[]){ "mpll_prediv" }, 720 .num_parents = 1, 721 }, 722 }; 723 724 static struct clk_regmap gxbb_mpll2 = { 725 .data = &(struct clk_regmap_gate_data){ 726 .offset = HHI_MPLL_CNTL9, 727 .bit_idx = 14, 728 }, 729 .hw.init = &(struct clk_init_data){ 730 .name = "mpll2", 731 .ops = &clk_regmap_gate_ops, 732 .parent_names = (const char *[]){ "mpll2_div" }, 733 .num_parents = 1, 734 .flags = CLK_SET_RATE_PARENT, 735 }, 736 }; 737 738 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 739 static const char * const clk81_parent_names[] = { 740 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", 741 "fclk_div3", "fclk_div5" 742 }; 743 744 static struct clk_regmap gxbb_mpeg_clk_sel = { 745 .data = &(struct clk_regmap_mux_data){ 746 .offset = HHI_MPEG_CLK_CNTL, 747 .mask = 0x7, 748 .shift = 12, 749 .table = mux_table_clk81, 750 }, 751 .hw.init = &(struct clk_init_data){ 752 .name = "mpeg_clk_sel", 753 .ops = &clk_regmap_mux_ro_ops, 754 /* 755 * bits 14:12 selects from 8 possible parents: 756 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 757 * fclk_div4, fclk_div3, fclk_div5 758 */ 759 .parent_names = clk81_parent_names, 760 .num_parents = ARRAY_SIZE(clk81_parent_names), 761 }, 762 }; 763 764 static struct clk_regmap gxbb_mpeg_clk_div = { 765 .data = &(struct clk_regmap_div_data){ 766 .offset = HHI_MPEG_CLK_CNTL, 767 .shift = 0, 768 .width = 7, 769 }, 770 .hw.init = &(struct clk_init_data){ 771 .name = "mpeg_clk_div", 772 .ops = &clk_regmap_divider_ro_ops, 773 .parent_names = (const char *[]){ "mpeg_clk_sel" }, 774 .num_parents = 1, 775 }, 776 }; 777 778 /* the mother of dragons gates */ 779 static struct clk_regmap gxbb_clk81 = { 780 .data = &(struct clk_regmap_gate_data){ 781 .offset = HHI_MPEG_CLK_CNTL, 782 .bit_idx = 7, 783 }, 784 .hw.init = &(struct clk_init_data){ 785 .name = "clk81", 786 .ops = &clk_regmap_gate_ops, 787 .parent_names = (const char *[]){ "mpeg_clk_div" }, 788 .num_parents = 1, 789 .flags = CLK_IS_CRITICAL, 790 }, 791 }; 792 793 static struct clk_regmap gxbb_sar_adc_clk_sel = { 794 .data = &(struct clk_regmap_mux_data){ 795 .offset = HHI_SAR_CLK_CNTL, 796 .mask = 0x3, 797 .shift = 9, 798 }, 799 .hw.init = &(struct clk_init_data){ 800 .name = "sar_adc_clk_sel", 801 .ops = &clk_regmap_mux_ops, 802 /* NOTE: The datasheet doesn't list the parents for bit 10 */ 803 .parent_names = (const char *[]){ "xtal", "clk81", }, 804 .num_parents = 2, 805 }, 806 }; 807 808 static struct clk_regmap gxbb_sar_adc_clk_div = { 809 .data = &(struct clk_regmap_div_data){ 810 .offset = HHI_SAR_CLK_CNTL, 811 .shift = 0, 812 .width = 8, 813 }, 814 .hw.init = &(struct clk_init_data){ 815 .name = "sar_adc_clk_div", 816 .ops = &clk_regmap_divider_ops, 817 .parent_names = (const char *[]){ "sar_adc_clk_sel" }, 818 .num_parents = 1, 819 }, 820 }; 821 822 static struct clk_regmap gxbb_sar_adc_clk = { 823 .data = &(struct clk_regmap_gate_data){ 824 .offset = HHI_SAR_CLK_CNTL, 825 .bit_idx = 8, 826 }, 827 .hw.init = &(struct clk_init_data){ 828 .name = "sar_adc_clk", 829 .ops = &clk_regmap_gate_ops, 830 .parent_names = (const char *[]){ "sar_adc_clk_div" }, 831 .num_parents = 1, 832 .flags = CLK_SET_RATE_PARENT, 833 }, 834 }; 835 836 /* 837 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 838 * muxed by a glitch-free switch. 839 */ 840 841 static const char * const gxbb_mali_0_1_parent_names[] = { 842 "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7", 843 "fclk_div4", "fclk_div3", "fclk_div5" 844 }; 845 846 static struct clk_regmap gxbb_mali_0_sel = { 847 .data = &(struct clk_regmap_mux_data){ 848 .offset = HHI_MALI_CLK_CNTL, 849 .mask = 0x7, 850 .shift = 9, 851 }, 852 .hw.init = &(struct clk_init_data){ 853 .name = "mali_0_sel", 854 .ops = &clk_regmap_mux_ops, 855 /* 856 * bits 10:9 selects from 8 possible parents: 857 * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 858 * fclk_div4, fclk_div3, fclk_div5 859 */ 860 .parent_names = gxbb_mali_0_1_parent_names, 861 .num_parents = 8, 862 .flags = CLK_SET_RATE_NO_REPARENT, 863 }, 864 }; 865 866 static struct clk_regmap gxbb_mali_0_div = { 867 .data = &(struct clk_regmap_div_data){ 868 .offset = HHI_MALI_CLK_CNTL, 869 .shift = 0, 870 .width = 7, 871 }, 872 .hw.init = &(struct clk_init_data){ 873 .name = "mali_0_div", 874 .ops = &clk_regmap_divider_ops, 875 .parent_names = (const char *[]){ "mali_0_sel" }, 876 .num_parents = 1, 877 .flags = CLK_SET_RATE_NO_REPARENT, 878 }, 879 }; 880 881 static struct clk_regmap gxbb_mali_0 = { 882 .data = &(struct clk_regmap_gate_data){ 883 .offset = HHI_MALI_CLK_CNTL, 884 .bit_idx = 8, 885 }, 886 .hw.init = &(struct clk_init_data){ 887 .name = "mali_0", 888 .ops = &clk_regmap_gate_ops, 889 .parent_names = (const char *[]){ "mali_0_div" }, 890 .num_parents = 1, 891 .flags = CLK_SET_RATE_PARENT, 892 }, 893 }; 894 895 static struct clk_regmap gxbb_mali_1_sel = { 896 .data = &(struct clk_regmap_mux_data){ 897 .offset = HHI_MALI_CLK_CNTL, 898 .mask = 0x7, 899 .shift = 25, 900 }, 901 .hw.init = &(struct clk_init_data){ 902 .name = "mali_1_sel", 903 .ops = &clk_regmap_mux_ops, 904 /* 905 * bits 10:9 selects from 8 possible parents: 906 * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 907 * fclk_div4, fclk_div3, fclk_div5 908 */ 909 .parent_names = gxbb_mali_0_1_parent_names, 910 .num_parents = 8, 911 .flags = CLK_SET_RATE_NO_REPARENT, 912 }, 913 }; 914 915 static struct clk_regmap gxbb_mali_1_div = { 916 .data = &(struct clk_regmap_div_data){ 917 .offset = HHI_MALI_CLK_CNTL, 918 .shift = 16, 919 .width = 7, 920 }, 921 .hw.init = &(struct clk_init_data){ 922 .name = "mali_1_div", 923 .ops = &clk_regmap_divider_ops, 924 .parent_names = (const char *[]){ "mali_1_sel" }, 925 .num_parents = 1, 926 .flags = CLK_SET_RATE_NO_REPARENT, 927 }, 928 }; 929 930 static struct clk_regmap gxbb_mali_1 = { 931 .data = &(struct clk_regmap_gate_data){ 932 .offset = HHI_MALI_CLK_CNTL, 933 .bit_idx = 24, 934 }, 935 .hw.init = &(struct clk_init_data){ 936 .name = "mali_1", 937 .ops = &clk_regmap_gate_ops, 938 .parent_names = (const char *[]){ "mali_1_div" }, 939 .num_parents = 1, 940 .flags = CLK_SET_RATE_PARENT, 941 }, 942 }; 943 944 static const char * const gxbb_mali_parent_names[] = { 945 "mali_0", "mali_1" 946 }; 947 948 static struct clk_regmap gxbb_mali = { 949 .data = &(struct clk_regmap_mux_data){ 950 .offset = HHI_MALI_CLK_CNTL, 951 .mask = 1, 952 .shift = 31, 953 }, 954 .hw.init = &(struct clk_init_data){ 955 .name = "mali", 956 .ops = &clk_regmap_mux_ops, 957 .parent_names = gxbb_mali_parent_names, 958 .num_parents = 2, 959 .flags = CLK_SET_RATE_NO_REPARENT, 960 }, 961 }; 962 963 static struct clk_regmap gxbb_cts_amclk_sel = { 964 .data = &(struct clk_regmap_mux_data){ 965 .offset = HHI_AUD_CLK_CNTL, 966 .mask = 0x3, 967 .shift = 9, 968 .table = (u32[]){ 1, 2, 3 }, 969 .flags = CLK_MUX_ROUND_CLOSEST, 970 }, 971 .hw.init = &(struct clk_init_data){ 972 .name = "cts_amclk_sel", 973 .ops = &clk_regmap_mux_ops, 974 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 975 .num_parents = 3, 976 }, 977 }; 978 979 static struct clk_regmap gxbb_cts_amclk_div = { 980 .data = &(struct clk_regmap_div_data) { 981 .offset = HHI_AUD_CLK_CNTL, 982 .shift = 0, 983 .width = 8, 984 .flags = CLK_DIVIDER_ROUND_CLOSEST, 985 }, 986 .hw.init = &(struct clk_init_data){ 987 .name = "cts_amclk_div", 988 .ops = &clk_regmap_divider_ops, 989 .parent_names = (const char *[]){ "cts_amclk_sel" }, 990 .num_parents = 1, 991 .flags = CLK_SET_RATE_PARENT, 992 }, 993 }; 994 995 static struct clk_regmap gxbb_cts_amclk = { 996 .data = &(struct clk_regmap_gate_data){ 997 .offset = HHI_AUD_CLK_CNTL, 998 .bit_idx = 8, 999 }, 1000 .hw.init = &(struct clk_init_data){ 1001 .name = "cts_amclk", 1002 .ops = &clk_regmap_gate_ops, 1003 .parent_names = (const char *[]){ "cts_amclk_div" }, 1004 .num_parents = 1, 1005 .flags = CLK_SET_RATE_PARENT, 1006 }, 1007 }; 1008 1009 static struct clk_regmap gxbb_cts_mclk_i958_sel = { 1010 .data = &(struct clk_regmap_mux_data){ 1011 .offset = HHI_AUD_CLK_CNTL2, 1012 .mask = 0x3, 1013 .shift = 25, 1014 .table = (u32[]){ 1, 2, 3 }, 1015 .flags = CLK_MUX_ROUND_CLOSEST, 1016 }, 1017 .hw.init = &(struct clk_init_data) { 1018 .name = "cts_mclk_i958_sel", 1019 .ops = &clk_regmap_mux_ops, 1020 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 1021 .num_parents = 3, 1022 }, 1023 }; 1024 1025 static struct clk_regmap gxbb_cts_mclk_i958_div = { 1026 .data = &(struct clk_regmap_div_data){ 1027 .offset = HHI_AUD_CLK_CNTL2, 1028 .shift = 16, 1029 .width = 8, 1030 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1031 }, 1032 .hw.init = &(struct clk_init_data) { 1033 .name = "cts_mclk_i958_div", 1034 .ops = &clk_regmap_divider_ops, 1035 .parent_names = (const char *[]){ "cts_mclk_i958_sel" }, 1036 .num_parents = 1, 1037 .flags = CLK_SET_RATE_PARENT, 1038 }, 1039 }; 1040 1041 static struct clk_regmap gxbb_cts_mclk_i958 = { 1042 .data = &(struct clk_regmap_gate_data){ 1043 .offset = HHI_AUD_CLK_CNTL2, 1044 .bit_idx = 24, 1045 }, 1046 .hw.init = &(struct clk_init_data){ 1047 .name = "cts_mclk_i958", 1048 .ops = &clk_regmap_gate_ops, 1049 .parent_names = (const char *[]){ "cts_mclk_i958_div" }, 1050 .num_parents = 1, 1051 .flags = CLK_SET_RATE_PARENT, 1052 }, 1053 }; 1054 1055 static struct clk_regmap gxbb_cts_i958 = { 1056 .data = &(struct clk_regmap_mux_data){ 1057 .offset = HHI_AUD_CLK_CNTL2, 1058 .mask = 0x1, 1059 .shift = 27, 1060 }, 1061 .hw.init = &(struct clk_init_data){ 1062 .name = "cts_i958", 1063 .ops = &clk_regmap_mux_ops, 1064 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" }, 1065 .num_parents = 2, 1066 /* 1067 *The parent is specific to origin of the audio data. Let the 1068 * consumer choose the appropriate parent 1069 */ 1070 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 1071 }, 1072 }; 1073 1074 static struct clk_regmap gxbb_32k_clk_div = { 1075 .data = &(struct clk_regmap_div_data){ 1076 .offset = HHI_32K_CLK_CNTL, 1077 .shift = 0, 1078 .width = 14, 1079 }, 1080 .hw.init = &(struct clk_init_data){ 1081 .name = "32k_clk_div", 1082 .ops = &clk_regmap_divider_ops, 1083 .parent_names = (const char *[]){ "32k_clk_sel" }, 1084 .num_parents = 1, 1085 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, 1086 }, 1087 }; 1088 1089 static struct clk_regmap gxbb_32k_clk = { 1090 .data = &(struct clk_regmap_gate_data){ 1091 .offset = HHI_32K_CLK_CNTL, 1092 .bit_idx = 15, 1093 }, 1094 .hw.init = &(struct clk_init_data){ 1095 .name = "32k_clk", 1096 .ops = &clk_regmap_gate_ops, 1097 .parent_names = (const char *[]){ "32k_clk_div" }, 1098 .num_parents = 1, 1099 .flags = CLK_SET_RATE_PARENT, 1100 }, 1101 }; 1102 1103 static const char * const gxbb_32k_clk_parent_names[] = { 1104 "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5" 1105 }; 1106 1107 static struct clk_regmap gxbb_32k_clk_sel = { 1108 .data = &(struct clk_regmap_mux_data){ 1109 .offset = HHI_32K_CLK_CNTL, 1110 .mask = 0x3, 1111 .shift = 16, 1112 }, 1113 .hw.init = &(struct clk_init_data){ 1114 .name = "32k_clk_sel", 1115 .ops = &clk_regmap_mux_ops, 1116 .parent_names = gxbb_32k_clk_parent_names, 1117 .num_parents = 4, 1118 .flags = CLK_SET_RATE_PARENT, 1119 }, 1120 }; 1121 1122 static const char * const gxbb_sd_emmc_clk0_parent_names[] = { 1123 "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", 1124 1125 /* 1126 * Following these parent clocks, we should also have had mpll2, mpll3 1127 * and gp0_pll but these clocks are too precious to be used here. All 1128 * the necessary rates for MMC and NAND operation can be acheived using 1129 * xtal or fclk_div clocks 1130 */ 1131 }; 1132 1133 /* SDIO clock */ 1134 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = { 1135 .data = &(struct clk_regmap_mux_data){ 1136 .offset = HHI_SD_EMMC_CLK_CNTL, 1137 .mask = 0x7, 1138 .shift = 9, 1139 }, 1140 .hw.init = &(struct clk_init_data) { 1141 .name = "sd_emmc_a_clk0_sel", 1142 .ops = &clk_regmap_mux_ops, 1143 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1144 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1145 .flags = CLK_SET_RATE_PARENT, 1146 }, 1147 }; 1148 1149 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = { 1150 .data = &(struct clk_regmap_div_data){ 1151 .offset = HHI_SD_EMMC_CLK_CNTL, 1152 .shift = 0, 1153 .width = 7, 1154 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1155 }, 1156 .hw.init = &(struct clk_init_data) { 1157 .name = "sd_emmc_a_clk0_div", 1158 .ops = &clk_regmap_divider_ops, 1159 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" }, 1160 .num_parents = 1, 1161 .flags = CLK_SET_RATE_PARENT, 1162 }, 1163 }; 1164 1165 static struct clk_regmap gxbb_sd_emmc_a_clk0 = { 1166 .data = &(struct clk_regmap_gate_data){ 1167 .offset = HHI_SD_EMMC_CLK_CNTL, 1168 .bit_idx = 7, 1169 }, 1170 .hw.init = &(struct clk_init_data){ 1171 .name = "sd_emmc_a_clk0", 1172 .ops = &clk_regmap_gate_ops, 1173 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" }, 1174 .num_parents = 1, 1175 .flags = CLK_SET_RATE_PARENT, 1176 }, 1177 }; 1178 1179 /* SDcard clock */ 1180 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = { 1181 .data = &(struct clk_regmap_mux_data){ 1182 .offset = HHI_SD_EMMC_CLK_CNTL, 1183 .mask = 0x7, 1184 .shift = 25, 1185 }, 1186 .hw.init = &(struct clk_init_data) { 1187 .name = "sd_emmc_b_clk0_sel", 1188 .ops = &clk_regmap_mux_ops, 1189 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1190 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1191 .flags = CLK_SET_RATE_PARENT, 1192 }, 1193 }; 1194 1195 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = { 1196 .data = &(struct clk_regmap_div_data){ 1197 .offset = HHI_SD_EMMC_CLK_CNTL, 1198 .shift = 16, 1199 .width = 7, 1200 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1201 }, 1202 .hw.init = &(struct clk_init_data) { 1203 .name = "sd_emmc_b_clk0_div", 1204 .ops = &clk_regmap_divider_ops, 1205 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, 1206 .num_parents = 1, 1207 .flags = CLK_SET_RATE_PARENT, 1208 }, 1209 }; 1210 1211 static struct clk_regmap gxbb_sd_emmc_b_clk0 = { 1212 .data = &(struct clk_regmap_gate_data){ 1213 .offset = HHI_SD_EMMC_CLK_CNTL, 1214 .bit_idx = 23, 1215 }, 1216 .hw.init = &(struct clk_init_data){ 1217 .name = "sd_emmc_b_clk0", 1218 .ops = &clk_regmap_gate_ops, 1219 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, 1220 .num_parents = 1, 1221 .flags = CLK_SET_RATE_PARENT, 1222 }, 1223 }; 1224 1225 /* EMMC/NAND clock */ 1226 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = { 1227 .data = &(struct clk_regmap_mux_data){ 1228 .offset = HHI_NAND_CLK_CNTL, 1229 .mask = 0x7, 1230 .shift = 9, 1231 }, 1232 .hw.init = &(struct clk_init_data) { 1233 .name = "sd_emmc_c_clk0_sel", 1234 .ops = &clk_regmap_mux_ops, 1235 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1236 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1237 .flags = CLK_SET_RATE_PARENT, 1238 }, 1239 }; 1240 1241 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = { 1242 .data = &(struct clk_regmap_div_data){ 1243 .offset = HHI_NAND_CLK_CNTL, 1244 .shift = 0, 1245 .width = 7, 1246 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1247 }, 1248 .hw.init = &(struct clk_init_data) { 1249 .name = "sd_emmc_c_clk0_div", 1250 .ops = &clk_regmap_divider_ops, 1251 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, 1252 .num_parents = 1, 1253 .flags = CLK_SET_RATE_PARENT, 1254 }, 1255 }; 1256 1257 static struct clk_regmap gxbb_sd_emmc_c_clk0 = { 1258 .data = &(struct clk_regmap_gate_data){ 1259 .offset = HHI_NAND_CLK_CNTL, 1260 .bit_idx = 7, 1261 }, 1262 .hw.init = &(struct clk_init_data){ 1263 .name = "sd_emmc_c_clk0", 1264 .ops = &clk_regmap_gate_ops, 1265 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, 1266 .num_parents = 1, 1267 .flags = CLK_SET_RATE_PARENT, 1268 }, 1269 }; 1270 1271 /* VPU Clock */ 1272 1273 static const char * const gxbb_vpu_parent_names[] = { 1274 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1275 }; 1276 1277 static struct clk_regmap gxbb_vpu_0_sel = { 1278 .data = &(struct clk_regmap_mux_data){ 1279 .offset = HHI_VPU_CLK_CNTL, 1280 .mask = 0x3, 1281 .shift = 9, 1282 }, 1283 .hw.init = &(struct clk_init_data){ 1284 .name = "vpu_0_sel", 1285 .ops = &clk_regmap_mux_ops, 1286 /* 1287 * bits 9:10 selects from 4 possible parents: 1288 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1289 */ 1290 .parent_names = gxbb_vpu_parent_names, 1291 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names), 1292 .flags = CLK_SET_RATE_NO_REPARENT, 1293 }, 1294 }; 1295 1296 static struct clk_regmap gxbb_vpu_0_div = { 1297 .data = &(struct clk_regmap_div_data){ 1298 .offset = HHI_VPU_CLK_CNTL, 1299 .shift = 0, 1300 .width = 7, 1301 }, 1302 .hw.init = &(struct clk_init_data){ 1303 .name = "vpu_0_div", 1304 .ops = &clk_regmap_divider_ops, 1305 .parent_names = (const char *[]){ "vpu_0_sel" }, 1306 .num_parents = 1, 1307 .flags = CLK_SET_RATE_PARENT, 1308 }, 1309 }; 1310 1311 static struct clk_regmap gxbb_vpu_0 = { 1312 .data = &(struct clk_regmap_gate_data){ 1313 .offset = HHI_VPU_CLK_CNTL, 1314 .bit_idx = 8, 1315 }, 1316 .hw.init = &(struct clk_init_data) { 1317 .name = "vpu_0", 1318 .ops = &clk_regmap_gate_ops, 1319 .parent_names = (const char *[]){ "vpu_0_div" }, 1320 .num_parents = 1, 1321 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1322 }, 1323 }; 1324 1325 static struct clk_regmap gxbb_vpu_1_sel = { 1326 .data = &(struct clk_regmap_mux_data){ 1327 .offset = HHI_VPU_CLK_CNTL, 1328 .mask = 0x3, 1329 .shift = 25, 1330 }, 1331 .hw.init = &(struct clk_init_data){ 1332 .name = "vpu_1_sel", 1333 .ops = &clk_regmap_mux_ops, 1334 /* 1335 * bits 25:26 selects from 4 possible parents: 1336 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1337 */ 1338 .parent_names = gxbb_vpu_parent_names, 1339 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names), 1340 .flags = CLK_SET_RATE_NO_REPARENT, 1341 }, 1342 }; 1343 1344 static struct clk_regmap gxbb_vpu_1_div = { 1345 .data = &(struct clk_regmap_div_data){ 1346 .offset = HHI_VPU_CLK_CNTL, 1347 .shift = 16, 1348 .width = 7, 1349 }, 1350 .hw.init = &(struct clk_init_data){ 1351 .name = "vpu_1_div", 1352 .ops = &clk_regmap_divider_ops, 1353 .parent_names = (const char *[]){ "vpu_1_sel" }, 1354 .num_parents = 1, 1355 .flags = CLK_SET_RATE_PARENT, 1356 }, 1357 }; 1358 1359 static struct clk_regmap gxbb_vpu_1 = { 1360 .data = &(struct clk_regmap_gate_data){ 1361 .offset = HHI_VPU_CLK_CNTL, 1362 .bit_idx = 24, 1363 }, 1364 .hw.init = &(struct clk_init_data) { 1365 .name = "vpu_1", 1366 .ops = &clk_regmap_gate_ops, 1367 .parent_names = (const char *[]){ "vpu_1_div" }, 1368 .num_parents = 1, 1369 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1370 }, 1371 }; 1372 1373 static struct clk_regmap gxbb_vpu = { 1374 .data = &(struct clk_regmap_mux_data){ 1375 .offset = HHI_VPU_CLK_CNTL, 1376 .mask = 1, 1377 .shift = 31, 1378 }, 1379 .hw.init = &(struct clk_init_data){ 1380 .name = "vpu", 1381 .ops = &clk_regmap_mux_ops, 1382 /* 1383 * bit 31 selects from 2 possible parents: 1384 * vpu_0 or vpu_1 1385 */ 1386 .parent_names = (const char *[]){ "vpu_0", "vpu_1" }, 1387 .num_parents = 2, 1388 .flags = CLK_SET_RATE_NO_REPARENT, 1389 }, 1390 }; 1391 1392 /* VAPB Clock */ 1393 1394 static const char * const gxbb_vapb_parent_names[] = { 1395 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1396 }; 1397 1398 static struct clk_regmap gxbb_vapb_0_sel = { 1399 .data = &(struct clk_regmap_mux_data){ 1400 .offset = HHI_VAPBCLK_CNTL, 1401 .mask = 0x3, 1402 .shift = 9, 1403 }, 1404 .hw.init = &(struct clk_init_data){ 1405 .name = "vapb_0_sel", 1406 .ops = &clk_regmap_mux_ops, 1407 /* 1408 * bits 9:10 selects from 4 possible parents: 1409 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1410 */ 1411 .parent_names = gxbb_vapb_parent_names, 1412 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names), 1413 .flags = CLK_SET_RATE_NO_REPARENT, 1414 }, 1415 }; 1416 1417 static struct clk_regmap gxbb_vapb_0_div = { 1418 .data = &(struct clk_regmap_div_data){ 1419 .offset = HHI_VAPBCLK_CNTL, 1420 .shift = 0, 1421 .width = 7, 1422 }, 1423 .hw.init = &(struct clk_init_data){ 1424 .name = "vapb_0_div", 1425 .ops = &clk_regmap_divider_ops, 1426 .parent_names = (const char *[]){ "vapb_0_sel" }, 1427 .num_parents = 1, 1428 .flags = CLK_SET_RATE_PARENT, 1429 }, 1430 }; 1431 1432 static struct clk_regmap gxbb_vapb_0 = { 1433 .data = &(struct clk_regmap_gate_data){ 1434 .offset = HHI_VAPBCLK_CNTL, 1435 .bit_idx = 8, 1436 }, 1437 .hw.init = &(struct clk_init_data) { 1438 .name = "vapb_0", 1439 .ops = &clk_regmap_gate_ops, 1440 .parent_names = (const char *[]){ "vapb_0_div" }, 1441 .num_parents = 1, 1442 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1443 }, 1444 }; 1445 1446 static struct clk_regmap gxbb_vapb_1_sel = { 1447 .data = &(struct clk_regmap_mux_data){ 1448 .offset = HHI_VAPBCLK_CNTL, 1449 .mask = 0x3, 1450 .shift = 25, 1451 }, 1452 .hw.init = &(struct clk_init_data){ 1453 .name = "vapb_1_sel", 1454 .ops = &clk_regmap_mux_ops, 1455 /* 1456 * bits 25:26 selects from 4 possible parents: 1457 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1458 */ 1459 .parent_names = gxbb_vapb_parent_names, 1460 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names), 1461 .flags = CLK_SET_RATE_NO_REPARENT, 1462 }, 1463 }; 1464 1465 static struct clk_regmap gxbb_vapb_1_div = { 1466 .data = &(struct clk_regmap_div_data){ 1467 .offset = HHI_VAPBCLK_CNTL, 1468 .shift = 16, 1469 .width = 7, 1470 }, 1471 .hw.init = &(struct clk_init_data){ 1472 .name = "vapb_1_div", 1473 .ops = &clk_regmap_divider_ops, 1474 .parent_names = (const char *[]){ "vapb_1_sel" }, 1475 .num_parents = 1, 1476 .flags = CLK_SET_RATE_PARENT, 1477 }, 1478 }; 1479 1480 static struct clk_regmap gxbb_vapb_1 = { 1481 .data = &(struct clk_regmap_gate_data){ 1482 .offset = HHI_VAPBCLK_CNTL, 1483 .bit_idx = 24, 1484 }, 1485 .hw.init = &(struct clk_init_data) { 1486 .name = "vapb_1", 1487 .ops = &clk_regmap_gate_ops, 1488 .parent_names = (const char *[]){ "vapb_1_div" }, 1489 .num_parents = 1, 1490 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1491 }, 1492 }; 1493 1494 static struct clk_regmap gxbb_vapb_sel = { 1495 .data = &(struct clk_regmap_mux_data){ 1496 .offset = HHI_VAPBCLK_CNTL, 1497 .mask = 1, 1498 .shift = 31, 1499 }, 1500 .hw.init = &(struct clk_init_data){ 1501 .name = "vapb_sel", 1502 .ops = &clk_regmap_mux_ops, 1503 /* 1504 * bit 31 selects from 2 possible parents: 1505 * vapb_0 or vapb_1 1506 */ 1507 .parent_names = (const char *[]){ "vapb_0", "vapb_1" }, 1508 .num_parents = 2, 1509 .flags = CLK_SET_RATE_NO_REPARENT, 1510 }, 1511 }; 1512 1513 static struct clk_regmap gxbb_vapb = { 1514 .data = &(struct clk_regmap_gate_data){ 1515 .offset = HHI_VAPBCLK_CNTL, 1516 .bit_idx = 30, 1517 }, 1518 .hw.init = &(struct clk_init_data) { 1519 .name = "vapb", 1520 .ops = &clk_regmap_gate_ops, 1521 .parent_names = (const char *[]){ "vapb_sel" }, 1522 .num_parents = 1, 1523 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1524 }, 1525 }; 1526 1527 /* VDEC clocks */ 1528 1529 static const char * const gxbb_vdec_parent_names[] = { 1530 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1531 }; 1532 1533 static struct clk_regmap gxbb_vdec_1_sel = { 1534 .data = &(struct clk_regmap_mux_data){ 1535 .offset = HHI_VDEC_CLK_CNTL, 1536 .mask = 0x3, 1537 .shift = 9, 1538 .flags = CLK_MUX_ROUND_CLOSEST, 1539 }, 1540 .hw.init = &(struct clk_init_data){ 1541 .name = "vdec_1_sel", 1542 .ops = &clk_regmap_mux_ops, 1543 .parent_names = gxbb_vdec_parent_names, 1544 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names), 1545 .flags = CLK_SET_RATE_PARENT, 1546 }, 1547 }; 1548 1549 static struct clk_regmap gxbb_vdec_1_div = { 1550 .data = &(struct clk_regmap_div_data){ 1551 .offset = HHI_VDEC_CLK_CNTL, 1552 .shift = 0, 1553 .width = 7, 1554 }, 1555 .hw.init = &(struct clk_init_data){ 1556 .name = "vdec_1_div", 1557 .ops = &clk_regmap_divider_ops, 1558 .parent_names = (const char *[]){ "vdec_1_sel" }, 1559 .num_parents = 1, 1560 .flags = CLK_SET_RATE_PARENT, 1561 }, 1562 }; 1563 1564 static struct clk_regmap gxbb_vdec_1 = { 1565 .data = &(struct clk_regmap_gate_data){ 1566 .offset = HHI_VDEC_CLK_CNTL, 1567 .bit_idx = 8, 1568 }, 1569 .hw.init = &(struct clk_init_data) { 1570 .name = "vdec_1", 1571 .ops = &clk_regmap_gate_ops, 1572 .parent_names = (const char *[]){ "vdec_1_div" }, 1573 .num_parents = 1, 1574 .flags = CLK_SET_RATE_PARENT, 1575 }, 1576 }; 1577 1578 static struct clk_regmap gxbb_vdec_hevc_sel = { 1579 .data = &(struct clk_regmap_mux_data){ 1580 .offset = HHI_VDEC2_CLK_CNTL, 1581 .mask = 0x3, 1582 .shift = 25, 1583 .flags = CLK_MUX_ROUND_CLOSEST, 1584 }, 1585 .hw.init = &(struct clk_init_data){ 1586 .name = "vdec_hevc_sel", 1587 .ops = &clk_regmap_mux_ops, 1588 .parent_names = gxbb_vdec_parent_names, 1589 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names), 1590 .flags = CLK_SET_RATE_PARENT, 1591 }, 1592 }; 1593 1594 static struct clk_regmap gxbb_vdec_hevc_div = { 1595 .data = &(struct clk_regmap_div_data){ 1596 .offset = HHI_VDEC2_CLK_CNTL, 1597 .shift = 16, 1598 .width = 7, 1599 }, 1600 .hw.init = &(struct clk_init_data){ 1601 .name = "vdec_hevc_div", 1602 .ops = &clk_regmap_divider_ops, 1603 .parent_names = (const char *[]){ "vdec_hevc_sel" }, 1604 .num_parents = 1, 1605 .flags = CLK_SET_RATE_PARENT, 1606 }, 1607 }; 1608 1609 static struct clk_regmap gxbb_vdec_hevc = { 1610 .data = &(struct clk_regmap_gate_data){ 1611 .offset = HHI_VDEC2_CLK_CNTL, 1612 .bit_idx = 24, 1613 }, 1614 .hw.init = &(struct clk_init_data) { 1615 .name = "vdec_hevc", 1616 .ops = &clk_regmap_gate_ops, 1617 .parent_names = (const char *[]){ "vdec_hevc_div" }, 1618 .num_parents = 1, 1619 .flags = CLK_SET_RATE_PARENT, 1620 }, 1621 }; 1622 1623 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, 1624 9, 10, 11, 13, 14, }; 1625 static const char * const gen_clk_parent_names[] = { 1626 "xtal", "vdec_1", "vdec_hevc", "mpll0", "mpll1", "mpll2", 1627 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll", 1628 }; 1629 1630 static struct clk_regmap gxbb_gen_clk_sel = { 1631 .data = &(struct clk_regmap_mux_data){ 1632 .offset = HHI_GEN_CLK_CNTL, 1633 .mask = 0xf, 1634 .shift = 12, 1635 .table = mux_table_gen_clk, 1636 }, 1637 .hw.init = &(struct clk_init_data){ 1638 .name = "gen_clk_sel", 1639 .ops = &clk_regmap_mux_ops, 1640 /* 1641 * bits 15:12 selects from 14 possible parents: 1642 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt], 1643 * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4, 1644 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 1645 */ 1646 .parent_names = gen_clk_parent_names, 1647 .num_parents = ARRAY_SIZE(gen_clk_parent_names), 1648 }, 1649 }; 1650 1651 static struct clk_regmap gxbb_gen_clk_div = { 1652 .data = &(struct clk_regmap_div_data){ 1653 .offset = HHI_GEN_CLK_CNTL, 1654 .shift = 0, 1655 .width = 11, 1656 }, 1657 .hw.init = &(struct clk_init_data){ 1658 .name = "gen_clk_div", 1659 .ops = &clk_regmap_divider_ops, 1660 .parent_names = (const char *[]){ "gen_clk_sel" }, 1661 .num_parents = 1, 1662 .flags = CLK_SET_RATE_PARENT, 1663 }, 1664 }; 1665 1666 static struct clk_regmap gxbb_gen_clk = { 1667 .data = &(struct clk_regmap_gate_data){ 1668 .offset = HHI_GEN_CLK_CNTL, 1669 .bit_idx = 7, 1670 }, 1671 .hw.init = &(struct clk_init_data){ 1672 .name = "gen_clk", 1673 .ops = &clk_regmap_gate_ops, 1674 .parent_names = (const char *[]){ "gen_clk_div" }, 1675 .num_parents = 1, 1676 .flags = CLK_SET_RATE_PARENT, 1677 }, 1678 }; 1679 1680 /* Everything Else (EE) domain gates */ 1681 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 1682 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); 1683 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5); 1684 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6); 1685 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7); 1686 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8); 1687 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9); 1688 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10); 1689 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11); 1690 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12); 1691 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13); 1692 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14); 1693 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15); 1694 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16); 1695 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17); 1696 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18); 1697 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19); 1698 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); 1699 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24); 1700 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25); 1701 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26); 1702 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30); 1703 1704 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2); 1705 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3); 1706 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4); 1707 static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6); 1708 static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7); 1709 static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8); 1710 static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9); 1711 static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10); 1712 static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11); 1713 static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12); 1714 static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13); 1715 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14); 1716 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15); 1717 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16); 1718 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20); 1719 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21); 1720 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22); 1721 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23); 1722 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24); 1723 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25); 1724 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26); 1725 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28); 1726 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29); 1727 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30); 1728 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31); 1729 1730 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1); 1731 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 1732 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); 1733 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4); 1734 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); 1735 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); 1736 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); 1737 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12); 1738 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15); 1739 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22); 1740 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); 1741 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 1742 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); 1743 1744 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1); 1745 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2); 1746 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3); 1747 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4); 1748 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8); 1749 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9); 1750 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10); 1751 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14); 1752 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16); 1753 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20); 1754 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21); 1755 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22); 1756 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24); 1757 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25); 1758 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26); 1759 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31); 1760 1761 /* Always On (AO) domain gates */ 1762 1763 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0); 1764 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1); 1765 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2); 1766 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3); 1767 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4); 1768 1769 /* Array of all clocks provided by this provider */ 1770 1771 static struct clk_hw_onecell_data gxbb_hw_onecell_data = { 1772 .hws = { 1773 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 1774 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 1775 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 1776 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 1777 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 1778 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 1779 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 1780 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 1781 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 1782 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 1783 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 1784 [CLKID_CLK81] = &gxbb_clk81.hw, 1785 [CLKID_MPLL0] = &gxbb_mpll0.hw, 1786 [CLKID_MPLL1] = &gxbb_mpll1.hw, 1787 [CLKID_MPLL2] = &gxbb_mpll2.hw, 1788 [CLKID_DDR] = &gxbb_ddr.hw, 1789 [CLKID_DOS] = &gxbb_dos.hw, 1790 [CLKID_ISA] = &gxbb_isa.hw, 1791 [CLKID_PL301] = &gxbb_pl301.hw, 1792 [CLKID_PERIPHS] = &gxbb_periphs.hw, 1793 [CLKID_SPICC] = &gxbb_spicc.hw, 1794 [CLKID_I2C] = &gxbb_i2c.hw, 1795 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 1796 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 1797 [CLKID_RNG0] = &gxbb_rng0.hw, 1798 [CLKID_UART0] = &gxbb_uart0.hw, 1799 [CLKID_SDHC] = &gxbb_sdhc.hw, 1800 [CLKID_STREAM] = &gxbb_stream.hw, 1801 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 1802 [CLKID_SDIO] = &gxbb_sdio.hw, 1803 [CLKID_ABUF] = &gxbb_abuf.hw, 1804 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 1805 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 1806 [CLKID_SPI] = &gxbb_spi.hw, 1807 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 1808 [CLKID_ETH] = &gxbb_eth.hw, 1809 [CLKID_DEMUX] = &gxbb_demux.hw, 1810 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 1811 [CLKID_IEC958] = &gxbb_iec958.hw, 1812 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 1813 [CLKID_AMCLK] = &gxbb_amclk.hw, 1814 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 1815 [CLKID_MIXER] = &gxbb_mixer.hw, 1816 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 1817 [CLKID_ADC] = &gxbb_adc.hw, 1818 [CLKID_BLKMV] = &gxbb_blkmv.hw, 1819 [CLKID_AIU] = &gxbb_aiu.hw, 1820 [CLKID_UART1] = &gxbb_uart1.hw, 1821 [CLKID_G2D] = &gxbb_g2d.hw, 1822 [CLKID_USB0] = &gxbb_usb0.hw, 1823 [CLKID_USB1] = &gxbb_usb1.hw, 1824 [CLKID_RESET] = &gxbb_reset.hw, 1825 [CLKID_NAND] = &gxbb_nand.hw, 1826 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 1827 [CLKID_USB] = &gxbb_usb.hw, 1828 [CLKID_VDIN1] = &gxbb_vdin1.hw, 1829 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 1830 [CLKID_EFUSE] = &gxbb_efuse.hw, 1831 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 1832 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 1833 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 1834 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 1835 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 1836 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 1837 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 1838 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 1839 [CLKID_DVIN] = &gxbb_dvin.hw, 1840 [CLKID_UART2] = &gxbb_uart2.hw, 1841 [CLKID_SANA] = &gxbb_sana.hw, 1842 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 1843 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 1844 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 1845 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 1846 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 1847 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 1848 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 1849 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 1850 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 1851 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 1852 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 1853 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 1854 [CLKID_ENC480P] = &gxbb_enc480p.hw, 1855 [CLKID_RNG1] = &gxbb_rng1.hw, 1856 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 1857 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 1858 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 1859 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 1860 [CLKID_EDP] = &gxbb_edp.hw, 1861 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 1862 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 1863 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 1864 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 1865 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 1866 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 1867 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 1868 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 1869 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 1870 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 1871 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 1872 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 1873 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 1874 [CLKID_MALI_0] = &gxbb_mali_0.hw, 1875 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 1876 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 1877 [CLKID_MALI_1] = &gxbb_mali_1.hw, 1878 [CLKID_MALI] = &gxbb_mali.hw, 1879 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 1880 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 1881 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 1882 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 1883 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 1884 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 1885 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 1886 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 1887 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 1888 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 1889 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 1890 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 1891 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 1892 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 1893 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 1894 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 1895 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 1896 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 1897 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 1898 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 1899 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 1900 [CLKID_VPU_0] = &gxbb_vpu_0.hw, 1901 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 1902 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 1903 [CLKID_VPU_1] = &gxbb_vpu_1.hw, 1904 [CLKID_VPU] = &gxbb_vpu.hw, 1905 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 1906 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 1907 [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 1908 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 1909 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 1910 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 1911 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 1912 [CLKID_VAPB] = &gxbb_vapb.hw, 1913 [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw, 1914 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 1915 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 1916 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 1917 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 1918 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 1919 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 1920 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 1921 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 1922 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 1923 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 1924 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 1925 [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 1926 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 1927 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 1928 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 1929 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 1930 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 1931 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 1932 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 1933 [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw, 1934 [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw, 1935 [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw, 1936 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 1937 [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw, 1938 [NR_CLKS] = NULL, 1939 }, 1940 .num = NR_CLKS, 1941 }; 1942 1943 static struct clk_hw_onecell_data gxl_hw_onecell_data = { 1944 .hws = { 1945 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 1946 [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw, 1947 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 1948 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 1949 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 1950 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 1951 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 1952 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 1953 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 1954 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 1955 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 1956 [CLKID_CLK81] = &gxbb_clk81.hw, 1957 [CLKID_MPLL0] = &gxbb_mpll0.hw, 1958 [CLKID_MPLL1] = &gxbb_mpll1.hw, 1959 [CLKID_MPLL2] = &gxbb_mpll2.hw, 1960 [CLKID_DDR] = &gxbb_ddr.hw, 1961 [CLKID_DOS] = &gxbb_dos.hw, 1962 [CLKID_ISA] = &gxbb_isa.hw, 1963 [CLKID_PL301] = &gxbb_pl301.hw, 1964 [CLKID_PERIPHS] = &gxbb_periphs.hw, 1965 [CLKID_SPICC] = &gxbb_spicc.hw, 1966 [CLKID_I2C] = &gxbb_i2c.hw, 1967 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 1968 [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 1969 [CLKID_RNG0] = &gxbb_rng0.hw, 1970 [CLKID_UART0] = &gxbb_uart0.hw, 1971 [CLKID_SDHC] = &gxbb_sdhc.hw, 1972 [CLKID_STREAM] = &gxbb_stream.hw, 1973 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 1974 [CLKID_SDIO] = &gxbb_sdio.hw, 1975 [CLKID_ABUF] = &gxbb_abuf.hw, 1976 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 1977 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 1978 [CLKID_SPI] = &gxbb_spi.hw, 1979 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 1980 [CLKID_ETH] = &gxbb_eth.hw, 1981 [CLKID_DEMUX] = &gxbb_demux.hw, 1982 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 1983 [CLKID_IEC958] = &gxbb_iec958.hw, 1984 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 1985 [CLKID_AMCLK] = &gxbb_amclk.hw, 1986 [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 1987 [CLKID_MIXER] = &gxbb_mixer.hw, 1988 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 1989 [CLKID_ADC] = &gxbb_adc.hw, 1990 [CLKID_BLKMV] = &gxbb_blkmv.hw, 1991 [CLKID_AIU] = &gxbb_aiu.hw, 1992 [CLKID_UART1] = &gxbb_uart1.hw, 1993 [CLKID_G2D] = &gxbb_g2d.hw, 1994 [CLKID_USB0] = &gxbb_usb0.hw, 1995 [CLKID_USB1] = &gxbb_usb1.hw, 1996 [CLKID_RESET] = &gxbb_reset.hw, 1997 [CLKID_NAND] = &gxbb_nand.hw, 1998 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 1999 [CLKID_USB] = &gxbb_usb.hw, 2000 [CLKID_VDIN1] = &gxbb_vdin1.hw, 2001 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 2002 [CLKID_EFUSE] = &gxbb_efuse.hw, 2003 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 2004 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 2005 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 2006 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 2007 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 2008 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 2009 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 2010 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 2011 [CLKID_DVIN] = &gxbb_dvin.hw, 2012 [CLKID_UART2] = &gxbb_uart2.hw, 2013 [CLKID_SANA] = &gxbb_sana.hw, 2014 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 2015 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 2016 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 2017 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 2018 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 2019 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 2020 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 2021 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 2022 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 2023 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 2024 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 2025 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 2026 [CLKID_ENC480P] = &gxbb_enc480p.hw, 2027 [CLKID_RNG1] = &gxbb_rng1.hw, 2028 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 2029 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 2030 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 2031 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 2032 [CLKID_EDP] = &gxbb_edp.hw, 2033 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 2034 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 2035 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 2036 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 2037 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 2038 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 2039 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 2040 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 2041 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 2042 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 2043 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 2044 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 2045 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 2046 [CLKID_MALI_0] = &gxbb_mali_0.hw, 2047 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 2048 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 2049 [CLKID_MALI_1] = &gxbb_mali_1.hw, 2050 [CLKID_MALI] = &gxbb_mali.hw, 2051 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 2052 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 2053 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 2054 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 2055 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 2056 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 2057 [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 2058 [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 2059 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 2060 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 2061 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 2062 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 2063 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 2064 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 2065 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 2066 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 2067 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 2068 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 2069 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 2070 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 2071 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 2072 [CLKID_VPU_0] = &gxbb_vpu_0.hw, 2073 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 2074 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 2075 [CLKID_VPU_1] = &gxbb_vpu_1.hw, 2076 [CLKID_VPU] = &gxbb_vpu.hw, 2077 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 2078 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 2079 [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 2080 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 2081 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 2082 [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 2083 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 2084 [CLKID_VAPB] = &gxbb_vapb.hw, 2085 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 2086 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 2087 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 2088 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 2089 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 2090 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 2091 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 2092 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 2093 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 2094 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 2095 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 2096 [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 2097 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 2098 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 2099 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 2100 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 2101 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 2102 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 2103 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 2104 [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw, 2105 [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw, 2106 [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw, 2107 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 2108 [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw, 2109 [NR_CLKS] = NULL, 2110 }, 2111 .num = NR_CLKS, 2112 }; 2113 2114 static struct clk_regmap *const gxbb_clk_regmaps[] = { 2115 &gxbb_gp0_pll_dco, 2116 &gxbb_hdmi_pll, 2117 &gxbb_hdmi_pll_od, 2118 &gxbb_hdmi_pll_od2, 2119 }; 2120 2121 static struct clk_regmap *const gxl_clk_regmaps[] = { 2122 &gxl_gp0_pll_dco, 2123 &gxl_hdmi_pll, 2124 &gxl_hdmi_pll_od, 2125 &gxl_hdmi_pll_od2, 2126 }; 2127 2128 static struct clk_regmap *const gx_clk_regmaps[] = { 2129 &gxbb_clk81, 2130 &gxbb_ddr, 2131 &gxbb_dos, 2132 &gxbb_isa, 2133 &gxbb_pl301, 2134 &gxbb_periphs, 2135 &gxbb_spicc, 2136 &gxbb_i2c, 2137 &gxbb_sar_adc, 2138 &gxbb_smart_card, 2139 &gxbb_rng0, 2140 &gxbb_uart0, 2141 &gxbb_sdhc, 2142 &gxbb_stream, 2143 &gxbb_async_fifo, 2144 &gxbb_sdio, 2145 &gxbb_abuf, 2146 &gxbb_hiu_iface, 2147 &gxbb_assist_misc, 2148 &gxbb_spi, 2149 &gxbb_i2s_spdif, 2150 &gxbb_eth, 2151 &gxbb_demux, 2152 &gxbb_aiu_glue, 2153 &gxbb_iec958, 2154 &gxbb_i2s_out, 2155 &gxbb_amclk, 2156 &gxbb_aififo2, 2157 &gxbb_mixer, 2158 &gxbb_mixer_iface, 2159 &gxbb_adc, 2160 &gxbb_blkmv, 2161 &gxbb_aiu, 2162 &gxbb_uart1, 2163 &gxbb_g2d, 2164 &gxbb_usb0, 2165 &gxbb_usb1, 2166 &gxbb_reset, 2167 &gxbb_nand, 2168 &gxbb_dos_parser, 2169 &gxbb_usb, 2170 &gxbb_vdin1, 2171 &gxbb_ahb_arb0, 2172 &gxbb_efuse, 2173 &gxbb_boot_rom, 2174 &gxbb_ahb_data_bus, 2175 &gxbb_ahb_ctrl_bus, 2176 &gxbb_hdmi_intr_sync, 2177 &gxbb_hdmi_pclk, 2178 &gxbb_usb1_ddr_bridge, 2179 &gxbb_usb0_ddr_bridge, 2180 &gxbb_mmc_pclk, 2181 &gxbb_dvin, 2182 &gxbb_uart2, 2183 &gxbb_sana, 2184 &gxbb_vpu_intr, 2185 &gxbb_sec_ahb_ahb3_bridge, 2186 &gxbb_clk81_a53, 2187 &gxbb_vclk2_venci0, 2188 &gxbb_vclk2_venci1, 2189 &gxbb_vclk2_vencp0, 2190 &gxbb_vclk2_vencp1, 2191 &gxbb_gclk_venci_int0, 2192 &gxbb_gclk_vencp_int, 2193 &gxbb_dac_clk, 2194 &gxbb_aoclk_gate, 2195 &gxbb_iec958_gate, 2196 &gxbb_enc480p, 2197 &gxbb_rng1, 2198 &gxbb_gclk_venci_int1, 2199 &gxbb_vclk2_venclmcc, 2200 &gxbb_vclk2_vencl, 2201 &gxbb_vclk_other, 2202 &gxbb_edp, 2203 &gxbb_ao_media_cpu, 2204 &gxbb_ao_ahb_sram, 2205 &gxbb_ao_ahb_bus, 2206 &gxbb_ao_iface, 2207 &gxbb_ao_i2c, 2208 &gxbb_emmc_a, 2209 &gxbb_emmc_b, 2210 &gxbb_emmc_c, 2211 &gxbb_sar_adc_clk, 2212 &gxbb_mali_0, 2213 &gxbb_mali_1, 2214 &gxbb_cts_amclk, 2215 &gxbb_cts_mclk_i958, 2216 &gxbb_32k_clk, 2217 &gxbb_sd_emmc_a_clk0, 2218 &gxbb_sd_emmc_b_clk0, 2219 &gxbb_sd_emmc_c_clk0, 2220 &gxbb_vpu_0, 2221 &gxbb_vpu_1, 2222 &gxbb_vapb_0, 2223 &gxbb_vapb_1, 2224 &gxbb_vapb, 2225 &gxbb_mpeg_clk_div, 2226 &gxbb_sar_adc_clk_div, 2227 &gxbb_mali_0_div, 2228 &gxbb_mali_1_div, 2229 &gxbb_cts_mclk_i958_div, 2230 &gxbb_32k_clk_div, 2231 &gxbb_sd_emmc_a_clk0_div, 2232 &gxbb_sd_emmc_b_clk0_div, 2233 &gxbb_sd_emmc_c_clk0_div, 2234 &gxbb_vpu_0_div, 2235 &gxbb_vpu_1_div, 2236 &gxbb_vapb_0_div, 2237 &gxbb_vapb_1_div, 2238 &gxbb_mpeg_clk_sel, 2239 &gxbb_sar_adc_clk_sel, 2240 &gxbb_mali_0_sel, 2241 &gxbb_mali_1_sel, 2242 &gxbb_mali, 2243 &gxbb_cts_amclk_sel, 2244 &gxbb_cts_mclk_i958_sel, 2245 &gxbb_cts_i958, 2246 &gxbb_32k_clk_sel, 2247 &gxbb_sd_emmc_a_clk0_sel, 2248 &gxbb_sd_emmc_b_clk0_sel, 2249 &gxbb_sd_emmc_c_clk0_sel, 2250 &gxbb_vpu_0_sel, 2251 &gxbb_vpu_1_sel, 2252 &gxbb_vpu, 2253 &gxbb_vapb_0_sel, 2254 &gxbb_vapb_1_sel, 2255 &gxbb_vapb_sel, 2256 &gxbb_mpll0, 2257 &gxbb_mpll1, 2258 &gxbb_mpll2, 2259 &gxbb_mpll0_div, 2260 &gxbb_mpll1_div, 2261 &gxbb_mpll2_div, 2262 &gxbb_cts_amclk_div, 2263 &gxbb_fixed_pll, 2264 &gxbb_sys_pll, 2265 &gxbb_mpll_prediv, 2266 &gxbb_fclk_div2, 2267 &gxbb_fclk_div3, 2268 &gxbb_fclk_div4, 2269 &gxbb_fclk_div5, 2270 &gxbb_fclk_div7, 2271 &gxbb_vdec_1_sel, 2272 &gxbb_vdec_1_div, 2273 &gxbb_vdec_1, 2274 &gxbb_vdec_hevc_sel, 2275 &gxbb_vdec_hevc_div, 2276 &gxbb_vdec_hevc, 2277 &gxbb_gen_clk_sel, 2278 &gxbb_gen_clk_div, 2279 &gxbb_gen_clk, 2280 &gxbb_fixed_pll_dco, 2281 &gxbb_hdmi_pll_dco, 2282 &gxbb_sys_pll_dco, 2283 &gxbb_gp0_pll, 2284 }; 2285 2286 struct clkc_data { 2287 struct clk_regmap *const *regmap_clks; 2288 unsigned int regmap_clks_count; 2289 struct clk_hw_onecell_data *hw_onecell_data; 2290 }; 2291 2292 static const struct clkc_data gxbb_clkc_data = { 2293 .regmap_clks = gxbb_clk_regmaps, 2294 .regmap_clks_count = ARRAY_SIZE(gxbb_clk_regmaps), 2295 .hw_onecell_data = &gxbb_hw_onecell_data, 2296 }; 2297 2298 static const struct clkc_data gxl_clkc_data = { 2299 .regmap_clks = gxl_clk_regmaps, 2300 .regmap_clks_count = ARRAY_SIZE(gxl_clk_regmaps), 2301 .hw_onecell_data = &gxl_hw_onecell_data, 2302 }; 2303 2304 static const struct of_device_id clkc_match_table[] = { 2305 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data }, 2306 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data }, 2307 {}, 2308 }; 2309 2310 static int gxbb_clkc_probe(struct platform_device *pdev) 2311 { 2312 const struct clkc_data *clkc_data; 2313 struct regmap *map; 2314 int ret, i; 2315 struct device *dev = &pdev->dev; 2316 2317 clkc_data = of_device_get_match_data(dev); 2318 if (!clkc_data) 2319 return -EINVAL; 2320 2321 /* Get the hhi system controller node if available */ 2322 map = syscon_node_to_regmap(of_get_parent(dev->of_node)); 2323 if (IS_ERR(map)) { 2324 dev_err(dev, "failed to get HHI regmap\n"); 2325 return PTR_ERR(map); 2326 } 2327 2328 /* Populate regmap for the common regmap backed clocks */ 2329 for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++) 2330 gx_clk_regmaps[i]->map = map; 2331 2332 /* Populate regmap for soc specific clocks */ 2333 for (i = 0; i < clkc_data->regmap_clks_count; i++) 2334 clkc_data->regmap_clks[i]->map = map; 2335 2336 /* Register all clks */ 2337 for (i = 0; i < clkc_data->hw_onecell_data->num; i++) { 2338 /* array might be sparse */ 2339 if (!clkc_data->hw_onecell_data->hws[i]) 2340 continue; 2341 2342 ret = devm_clk_hw_register(dev, 2343 clkc_data->hw_onecell_data->hws[i]); 2344 if (ret) { 2345 dev_err(dev, "Clock registration failed\n"); 2346 return ret; 2347 } 2348 } 2349 2350 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 2351 clkc_data->hw_onecell_data); 2352 } 2353 2354 static struct platform_driver gxbb_driver = { 2355 .probe = gxbb_clkc_probe, 2356 .driver = { 2357 .name = "gxbb-clkc", 2358 .of_match_table = clkc_match_table, 2359 }, 2360 }; 2361 2362 builtin_platform_driver(gxbb_driver); 2363