122f65a38SJerome Brunet // SPDX-License-Identifier: GPL-2.0 2738f66d3SMichael Turquette /* 3738f66d3SMichael Turquette * Copyright (c) 2016 AmLogic, Inc. 4738f66d3SMichael Turquette * Michael Turquette <mturquette@baylibre.com> 5738f66d3SMichael Turquette */ 6738f66d3SMichael Turquette 7738f66d3SMichael Turquette #include <linux/clk-provider.h> 8161f6e5bSJerome Brunet #include <linux/init.h> 90d48fc55SNeil Armstrong #include <linux/of_device.h> 10738f66d3SMichael Turquette #include <linux/platform_device.h> 1120425f63SKevin Hilman #include <linux/module.h> 12738f66d3SMichael Turquette 13738f66d3SMichael Turquette #include "gxbb.h" 147f9768a5SJerome Brunet #include "clk-regmap.h" 15889c2b7eSJerome Brunet #include "clk-pll.h" 16889c2b7eSJerome Brunet #include "clk-mpll.h" 176682bd4dSJerome Brunet #include "meson-eeclk.h" 18889c2b7eSJerome Brunet #include "vid-pll-div.h" 19738f66d3SMichael Turquette 2027aad905SYixun Lan static DEFINE_SPINLOCK(meson_clk_lock); 21738f66d3SMichael Turquette 22dd601dbcSJerome Brunet static const struct pll_params_table gxbb_gp0_pll_params_table[] = { 23dd601dbcSJerome Brunet PLL_PARAMS(32, 1), 24dd601dbcSJerome Brunet PLL_PARAMS(33, 1), 25dd601dbcSJerome Brunet PLL_PARAMS(34, 1), 26dd601dbcSJerome Brunet PLL_PARAMS(35, 1), 27dd601dbcSJerome Brunet PLL_PARAMS(36, 1), 28dd601dbcSJerome Brunet PLL_PARAMS(37, 1), 29dd601dbcSJerome Brunet PLL_PARAMS(38, 1), 30dd601dbcSJerome Brunet PLL_PARAMS(39, 1), 31dd601dbcSJerome Brunet PLL_PARAMS(40, 1), 32dd601dbcSJerome Brunet PLL_PARAMS(41, 1), 33dd601dbcSJerome Brunet PLL_PARAMS(42, 1), 34dd601dbcSJerome Brunet PLL_PARAMS(43, 1), 35dd601dbcSJerome Brunet PLL_PARAMS(44, 1), 36dd601dbcSJerome Brunet PLL_PARAMS(45, 1), 37dd601dbcSJerome Brunet PLL_PARAMS(46, 1), 38dd601dbcSJerome Brunet PLL_PARAMS(47, 1), 39dd601dbcSJerome Brunet PLL_PARAMS(48, 1), 40dd601dbcSJerome Brunet PLL_PARAMS(49, 1), 41dd601dbcSJerome Brunet PLL_PARAMS(50, 1), 42dd601dbcSJerome Brunet PLL_PARAMS(51, 1), 43dd601dbcSJerome Brunet PLL_PARAMS(52, 1), 44dd601dbcSJerome Brunet PLL_PARAMS(53, 1), 45dd601dbcSJerome Brunet PLL_PARAMS(54, 1), 46dd601dbcSJerome Brunet PLL_PARAMS(55, 1), 47dd601dbcSJerome Brunet PLL_PARAMS(56, 1), 48dd601dbcSJerome Brunet PLL_PARAMS(57, 1), 49dd601dbcSJerome Brunet PLL_PARAMS(58, 1), 50dd601dbcSJerome Brunet PLL_PARAMS(59, 1), 51dd601dbcSJerome Brunet PLL_PARAMS(60, 1), 52dd601dbcSJerome Brunet PLL_PARAMS(61, 1), 53dd601dbcSJerome Brunet PLL_PARAMS(62, 1), 54738f66d3SMichael Turquette { /* sentinel */ }, 55738f66d3SMichael Turquette }; 56738f66d3SMichael Turquette 57dd601dbcSJerome Brunet static const struct pll_params_table gxl_gp0_pll_params_table[] = { 58dd601dbcSJerome Brunet PLL_PARAMS(42, 1), 59dd601dbcSJerome Brunet PLL_PARAMS(43, 1), 60dd601dbcSJerome Brunet PLL_PARAMS(44, 1), 61dd601dbcSJerome Brunet PLL_PARAMS(45, 1), 62dd601dbcSJerome Brunet PLL_PARAMS(46, 1), 63dd601dbcSJerome Brunet PLL_PARAMS(47, 1), 64dd601dbcSJerome Brunet PLL_PARAMS(48, 1), 65dd601dbcSJerome Brunet PLL_PARAMS(49, 1), 66dd601dbcSJerome Brunet PLL_PARAMS(50, 1), 67dd601dbcSJerome Brunet PLL_PARAMS(51, 1), 68dd601dbcSJerome Brunet PLL_PARAMS(52, 1), 69dd601dbcSJerome Brunet PLL_PARAMS(53, 1), 70dd601dbcSJerome Brunet PLL_PARAMS(54, 1), 71dd601dbcSJerome Brunet PLL_PARAMS(55, 1), 72dd601dbcSJerome Brunet PLL_PARAMS(56, 1), 73dd601dbcSJerome Brunet PLL_PARAMS(57, 1), 74dd601dbcSJerome Brunet PLL_PARAMS(58, 1), 75dd601dbcSJerome Brunet PLL_PARAMS(59, 1), 76dd601dbcSJerome Brunet PLL_PARAMS(60, 1), 77dd601dbcSJerome Brunet PLL_PARAMS(61, 1), 78dd601dbcSJerome Brunet PLL_PARAMS(62, 1), 79dd601dbcSJerome Brunet PLL_PARAMS(63, 1), 80dd601dbcSJerome Brunet PLL_PARAMS(64, 1), 81dd601dbcSJerome Brunet PLL_PARAMS(65, 1), 82dd601dbcSJerome Brunet PLL_PARAMS(66, 1), 830d48fc55SNeil Armstrong { /* sentinel */ }, 840d48fc55SNeil Armstrong }; 850d48fc55SNeil Armstrong 8687173557SJerome Brunet static struct clk_regmap gxbb_fixed_pll_dco = { 87722825dcSJerome Brunet .data = &(struct meson_clk_pll_data){ 88e40c7e3cSJerome Brunet .en = { 89e40c7e3cSJerome Brunet .reg_off = HHI_MPLL_CNTL, 90e40c7e3cSJerome Brunet .shift = 30, 91e40c7e3cSJerome Brunet .width = 1, 92e40c7e3cSJerome Brunet }, 93738f66d3SMichael Turquette .m = { 94738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL, 95738f66d3SMichael Turquette .shift = 0, 96738f66d3SMichael Turquette .width = 9, 97738f66d3SMichael Turquette }, 98738f66d3SMichael Turquette .n = { 99738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL, 100738f66d3SMichael Turquette .shift = 9, 101738f66d3SMichael Turquette .width = 5, 102738f66d3SMichael Turquette }, 10307f45e2eSJerome Brunet .frac = { 10407f45e2eSJerome Brunet .reg_off = HHI_MPLL_CNTL2, 10507f45e2eSJerome Brunet .shift = 0, 10607f45e2eSJerome Brunet .width = 12, 10707f45e2eSJerome Brunet }, 108722825dcSJerome Brunet .l = { 109722825dcSJerome Brunet .reg_off = HHI_MPLL_CNTL, 110722825dcSJerome Brunet .shift = 31, 111722825dcSJerome Brunet .width = 1, 112722825dcSJerome Brunet }, 113722825dcSJerome Brunet .rst = { 114722825dcSJerome Brunet .reg_off = HHI_MPLL_CNTL, 115722825dcSJerome Brunet .shift = 29, 116722825dcSJerome Brunet .width = 1, 117722825dcSJerome Brunet }, 118722825dcSJerome Brunet }, 119738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 12087173557SJerome Brunet .name = "fixed_pll_dco", 121738f66d3SMichael Turquette .ops = &meson_clk_pll_ro_ops, 1220dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 1230dea3f35SAlexandre Mergnat .fw_name = "xtal", 1240dea3f35SAlexandre Mergnat }, 125738f66d3SMichael Turquette .num_parents = 1, 126738f66d3SMichael Turquette }, 127738f66d3SMichael Turquette }; 128738f66d3SMichael Turquette 12987173557SJerome Brunet static struct clk_regmap gxbb_fixed_pll = { 13087173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 13187173557SJerome Brunet .offset = HHI_MPLL_CNTL, 13287173557SJerome Brunet .shift = 16, 13387173557SJerome Brunet .width = 2, 13487173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 13587173557SJerome Brunet }, 13687173557SJerome Brunet .hw.init = &(struct clk_init_data){ 13787173557SJerome Brunet .name = "fixed_pll", 13887173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 1390dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 1400dea3f35SAlexandre Mergnat &gxbb_fixed_pll_dco.hw 1410dea3f35SAlexandre Mergnat }, 14287173557SJerome Brunet .num_parents = 1, 14387173557SJerome Brunet /* 14487173557SJerome Brunet * This clock won't ever change at runtime so 14587173557SJerome Brunet * CLK_SET_RATE_PARENT is not required 14687173557SJerome Brunet */ 14787173557SJerome Brunet }, 14887173557SJerome Brunet }; 14987173557SJerome Brunet 1503c4fe763SJerome Brunet static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = { 1513c4fe763SJerome Brunet .mult = 2, 1523c4fe763SJerome Brunet .div = 1, 1533c4fe763SJerome Brunet .hw.init = &(struct clk_init_data){ 1543c4fe763SJerome Brunet .name = "hdmi_pll_pre_mult", 1553c4fe763SJerome Brunet .ops = &clk_fixed_factor_ops, 1560dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 1570dea3f35SAlexandre Mergnat .fw_name = "xtal", 1580dea3f35SAlexandre Mergnat }, 1593c4fe763SJerome Brunet .num_parents = 1, 1603c4fe763SJerome Brunet }, 1613c4fe763SJerome Brunet }; 1623c4fe763SJerome Brunet 16387173557SJerome Brunet static struct clk_regmap gxbb_hdmi_pll_dco = { 164722825dcSJerome Brunet .data = &(struct meson_clk_pll_data){ 165e40c7e3cSJerome Brunet .en = { 166e40c7e3cSJerome Brunet .reg_off = HHI_HDMI_PLL_CNTL, 167e40c7e3cSJerome Brunet .shift = 30, 168e40c7e3cSJerome Brunet .width = 1, 169e40c7e3cSJerome Brunet }, 170738f66d3SMichael Turquette .m = { 171738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL, 172738f66d3SMichael Turquette .shift = 0, 173738f66d3SMichael Turquette .width = 9, 174738f66d3SMichael Turquette }, 175738f66d3SMichael Turquette .n = { 176738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL, 177738f66d3SMichael Turquette .shift = 9, 178738f66d3SMichael Turquette .width = 5, 179738f66d3SMichael Turquette }, 180738f66d3SMichael Turquette .frac = { 181738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL2, 182738f66d3SMichael Turquette .shift = 0, 183738f66d3SMichael Turquette .width = 12, 184738f66d3SMichael Turquette }, 185722825dcSJerome Brunet .l = { 186722825dcSJerome Brunet .reg_off = HHI_HDMI_PLL_CNTL, 187722825dcSJerome Brunet .shift = 31, 188722825dcSJerome Brunet .width = 1, 189722825dcSJerome Brunet }, 190722825dcSJerome Brunet .rst = { 191722825dcSJerome Brunet .reg_off = HHI_HDMI_PLL_CNTL, 192722825dcSJerome Brunet .shift = 28, 193722825dcSJerome Brunet .width = 1, 194722825dcSJerome Brunet }, 195722825dcSJerome Brunet }, 196738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 19787173557SJerome Brunet .name = "hdmi_pll_dco", 198738f66d3SMichael Turquette .ops = &meson_clk_pll_ro_ops, 1990dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 2000dea3f35SAlexandre Mergnat &gxbb_hdmi_pll_pre_mult.hw 2010dea3f35SAlexandre Mergnat }, 202738f66d3SMichael Turquette .num_parents = 1, 2032303a9caSJerome Brunet /* 2042303a9caSJerome Brunet * Display directly handle hdmi pll registers ATM, we need 2052303a9caSJerome Brunet * NOCACHE to keep our view of the clock as accurate as possible 2062303a9caSJerome Brunet */ 207738f66d3SMichael Turquette .flags = CLK_GET_RATE_NOCACHE, 208738f66d3SMichael Turquette }, 209738f66d3SMichael Turquette }; 210738f66d3SMichael Turquette 2110058502fSNeil Armstrong static struct clk_regmap gxl_hdmi_pll_dco = { 2120058502fSNeil Armstrong .data = &(struct meson_clk_pll_data){ 2130058502fSNeil Armstrong .en = { 2140058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL, 2150058502fSNeil Armstrong .shift = 30, 2160058502fSNeil Armstrong .width = 1, 2170058502fSNeil Armstrong }, 2180058502fSNeil Armstrong .m = { 2190058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL, 2200058502fSNeil Armstrong .shift = 0, 2210058502fSNeil Armstrong .width = 9, 2220058502fSNeil Armstrong }, 2230058502fSNeil Armstrong .n = { 2240058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL, 2250058502fSNeil Armstrong .shift = 9, 2260058502fSNeil Armstrong .width = 5, 2270058502fSNeil Armstrong }, 22821310c39SNeil Armstrong /* 22921310c39SNeil Armstrong * On gxl, there is a register shift due to 23021310c39SNeil Armstrong * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb, 23121310c39SNeil Armstrong * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB 23221310c39SNeil Armstrong * instead which is defined at the same offset. 23321310c39SNeil Armstrong */ 2340058502fSNeil Armstrong .frac = { 2350058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL2, 2360058502fSNeil Armstrong .shift = 0, 23721310c39SNeil Armstrong .width = 10, 2380058502fSNeil Armstrong }, 2390058502fSNeil Armstrong .l = { 2400058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL, 2410058502fSNeil Armstrong .shift = 31, 2420058502fSNeil Armstrong .width = 1, 2430058502fSNeil Armstrong }, 2440058502fSNeil Armstrong .rst = { 2450058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL, 2460058502fSNeil Armstrong .shift = 28, 2470058502fSNeil Armstrong .width = 1, 2480058502fSNeil Armstrong }, 2490058502fSNeil Armstrong }, 2500058502fSNeil Armstrong .hw.init = &(struct clk_init_data){ 2510058502fSNeil Armstrong .name = "hdmi_pll_dco", 2520058502fSNeil Armstrong .ops = &meson_clk_pll_ro_ops, 2530dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 2540dea3f35SAlexandre Mergnat .fw_name = "xtal", 2550dea3f35SAlexandre Mergnat }, 2560058502fSNeil Armstrong .num_parents = 1, 2570058502fSNeil Armstrong /* 2580058502fSNeil Armstrong * Display directly handle hdmi pll registers ATM, we need 2590058502fSNeil Armstrong * NOCACHE to keep our view of the clock as accurate as possible 2600058502fSNeil Armstrong */ 2610058502fSNeil Armstrong .flags = CLK_GET_RATE_NOCACHE, 2620058502fSNeil Armstrong }, 2630058502fSNeil Armstrong }; 2640058502fSNeil Armstrong 26587173557SJerome Brunet static struct clk_regmap gxbb_hdmi_pll_od = { 26687173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 26787173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL2, 26887173557SJerome Brunet .shift = 16, 26987173557SJerome Brunet .width = 2, 27087173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 27187173557SJerome Brunet }, 27287173557SJerome Brunet .hw.init = &(struct clk_init_data){ 27387173557SJerome Brunet .name = "hdmi_pll_od", 27487173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 2750dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 2760dea3f35SAlexandre Mergnat &gxbb_hdmi_pll_dco.hw 2770dea3f35SAlexandre Mergnat }, 27887173557SJerome Brunet .num_parents = 1, 27987173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 28087173557SJerome Brunet }, 28187173557SJerome Brunet }; 28287173557SJerome Brunet 28387173557SJerome Brunet static struct clk_regmap gxbb_hdmi_pll_od2 = { 28487173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 28587173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL2, 28687173557SJerome Brunet .shift = 22, 28787173557SJerome Brunet .width = 2, 28887173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 28987173557SJerome Brunet }, 29087173557SJerome Brunet .hw.init = &(struct clk_init_data){ 29187173557SJerome Brunet .name = "hdmi_pll_od2", 29287173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 2930dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 2940dea3f35SAlexandre Mergnat &gxbb_hdmi_pll_od.hw 2950dea3f35SAlexandre Mergnat }, 29687173557SJerome Brunet .num_parents = 1, 29787173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 29887173557SJerome Brunet }, 29987173557SJerome Brunet }; 30087173557SJerome Brunet 30187173557SJerome Brunet static struct clk_regmap gxbb_hdmi_pll = { 30287173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 30387173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL2, 30487173557SJerome Brunet .shift = 18, 30587173557SJerome Brunet .width = 2, 30687173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 30787173557SJerome Brunet }, 30887173557SJerome Brunet .hw.init = &(struct clk_init_data){ 30987173557SJerome Brunet .name = "hdmi_pll", 31087173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 3110dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 3120dea3f35SAlexandre Mergnat &gxbb_hdmi_pll_od2.hw 3130dea3f35SAlexandre Mergnat }, 31487173557SJerome Brunet .num_parents = 1, 31587173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 31687173557SJerome Brunet }, 31787173557SJerome Brunet }; 31887173557SJerome Brunet 31987173557SJerome Brunet static struct clk_regmap gxl_hdmi_pll_od = { 32087173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 32187173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL + 8, 32287173557SJerome Brunet .shift = 21, 32387173557SJerome Brunet .width = 2, 32487173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 32587173557SJerome Brunet }, 32687173557SJerome Brunet .hw.init = &(struct clk_init_data){ 32787173557SJerome Brunet .name = "hdmi_pll_od", 32887173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 3290dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 3300dea3f35SAlexandre Mergnat &gxl_hdmi_pll_dco.hw 3310dea3f35SAlexandre Mergnat }, 33287173557SJerome Brunet .num_parents = 1, 33387173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 33487173557SJerome Brunet }, 33587173557SJerome Brunet }; 33687173557SJerome Brunet 33787173557SJerome Brunet static struct clk_regmap gxl_hdmi_pll_od2 = { 33887173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 33987173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL + 8, 34087173557SJerome Brunet .shift = 23, 34187173557SJerome Brunet .width = 2, 34287173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 34387173557SJerome Brunet }, 34487173557SJerome Brunet .hw.init = &(struct clk_init_data){ 34587173557SJerome Brunet .name = "hdmi_pll_od2", 34687173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 3470dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 3480dea3f35SAlexandre Mergnat &gxl_hdmi_pll_od.hw 3490dea3f35SAlexandre Mergnat }, 35087173557SJerome Brunet .num_parents = 1, 35187173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 35287173557SJerome Brunet }, 35387173557SJerome Brunet }; 35487173557SJerome Brunet 355722825dcSJerome Brunet static struct clk_regmap gxl_hdmi_pll = { 35687173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 35787173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL + 8, 35887173557SJerome Brunet .shift = 19, 35987173557SJerome Brunet .width = 2, 36087173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 36187173557SJerome Brunet }, 36287173557SJerome Brunet .hw.init = &(struct clk_init_data){ 36387173557SJerome Brunet .name = "hdmi_pll", 36487173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 3650dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 3660dea3f35SAlexandre Mergnat &gxl_hdmi_pll_od2.hw 3670dea3f35SAlexandre Mergnat }, 36887173557SJerome Brunet .num_parents = 1, 36987173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 37087173557SJerome Brunet }, 37187173557SJerome Brunet }; 37287173557SJerome Brunet 37387173557SJerome Brunet static struct clk_regmap gxbb_sys_pll_dco = { 374722825dcSJerome Brunet .data = &(struct meson_clk_pll_data){ 375e40c7e3cSJerome Brunet .en = { 37687173557SJerome Brunet .reg_off = HHI_SYS_PLL_CNTL, 377e40c7e3cSJerome Brunet .shift = 30, 378e40c7e3cSJerome Brunet .width = 1, 379e40c7e3cSJerome Brunet }, 38069d92293SJerome Brunet .m = { 38187173557SJerome Brunet .reg_off = HHI_SYS_PLL_CNTL, 38269d92293SJerome Brunet .shift = 0, 38369d92293SJerome Brunet .width = 9, 38469d92293SJerome Brunet }, 38569d92293SJerome Brunet .n = { 38687173557SJerome Brunet .reg_off = HHI_SYS_PLL_CNTL, 38769d92293SJerome Brunet .shift = 9, 38869d92293SJerome Brunet .width = 5, 38969d92293SJerome Brunet }, 390722825dcSJerome Brunet .l = { 39187173557SJerome Brunet .reg_off = HHI_SYS_PLL_CNTL, 392722825dcSJerome Brunet .shift = 31, 393722825dcSJerome Brunet .width = 1, 394722825dcSJerome Brunet }, 395722825dcSJerome Brunet .rst = { 39687173557SJerome Brunet .reg_off = HHI_SYS_PLL_CNTL, 397722825dcSJerome Brunet .shift = 29, 398722825dcSJerome Brunet .width = 1, 399722825dcSJerome Brunet }, 400722825dcSJerome Brunet }, 40169d92293SJerome Brunet .hw.init = &(struct clk_init_data){ 40287173557SJerome Brunet .name = "sys_pll_dco", 40369d92293SJerome Brunet .ops = &meson_clk_pll_ro_ops, 4040dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 4050dea3f35SAlexandre Mergnat .fw_name = "xtal", 4060dea3f35SAlexandre Mergnat }, 40769d92293SJerome Brunet .num_parents = 1, 40869d92293SJerome Brunet }, 40969d92293SJerome Brunet }; 41069d92293SJerome Brunet 411722825dcSJerome Brunet static struct clk_regmap gxbb_sys_pll = { 41287173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 41387173557SJerome Brunet .offset = HHI_SYS_PLL_CNTL, 414738f66d3SMichael Turquette .shift = 10, 415738f66d3SMichael Turquette .width = 2, 41687173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 417722825dcSJerome Brunet }, 418738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 419738f66d3SMichael Turquette .name = "sys_pll", 42087173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 4210dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 4220dea3f35SAlexandre Mergnat &gxbb_sys_pll_dco.hw 4230dea3f35SAlexandre Mergnat }, 424738f66d3SMichael Turquette .num_parents = 1, 42587173557SJerome Brunet .flags = CLK_SET_RATE_PARENT, 426738f66d3SMichael Turquette }, 427738f66d3SMichael Turquette }; 428738f66d3SMichael Turquette 4295d1c04ddSStephen Boyd static const struct reg_sequence gxbb_gp0_init_regs[] = { 430722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 }, 431722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 }, 432722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d }, 433e194401cSNeil Armstrong }; 434e194401cSNeil Armstrong 43587173557SJerome Brunet static struct clk_regmap gxbb_gp0_pll_dco = { 436722825dcSJerome Brunet .data = &(struct meson_clk_pll_data){ 437e40c7e3cSJerome Brunet .en = { 438e40c7e3cSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 439e40c7e3cSJerome Brunet .shift = 30, 440e40c7e3cSJerome Brunet .width = 1, 441e40c7e3cSJerome Brunet }, 442738f66d3SMichael Turquette .m = { 443738f66d3SMichael Turquette .reg_off = HHI_GP0_PLL_CNTL, 444738f66d3SMichael Turquette .shift = 0, 445738f66d3SMichael Turquette .width = 9, 446738f66d3SMichael Turquette }, 447738f66d3SMichael Turquette .n = { 448738f66d3SMichael Turquette .reg_off = HHI_GP0_PLL_CNTL, 449738f66d3SMichael Turquette .shift = 9, 450738f66d3SMichael Turquette .width = 5, 451738f66d3SMichael Turquette }, 452722825dcSJerome Brunet .l = { 453722825dcSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 454722825dcSJerome Brunet .shift = 31, 455722825dcSJerome Brunet .width = 1, 456e194401cSNeil Armstrong }, 457722825dcSJerome Brunet .rst = { 458722825dcSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 459722825dcSJerome Brunet .shift = 29, 460722825dcSJerome Brunet .width = 1, 461722825dcSJerome Brunet }, 462dd601dbcSJerome Brunet .table = gxbb_gp0_pll_params_table, 463722825dcSJerome Brunet .init_regs = gxbb_gp0_init_regs, 464722825dcSJerome Brunet .init_count = ARRAY_SIZE(gxbb_gp0_init_regs), 465722825dcSJerome Brunet }, 4660d48fc55SNeil Armstrong .hw.init = &(struct clk_init_data){ 46787173557SJerome Brunet .name = "gp0_pll_dco", 4680d48fc55SNeil Armstrong .ops = &meson_clk_pll_ops, 4690dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 4700dea3f35SAlexandre Mergnat .fw_name = "xtal", 4710dea3f35SAlexandre Mergnat }, 4720d48fc55SNeil Armstrong .num_parents = 1, 4730d48fc55SNeil Armstrong }, 4740d48fc55SNeil Armstrong }; 4750d48fc55SNeil Armstrong 4765d1c04ddSStephen Boyd static const struct reg_sequence gxl_gp0_init_regs[] = { 477c77de0e5SJerome Brunet { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, 478722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, 479722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 480722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 481722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 4820d48fc55SNeil Armstrong }; 4830d48fc55SNeil Armstrong 48487173557SJerome Brunet static struct clk_regmap gxl_gp0_pll_dco = { 485722825dcSJerome Brunet .data = &(struct meson_clk_pll_data){ 486e40c7e3cSJerome Brunet .en = { 487e40c7e3cSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 488e40c7e3cSJerome Brunet .shift = 30, 489e40c7e3cSJerome Brunet .width = 1, 490e40c7e3cSJerome Brunet }, 4910d48fc55SNeil Armstrong .m = { 4920d48fc55SNeil Armstrong .reg_off = HHI_GP0_PLL_CNTL, 4930d48fc55SNeil Armstrong .shift = 0, 4940d48fc55SNeil Armstrong .width = 9, 4950d48fc55SNeil Armstrong }, 4960d48fc55SNeil Armstrong .n = { 4970d48fc55SNeil Armstrong .reg_off = HHI_GP0_PLL_CNTL, 4980d48fc55SNeil Armstrong .shift = 9, 4990d48fc55SNeil Armstrong .width = 5, 5000d48fc55SNeil Armstrong }, 501c77de0e5SJerome Brunet .frac = { 502c77de0e5SJerome Brunet .reg_off = HHI_GP0_PLL_CNTL1, 503c77de0e5SJerome Brunet .shift = 0, 504c77de0e5SJerome Brunet .width = 10, 505c77de0e5SJerome Brunet }, 506722825dcSJerome Brunet .l = { 507722825dcSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 508722825dcSJerome Brunet .shift = 31, 509722825dcSJerome Brunet .width = 1, 5100d48fc55SNeil Armstrong }, 511722825dcSJerome Brunet .rst = { 512722825dcSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 513722825dcSJerome Brunet .shift = 29, 514722825dcSJerome Brunet .width = 1, 515722825dcSJerome Brunet }, 516dd601dbcSJerome Brunet .table = gxl_gp0_pll_params_table, 517722825dcSJerome Brunet .init_regs = gxl_gp0_init_regs, 518722825dcSJerome Brunet .init_count = ARRAY_SIZE(gxl_gp0_init_regs), 519722825dcSJerome Brunet }, 520738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 52187173557SJerome Brunet .name = "gp0_pll_dco", 522738f66d3SMichael Turquette .ops = &meson_clk_pll_ops, 5230dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 5240dea3f35SAlexandre Mergnat .fw_name = "xtal", 5250dea3f35SAlexandre Mergnat }, 526738f66d3SMichael Turquette .num_parents = 1, 527738f66d3SMichael Turquette }, 528738f66d3SMichael Turquette }; 529738f66d3SMichael Turquette 53087173557SJerome Brunet static struct clk_regmap gxbb_gp0_pll = { 53187173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 53287173557SJerome Brunet .offset = HHI_GP0_PLL_CNTL, 53387173557SJerome Brunet .shift = 16, 53487173557SJerome Brunet .width = 2, 53587173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 53687173557SJerome Brunet }, 53787173557SJerome Brunet .hw.init = &(struct clk_init_data){ 53887173557SJerome Brunet .name = "gp0_pll", 53987173557SJerome Brunet .ops = &clk_regmap_divider_ops, 5400dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 5410dea3f35SAlexandre Mergnat /* 5420dea3f35SAlexandre Mergnat * Note: 5430dea3f35SAlexandre Mergnat * GXL and GXBB have different gp0_pll_dco (with 5440dea3f35SAlexandre Mergnat * different struct clk_hw). We fallback to the global 5450dea3f35SAlexandre Mergnat * naming string mechanism so gp0_pll picks up the 5460dea3f35SAlexandre Mergnat * appropriate one. 5470dea3f35SAlexandre Mergnat */ 5480dea3f35SAlexandre Mergnat .name = "gp0_pll_dco", 5490dea3f35SAlexandre Mergnat .index = -1, 5500dea3f35SAlexandre Mergnat }, 55187173557SJerome Brunet .num_parents = 1, 55287173557SJerome Brunet .flags = CLK_SET_RATE_PARENT, 55387173557SJerome Brunet }, 55487173557SJerome Brunet }; 55587173557SJerome Brunet 55605f81440SJerome Brunet static struct clk_fixed_factor gxbb_fclk_div2_div = { 557738f66d3SMichael Turquette .mult = 1, 558738f66d3SMichael Turquette .div = 2, 559738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 56005f81440SJerome Brunet .name = "fclk_div2_div", 561738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 5620dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 5630dea3f35SAlexandre Mergnat &gxbb_fixed_pll.hw 5640dea3f35SAlexandre Mergnat }, 565738f66d3SMichael Turquette .num_parents = 1, 566738f66d3SMichael Turquette }, 567738f66d3SMichael Turquette }; 568738f66d3SMichael Turquette 56905f81440SJerome Brunet static struct clk_regmap gxbb_fclk_div2 = { 57005f81440SJerome Brunet .data = &(struct clk_regmap_gate_data){ 57105f81440SJerome Brunet .offset = HHI_MPLL_CNTL6, 57205f81440SJerome Brunet .bit_idx = 27, 57305f81440SJerome Brunet }, 57405f81440SJerome Brunet .hw.init = &(struct clk_init_data){ 57505f81440SJerome Brunet .name = "fclk_div2", 57605f81440SJerome Brunet .ops = &clk_regmap_gate_ops, 5770dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 5780dea3f35SAlexandre Mergnat &gxbb_fclk_div2_div.hw 5790dea3f35SAlexandre Mergnat }, 58005f81440SJerome Brunet .num_parents = 1, 581c987ac6fSNeil Armstrong .flags = CLK_IS_CRITICAL, 58205f81440SJerome Brunet }, 58305f81440SJerome Brunet }; 58405f81440SJerome Brunet 58505f81440SJerome Brunet static struct clk_fixed_factor gxbb_fclk_div3_div = { 586738f66d3SMichael Turquette .mult = 1, 587738f66d3SMichael Turquette .div = 3, 588738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 58905f81440SJerome Brunet .name = "fclk_div3_div", 590738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 5910dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 592738f66d3SMichael Turquette .num_parents = 1, 593738f66d3SMichael Turquette }, 594738f66d3SMichael Turquette }; 595738f66d3SMichael Turquette 59605f81440SJerome Brunet static struct clk_regmap gxbb_fclk_div3 = { 59705f81440SJerome Brunet .data = &(struct clk_regmap_gate_data){ 59805f81440SJerome Brunet .offset = HHI_MPLL_CNTL6, 59905f81440SJerome Brunet .bit_idx = 28, 60005f81440SJerome Brunet }, 60105f81440SJerome Brunet .hw.init = &(struct clk_init_data){ 60205f81440SJerome Brunet .name = "fclk_div3", 60305f81440SJerome Brunet .ops = &clk_regmap_gate_ops, 6040dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 6050dea3f35SAlexandre Mergnat &gxbb_fclk_div3_div.hw 6060dea3f35SAlexandre Mergnat }, 60705f81440SJerome Brunet .num_parents = 1, 608e2576c8bSChristian Hewitt /* 609e2576c8bSChristian Hewitt * FIXME: 610e2576c8bSChristian Hewitt * This clock, as fdiv2, is used by the SCPI FW and is required 611e2576c8bSChristian Hewitt * by the platform to operate correctly. 612e2576c8bSChristian Hewitt * Until the following condition are met, we need this clock to 613e2576c8bSChristian Hewitt * be marked as critical: 614e2576c8bSChristian Hewitt * a) The SCPI generic driver claims and enable all the clocks 615e2576c8bSChristian Hewitt * it needs 616e2576c8bSChristian Hewitt * b) CCF has a clock hand-off mechanism to make the sure the 617e2576c8bSChristian Hewitt * clock stays on until the proper driver comes along 618e2576c8bSChristian Hewitt */ 619e2576c8bSChristian Hewitt .flags = CLK_IS_CRITICAL, 62005f81440SJerome Brunet }, 62105f81440SJerome Brunet }; 62205f81440SJerome Brunet 62305f81440SJerome Brunet static struct clk_fixed_factor gxbb_fclk_div4_div = { 624738f66d3SMichael Turquette .mult = 1, 625738f66d3SMichael Turquette .div = 4, 626738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 62705f81440SJerome Brunet .name = "fclk_div4_div", 628738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 6290dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 630738f66d3SMichael Turquette .num_parents = 1, 631738f66d3SMichael Turquette }, 632738f66d3SMichael Turquette }; 633738f66d3SMichael Turquette 63405f81440SJerome Brunet static struct clk_regmap gxbb_fclk_div4 = { 63505f81440SJerome Brunet .data = &(struct clk_regmap_gate_data){ 63605f81440SJerome Brunet .offset = HHI_MPLL_CNTL6, 63705f81440SJerome Brunet .bit_idx = 29, 63805f81440SJerome Brunet }, 63905f81440SJerome Brunet .hw.init = &(struct clk_init_data){ 64005f81440SJerome Brunet .name = "fclk_div4", 64105f81440SJerome Brunet .ops = &clk_regmap_gate_ops, 6420dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 6430dea3f35SAlexandre Mergnat &gxbb_fclk_div4_div.hw 6440dea3f35SAlexandre Mergnat }, 64505f81440SJerome Brunet .num_parents = 1, 64605f81440SJerome Brunet }, 64705f81440SJerome Brunet }; 64805f81440SJerome Brunet 64905f81440SJerome Brunet static struct clk_fixed_factor gxbb_fclk_div5_div = { 650738f66d3SMichael Turquette .mult = 1, 651738f66d3SMichael Turquette .div = 5, 652738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 65305f81440SJerome Brunet .name = "fclk_div5_div", 654738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 6550dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 656738f66d3SMichael Turquette .num_parents = 1, 657738f66d3SMichael Turquette }, 658738f66d3SMichael Turquette }; 659738f66d3SMichael Turquette 66005f81440SJerome Brunet static struct clk_regmap gxbb_fclk_div5 = { 66105f81440SJerome Brunet .data = &(struct clk_regmap_gate_data){ 66205f81440SJerome Brunet .offset = HHI_MPLL_CNTL6, 66305f81440SJerome Brunet .bit_idx = 30, 66405f81440SJerome Brunet }, 66505f81440SJerome Brunet .hw.init = &(struct clk_init_data){ 66605f81440SJerome Brunet .name = "fclk_div5", 66705f81440SJerome Brunet .ops = &clk_regmap_gate_ops, 6680dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 6690dea3f35SAlexandre Mergnat &gxbb_fclk_div5_div.hw 6700dea3f35SAlexandre Mergnat }, 67105f81440SJerome Brunet .num_parents = 1, 67205f81440SJerome Brunet }, 67305f81440SJerome Brunet }; 67405f81440SJerome Brunet 67505f81440SJerome Brunet static struct clk_fixed_factor gxbb_fclk_div7_div = { 676738f66d3SMichael Turquette .mult = 1, 677738f66d3SMichael Turquette .div = 7, 678738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 67905f81440SJerome Brunet .name = "fclk_div7_div", 680738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 6810dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 682738f66d3SMichael Turquette .num_parents = 1, 683738f66d3SMichael Turquette }, 684738f66d3SMichael Turquette }; 685738f66d3SMichael Turquette 68605f81440SJerome Brunet static struct clk_regmap gxbb_fclk_div7 = { 68705f81440SJerome Brunet .data = &(struct clk_regmap_gate_data){ 68805f81440SJerome Brunet .offset = HHI_MPLL_CNTL6, 68905f81440SJerome Brunet .bit_idx = 31, 69005f81440SJerome Brunet }, 69105f81440SJerome Brunet .hw.init = &(struct clk_init_data){ 69205f81440SJerome Brunet .name = "fclk_div7", 69305f81440SJerome Brunet .ops = &clk_regmap_gate_ops, 6940dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 6950dea3f35SAlexandre Mergnat &gxbb_fclk_div7_div.hw 6960dea3f35SAlexandre Mergnat }, 69705f81440SJerome Brunet .num_parents = 1, 69805f81440SJerome Brunet }, 69905f81440SJerome Brunet }; 70005f81440SJerome Brunet 701513b67acSJerome Brunet static struct clk_regmap gxbb_mpll_prediv = { 702513b67acSJerome Brunet .data = &(struct clk_regmap_div_data){ 703513b67acSJerome Brunet .offset = HHI_MPLL_CNTL5, 704513b67acSJerome Brunet .shift = 12, 705513b67acSJerome Brunet .width = 1, 706513b67acSJerome Brunet }, 707513b67acSJerome Brunet .hw.init = &(struct clk_init_data){ 708513b67acSJerome Brunet .name = "mpll_prediv", 709513b67acSJerome Brunet .ops = &clk_regmap_divider_ro_ops, 7100dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 711513b67acSJerome Brunet .num_parents = 1, 712513b67acSJerome Brunet }, 713513b67acSJerome Brunet }; 714513b67acSJerome Brunet 715d610b54fSJerome Brunet static struct clk_regmap gxbb_mpll0_div = { 716c763e61aSJerome Brunet .data = &(struct meson_clk_mpll_data){ 717738f66d3SMichael Turquette .sdm = { 718738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL7, 719738f66d3SMichael Turquette .shift = 0, 720738f66d3SMichael Turquette .width = 14, 721738f66d3SMichael Turquette }, 722007e6e5cSJerome Brunet .sdm_en = { 723*ff54938dSMartin Blumenstingl .reg_off = HHI_MPLL_CNTL, 724*ff54938dSMartin Blumenstingl .shift = 25, 725*ff54938dSMartin Blumenstingl .width = 1, 726*ff54938dSMartin Blumenstingl }, 727*ff54938dSMartin Blumenstingl .n2 = { 728*ff54938dSMartin Blumenstingl .reg_off = HHI_MPLL_CNTL7, 729*ff54938dSMartin Blumenstingl .shift = 16, 730*ff54938dSMartin Blumenstingl .width = 9, 731*ff54938dSMartin Blumenstingl }, 732*ff54938dSMartin Blumenstingl .lock = &meson_clk_lock, 733*ff54938dSMartin Blumenstingl }, 734*ff54938dSMartin Blumenstingl .hw.init = &(struct clk_init_data){ 735*ff54938dSMartin Blumenstingl .name = "mpll0_div", 736*ff54938dSMartin Blumenstingl .ops = &meson_clk_mpll_ops, 737*ff54938dSMartin Blumenstingl .parent_hws = (const struct clk_hw *[]) { 738*ff54938dSMartin Blumenstingl &gxbb_mpll_prediv.hw 739*ff54938dSMartin Blumenstingl }, 740*ff54938dSMartin Blumenstingl .num_parents = 1, 741*ff54938dSMartin Blumenstingl }, 742*ff54938dSMartin Blumenstingl }; 743*ff54938dSMartin Blumenstingl 744*ff54938dSMartin Blumenstingl static struct clk_regmap gxl_mpll0_div = { 745*ff54938dSMartin Blumenstingl .data = &(struct meson_clk_mpll_data){ 746*ff54938dSMartin Blumenstingl .sdm = { 747*ff54938dSMartin Blumenstingl .reg_off = HHI_MPLL_CNTL7, 748*ff54938dSMartin Blumenstingl .shift = 0, 749*ff54938dSMartin Blumenstingl .width = 14, 750*ff54938dSMartin Blumenstingl }, 751*ff54938dSMartin Blumenstingl .sdm_en = { 752007e6e5cSJerome Brunet .reg_off = HHI_MPLL_CNTL7, 753007e6e5cSJerome Brunet .shift = 15, 754007e6e5cSJerome Brunet .width = 1, 755007e6e5cSJerome Brunet }, 756738f66d3SMichael Turquette .n2 = { 757738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL7, 758738f66d3SMichael Turquette .shift = 16, 759738f66d3SMichael Turquette .width = 9, 760738f66d3SMichael Turquette }, 76127aad905SYixun Lan .lock = &meson_clk_lock, 762c763e61aSJerome Brunet }, 763738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 764d610b54fSJerome Brunet .name = "mpll0_div", 765d610b54fSJerome Brunet .ops = &meson_clk_mpll_ops, 7660dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 7670dea3f35SAlexandre Mergnat &gxbb_mpll_prediv.hw 7680dea3f35SAlexandre Mergnat }, 769d610b54fSJerome Brunet .num_parents = 1, 770d610b54fSJerome Brunet }, 771d610b54fSJerome Brunet }; 772d610b54fSJerome Brunet 773d610b54fSJerome Brunet static struct clk_regmap gxbb_mpll0 = { 774d610b54fSJerome Brunet .data = &(struct clk_regmap_gate_data){ 775d610b54fSJerome Brunet .offset = HHI_MPLL_CNTL7, 776d610b54fSJerome Brunet .bit_idx = 14, 777d610b54fSJerome Brunet }, 778d610b54fSJerome Brunet .hw.init = &(struct clk_init_data){ 779738f66d3SMichael Turquette .name = "mpll0", 780d610b54fSJerome Brunet .ops = &clk_regmap_gate_ops, 781*ff54938dSMartin Blumenstingl .parent_data = &(const struct clk_parent_data) { 782*ff54938dSMartin Blumenstingl /* 783*ff54938dSMartin Blumenstingl * Note: 784*ff54938dSMartin Blumenstingl * GXL and GXBB have different SDM_EN registers. We 785*ff54938dSMartin Blumenstingl * fallback to the global naming string mechanism so 786*ff54938dSMartin Blumenstingl * mpll0_div picks up the appropriate one. 787*ff54938dSMartin Blumenstingl */ 788*ff54938dSMartin Blumenstingl .name = "mpll0_div", 789*ff54938dSMartin Blumenstingl .index = -1, 790*ff54938dSMartin Blumenstingl }, 791d610b54fSJerome Brunet .num_parents = 1, 792d610b54fSJerome Brunet .flags = CLK_SET_RATE_PARENT, 793d610b54fSJerome Brunet }, 794d610b54fSJerome Brunet }; 795d610b54fSJerome Brunet 796d610b54fSJerome Brunet static struct clk_regmap gxbb_mpll1_div = { 797d610b54fSJerome Brunet .data = &(struct meson_clk_mpll_data){ 798d610b54fSJerome Brunet .sdm = { 799d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL8, 800d610b54fSJerome Brunet .shift = 0, 801d610b54fSJerome Brunet .width = 14, 802d610b54fSJerome Brunet }, 803d610b54fSJerome Brunet .sdm_en = { 804d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL8, 805d610b54fSJerome Brunet .shift = 15, 806d610b54fSJerome Brunet .width = 1, 807d610b54fSJerome Brunet }, 808d610b54fSJerome Brunet .n2 = { 809d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL8, 810d610b54fSJerome Brunet .shift = 16, 811d610b54fSJerome Brunet .width = 9, 812d610b54fSJerome Brunet }, 813d610b54fSJerome Brunet .lock = &meson_clk_lock, 814d610b54fSJerome Brunet }, 815d610b54fSJerome Brunet .hw.init = &(struct clk_init_data){ 816d610b54fSJerome Brunet .name = "mpll1_div", 81705b43aa2SJerome Brunet .ops = &meson_clk_mpll_ops, 8180dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 8190dea3f35SAlexandre Mergnat &gxbb_mpll_prediv.hw 8200dea3f35SAlexandre Mergnat }, 821738f66d3SMichael Turquette .num_parents = 1, 822738f66d3SMichael Turquette }, 823738f66d3SMichael Turquette }; 824738f66d3SMichael Turquette 825c763e61aSJerome Brunet static struct clk_regmap gxbb_mpll1 = { 826d610b54fSJerome Brunet .data = &(struct clk_regmap_gate_data){ 827d610b54fSJerome Brunet .offset = HHI_MPLL_CNTL8, 828d610b54fSJerome Brunet .bit_idx = 14, 829d610b54fSJerome Brunet }, 830d610b54fSJerome Brunet .hw.init = &(struct clk_init_data){ 831d610b54fSJerome Brunet .name = "mpll1", 832d610b54fSJerome Brunet .ops = &clk_regmap_gate_ops, 8330dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw }, 834d610b54fSJerome Brunet .num_parents = 1, 835d610b54fSJerome Brunet .flags = CLK_SET_RATE_PARENT, 836d610b54fSJerome Brunet }, 837d610b54fSJerome Brunet }; 838d610b54fSJerome Brunet 839d610b54fSJerome Brunet static struct clk_regmap gxbb_mpll2_div = { 840c763e61aSJerome Brunet .data = &(struct meson_clk_mpll_data){ 841738f66d3SMichael Turquette .sdm = { 842d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL9, 843738f66d3SMichael Turquette .shift = 0, 844738f66d3SMichael Turquette .width = 14, 845738f66d3SMichael Turquette }, 846007e6e5cSJerome Brunet .sdm_en = { 847d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL9, 848007e6e5cSJerome Brunet .shift = 15, 849007e6e5cSJerome Brunet .width = 1, 850007e6e5cSJerome Brunet }, 851738f66d3SMichael Turquette .n2 = { 852d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL9, 853738f66d3SMichael Turquette .shift = 16, 854738f66d3SMichael Turquette .width = 9, 855738f66d3SMichael Turquette }, 85627aad905SYixun Lan .lock = &meson_clk_lock, 857c763e61aSJerome Brunet }, 858738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 859d610b54fSJerome Brunet .name = "mpll2_div", 86005b43aa2SJerome Brunet .ops = &meson_clk_mpll_ops, 8610dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 8620dea3f35SAlexandre Mergnat &gxbb_mpll_prediv.hw 8630dea3f35SAlexandre Mergnat }, 864738f66d3SMichael Turquette .num_parents = 1, 865738f66d3SMichael Turquette }, 866738f66d3SMichael Turquette }; 867738f66d3SMichael Turquette 868c763e61aSJerome Brunet static struct clk_regmap gxbb_mpll2 = { 869d610b54fSJerome Brunet .data = &(struct clk_regmap_gate_data){ 870d610b54fSJerome Brunet .offset = HHI_MPLL_CNTL9, 871d610b54fSJerome Brunet .bit_idx = 14, 872c763e61aSJerome Brunet }, 873738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 874738f66d3SMichael Turquette .name = "mpll2", 875d610b54fSJerome Brunet .ops = &clk_regmap_gate_ops, 8760dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw }, 877738f66d3SMichael Turquette .num_parents = 1, 878d610b54fSJerome Brunet .flags = CLK_SET_RATE_PARENT, 879738f66d3SMichael Turquette }, 880738f66d3SMichael Turquette }; 881738f66d3SMichael Turquette 882215c80a7SJerome Brunet static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 8830dea3f35SAlexandre Mergnat static const struct clk_parent_data clk81_parent_data[] = { 8840dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 8850dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div7.hw }, 8860dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll1.hw }, 8870dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll2.hw }, 8880dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div4.hw }, 8890dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 8900dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 891215c80a7SJerome Brunet }; 892738f66d3SMichael Turquette 8932513a28cSJerome Brunet static struct clk_regmap gxbb_mpeg_clk_sel = { 8942513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 8952513a28cSJerome Brunet .offset = HHI_MPEG_CLK_CNTL, 896738f66d3SMichael Turquette .mask = 0x7, 897738f66d3SMichael Turquette .shift = 12, 898738f66d3SMichael Turquette .table = mux_table_clk81, 8992513a28cSJerome Brunet }, 900738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 901738f66d3SMichael Turquette .name = "mpeg_clk_sel", 9022513a28cSJerome Brunet .ops = &clk_regmap_mux_ro_ops, 903738f66d3SMichael Turquette /* 904215c80a7SJerome Brunet * bits 14:12 selects from 8 possible parents: 905738f66d3SMichael Turquette * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 906738f66d3SMichael Turquette * fclk_div4, fclk_div3, fclk_div5 907738f66d3SMichael Turquette */ 9080dea3f35SAlexandre Mergnat .parent_data = clk81_parent_data, 9090dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(clk81_parent_data), 910738f66d3SMichael Turquette }, 911738f66d3SMichael Turquette }; 912738f66d3SMichael Turquette 913f06ddd28SJerome Brunet static struct clk_regmap gxbb_mpeg_clk_div = { 914f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 915f06ddd28SJerome Brunet .offset = HHI_MPEG_CLK_CNTL, 916738f66d3SMichael Turquette .shift = 0, 917738f66d3SMichael Turquette .width = 7, 918f06ddd28SJerome Brunet }, 919738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 920738f66d3SMichael Turquette .name = "mpeg_clk_div", 9215b13ef64SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 9220dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 9230dea3f35SAlexandre Mergnat &gxbb_mpeg_clk_sel.hw 9240dea3f35SAlexandre Mergnat }, 925738f66d3SMichael Turquette .num_parents = 1, 926738f66d3SMichael Turquette }, 927738f66d3SMichael Turquette }; 928738f66d3SMichael Turquette 9297f9768a5SJerome Brunet /* the mother of dragons gates */ 9307f9768a5SJerome Brunet static struct clk_regmap gxbb_clk81 = { 9317f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 9327f9768a5SJerome Brunet .offset = HHI_MPEG_CLK_CNTL, 933738f66d3SMichael Turquette .bit_idx = 7, 9347f9768a5SJerome Brunet }, 935738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 936738f66d3SMichael Turquette .name = "clk81", 9377f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 9380dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 9390dea3f35SAlexandre Mergnat &gxbb_mpeg_clk_div.hw 9400dea3f35SAlexandre Mergnat }, 941738f66d3SMichael Turquette .num_parents = 1, 9425b13ef64SJerome Brunet .flags = CLK_IS_CRITICAL, 943738f66d3SMichael Turquette }, 944738f66d3SMichael Turquette }; 945738f66d3SMichael Turquette 9462513a28cSJerome Brunet static struct clk_regmap gxbb_sar_adc_clk_sel = { 9472513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 9482513a28cSJerome Brunet .offset = HHI_SAR_CLK_CNTL, 94933d0fcdfSMartin Blumenstingl .mask = 0x3, 95033d0fcdfSMartin Blumenstingl .shift = 9, 9512513a28cSJerome Brunet }, 95233d0fcdfSMartin Blumenstingl .hw.init = &(struct clk_init_data){ 95333d0fcdfSMartin Blumenstingl .name = "sar_adc_clk_sel", 9542513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 95533d0fcdfSMartin Blumenstingl /* NOTE: The datasheet doesn't list the parents for bit 10 */ 9560dea3f35SAlexandre Mergnat .parent_data = (const struct clk_parent_data []) { 9570dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 9580dea3f35SAlexandre Mergnat { .hw = &gxbb_clk81.hw }, 9590dea3f35SAlexandre Mergnat }, 96033d0fcdfSMartin Blumenstingl .num_parents = 2, 96133d0fcdfSMartin Blumenstingl }, 96233d0fcdfSMartin Blumenstingl }; 96333d0fcdfSMartin Blumenstingl 964f06ddd28SJerome Brunet static struct clk_regmap gxbb_sar_adc_clk_div = { 965f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 966f06ddd28SJerome Brunet .offset = HHI_SAR_CLK_CNTL, 96733d0fcdfSMartin Blumenstingl .shift = 0, 96833d0fcdfSMartin Blumenstingl .width = 8, 969f06ddd28SJerome Brunet }, 97033d0fcdfSMartin Blumenstingl .hw.init = &(struct clk_init_data){ 97133d0fcdfSMartin Blumenstingl .name = "sar_adc_clk_div", 972f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 9730dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 9740dea3f35SAlexandre Mergnat &gxbb_sar_adc_clk_sel.hw 9750dea3f35SAlexandre Mergnat }, 97633d0fcdfSMartin Blumenstingl .num_parents = 1, 97744b09b11SMartin Blumenstingl .flags = CLK_SET_RATE_PARENT, 97833d0fcdfSMartin Blumenstingl }, 97933d0fcdfSMartin Blumenstingl }; 98033d0fcdfSMartin Blumenstingl 9817f9768a5SJerome Brunet static struct clk_regmap gxbb_sar_adc_clk = { 9827f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 9837f9768a5SJerome Brunet .offset = HHI_SAR_CLK_CNTL, 98433d0fcdfSMartin Blumenstingl .bit_idx = 8, 9857f9768a5SJerome Brunet }, 98633d0fcdfSMartin Blumenstingl .hw.init = &(struct clk_init_data){ 98733d0fcdfSMartin Blumenstingl .name = "sar_adc_clk", 9887f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 9890dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 9900dea3f35SAlexandre Mergnat &gxbb_sar_adc_clk_div.hw 9910dea3f35SAlexandre Mergnat }, 99233d0fcdfSMartin Blumenstingl .num_parents = 1, 99333d0fcdfSMartin Blumenstingl .flags = CLK_SET_RATE_PARENT, 99433d0fcdfSMartin Blumenstingl }, 99533d0fcdfSMartin Blumenstingl }; 99633d0fcdfSMartin Blumenstingl 997fac9a55bSNeil Armstrong /* 998fac9a55bSNeil Armstrong * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 9995c2602e5SMartin Blumenstingl * muxed by a glitch-free switch. The CCF can manage this glitch-free 10005c2602e5SMartin Blumenstingl * mux because it does top-to-bottom updates the each clock tree and 10015c2602e5SMartin Blumenstingl * switches to the "inactive" one when CLK_SET_RATE_GATE is set. 1002fac9a55bSNeil Armstrong */ 1003fac9a55bSNeil Armstrong 10040dea3f35SAlexandre Mergnat static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = { 10050dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 10060dea3f35SAlexandre Mergnat { .hw = &gxbb_gp0_pll.hw }, 10070dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll2.hw }, 10080dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll1.hw }, 10090dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div7.hw }, 10100dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div4.hw }, 10110dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 10120dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 1013fac9a55bSNeil Armstrong }; 1014fac9a55bSNeil Armstrong 10152513a28cSJerome Brunet static struct clk_regmap gxbb_mali_0_sel = { 10162513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 10172513a28cSJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1018fac9a55bSNeil Armstrong .mask = 0x7, 1019fac9a55bSNeil Armstrong .shift = 9, 10202513a28cSJerome Brunet }, 1021fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1022fac9a55bSNeil Armstrong .name = "mali_0_sel", 10232513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 10240dea3f35SAlexandre Mergnat .parent_data = gxbb_mali_0_1_parent_data, 1025fac9a55bSNeil Armstrong .num_parents = 8, 10265c2602e5SMartin Blumenstingl /* 10275c2602e5SMartin Blumenstingl * Don't request the parent to change the rate because 10285c2602e5SMartin Blumenstingl * all GPU frequencies can be derived from the fclk_* 10295c2602e5SMartin Blumenstingl * clocks and one special GP0_PLL setting. This is 10305c2602e5SMartin Blumenstingl * important because we need the MPLL clocks for audio. 10315c2602e5SMartin Blumenstingl */ 10325c2602e5SMartin Blumenstingl .flags = 0, 1033fac9a55bSNeil Armstrong }, 1034fac9a55bSNeil Armstrong }; 1035fac9a55bSNeil Armstrong 1036f06ddd28SJerome Brunet static struct clk_regmap gxbb_mali_0_div = { 1037f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1038f06ddd28SJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1039fac9a55bSNeil Armstrong .shift = 0, 1040fac9a55bSNeil Armstrong .width = 7, 1041f06ddd28SJerome Brunet }, 1042fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1043fac9a55bSNeil Armstrong .name = "mali_0_div", 1044f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 10450dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 10460dea3f35SAlexandre Mergnat &gxbb_mali_0_sel.hw 10470dea3f35SAlexandre Mergnat }, 1048fac9a55bSNeil Armstrong .num_parents = 1, 10495c2602e5SMartin Blumenstingl .flags = CLK_SET_RATE_PARENT, 1050fac9a55bSNeil Armstrong }, 1051fac9a55bSNeil Armstrong }; 1052fac9a55bSNeil Armstrong 10537f9768a5SJerome Brunet static struct clk_regmap gxbb_mali_0 = { 10547f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 10557f9768a5SJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1056fac9a55bSNeil Armstrong .bit_idx = 8, 10577f9768a5SJerome Brunet }, 1058fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1059fac9a55bSNeil Armstrong .name = "mali_0", 10607f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 10610dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 10620dea3f35SAlexandre Mergnat &gxbb_mali_0_div.hw 10630dea3f35SAlexandre Mergnat }, 1064fac9a55bSNeil Armstrong .num_parents = 1, 10655c2602e5SMartin Blumenstingl .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 1066fac9a55bSNeil Armstrong }, 1067fac9a55bSNeil Armstrong }; 1068fac9a55bSNeil Armstrong 10692513a28cSJerome Brunet static struct clk_regmap gxbb_mali_1_sel = { 10702513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 10712513a28cSJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1072fac9a55bSNeil Armstrong .mask = 0x7, 1073fac9a55bSNeil Armstrong .shift = 25, 10742513a28cSJerome Brunet }, 1075fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1076fac9a55bSNeil Armstrong .name = "mali_1_sel", 10772513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 10780dea3f35SAlexandre Mergnat .parent_data = gxbb_mali_0_1_parent_data, 1079fac9a55bSNeil Armstrong .num_parents = 8, 10805c2602e5SMartin Blumenstingl /* 10815c2602e5SMartin Blumenstingl * Don't request the parent to change the rate because 10825c2602e5SMartin Blumenstingl * all GPU frequencies can be derived from the fclk_* 10835c2602e5SMartin Blumenstingl * clocks and one special GP0_PLL setting. This is 10845c2602e5SMartin Blumenstingl * important because we need the MPLL clocks for audio. 10855c2602e5SMartin Blumenstingl */ 10865c2602e5SMartin Blumenstingl .flags = 0, 1087fac9a55bSNeil Armstrong }, 1088fac9a55bSNeil Armstrong }; 1089fac9a55bSNeil Armstrong 1090f06ddd28SJerome Brunet static struct clk_regmap gxbb_mali_1_div = { 1091f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1092f06ddd28SJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1093fac9a55bSNeil Armstrong .shift = 16, 1094fac9a55bSNeil Armstrong .width = 7, 1095f06ddd28SJerome Brunet }, 1096fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1097fac9a55bSNeil Armstrong .name = "mali_1_div", 1098f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 10990dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 11000dea3f35SAlexandre Mergnat &gxbb_mali_1_sel.hw 11010dea3f35SAlexandre Mergnat }, 1102fac9a55bSNeil Armstrong .num_parents = 1, 11035c2602e5SMartin Blumenstingl .flags = CLK_SET_RATE_PARENT, 1104fac9a55bSNeil Armstrong }, 1105fac9a55bSNeil Armstrong }; 1106fac9a55bSNeil Armstrong 11077f9768a5SJerome Brunet static struct clk_regmap gxbb_mali_1 = { 11087f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 11097f9768a5SJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1110fac9a55bSNeil Armstrong .bit_idx = 24, 11117f9768a5SJerome Brunet }, 1112fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1113fac9a55bSNeil Armstrong .name = "mali_1", 11147f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 11150dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 11160dea3f35SAlexandre Mergnat &gxbb_mali_1_div.hw 11170dea3f35SAlexandre Mergnat }, 1118fac9a55bSNeil Armstrong .num_parents = 1, 11195c2602e5SMartin Blumenstingl .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 1120fac9a55bSNeil Armstrong }, 1121fac9a55bSNeil Armstrong }; 1122fac9a55bSNeil Armstrong 11230dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_mali_parent_hws[] = { 11240dea3f35SAlexandre Mergnat &gxbb_mali_0.hw, 11250dea3f35SAlexandre Mergnat &gxbb_mali_1.hw, 1126fac9a55bSNeil Armstrong }; 1127fac9a55bSNeil Armstrong 11282513a28cSJerome Brunet static struct clk_regmap gxbb_mali = { 11292513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 11302513a28cSJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1131fac9a55bSNeil Armstrong .mask = 1, 1132fac9a55bSNeil Armstrong .shift = 31, 11332513a28cSJerome Brunet }, 1134fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1135fac9a55bSNeil Armstrong .name = "mali", 11362513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 11370dea3f35SAlexandre Mergnat .parent_hws = gxbb_mali_parent_hws, 1138fac9a55bSNeil Armstrong .num_parents = 2, 11395c2602e5SMartin Blumenstingl .flags = CLK_SET_RATE_PARENT, 1140fac9a55bSNeil Armstrong }, 1141fac9a55bSNeil Armstrong }; 1142fac9a55bSNeil Armstrong 11432513a28cSJerome Brunet static struct clk_regmap gxbb_cts_amclk_sel = { 11442513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 11452513a28cSJerome Brunet .offset = HHI_AUD_CLK_CNTL, 11464087bd4bSJerome Brunet .mask = 0x3, 11474087bd4bSJerome Brunet .shift = 9, 11484087bd4bSJerome Brunet .table = (u32[]){ 1, 2, 3 }, 11499799d5aeSJerome Brunet .flags = CLK_MUX_ROUND_CLOSEST, 11502513a28cSJerome Brunet }, 11514087bd4bSJerome Brunet .hw.init = &(struct clk_init_data){ 11524087bd4bSJerome Brunet .name = "cts_amclk_sel", 11532513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 11540dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 11550dea3f35SAlexandre Mergnat &gxbb_mpll0.hw, 11560dea3f35SAlexandre Mergnat &gxbb_mpll1.hw, 11570dea3f35SAlexandre Mergnat &gxbb_mpll2.hw, 11580dea3f35SAlexandre Mergnat }, 11594087bd4bSJerome Brunet .num_parents = 3, 11604087bd4bSJerome Brunet }, 11614087bd4bSJerome Brunet }; 11624087bd4bSJerome Brunet 116388a4e128SJerome Brunet static struct clk_regmap gxbb_cts_amclk_div = { 11649799d5aeSJerome Brunet .data = &(struct clk_regmap_div_data) { 11659799d5aeSJerome Brunet .offset = HHI_AUD_CLK_CNTL, 11664087bd4bSJerome Brunet .shift = 0, 11674087bd4bSJerome Brunet .width = 8, 1168004f6f46SJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 116988a4e128SJerome Brunet }, 11704087bd4bSJerome Brunet .hw.init = &(struct clk_init_data){ 11714087bd4bSJerome Brunet .name = "cts_amclk_div", 11729799d5aeSJerome Brunet .ops = &clk_regmap_divider_ops, 11730dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 11740dea3f35SAlexandre Mergnat &gxbb_cts_amclk_sel.hw 11750dea3f35SAlexandre Mergnat }, 11764087bd4bSJerome Brunet .num_parents = 1, 1177004f6f46SJerome Brunet .flags = CLK_SET_RATE_PARENT, 11784087bd4bSJerome Brunet }, 11794087bd4bSJerome Brunet }; 11804087bd4bSJerome Brunet 11817f9768a5SJerome Brunet static struct clk_regmap gxbb_cts_amclk = { 11827f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 11837f9768a5SJerome Brunet .offset = HHI_AUD_CLK_CNTL, 11844087bd4bSJerome Brunet .bit_idx = 8, 11857f9768a5SJerome Brunet }, 11864087bd4bSJerome Brunet .hw.init = &(struct clk_init_data){ 11874087bd4bSJerome Brunet .name = "cts_amclk", 11887f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 11890dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 11900dea3f35SAlexandre Mergnat &gxbb_cts_amclk_div.hw 11910dea3f35SAlexandre Mergnat }, 11924087bd4bSJerome Brunet .num_parents = 1, 11934087bd4bSJerome Brunet .flags = CLK_SET_RATE_PARENT, 11944087bd4bSJerome Brunet }, 11954087bd4bSJerome Brunet }; 11964087bd4bSJerome Brunet 11972513a28cSJerome Brunet static struct clk_regmap gxbb_cts_mclk_i958_sel = { 11982513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 11992513a28cSJerome Brunet .offset = HHI_AUD_CLK_CNTL2, 12003c277c24SJerome Brunet .mask = 0x3, 12013c277c24SJerome Brunet .shift = 25, 12023c277c24SJerome Brunet .table = (u32[]){ 1, 2, 3 }, 12039799d5aeSJerome Brunet .flags = CLK_MUX_ROUND_CLOSEST, 12042513a28cSJerome Brunet }, 12053c277c24SJerome Brunet .hw.init = &(struct clk_init_data) { 12063c277c24SJerome Brunet .name = "cts_mclk_i958_sel", 12072513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 12080dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 12090dea3f35SAlexandre Mergnat &gxbb_mpll0.hw, 12100dea3f35SAlexandre Mergnat &gxbb_mpll1.hw, 12110dea3f35SAlexandre Mergnat &gxbb_mpll2.hw, 12120dea3f35SAlexandre Mergnat }, 12133c277c24SJerome Brunet .num_parents = 3, 12143c277c24SJerome Brunet }, 12153c277c24SJerome Brunet }; 12163c277c24SJerome Brunet 1217f06ddd28SJerome Brunet static struct clk_regmap gxbb_cts_mclk_i958_div = { 1218f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1219f06ddd28SJerome Brunet .offset = HHI_AUD_CLK_CNTL2, 12203c277c24SJerome Brunet .shift = 16, 12213c277c24SJerome Brunet .width = 8, 12227605aa5bSJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 1223f06ddd28SJerome Brunet }, 12243c277c24SJerome Brunet .hw.init = &(struct clk_init_data) { 12253c277c24SJerome Brunet .name = "cts_mclk_i958_div", 1226f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 12270dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 12280dea3f35SAlexandre Mergnat &gxbb_cts_mclk_i958_sel.hw 12290dea3f35SAlexandre Mergnat }, 12303c277c24SJerome Brunet .num_parents = 1, 12317605aa5bSJerome Brunet .flags = CLK_SET_RATE_PARENT, 12323c277c24SJerome Brunet }, 12333c277c24SJerome Brunet }; 12343c277c24SJerome Brunet 12357f9768a5SJerome Brunet static struct clk_regmap gxbb_cts_mclk_i958 = { 12367f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 12377f9768a5SJerome Brunet .offset = HHI_AUD_CLK_CNTL2, 12383c277c24SJerome Brunet .bit_idx = 24, 12397f9768a5SJerome Brunet }, 12403c277c24SJerome Brunet .hw.init = &(struct clk_init_data){ 12413c277c24SJerome Brunet .name = "cts_mclk_i958", 12427f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 12430dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 12440dea3f35SAlexandre Mergnat &gxbb_cts_mclk_i958_div.hw 12450dea3f35SAlexandre Mergnat }, 12463c277c24SJerome Brunet .num_parents = 1, 12473c277c24SJerome Brunet .flags = CLK_SET_RATE_PARENT, 12483c277c24SJerome Brunet }, 12493c277c24SJerome Brunet }; 12503c277c24SJerome Brunet 12512513a28cSJerome Brunet static struct clk_regmap gxbb_cts_i958 = { 12522513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 12532513a28cSJerome Brunet .offset = HHI_AUD_CLK_CNTL2, 12547eaa44f6SJerome Brunet .mask = 0x1, 12557eaa44f6SJerome Brunet .shift = 27, 12562513a28cSJerome Brunet }, 12577eaa44f6SJerome Brunet .hw.init = &(struct clk_init_data){ 12587eaa44f6SJerome Brunet .name = "cts_i958", 12592513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 12600dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 12610dea3f35SAlexandre Mergnat &gxbb_cts_amclk.hw, 12620dea3f35SAlexandre Mergnat &gxbb_cts_mclk_i958.hw 12630dea3f35SAlexandre Mergnat }, 12647eaa44f6SJerome Brunet .num_parents = 2, 12657eaa44f6SJerome Brunet /* 12667eaa44f6SJerome Brunet *The parent is specific to origin of the audio data. Let the 12677eaa44f6SJerome Brunet * consumer choose the appropriate parent 12687eaa44f6SJerome Brunet */ 12697eaa44f6SJerome Brunet .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 12707eaa44f6SJerome Brunet }, 12717eaa44f6SJerome Brunet }; 12727eaa44f6SJerome Brunet 12730dea3f35SAlexandre Mergnat static const struct clk_parent_data gxbb_32k_clk_parent_data[] = { 12740dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 12750dea3f35SAlexandre Mergnat /* 12760dea3f35SAlexandre Mergnat * FIXME: This clock is provided by the ao clock controller but the 12770dea3f35SAlexandre Mergnat * clock is not yet part of the binding of this controller, so string 12780dea3f35SAlexandre Mergnat * name must be use to set this parent. 12790dea3f35SAlexandre Mergnat */ 12800dea3f35SAlexandre Mergnat { .name = "cts_slow_oscin", .index = -1 }, 12810dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 12820dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 12830dea3f35SAlexandre Mergnat }; 12840dea3f35SAlexandre Mergnat 12850dea3f35SAlexandre Mergnat static struct clk_regmap gxbb_32k_clk_sel = { 12860dea3f35SAlexandre Mergnat .data = &(struct clk_regmap_mux_data){ 12870dea3f35SAlexandre Mergnat .offset = HHI_32K_CLK_CNTL, 12880dea3f35SAlexandre Mergnat .mask = 0x3, 12890dea3f35SAlexandre Mergnat .shift = 16, 12900dea3f35SAlexandre Mergnat }, 12910dea3f35SAlexandre Mergnat .hw.init = &(struct clk_init_data){ 12920dea3f35SAlexandre Mergnat .name = "32k_clk_sel", 12930dea3f35SAlexandre Mergnat .ops = &clk_regmap_mux_ops, 12940dea3f35SAlexandre Mergnat .parent_data = gxbb_32k_clk_parent_data, 12950dea3f35SAlexandre Mergnat .num_parents = 4, 12960dea3f35SAlexandre Mergnat .flags = CLK_SET_RATE_PARENT, 12970dea3f35SAlexandre Mergnat }, 12980dea3f35SAlexandre Mergnat }; 12990dea3f35SAlexandre Mergnat 1300f06ddd28SJerome Brunet static struct clk_regmap gxbb_32k_clk_div = { 1301f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1302f06ddd28SJerome Brunet .offset = HHI_32K_CLK_CNTL, 130314c735c8SNeil Armstrong .shift = 0, 130414c735c8SNeil Armstrong .width = 14, 1305f06ddd28SJerome Brunet }, 130614c735c8SNeil Armstrong .hw.init = &(struct clk_init_data){ 130714c735c8SNeil Armstrong .name = "32k_clk_div", 1308f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 13090dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 13100dea3f35SAlexandre Mergnat &gxbb_32k_clk_sel.hw 13110dea3f35SAlexandre Mergnat }, 131214c735c8SNeil Armstrong .num_parents = 1, 131314c735c8SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, 131414c735c8SNeil Armstrong }, 131514c735c8SNeil Armstrong }; 131614c735c8SNeil Armstrong 13177f9768a5SJerome Brunet static struct clk_regmap gxbb_32k_clk = { 13187f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 13197f9768a5SJerome Brunet .offset = HHI_32K_CLK_CNTL, 132014c735c8SNeil Armstrong .bit_idx = 15, 13217f9768a5SJerome Brunet }, 132214c735c8SNeil Armstrong .hw.init = &(struct clk_init_data){ 132314c735c8SNeil Armstrong .name = "32k_clk", 13247f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 13250dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 13260dea3f35SAlexandre Mergnat &gxbb_32k_clk_div.hw 13270dea3f35SAlexandre Mergnat }, 132814c735c8SNeil Armstrong .num_parents = 1, 132914c735c8SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 133014c735c8SNeil Armstrong }, 133114c735c8SNeil Armstrong }; 133214c735c8SNeil Armstrong 13330dea3f35SAlexandre Mergnat static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = { 13340dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 13350dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div2.hw }, 13360dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 13370dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 13380dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div7.hw }, 1339914e6e80SJerome Brunet /* 1340914e6e80SJerome Brunet * Following these parent clocks, we should also have had mpll2, mpll3 1341914e6e80SJerome Brunet * and gp0_pll but these clocks are too precious to be used here. All 1342914e6e80SJerome Brunet * the necessary rates for MMC and NAND operation can be acheived using 1343914e6e80SJerome Brunet * xtal or fclk_div clocks 1344914e6e80SJerome Brunet */ 1345914e6e80SJerome Brunet }; 1346914e6e80SJerome Brunet 1347914e6e80SJerome Brunet /* SDIO clock */ 13482513a28cSJerome Brunet static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = { 13492513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 13502513a28cSJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1351914e6e80SJerome Brunet .mask = 0x7, 1352914e6e80SJerome Brunet .shift = 9, 13532513a28cSJerome Brunet }, 1354914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1355914e6e80SJerome Brunet .name = "sd_emmc_a_clk0_sel", 13562513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 13570dea3f35SAlexandre Mergnat .parent_data = gxbb_sd_emmc_clk0_parent_data, 13580dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data), 1359914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1360914e6e80SJerome Brunet }, 1361914e6e80SJerome Brunet }; 1362914e6e80SJerome Brunet 1363f06ddd28SJerome Brunet static struct clk_regmap gxbb_sd_emmc_a_clk0_div = { 1364f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1365f06ddd28SJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1366914e6e80SJerome Brunet .shift = 0, 1367914e6e80SJerome Brunet .width = 7, 1368914e6e80SJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 1369f06ddd28SJerome Brunet }, 1370914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1371914e6e80SJerome Brunet .name = "sd_emmc_a_clk0_div", 1372f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 13730dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 13740dea3f35SAlexandre Mergnat &gxbb_sd_emmc_a_clk0_sel.hw 13750dea3f35SAlexandre Mergnat }, 1376914e6e80SJerome Brunet .num_parents = 1, 1377914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1378914e6e80SJerome Brunet }, 1379914e6e80SJerome Brunet }; 1380914e6e80SJerome Brunet 13817f9768a5SJerome Brunet static struct clk_regmap gxbb_sd_emmc_a_clk0 = { 13827f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 13837f9768a5SJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1384914e6e80SJerome Brunet .bit_idx = 7, 13857f9768a5SJerome Brunet }, 1386914e6e80SJerome Brunet .hw.init = &(struct clk_init_data){ 1387914e6e80SJerome Brunet .name = "sd_emmc_a_clk0", 13887f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 13890dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 13900dea3f35SAlexandre Mergnat &gxbb_sd_emmc_a_clk0_div.hw 13910dea3f35SAlexandre Mergnat }, 1392914e6e80SJerome Brunet .num_parents = 1, 1393ed3fb5afSJerome Brunet .flags = CLK_SET_RATE_PARENT, 1394914e6e80SJerome Brunet }, 1395914e6e80SJerome Brunet }; 1396914e6e80SJerome Brunet 1397914e6e80SJerome Brunet /* SDcard clock */ 13982513a28cSJerome Brunet static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = { 13992513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 14002513a28cSJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1401914e6e80SJerome Brunet .mask = 0x7, 1402914e6e80SJerome Brunet .shift = 25, 14032513a28cSJerome Brunet }, 1404914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1405914e6e80SJerome Brunet .name = "sd_emmc_b_clk0_sel", 14062513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 14070dea3f35SAlexandre Mergnat .parent_data = gxbb_sd_emmc_clk0_parent_data, 14080dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data), 1409914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1410914e6e80SJerome Brunet }, 1411914e6e80SJerome Brunet }; 1412914e6e80SJerome Brunet 1413f06ddd28SJerome Brunet static struct clk_regmap gxbb_sd_emmc_b_clk0_div = { 1414f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1415f06ddd28SJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1416914e6e80SJerome Brunet .shift = 16, 1417914e6e80SJerome Brunet .width = 7, 1418914e6e80SJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 1419f06ddd28SJerome Brunet }, 1420914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1421914e6e80SJerome Brunet .name = "sd_emmc_b_clk0_div", 1422f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 14230dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 14240dea3f35SAlexandre Mergnat &gxbb_sd_emmc_b_clk0_sel.hw 14250dea3f35SAlexandre Mergnat }, 1426914e6e80SJerome Brunet .num_parents = 1, 1427914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1428914e6e80SJerome Brunet }, 1429914e6e80SJerome Brunet }; 1430914e6e80SJerome Brunet 14317f9768a5SJerome Brunet static struct clk_regmap gxbb_sd_emmc_b_clk0 = { 14327f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 14337f9768a5SJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1434914e6e80SJerome Brunet .bit_idx = 23, 14357f9768a5SJerome Brunet }, 1436914e6e80SJerome Brunet .hw.init = &(struct clk_init_data){ 1437914e6e80SJerome Brunet .name = "sd_emmc_b_clk0", 14387f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 14390dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 14400dea3f35SAlexandre Mergnat &gxbb_sd_emmc_b_clk0_div.hw 14410dea3f35SAlexandre Mergnat }, 1442914e6e80SJerome Brunet .num_parents = 1, 1443ed3fb5afSJerome Brunet .flags = CLK_SET_RATE_PARENT, 1444914e6e80SJerome Brunet }, 1445914e6e80SJerome Brunet }; 1446914e6e80SJerome Brunet 1447914e6e80SJerome Brunet /* EMMC/NAND clock */ 14482513a28cSJerome Brunet static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = { 14492513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 14502513a28cSJerome Brunet .offset = HHI_NAND_CLK_CNTL, 1451914e6e80SJerome Brunet .mask = 0x7, 1452914e6e80SJerome Brunet .shift = 9, 14532513a28cSJerome Brunet }, 1454914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1455914e6e80SJerome Brunet .name = "sd_emmc_c_clk0_sel", 14562513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 14570dea3f35SAlexandre Mergnat .parent_data = gxbb_sd_emmc_clk0_parent_data, 14580dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data), 1459914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1460914e6e80SJerome Brunet }, 1461914e6e80SJerome Brunet }; 1462914e6e80SJerome Brunet 1463f06ddd28SJerome Brunet static struct clk_regmap gxbb_sd_emmc_c_clk0_div = { 1464f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1465f06ddd28SJerome Brunet .offset = HHI_NAND_CLK_CNTL, 1466914e6e80SJerome Brunet .shift = 0, 1467914e6e80SJerome Brunet .width = 7, 1468914e6e80SJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 1469f06ddd28SJerome Brunet }, 1470914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1471914e6e80SJerome Brunet .name = "sd_emmc_c_clk0_div", 1472f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 14730dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 14740dea3f35SAlexandre Mergnat &gxbb_sd_emmc_c_clk0_sel.hw 14750dea3f35SAlexandre Mergnat }, 1476914e6e80SJerome Brunet .num_parents = 1, 1477914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1478914e6e80SJerome Brunet }, 1479914e6e80SJerome Brunet }; 1480914e6e80SJerome Brunet 14817f9768a5SJerome Brunet static struct clk_regmap gxbb_sd_emmc_c_clk0 = { 14827f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 14837f9768a5SJerome Brunet .offset = HHI_NAND_CLK_CNTL, 1484914e6e80SJerome Brunet .bit_idx = 7, 14857f9768a5SJerome Brunet }, 1486914e6e80SJerome Brunet .hw.init = &(struct clk_init_data){ 1487914e6e80SJerome Brunet .name = "sd_emmc_c_clk0", 14887f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 14890dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 14900dea3f35SAlexandre Mergnat &gxbb_sd_emmc_c_clk0_div.hw 14910dea3f35SAlexandre Mergnat }, 1492914e6e80SJerome Brunet .num_parents = 1, 1493ed3fb5afSJerome Brunet .flags = CLK_SET_RATE_PARENT, 1494914e6e80SJerome Brunet }, 1495914e6e80SJerome Brunet }; 1496914e6e80SJerome Brunet 1497762a1f20SNeil Armstrong /* VPU Clock */ 1498762a1f20SNeil Armstrong 14990dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_vpu_parent_hws[] = { 15000dea3f35SAlexandre Mergnat &gxbb_fclk_div4.hw, 15010dea3f35SAlexandre Mergnat &gxbb_fclk_div3.hw, 15020dea3f35SAlexandre Mergnat &gxbb_fclk_div5.hw, 15030dea3f35SAlexandre Mergnat &gxbb_fclk_div7.hw, 1504762a1f20SNeil Armstrong }; 1505762a1f20SNeil Armstrong 15062513a28cSJerome Brunet static struct clk_regmap gxbb_vpu_0_sel = { 15072513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 15082513a28cSJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1509762a1f20SNeil Armstrong .mask = 0x3, 1510762a1f20SNeil Armstrong .shift = 9, 15112513a28cSJerome Brunet }, 1512762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1513762a1f20SNeil Armstrong .name = "vpu_0_sel", 15142513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1515762a1f20SNeil Armstrong /* 1516762a1f20SNeil Armstrong * bits 9:10 selects from 4 possible parents: 1517762a1f20SNeil Armstrong * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1518762a1f20SNeil Armstrong */ 15190dea3f35SAlexandre Mergnat .parent_hws = gxbb_vpu_parent_hws, 15200dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws), 1521762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1522762a1f20SNeil Armstrong }, 1523762a1f20SNeil Armstrong }; 1524762a1f20SNeil Armstrong 1525f06ddd28SJerome Brunet static struct clk_regmap gxbb_vpu_0_div = { 1526f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1527f06ddd28SJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1528762a1f20SNeil Armstrong .shift = 0, 1529762a1f20SNeil Armstrong .width = 7, 1530f06ddd28SJerome Brunet }, 1531762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1532762a1f20SNeil Armstrong .name = "vpu_0_div", 1533f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 15340dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw }, 1535762a1f20SNeil Armstrong .num_parents = 1, 1536762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1537762a1f20SNeil Armstrong }, 1538762a1f20SNeil Armstrong }; 1539762a1f20SNeil Armstrong 15407f9768a5SJerome Brunet static struct clk_regmap gxbb_vpu_0 = { 15417f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 15427f9768a5SJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1543762a1f20SNeil Armstrong .bit_idx = 8, 15447f9768a5SJerome Brunet }, 1545762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1546762a1f20SNeil Armstrong .name = "vpu_0", 15477f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 15480dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw }, 1549762a1f20SNeil Armstrong .num_parents = 1, 1550762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1551762a1f20SNeil Armstrong }, 1552762a1f20SNeil Armstrong }; 1553762a1f20SNeil Armstrong 15542513a28cSJerome Brunet static struct clk_regmap gxbb_vpu_1_sel = { 15552513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 15562513a28cSJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1557762a1f20SNeil Armstrong .mask = 0x3, 1558762a1f20SNeil Armstrong .shift = 25, 15592513a28cSJerome Brunet }, 1560762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1561762a1f20SNeil Armstrong .name = "vpu_1_sel", 15622513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1563762a1f20SNeil Armstrong /* 1564762a1f20SNeil Armstrong * bits 25:26 selects from 4 possible parents: 1565762a1f20SNeil Armstrong * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1566762a1f20SNeil Armstrong */ 15670dea3f35SAlexandre Mergnat .parent_hws = gxbb_vpu_parent_hws, 15680dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws), 1569762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1570762a1f20SNeil Armstrong }, 1571762a1f20SNeil Armstrong }; 1572762a1f20SNeil Armstrong 1573f06ddd28SJerome Brunet static struct clk_regmap gxbb_vpu_1_div = { 1574f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1575f06ddd28SJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1576762a1f20SNeil Armstrong .shift = 16, 1577762a1f20SNeil Armstrong .width = 7, 1578f06ddd28SJerome Brunet }, 1579762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1580762a1f20SNeil Armstrong .name = "vpu_1_div", 1581f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 15820dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw }, 1583762a1f20SNeil Armstrong .num_parents = 1, 1584762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1585762a1f20SNeil Armstrong }, 1586762a1f20SNeil Armstrong }; 1587762a1f20SNeil Armstrong 15887f9768a5SJerome Brunet static struct clk_regmap gxbb_vpu_1 = { 15897f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 15907f9768a5SJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1591762a1f20SNeil Armstrong .bit_idx = 24, 15927f9768a5SJerome Brunet }, 1593762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1594762a1f20SNeil Armstrong .name = "vpu_1", 15957f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 15960dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw }, 1597762a1f20SNeil Armstrong .num_parents = 1, 1598762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1599762a1f20SNeil Armstrong }, 1600762a1f20SNeil Armstrong }; 1601762a1f20SNeil Armstrong 16022513a28cSJerome Brunet static struct clk_regmap gxbb_vpu = { 16032513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 16042513a28cSJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1605762a1f20SNeil Armstrong .mask = 1, 1606762a1f20SNeil Armstrong .shift = 31, 16072513a28cSJerome Brunet }, 1608762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1609762a1f20SNeil Armstrong .name = "vpu", 16102513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1611762a1f20SNeil Armstrong /* 1612762a1f20SNeil Armstrong * bit 31 selects from 2 possible parents: 1613762a1f20SNeil Armstrong * vpu_0 or vpu_1 1614762a1f20SNeil Armstrong */ 16150dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 16160dea3f35SAlexandre Mergnat &gxbb_vpu_0.hw, 16170dea3f35SAlexandre Mergnat &gxbb_vpu_1.hw 16180dea3f35SAlexandre Mergnat }, 1619762a1f20SNeil Armstrong .num_parents = 2, 1620762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1621762a1f20SNeil Armstrong }, 1622762a1f20SNeil Armstrong }; 1623762a1f20SNeil Armstrong 1624762a1f20SNeil Armstrong /* VAPB Clock */ 1625762a1f20SNeil Armstrong 16260dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_vapb_parent_hws[] = { 16270dea3f35SAlexandre Mergnat &gxbb_fclk_div4.hw, 16280dea3f35SAlexandre Mergnat &gxbb_fclk_div3.hw, 16290dea3f35SAlexandre Mergnat &gxbb_fclk_div5.hw, 16300dea3f35SAlexandre Mergnat &gxbb_fclk_div7.hw, 1631762a1f20SNeil Armstrong }; 1632762a1f20SNeil Armstrong 16332513a28cSJerome Brunet static struct clk_regmap gxbb_vapb_0_sel = { 16342513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 16352513a28cSJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1636762a1f20SNeil Armstrong .mask = 0x3, 1637762a1f20SNeil Armstrong .shift = 9, 16382513a28cSJerome Brunet }, 1639762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1640762a1f20SNeil Armstrong .name = "vapb_0_sel", 16412513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1642762a1f20SNeil Armstrong /* 1643762a1f20SNeil Armstrong * bits 9:10 selects from 4 possible parents: 1644762a1f20SNeil Armstrong * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1645762a1f20SNeil Armstrong */ 16460dea3f35SAlexandre Mergnat .parent_hws = gxbb_vapb_parent_hws, 16470dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws), 1648762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1649762a1f20SNeil Armstrong }, 1650762a1f20SNeil Armstrong }; 1651762a1f20SNeil Armstrong 1652f06ddd28SJerome Brunet static struct clk_regmap gxbb_vapb_0_div = { 1653f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1654f06ddd28SJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1655762a1f20SNeil Armstrong .shift = 0, 1656762a1f20SNeil Armstrong .width = 7, 1657f06ddd28SJerome Brunet }, 1658762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1659762a1f20SNeil Armstrong .name = "vapb_0_div", 1660f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 16610dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 16620dea3f35SAlexandre Mergnat &gxbb_vapb_0_sel.hw 16630dea3f35SAlexandre Mergnat }, 1664762a1f20SNeil Armstrong .num_parents = 1, 1665762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1666762a1f20SNeil Armstrong }, 1667762a1f20SNeil Armstrong }; 1668762a1f20SNeil Armstrong 16697f9768a5SJerome Brunet static struct clk_regmap gxbb_vapb_0 = { 16707f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 16717f9768a5SJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1672762a1f20SNeil Armstrong .bit_idx = 8, 16737f9768a5SJerome Brunet }, 1674762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1675762a1f20SNeil Armstrong .name = "vapb_0", 16767f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 16770dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 16780dea3f35SAlexandre Mergnat &gxbb_vapb_0_div.hw 16790dea3f35SAlexandre Mergnat }, 1680762a1f20SNeil Armstrong .num_parents = 1, 1681762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1682762a1f20SNeil Armstrong }, 1683762a1f20SNeil Armstrong }; 1684762a1f20SNeil Armstrong 16852513a28cSJerome Brunet static struct clk_regmap gxbb_vapb_1_sel = { 16862513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 16872513a28cSJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1688762a1f20SNeil Armstrong .mask = 0x3, 1689762a1f20SNeil Armstrong .shift = 25, 16902513a28cSJerome Brunet }, 1691762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1692762a1f20SNeil Armstrong .name = "vapb_1_sel", 16932513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1694762a1f20SNeil Armstrong /* 1695762a1f20SNeil Armstrong * bits 25:26 selects from 4 possible parents: 1696762a1f20SNeil Armstrong * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1697762a1f20SNeil Armstrong */ 16980dea3f35SAlexandre Mergnat .parent_hws = gxbb_vapb_parent_hws, 16990dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws), 1700762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1701762a1f20SNeil Armstrong }, 1702762a1f20SNeil Armstrong }; 1703762a1f20SNeil Armstrong 1704f06ddd28SJerome Brunet static struct clk_regmap gxbb_vapb_1_div = { 1705f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1706f06ddd28SJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1707762a1f20SNeil Armstrong .shift = 16, 1708762a1f20SNeil Armstrong .width = 7, 1709f06ddd28SJerome Brunet }, 1710762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1711762a1f20SNeil Armstrong .name = "vapb_1_div", 1712f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 17130dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 17140dea3f35SAlexandre Mergnat &gxbb_vapb_1_sel.hw 17150dea3f35SAlexandre Mergnat }, 1716762a1f20SNeil Armstrong .num_parents = 1, 1717762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1718762a1f20SNeil Armstrong }, 1719762a1f20SNeil Armstrong }; 1720762a1f20SNeil Armstrong 17217f9768a5SJerome Brunet static struct clk_regmap gxbb_vapb_1 = { 17227f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 17237f9768a5SJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1724762a1f20SNeil Armstrong .bit_idx = 24, 17257f9768a5SJerome Brunet }, 1726762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1727762a1f20SNeil Armstrong .name = "vapb_1", 17287f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 17290dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 17300dea3f35SAlexandre Mergnat &gxbb_vapb_1_div.hw 17310dea3f35SAlexandre Mergnat }, 1732762a1f20SNeil Armstrong .num_parents = 1, 1733762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1734762a1f20SNeil Armstrong }, 1735762a1f20SNeil Armstrong }; 1736762a1f20SNeil Armstrong 17372513a28cSJerome Brunet static struct clk_regmap gxbb_vapb_sel = { 17382513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 17392513a28cSJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1740762a1f20SNeil Armstrong .mask = 1, 1741762a1f20SNeil Armstrong .shift = 31, 17422513a28cSJerome Brunet }, 1743762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1744762a1f20SNeil Armstrong .name = "vapb_sel", 17452513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1746762a1f20SNeil Armstrong /* 1747762a1f20SNeil Armstrong * bit 31 selects from 2 possible parents: 1748762a1f20SNeil Armstrong * vapb_0 or vapb_1 1749762a1f20SNeil Armstrong */ 17500dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 17510dea3f35SAlexandre Mergnat &gxbb_vapb_0.hw, 17520dea3f35SAlexandre Mergnat &gxbb_vapb_1.hw 17530dea3f35SAlexandre Mergnat }, 1754762a1f20SNeil Armstrong .num_parents = 2, 1755762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1756762a1f20SNeil Armstrong }, 1757762a1f20SNeil Armstrong }; 1758762a1f20SNeil Armstrong 17597f9768a5SJerome Brunet static struct clk_regmap gxbb_vapb = { 17607f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 17617f9768a5SJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1762762a1f20SNeil Armstrong .bit_idx = 30, 17637f9768a5SJerome Brunet }, 1764762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1765762a1f20SNeil Armstrong .name = "vapb", 17667f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 17670dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw }, 1768762a1f20SNeil Armstrong .num_parents = 1, 1769762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1770762a1f20SNeil Armstrong }, 1771762a1f20SNeil Armstrong }; 1772762a1f20SNeil Armstrong 1773a8080f24SNeil Armstrong /* Video Clocks */ 1774a8080f24SNeil Armstrong 1775a8080f24SNeil Armstrong static struct clk_regmap gxbb_vid_pll_div = { 1776a8080f24SNeil Armstrong .data = &(struct meson_vid_pll_div_data){ 1777a8080f24SNeil Armstrong .val = { 1778a8080f24SNeil Armstrong .reg_off = HHI_VID_PLL_CLK_DIV, 1779a8080f24SNeil Armstrong .shift = 0, 1780a8080f24SNeil Armstrong .width = 15, 1781a8080f24SNeil Armstrong }, 1782a8080f24SNeil Armstrong .sel = { 1783a8080f24SNeil Armstrong .reg_off = HHI_VID_PLL_CLK_DIV, 1784a8080f24SNeil Armstrong .shift = 16, 1785a8080f24SNeil Armstrong .width = 2, 1786a8080f24SNeil Armstrong }, 1787a8080f24SNeil Armstrong }, 1788a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1789a8080f24SNeil Armstrong .name = "vid_pll_div", 1790a8080f24SNeil Armstrong .ops = &meson_vid_pll_div_ro_ops, 17910dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 17920dea3f35SAlexandre Mergnat /* 17930dea3f35SAlexandre Mergnat * Note: 17940dea3f35SAlexandre Mergnat * GXL and GXBB have different hdmi_plls (with 17950dea3f35SAlexandre Mergnat * different struct clk_hw). We fallback to the global 17960dea3f35SAlexandre Mergnat * naming string mechanism so vid_pll_div picks up the 17970dea3f35SAlexandre Mergnat * appropriate one. 17980dea3f35SAlexandre Mergnat */ 17990dea3f35SAlexandre Mergnat .name = "hdmi_pll", 18000dea3f35SAlexandre Mergnat .index = -1, 18010dea3f35SAlexandre Mergnat }, 1802a8080f24SNeil Armstrong .num_parents = 1, 1803a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 1804a8080f24SNeil Armstrong }, 1805a8080f24SNeil Armstrong }; 1806a8080f24SNeil Armstrong 18070dea3f35SAlexandre Mergnat static const struct clk_parent_data gxbb_vid_pll_parent_data[] = { 18080dea3f35SAlexandre Mergnat { .hw = &gxbb_vid_pll_div.hw }, 18090dea3f35SAlexandre Mergnat /* 18100dea3f35SAlexandre Mergnat * Note: 18110dea3f35SAlexandre Mergnat * GXL and GXBB have different hdmi_plls (with 18120dea3f35SAlexandre Mergnat * different struct clk_hw). We fallback to the global 18130dea3f35SAlexandre Mergnat * naming string mechanism so vid_pll_div picks up the 18140dea3f35SAlexandre Mergnat * appropriate one. 18150dea3f35SAlexandre Mergnat */ 18160dea3f35SAlexandre Mergnat { .name = "hdmi_pll", .index = -1 }, 18170dea3f35SAlexandre Mergnat }; 1818a8080f24SNeil Armstrong 1819a8080f24SNeil Armstrong static struct clk_regmap gxbb_vid_pll_sel = { 1820a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 1821a8080f24SNeil Armstrong .offset = HHI_VID_PLL_CLK_DIV, 1822a8080f24SNeil Armstrong .mask = 0x1, 1823a8080f24SNeil Armstrong .shift = 18, 1824a8080f24SNeil Armstrong }, 1825a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 1826a8080f24SNeil Armstrong .name = "vid_pll_sel", 1827a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 1828a8080f24SNeil Armstrong /* 1829a8080f24SNeil Armstrong * bit 18 selects from 2 possible parents: 1830a8080f24SNeil Armstrong * vid_pll_div or hdmi_pll 1831a8080f24SNeil Armstrong */ 18320dea3f35SAlexandre Mergnat .parent_data = gxbb_vid_pll_parent_data, 18330dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data), 1834a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1835a8080f24SNeil Armstrong }, 1836a8080f24SNeil Armstrong }; 1837a8080f24SNeil Armstrong 1838a8080f24SNeil Armstrong static struct clk_regmap gxbb_vid_pll = { 1839a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1840a8080f24SNeil Armstrong .offset = HHI_VID_PLL_CLK_DIV, 1841a8080f24SNeil Armstrong .bit_idx = 19, 1842a8080f24SNeil Armstrong }, 1843a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1844a8080f24SNeil Armstrong .name = "vid_pll", 1845a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 18460dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 18470dea3f35SAlexandre Mergnat &gxbb_vid_pll_sel.hw 18480dea3f35SAlexandre Mergnat }, 1849a8080f24SNeil Armstrong .num_parents = 1, 1850a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1851a8080f24SNeil Armstrong }, 1852a8080f24SNeil Armstrong }; 1853a8080f24SNeil Armstrong 18540dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_vclk_parent_hws[] = { 18550dea3f35SAlexandre Mergnat &gxbb_vid_pll.hw, 18560dea3f35SAlexandre Mergnat &gxbb_fclk_div4.hw, 18570dea3f35SAlexandre Mergnat &gxbb_fclk_div3.hw, 18580dea3f35SAlexandre Mergnat &gxbb_fclk_div5.hw, 18590dea3f35SAlexandre Mergnat &gxbb_vid_pll.hw, 18600dea3f35SAlexandre Mergnat &gxbb_fclk_div7.hw, 18610dea3f35SAlexandre Mergnat &gxbb_mpll1.hw, 1862a8080f24SNeil Armstrong }; 1863a8080f24SNeil Armstrong 1864a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_sel = { 1865a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 1866a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 1867a8080f24SNeil Armstrong .mask = 0x7, 1868a8080f24SNeil Armstrong .shift = 16, 1869a8080f24SNeil Armstrong }, 1870a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 1871a8080f24SNeil Armstrong .name = "vclk_sel", 1872a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 1873a8080f24SNeil Armstrong /* 1874a8080f24SNeil Armstrong * bits 16:18 selects from 8 possible parents: 1875a8080f24SNeil Armstrong * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1876a8080f24SNeil Armstrong * vid_pll, fclk_div7, mp1 1877a8080f24SNeil Armstrong */ 18780dea3f35SAlexandre Mergnat .parent_hws = gxbb_vclk_parent_hws, 18790dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws), 1880a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1881a8080f24SNeil Armstrong }, 1882a8080f24SNeil Armstrong }; 1883a8080f24SNeil Armstrong 1884a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_sel = { 1885a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 1886a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 1887a8080f24SNeil Armstrong .mask = 0x7, 1888a8080f24SNeil Armstrong .shift = 16, 1889a8080f24SNeil Armstrong }, 1890a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 1891a8080f24SNeil Armstrong .name = "vclk2_sel", 1892a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 1893a8080f24SNeil Armstrong /* 1894a8080f24SNeil Armstrong * bits 16:18 selects from 8 possible parents: 1895a8080f24SNeil Armstrong * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1896a8080f24SNeil Armstrong * vid_pll, fclk_div7, mp1 1897a8080f24SNeil Armstrong */ 18980dea3f35SAlexandre Mergnat .parent_hws = gxbb_vclk_parent_hws, 18990dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws), 1900a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1901a8080f24SNeil Armstrong }, 1902a8080f24SNeil Armstrong }; 1903a8080f24SNeil Armstrong 1904a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_input = { 1905a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1906a8080f24SNeil Armstrong .offset = HHI_VID_CLK_DIV, 1907a8080f24SNeil Armstrong .bit_idx = 16, 1908a8080f24SNeil Armstrong }, 1909a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1910a8080f24SNeil Armstrong .name = "vclk_input", 1911a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 19120dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw }, 1913a8080f24SNeil Armstrong .num_parents = 1, 1914a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1915a8080f24SNeil Armstrong }, 1916a8080f24SNeil Armstrong }; 1917a8080f24SNeil Armstrong 1918a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_input = { 1919a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1920a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_DIV, 1921a8080f24SNeil Armstrong .bit_idx = 16, 1922a8080f24SNeil Armstrong }, 1923a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1924a8080f24SNeil Armstrong .name = "vclk2_input", 1925a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 19260dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw }, 1927a8080f24SNeil Armstrong .num_parents = 1, 1928a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1929a8080f24SNeil Armstrong }, 1930a8080f24SNeil Armstrong }; 1931a8080f24SNeil Armstrong 1932a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div = { 1933a8080f24SNeil Armstrong .data = &(struct clk_regmap_div_data){ 1934a8080f24SNeil Armstrong .offset = HHI_VID_CLK_DIV, 1935a8080f24SNeil Armstrong .shift = 0, 1936a8080f24SNeil Armstrong .width = 8, 1937a8080f24SNeil Armstrong }, 1938a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 1939a8080f24SNeil Armstrong .name = "vclk_div", 1940a8080f24SNeil Armstrong .ops = &clk_regmap_divider_ops, 19410dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 19420dea3f35SAlexandre Mergnat &gxbb_vclk_input.hw 19430dea3f35SAlexandre Mergnat }, 1944a8080f24SNeil Armstrong .num_parents = 1, 1945a8080f24SNeil Armstrong .flags = CLK_GET_RATE_NOCACHE, 1946a8080f24SNeil Armstrong }, 1947a8080f24SNeil Armstrong }; 1948a8080f24SNeil Armstrong 1949a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div = { 1950a8080f24SNeil Armstrong .data = &(struct clk_regmap_div_data){ 1951a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_DIV, 1952a8080f24SNeil Armstrong .shift = 0, 1953a8080f24SNeil Armstrong .width = 8, 1954a8080f24SNeil Armstrong }, 1955a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 1956a8080f24SNeil Armstrong .name = "vclk2_div", 1957a8080f24SNeil Armstrong .ops = &clk_regmap_divider_ops, 19580dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 19590dea3f35SAlexandre Mergnat &gxbb_vclk2_input.hw 19600dea3f35SAlexandre Mergnat }, 1961a8080f24SNeil Armstrong .num_parents = 1, 1962a8080f24SNeil Armstrong .flags = CLK_GET_RATE_NOCACHE, 1963a8080f24SNeil Armstrong }, 1964a8080f24SNeil Armstrong }; 1965a8080f24SNeil Armstrong 1966a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk = { 1967a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1968a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 1969a8080f24SNeil Armstrong .bit_idx = 19, 1970a8080f24SNeil Armstrong }, 1971a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1972a8080f24SNeil Armstrong .name = "vclk", 1973a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 19740dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw }, 1975a8080f24SNeil Armstrong .num_parents = 1, 1976a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1977a8080f24SNeil Armstrong }, 1978a8080f24SNeil Armstrong }; 1979a8080f24SNeil Armstrong 1980a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2 = { 1981a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1982a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 1983a8080f24SNeil Armstrong .bit_idx = 19, 1984a8080f24SNeil Armstrong }, 1985a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1986a8080f24SNeil Armstrong .name = "vclk2", 1987a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 19880dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw }, 1989a8080f24SNeil Armstrong .num_parents = 1, 1990a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1991a8080f24SNeil Armstrong }, 1992a8080f24SNeil Armstrong }; 1993a8080f24SNeil Armstrong 1994a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div1 = { 1995a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1996a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 1997a8080f24SNeil Armstrong .bit_idx = 0, 1998a8080f24SNeil Armstrong }, 1999a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2000a8080f24SNeil Armstrong .name = "vclk_div1", 2001a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20020dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2003a8080f24SNeil Armstrong .num_parents = 1, 2004a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2005a8080f24SNeil Armstrong }, 2006a8080f24SNeil Armstrong }; 2007a8080f24SNeil Armstrong 2008a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div2_en = { 2009a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2010a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 2011a8080f24SNeil Armstrong .bit_idx = 1, 2012a8080f24SNeil Armstrong }, 2013a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2014a8080f24SNeil Armstrong .name = "vclk_div2_en", 2015a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20160dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2017a8080f24SNeil Armstrong .num_parents = 1, 2018a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2019a8080f24SNeil Armstrong }, 2020a8080f24SNeil Armstrong }; 2021a8080f24SNeil Armstrong 2022a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div4_en = { 2023a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2024a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 2025a8080f24SNeil Armstrong .bit_idx = 2, 2026a8080f24SNeil Armstrong }, 2027a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2028a8080f24SNeil Armstrong .name = "vclk_div4_en", 2029a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20300dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2031a8080f24SNeil Armstrong .num_parents = 1, 2032a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2033a8080f24SNeil Armstrong }, 2034a8080f24SNeil Armstrong }; 2035a8080f24SNeil Armstrong 2036a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div6_en = { 2037a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2038a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 2039a8080f24SNeil Armstrong .bit_idx = 3, 2040a8080f24SNeil Armstrong }, 2041a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2042a8080f24SNeil Armstrong .name = "vclk_div6_en", 2043a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20440dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2045a8080f24SNeil Armstrong .num_parents = 1, 2046a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2047a8080f24SNeil Armstrong }, 2048a8080f24SNeil Armstrong }; 2049a8080f24SNeil Armstrong 2050a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div12_en = { 2051a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2052a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 2053a8080f24SNeil Armstrong .bit_idx = 4, 2054a8080f24SNeil Armstrong }, 2055a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2056a8080f24SNeil Armstrong .name = "vclk_div12_en", 2057a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20580dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2059a8080f24SNeil Armstrong .num_parents = 1, 2060a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2061a8080f24SNeil Armstrong }, 2062a8080f24SNeil Armstrong }; 2063a8080f24SNeil Armstrong 2064a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div1 = { 2065a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2066a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 2067a8080f24SNeil Armstrong .bit_idx = 0, 2068a8080f24SNeil Armstrong }, 2069a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2070a8080f24SNeil Armstrong .name = "vclk2_div1", 2071a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20720dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2073a8080f24SNeil Armstrong .num_parents = 1, 2074a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2075a8080f24SNeil Armstrong }, 2076a8080f24SNeil Armstrong }; 2077a8080f24SNeil Armstrong 2078a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div2_en = { 2079a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2080a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 2081a8080f24SNeil Armstrong .bit_idx = 1, 2082a8080f24SNeil Armstrong }, 2083a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2084a8080f24SNeil Armstrong .name = "vclk2_div2_en", 2085a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20860dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2087a8080f24SNeil Armstrong .num_parents = 1, 2088a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2089a8080f24SNeil Armstrong }, 2090a8080f24SNeil Armstrong }; 2091a8080f24SNeil Armstrong 2092a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div4_en = { 2093a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2094a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 2095a8080f24SNeil Armstrong .bit_idx = 2, 2096a8080f24SNeil Armstrong }, 2097a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2098a8080f24SNeil Armstrong .name = "vclk2_div4_en", 2099a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 21000dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2101a8080f24SNeil Armstrong .num_parents = 1, 2102a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2103a8080f24SNeil Armstrong }, 2104a8080f24SNeil Armstrong }; 2105a8080f24SNeil Armstrong 2106a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div6_en = { 2107a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2108a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 2109a8080f24SNeil Armstrong .bit_idx = 3, 2110a8080f24SNeil Armstrong }, 2111a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2112a8080f24SNeil Armstrong .name = "vclk2_div6_en", 2113a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 21140dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2115a8080f24SNeil Armstrong .num_parents = 1, 2116a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2117a8080f24SNeil Armstrong }, 2118a8080f24SNeil Armstrong }; 2119a8080f24SNeil Armstrong 2120a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div12_en = { 2121a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2122a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 2123a8080f24SNeil Armstrong .bit_idx = 4, 2124a8080f24SNeil Armstrong }, 2125a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2126a8080f24SNeil Armstrong .name = "vclk2_div12_en", 2127a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 21280dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2129a8080f24SNeil Armstrong .num_parents = 1, 2130a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2131a8080f24SNeil Armstrong }, 2132a8080f24SNeil Armstrong }; 2133a8080f24SNeil Armstrong 2134a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk_div2 = { 2135a8080f24SNeil Armstrong .mult = 1, 2136a8080f24SNeil Armstrong .div = 2, 2137a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2138a8080f24SNeil Armstrong .name = "vclk_div2", 2139a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 21400dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 21410dea3f35SAlexandre Mergnat &gxbb_vclk_div2_en.hw 21420dea3f35SAlexandre Mergnat }, 2143a8080f24SNeil Armstrong .num_parents = 1, 2144a8080f24SNeil Armstrong }, 2145a8080f24SNeil Armstrong }; 2146a8080f24SNeil Armstrong 2147a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk_div4 = { 2148a8080f24SNeil Armstrong .mult = 1, 2149a8080f24SNeil Armstrong .div = 4, 2150a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2151a8080f24SNeil Armstrong .name = "vclk_div4", 2152a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 21530dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 21540dea3f35SAlexandre Mergnat &gxbb_vclk_div4_en.hw 21550dea3f35SAlexandre Mergnat }, 2156a8080f24SNeil Armstrong .num_parents = 1, 2157a8080f24SNeil Armstrong }, 2158a8080f24SNeil Armstrong }; 2159a8080f24SNeil Armstrong 2160a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk_div6 = { 2161a8080f24SNeil Armstrong .mult = 1, 2162a8080f24SNeil Armstrong .div = 6, 2163a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2164a8080f24SNeil Armstrong .name = "vclk_div6", 2165a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 21660dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 21670dea3f35SAlexandre Mergnat &gxbb_vclk_div6_en.hw 21680dea3f35SAlexandre Mergnat }, 2169a8080f24SNeil Armstrong .num_parents = 1, 2170a8080f24SNeil Armstrong }, 2171a8080f24SNeil Armstrong }; 2172a8080f24SNeil Armstrong 2173a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk_div12 = { 2174a8080f24SNeil Armstrong .mult = 1, 2175a8080f24SNeil Armstrong .div = 12, 2176a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2177a8080f24SNeil Armstrong .name = "vclk_div12", 2178a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 21790dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 21800dea3f35SAlexandre Mergnat &gxbb_vclk_div12_en.hw 21810dea3f35SAlexandre Mergnat }, 2182a8080f24SNeil Armstrong .num_parents = 1, 2183a8080f24SNeil Armstrong }, 2184a8080f24SNeil Armstrong }; 2185a8080f24SNeil Armstrong 2186a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk2_div2 = { 2187a8080f24SNeil Armstrong .mult = 1, 2188a8080f24SNeil Armstrong .div = 2, 2189a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2190a8080f24SNeil Armstrong .name = "vclk2_div2", 2191a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 21920dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 21930dea3f35SAlexandre Mergnat &gxbb_vclk2_div2_en.hw 21940dea3f35SAlexandre Mergnat }, 2195a8080f24SNeil Armstrong .num_parents = 1, 2196a8080f24SNeil Armstrong }, 2197a8080f24SNeil Armstrong }; 2198a8080f24SNeil Armstrong 2199a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk2_div4 = { 2200a8080f24SNeil Armstrong .mult = 1, 2201a8080f24SNeil Armstrong .div = 4, 2202a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2203a8080f24SNeil Armstrong .name = "vclk2_div4", 2204a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 22050dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 22060dea3f35SAlexandre Mergnat &gxbb_vclk2_div4_en.hw 22070dea3f35SAlexandre Mergnat }, 2208a8080f24SNeil Armstrong .num_parents = 1, 2209a8080f24SNeil Armstrong }, 2210a8080f24SNeil Armstrong }; 2211a8080f24SNeil Armstrong 2212a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk2_div6 = { 2213a8080f24SNeil Armstrong .mult = 1, 2214a8080f24SNeil Armstrong .div = 6, 2215a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2216a8080f24SNeil Armstrong .name = "vclk2_div6", 2217a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 22180dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 22190dea3f35SAlexandre Mergnat &gxbb_vclk2_div6_en.hw 22200dea3f35SAlexandre Mergnat }, 2221a8080f24SNeil Armstrong .num_parents = 1, 2222a8080f24SNeil Armstrong }, 2223a8080f24SNeil Armstrong }; 2224a8080f24SNeil Armstrong 2225a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk2_div12 = { 2226a8080f24SNeil Armstrong .mult = 1, 2227a8080f24SNeil Armstrong .div = 12, 2228a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2229a8080f24SNeil Armstrong .name = "vclk2_div12", 2230a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 22310dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 22320dea3f35SAlexandre Mergnat &gxbb_vclk2_div12_en.hw 22330dea3f35SAlexandre Mergnat }, 2234a8080f24SNeil Armstrong .num_parents = 1, 2235a8080f24SNeil Armstrong }, 2236a8080f24SNeil Armstrong }; 2237a8080f24SNeil Armstrong 2238a8080f24SNeil Armstrong static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 22390dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_cts_parent_hws[] = { 22400dea3f35SAlexandre Mergnat &gxbb_vclk_div1.hw, 22410dea3f35SAlexandre Mergnat &gxbb_vclk_div2.hw, 22420dea3f35SAlexandre Mergnat &gxbb_vclk_div4.hw, 22430dea3f35SAlexandre Mergnat &gxbb_vclk_div6.hw, 22440dea3f35SAlexandre Mergnat &gxbb_vclk_div12.hw, 22450dea3f35SAlexandre Mergnat &gxbb_vclk2_div1.hw, 22460dea3f35SAlexandre Mergnat &gxbb_vclk2_div2.hw, 22470dea3f35SAlexandre Mergnat &gxbb_vclk2_div4.hw, 22480dea3f35SAlexandre Mergnat &gxbb_vclk2_div6.hw, 22490dea3f35SAlexandre Mergnat &gxbb_vclk2_div12.hw, 2250a8080f24SNeil Armstrong }; 2251a8080f24SNeil Armstrong 2252a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_enci_sel = { 2253a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 2254a8080f24SNeil Armstrong .offset = HHI_VID_CLK_DIV, 2255a8080f24SNeil Armstrong .mask = 0xf, 2256a8080f24SNeil Armstrong .shift = 28, 2257a8080f24SNeil Armstrong .table = mux_table_cts_sel, 2258a8080f24SNeil Armstrong }, 2259a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2260a8080f24SNeil Armstrong .name = "cts_enci_sel", 2261a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 22620dea3f35SAlexandre Mergnat .parent_hws = gxbb_cts_parent_hws, 22630dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws), 2264a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2265a8080f24SNeil Armstrong }, 2266a8080f24SNeil Armstrong }; 2267a8080f24SNeil Armstrong 2268a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_encp_sel = { 2269a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 2270a8080f24SNeil Armstrong .offset = HHI_VID_CLK_DIV, 2271a8080f24SNeil Armstrong .mask = 0xf, 2272a8080f24SNeil Armstrong .shift = 20, 2273a8080f24SNeil Armstrong .table = mux_table_cts_sel, 2274a8080f24SNeil Armstrong }, 2275a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2276a8080f24SNeil Armstrong .name = "cts_encp_sel", 2277a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 22780dea3f35SAlexandre Mergnat .parent_hws = gxbb_cts_parent_hws, 22790dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws), 2280a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2281a8080f24SNeil Armstrong }, 2282a8080f24SNeil Armstrong }; 2283a8080f24SNeil Armstrong 2284a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_vdac_sel = { 2285a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 2286a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_DIV, 2287a8080f24SNeil Armstrong .mask = 0xf, 2288a8080f24SNeil Armstrong .shift = 28, 2289a8080f24SNeil Armstrong .table = mux_table_cts_sel, 2290a8080f24SNeil Armstrong }, 2291a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2292a8080f24SNeil Armstrong .name = "cts_vdac_sel", 2293a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 22940dea3f35SAlexandre Mergnat .parent_hws = gxbb_cts_parent_hws, 22950dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws), 2296a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2297a8080f24SNeil Armstrong }, 2298a8080f24SNeil Armstrong }; 2299a8080f24SNeil Armstrong 2300a8080f24SNeil Armstrong /* TOFIX: add support for cts_tcon */ 2301a8080f24SNeil Armstrong static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 23020dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = { 23030dea3f35SAlexandre Mergnat &gxbb_vclk_div1.hw, 23040dea3f35SAlexandre Mergnat &gxbb_vclk_div2.hw, 23050dea3f35SAlexandre Mergnat &gxbb_vclk_div4.hw, 23060dea3f35SAlexandre Mergnat &gxbb_vclk_div6.hw, 23070dea3f35SAlexandre Mergnat &gxbb_vclk_div12.hw, 23080dea3f35SAlexandre Mergnat &gxbb_vclk2_div1.hw, 23090dea3f35SAlexandre Mergnat &gxbb_vclk2_div2.hw, 23100dea3f35SAlexandre Mergnat &gxbb_vclk2_div4.hw, 23110dea3f35SAlexandre Mergnat &gxbb_vclk2_div6.hw, 23120dea3f35SAlexandre Mergnat &gxbb_vclk2_div12.hw, 2313a8080f24SNeil Armstrong }; 2314a8080f24SNeil Armstrong 2315a8080f24SNeil Armstrong static struct clk_regmap gxbb_hdmi_tx_sel = { 2316a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 2317a8080f24SNeil Armstrong .offset = HHI_HDMI_CLK_CNTL, 2318a8080f24SNeil Armstrong .mask = 0xf, 2319a8080f24SNeil Armstrong .shift = 16, 2320a8080f24SNeil Armstrong .table = mux_table_hdmi_tx_sel, 2321a8080f24SNeil Armstrong }, 2322a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2323a8080f24SNeil Armstrong .name = "hdmi_tx_sel", 2324a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 2325a8080f24SNeil Armstrong /* 2326a8080f24SNeil Armstrong * bits 31:28 selects from 12 possible parents: 2327a8080f24SNeil Armstrong * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12 2328a8080f24SNeil Armstrong * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12, 2329a8080f24SNeil Armstrong * cts_tcon 2330a8080f24SNeil Armstrong */ 23310dea3f35SAlexandre Mergnat .parent_hws = gxbb_cts_hdmi_tx_parent_hws, 23320dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws), 2333a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2334a8080f24SNeil Armstrong }, 2335a8080f24SNeil Armstrong }; 2336a8080f24SNeil Armstrong 2337a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_enci = { 2338a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2339a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL2, 2340a8080f24SNeil Armstrong .bit_idx = 0, 2341a8080f24SNeil Armstrong }, 2342a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2343a8080f24SNeil Armstrong .name = "cts_enci", 2344a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 23450dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 23460dea3f35SAlexandre Mergnat &gxbb_cts_enci_sel.hw 23470dea3f35SAlexandre Mergnat }, 2348a8080f24SNeil Armstrong .num_parents = 1, 2349a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2350a8080f24SNeil Armstrong }, 2351a8080f24SNeil Armstrong }; 2352a8080f24SNeil Armstrong 2353a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_encp = { 2354a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2355a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL2, 2356a8080f24SNeil Armstrong .bit_idx = 2, 2357a8080f24SNeil Armstrong }, 2358a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2359a8080f24SNeil Armstrong .name = "cts_encp", 2360a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 23610dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 23620dea3f35SAlexandre Mergnat &gxbb_cts_encp_sel.hw 23630dea3f35SAlexandre Mergnat }, 2364a8080f24SNeil Armstrong .num_parents = 1, 2365a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2366a8080f24SNeil Armstrong }, 2367a8080f24SNeil Armstrong }; 2368a8080f24SNeil Armstrong 2369a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_vdac = { 2370a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2371a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL2, 2372a8080f24SNeil Armstrong .bit_idx = 4, 2373a8080f24SNeil Armstrong }, 2374a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2375a8080f24SNeil Armstrong .name = "cts_vdac", 2376a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 23770dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 23780dea3f35SAlexandre Mergnat &gxbb_cts_vdac_sel.hw 23790dea3f35SAlexandre Mergnat }, 2380a8080f24SNeil Armstrong .num_parents = 1, 2381a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2382a8080f24SNeil Armstrong }, 2383a8080f24SNeil Armstrong }; 2384a8080f24SNeil Armstrong 2385a8080f24SNeil Armstrong static struct clk_regmap gxbb_hdmi_tx = { 2386a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2387a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL2, 2388a8080f24SNeil Armstrong .bit_idx = 5, 2389a8080f24SNeil Armstrong }, 2390a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2391a8080f24SNeil Armstrong .name = "hdmi_tx", 2392a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 23930dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 23940dea3f35SAlexandre Mergnat &gxbb_hdmi_tx_sel.hw 23950dea3f35SAlexandre Mergnat }, 2396a8080f24SNeil Armstrong .num_parents = 1, 2397a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2398a8080f24SNeil Armstrong }, 2399a8080f24SNeil Armstrong }; 2400a8080f24SNeil Armstrong 2401a8080f24SNeil Armstrong /* HDMI Clocks */ 2402a8080f24SNeil Armstrong 24030dea3f35SAlexandre Mergnat static const struct clk_parent_data gxbb_hdmi_parent_data[] = { 24040dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 24050dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div4.hw }, 24060dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 24070dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 2408a8080f24SNeil Armstrong }; 2409a8080f24SNeil Armstrong 2410a8080f24SNeil Armstrong static struct clk_regmap gxbb_hdmi_sel = { 2411a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 2412a8080f24SNeil Armstrong .offset = HHI_HDMI_CLK_CNTL, 2413a8080f24SNeil Armstrong .mask = 0x3, 2414a8080f24SNeil Armstrong .shift = 9, 2415a8080f24SNeil Armstrong .flags = CLK_MUX_ROUND_CLOSEST, 2416a8080f24SNeil Armstrong }, 2417a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2418a8080f24SNeil Armstrong .name = "hdmi_sel", 2419a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 24200dea3f35SAlexandre Mergnat .parent_data = gxbb_hdmi_parent_data, 24210dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data), 2422a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2423a8080f24SNeil Armstrong }, 2424a8080f24SNeil Armstrong }; 2425a8080f24SNeil Armstrong 2426a8080f24SNeil Armstrong static struct clk_regmap gxbb_hdmi_div = { 2427a8080f24SNeil Armstrong .data = &(struct clk_regmap_div_data){ 2428a8080f24SNeil Armstrong .offset = HHI_HDMI_CLK_CNTL, 2429a8080f24SNeil Armstrong .shift = 0, 2430a8080f24SNeil Armstrong .width = 7, 2431a8080f24SNeil Armstrong }, 2432a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2433a8080f24SNeil Armstrong .name = "hdmi_div", 2434a8080f24SNeil Armstrong .ops = &clk_regmap_divider_ops, 24350dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw }, 2436a8080f24SNeil Armstrong .num_parents = 1, 2437a8080f24SNeil Armstrong .flags = CLK_GET_RATE_NOCACHE, 2438a8080f24SNeil Armstrong }, 2439a8080f24SNeil Armstrong }; 2440a8080f24SNeil Armstrong 2441a8080f24SNeil Armstrong static struct clk_regmap gxbb_hdmi = { 2442a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2443a8080f24SNeil Armstrong .offset = HHI_HDMI_CLK_CNTL, 2444a8080f24SNeil Armstrong .bit_idx = 8, 2445a8080f24SNeil Armstrong }, 2446a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2447a8080f24SNeil Armstrong .name = "hdmi", 2448a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 24490dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw }, 2450a8080f24SNeil Armstrong .num_parents = 1, 2451a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2452a8080f24SNeil Armstrong }, 2453a8080f24SNeil Armstrong }; 2454a8080f24SNeil Armstrong 2455a565242eSMaxime Jourdan /* VDEC clocks */ 2456a565242eSMaxime Jourdan 24570dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_vdec_parent_hws[] = { 24580dea3f35SAlexandre Mergnat &gxbb_fclk_div4.hw, 24590dea3f35SAlexandre Mergnat &gxbb_fclk_div3.hw, 24600dea3f35SAlexandre Mergnat &gxbb_fclk_div5.hw, 24610dea3f35SAlexandre Mergnat &gxbb_fclk_div7.hw, 2462a565242eSMaxime Jourdan }; 2463a565242eSMaxime Jourdan 2464a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_1_sel = { 2465a565242eSMaxime Jourdan .data = &(struct clk_regmap_mux_data){ 2466a565242eSMaxime Jourdan .offset = HHI_VDEC_CLK_CNTL, 2467a565242eSMaxime Jourdan .mask = 0x3, 2468a565242eSMaxime Jourdan .shift = 9, 2469a565242eSMaxime Jourdan .flags = CLK_MUX_ROUND_CLOSEST, 2470a565242eSMaxime Jourdan }, 2471a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data){ 2472a565242eSMaxime Jourdan .name = "vdec_1_sel", 2473a565242eSMaxime Jourdan .ops = &clk_regmap_mux_ops, 24740dea3f35SAlexandre Mergnat .parent_hws = gxbb_vdec_parent_hws, 24750dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws), 2476a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2477a565242eSMaxime Jourdan }, 2478a565242eSMaxime Jourdan }; 2479a565242eSMaxime Jourdan 2480a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_1_div = { 2481a565242eSMaxime Jourdan .data = &(struct clk_regmap_div_data){ 2482a565242eSMaxime Jourdan .offset = HHI_VDEC_CLK_CNTL, 2483a565242eSMaxime Jourdan .shift = 0, 2484a565242eSMaxime Jourdan .width = 7, 24859b70c697SMaxime Jourdan .flags = CLK_DIVIDER_ROUND_CLOSEST, 2486a565242eSMaxime Jourdan }, 2487a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data){ 2488a565242eSMaxime Jourdan .name = "vdec_1_div", 2489a565242eSMaxime Jourdan .ops = &clk_regmap_divider_ops, 24900dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 24910dea3f35SAlexandre Mergnat &gxbb_vdec_1_sel.hw 24920dea3f35SAlexandre Mergnat }, 2493a565242eSMaxime Jourdan .num_parents = 1, 2494a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2495a565242eSMaxime Jourdan }, 2496a565242eSMaxime Jourdan }; 2497a565242eSMaxime Jourdan 2498a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_1 = { 2499a565242eSMaxime Jourdan .data = &(struct clk_regmap_gate_data){ 2500a565242eSMaxime Jourdan .offset = HHI_VDEC_CLK_CNTL, 2501a565242eSMaxime Jourdan .bit_idx = 8, 2502a565242eSMaxime Jourdan }, 2503a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data) { 2504a565242eSMaxime Jourdan .name = "vdec_1", 2505a565242eSMaxime Jourdan .ops = &clk_regmap_gate_ops, 25060dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 25070dea3f35SAlexandre Mergnat &gxbb_vdec_1_div.hw 25080dea3f35SAlexandre Mergnat }, 2509a565242eSMaxime Jourdan .num_parents = 1, 2510a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2511a565242eSMaxime Jourdan }, 2512a565242eSMaxime Jourdan }; 2513a565242eSMaxime Jourdan 2514a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_hevc_sel = { 2515a565242eSMaxime Jourdan .data = &(struct clk_regmap_mux_data){ 2516a565242eSMaxime Jourdan .offset = HHI_VDEC2_CLK_CNTL, 2517a565242eSMaxime Jourdan .mask = 0x3, 2518a565242eSMaxime Jourdan .shift = 25, 2519a565242eSMaxime Jourdan .flags = CLK_MUX_ROUND_CLOSEST, 2520a565242eSMaxime Jourdan }, 2521a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data){ 2522a565242eSMaxime Jourdan .name = "vdec_hevc_sel", 2523a565242eSMaxime Jourdan .ops = &clk_regmap_mux_ops, 25240dea3f35SAlexandre Mergnat .parent_hws = gxbb_vdec_parent_hws, 25250dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws), 2526a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2527a565242eSMaxime Jourdan }, 2528a565242eSMaxime Jourdan }; 2529a565242eSMaxime Jourdan 2530a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_hevc_div = { 2531a565242eSMaxime Jourdan .data = &(struct clk_regmap_div_data){ 2532a565242eSMaxime Jourdan .offset = HHI_VDEC2_CLK_CNTL, 2533a565242eSMaxime Jourdan .shift = 16, 2534a565242eSMaxime Jourdan .width = 7, 25359b70c697SMaxime Jourdan .flags = CLK_DIVIDER_ROUND_CLOSEST, 2536a565242eSMaxime Jourdan }, 2537a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data){ 2538a565242eSMaxime Jourdan .name = "vdec_hevc_div", 2539a565242eSMaxime Jourdan .ops = &clk_regmap_divider_ops, 25400dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 25410dea3f35SAlexandre Mergnat &gxbb_vdec_hevc_sel.hw 25420dea3f35SAlexandre Mergnat }, 2543a565242eSMaxime Jourdan .num_parents = 1, 2544a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2545a565242eSMaxime Jourdan }, 2546a565242eSMaxime Jourdan }; 2547a565242eSMaxime Jourdan 2548a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_hevc = { 2549a565242eSMaxime Jourdan .data = &(struct clk_regmap_gate_data){ 2550a565242eSMaxime Jourdan .offset = HHI_VDEC2_CLK_CNTL, 2551a565242eSMaxime Jourdan .bit_idx = 24, 2552a565242eSMaxime Jourdan }, 2553a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data) { 2554a565242eSMaxime Jourdan .name = "vdec_hevc", 2555a565242eSMaxime Jourdan .ops = &clk_regmap_gate_ops, 25560dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 25570dea3f35SAlexandre Mergnat &gxbb_vdec_hevc_div.hw 25580dea3f35SAlexandre Mergnat }, 2559a565242eSMaxime Jourdan .num_parents = 1, 2560a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2561a565242eSMaxime Jourdan }, 2562a565242eSMaxime Jourdan }; 2563a565242eSMaxime Jourdan 25647df533a7SJerome Brunet static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, 25657df533a7SJerome Brunet 9, 10, 11, 13, 14, }; 25660dea3f35SAlexandre Mergnat static const struct clk_parent_data gen_clk_parent_data[] = { 25670dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 25680dea3f35SAlexandre Mergnat { .hw = &gxbb_vdec_1.hw }, 25690dea3f35SAlexandre Mergnat { .hw = &gxbb_vdec_hevc.hw }, 25700dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll0.hw }, 25710dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll1.hw }, 25720dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll2.hw }, 25730dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div4.hw }, 25740dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 25750dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 25760dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div7.hw }, 25770dea3f35SAlexandre Mergnat { .hw = &gxbb_gp0_pll.hw }, 25787df533a7SJerome Brunet }; 25797df533a7SJerome Brunet 25807df533a7SJerome Brunet static struct clk_regmap gxbb_gen_clk_sel = { 25817df533a7SJerome Brunet .data = &(struct clk_regmap_mux_data){ 25827df533a7SJerome Brunet .offset = HHI_GEN_CLK_CNTL, 25837df533a7SJerome Brunet .mask = 0xf, 25847df533a7SJerome Brunet .shift = 12, 25857df533a7SJerome Brunet .table = mux_table_gen_clk, 25867df533a7SJerome Brunet }, 25877df533a7SJerome Brunet .hw.init = &(struct clk_init_data){ 25887df533a7SJerome Brunet .name = "gen_clk_sel", 25897df533a7SJerome Brunet .ops = &clk_regmap_mux_ops, 25907df533a7SJerome Brunet /* 25917df533a7SJerome Brunet * bits 15:12 selects from 14 possible parents: 25927df533a7SJerome Brunet * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt], 25937df533a7SJerome Brunet * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4, 25947df533a7SJerome Brunet * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 25957df533a7SJerome Brunet */ 25960dea3f35SAlexandre Mergnat .parent_data = gen_clk_parent_data, 25970dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gen_clk_parent_data), 25987df533a7SJerome Brunet }, 25997df533a7SJerome Brunet }; 26007df533a7SJerome Brunet 26017df533a7SJerome Brunet static struct clk_regmap gxbb_gen_clk_div = { 26027df533a7SJerome Brunet .data = &(struct clk_regmap_div_data){ 26037df533a7SJerome Brunet .offset = HHI_GEN_CLK_CNTL, 26047df533a7SJerome Brunet .shift = 0, 26057df533a7SJerome Brunet .width = 11, 26067df533a7SJerome Brunet }, 26077df533a7SJerome Brunet .hw.init = &(struct clk_init_data){ 26087df533a7SJerome Brunet .name = "gen_clk_div", 26097df533a7SJerome Brunet .ops = &clk_regmap_divider_ops, 26100dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 26110dea3f35SAlexandre Mergnat &gxbb_gen_clk_sel.hw 26120dea3f35SAlexandre Mergnat }, 26137df533a7SJerome Brunet .num_parents = 1, 26147df533a7SJerome Brunet .flags = CLK_SET_RATE_PARENT, 26157df533a7SJerome Brunet }, 26167df533a7SJerome Brunet }; 26177df533a7SJerome Brunet 26187df533a7SJerome Brunet static struct clk_regmap gxbb_gen_clk = { 26197df533a7SJerome Brunet .data = &(struct clk_regmap_gate_data){ 26207df533a7SJerome Brunet .offset = HHI_GEN_CLK_CNTL, 26217df533a7SJerome Brunet .bit_idx = 7, 26227df533a7SJerome Brunet }, 26237df533a7SJerome Brunet .hw.init = &(struct clk_init_data){ 26247df533a7SJerome Brunet .name = "gen_clk", 26257df533a7SJerome Brunet .ops = &clk_regmap_gate_ops, 26260dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 26270dea3f35SAlexandre Mergnat &gxbb_gen_clk_div.hw 26280dea3f35SAlexandre Mergnat }, 26297df533a7SJerome Brunet .num_parents = 1, 26307df533a7SJerome Brunet .flags = CLK_SET_RATE_PARENT, 26317df533a7SJerome Brunet }, 26327df533a7SJerome Brunet }; 26337df533a7SJerome Brunet 26343a36044eSAlexandre Mergnat #define MESON_GATE(_name, _reg, _bit) \ 26353a36044eSAlexandre Mergnat MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw) 26363a36044eSAlexandre Mergnat 2637738f66d3SMichael Turquette /* Everything Else (EE) domain gates */ 26387ba64d82SAlexander Müller static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 26397ba64d82SAlexander Müller static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); 26407ba64d82SAlexander Müller static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5); 26417ba64d82SAlexander Müller static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6); 26427ba64d82SAlexander Müller static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7); 26437ba64d82SAlexander Müller static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8); 26447ba64d82SAlexander Müller static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9); 264575eccf5eSYixun Lan static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10); 26467ba64d82SAlexander Müller static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11); 26477ba64d82SAlexander Müller static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12); 26487ba64d82SAlexander Müller static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13); 26497ba64d82SAlexander Müller static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14); 26507ba64d82SAlexander Müller static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15); 26517ba64d82SAlexander Müller static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16); 26527ba64d82SAlexander Müller static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17); 26537ba64d82SAlexander Müller static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18); 26547ba64d82SAlexander Müller static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19); 26557ba64d82SAlexander Müller static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); 26567ba64d82SAlexander Müller static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24); 26577ba64d82SAlexander Müller static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25); 26587ba64d82SAlexander Müller static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26); 265973c7ddd8SJerome Brunet static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28); 26607ba64d82SAlexander Müller static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30); 2661738f66d3SMichael Turquette 26627ba64d82SAlexander Müller static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2); 26637ba64d82SAlexander Müller static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3); 26647ba64d82SAlexander Müller static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4); 26657ba64d82SAlexander Müller static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14); 26667ba64d82SAlexander Müller static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15); 26677ba64d82SAlexander Müller static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16); 26687ba64d82SAlexander Müller static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20); 26697ba64d82SAlexander Müller static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21); 26707ba64d82SAlexander Müller static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22); 26717ba64d82SAlexander Müller static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23); 26727ba64d82SAlexander Müller static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24); 26737ba64d82SAlexander Müller static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25); 26747ba64d82SAlexander Müller static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26); 26757ba64d82SAlexander Müller static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28); 26767ba64d82SAlexander Müller static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29); 26777ba64d82SAlexander Müller static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30); 26787ba64d82SAlexander Müller static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31); 2679738f66d3SMichael Turquette 26807ba64d82SAlexander Müller static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1); 26817ba64d82SAlexander Müller static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 26827ba64d82SAlexander Müller static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); 26837ba64d82SAlexander Müller static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4); 26847ba64d82SAlexander Müller static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); 26857ba64d82SAlexander Müller static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); 26867ba64d82SAlexander Müller static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); 26877ba64d82SAlexander Müller static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12); 26887ba64d82SAlexander Müller static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15); 268975eccf5eSYixun Lan static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22); 26907ba64d82SAlexander Müller static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); 26917ba64d82SAlexander Müller static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 26927ba64d82SAlexander Müller static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); 2693738f66d3SMichael Turquette 26947ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1); 26957ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2); 26967ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3); 26977ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4); 26987ba64d82SAlexander Müller static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8); 26997ba64d82SAlexander Müller static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9); 27007ba64d82SAlexander Müller static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10); 27017ba64d82SAlexander Müller static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14); 27027ba64d82SAlexander Müller static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16); 27037ba64d82SAlexander Müller static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20); 27047ba64d82SAlexander Müller static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21); 27057ba64d82SAlexander Müller static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22); 27067ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24); 27077ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25); 27087ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26); 27097ba64d82SAlexander Müller static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31); 2710738f66d3SMichael Turquette 2711738f66d3SMichael Turquette /* Always On (AO) domain gates */ 2712738f66d3SMichael Turquette 27137ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0); 27147ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1); 27157ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2); 27167ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3); 27177ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4); 2718738f66d3SMichael Turquette 271983b89a75SJerome Brunet /* AIU gates */ 272083b89a75SJerome Brunet static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw); 272183b89a75SJerome Brunet static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw); 272283b89a75SJerome Brunet static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw); 272383b89a75SJerome Brunet static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw); 272483b89a75SJerome Brunet static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw); 272583b89a75SJerome Brunet static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw); 272683b89a75SJerome Brunet static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw); 272783b89a75SJerome Brunet static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw); 272883b89a75SJerome Brunet 2729738f66d3SMichael Turquette /* Array of all clocks provided by this provider */ 2730738f66d3SMichael Turquette 2731738f66d3SMichael Turquette static struct clk_hw_onecell_data gxbb_hw_onecell_data = { 2732738f66d3SMichael Turquette .hws = { 2733738f66d3SMichael Turquette [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 2734738f66d3SMichael Turquette [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 2735738f66d3SMichael Turquette [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 2736738f66d3SMichael Turquette [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 2737738f66d3SMichael Turquette [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 2738738f66d3SMichael Turquette [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 2739738f66d3SMichael Turquette [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 2740738f66d3SMichael Turquette [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 2741738f66d3SMichael Turquette [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 2742738f66d3SMichael Turquette [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 2743738f66d3SMichael Turquette [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 2744738f66d3SMichael Turquette [CLKID_CLK81] = &gxbb_clk81.hw, 2745738f66d3SMichael Turquette [CLKID_MPLL0] = &gxbb_mpll0.hw, 2746738f66d3SMichael Turquette [CLKID_MPLL1] = &gxbb_mpll1.hw, 2747738f66d3SMichael Turquette [CLKID_MPLL2] = &gxbb_mpll2.hw, 2748738f66d3SMichael Turquette [CLKID_DDR] = &gxbb_ddr.hw, 2749738f66d3SMichael Turquette [CLKID_DOS] = &gxbb_dos.hw, 2750738f66d3SMichael Turquette [CLKID_ISA] = &gxbb_isa.hw, 2751738f66d3SMichael Turquette [CLKID_PL301] = &gxbb_pl301.hw, 2752738f66d3SMichael Turquette [CLKID_PERIPHS] = &gxbb_periphs.hw, 2753738f66d3SMichael Turquette [CLKID_SPICC] = &gxbb_spicc.hw, 2754738f66d3SMichael Turquette [CLKID_I2C] = &gxbb_i2c.hw, 2755738f66d3SMichael Turquette [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 2756738f66d3SMichael Turquette [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 2757738f66d3SMichael Turquette [CLKID_RNG0] = &gxbb_rng0.hw, 2758738f66d3SMichael Turquette [CLKID_UART0] = &gxbb_uart0.hw, 2759738f66d3SMichael Turquette [CLKID_SDHC] = &gxbb_sdhc.hw, 2760738f66d3SMichael Turquette [CLKID_STREAM] = &gxbb_stream.hw, 2761738f66d3SMichael Turquette [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 2762738f66d3SMichael Turquette [CLKID_SDIO] = &gxbb_sdio.hw, 2763738f66d3SMichael Turquette [CLKID_ABUF] = &gxbb_abuf.hw, 2764738f66d3SMichael Turquette [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 2765738f66d3SMichael Turquette [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 2766738f66d3SMichael Turquette [CLKID_SPI] = &gxbb_spi.hw, 2767738f66d3SMichael Turquette [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 2768738f66d3SMichael Turquette [CLKID_ETH] = &gxbb_eth.hw, 2769738f66d3SMichael Turquette [CLKID_DEMUX] = &gxbb_demux.hw, 2770738f66d3SMichael Turquette [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 2771738f66d3SMichael Turquette [CLKID_IEC958] = &gxbb_iec958.hw, 2772738f66d3SMichael Turquette [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 2773738f66d3SMichael Turquette [CLKID_AMCLK] = &gxbb_amclk.hw, 2774738f66d3SMichael Turquette [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 2775738f66d3SMichael Turquette [CLKID_MIXER] = &gxbb_mixer.hw, 2776738f66d3SMichael Turquette [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 2777738f66d3SMichael Turquette [CLKID_ADC] = &gxbb_adc.hw, 2778738f66d3SMichael Turquette [CLKID_BLKMV] = &gxbb_blkmv.hw, 2779738f66d3SMichael Turquette [CLKID_AIU] = &gxbb_aiu.hw, 2780738f66d3SMichael Turquette [CLKID_UART1] = &gxbb_uart1.hw, 2781738f66d3SMichael Turquette [CLKID_G2D] = &gxbb_g2d.hw, 2782738f66d3SMichael Turquette [CLKID_USB0] = &gxbb_usb0.hw, 2783738f66d3SMichael Turquette [CLKID_USB1] = &gxbb_usb1.hw, 2784738f66d3SMichael Turquette [CLKID_RESET] = &gxbb_reset.hw, 2785738f66d3SMichael Turquette [CLKID_NAND] = &gxbb_nand.hw, 2786738f66d3SMichael Turquette [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 2787738f66d3SMichael Turquette [CLKID_USB] = &gxbb_usb.hw, 2788738f66d3SMichael Turquette [CLKID_VDIN1] = &gxbb_vdin1.hw, 2789738f66d3SMichael Turquette [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 2790738f66d3SMichael Turquette [CLKID_EFUSE] = &gxbb_efuse.hw, 2791738f66d3SMichael Turquette [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 2792738f66d3SMichael Turquette [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 2793738f66d3SMichael Turquette [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 2794738f66d3SMichael Turquette [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 2795738f66d3SMichael Turquette [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 2796738f66d3SMichael Turquette [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 2797738f66d3SMichael Turquette [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 2798738f66d3SMichael Turquette [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 2799738f66d3SMichael Turquette [CLKID_DVIN] = &gxbb_dvin.hw, 2800738f66d3SMichael Turquette [CLKID_UART2] = &gxbb_uart2.hw, 2801738f66d3SMichael Turquette [CLKID_SANA] = &gxbb_sana.hw, 2802738f66d3SMichael Turquette [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 2803738f66d3SMichael Turquette [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 2804738f66d3SMichael Turquette [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 2805738f66d3SMichael Turquette [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 2806738f66d3SMichael Turquette [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 2807738f66d3SMichael Turquette [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 2808738f66d3SMichael Turquette [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 2809738f66d3SMichael Turquette [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 2810738f66d3SMichael Turquette [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 2811738f66d3SMichael Turquette [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 2812738f66d3SMichael Turquette [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 2813738f66d3SMichael Turquette [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 2814738f66d3SMichael Turquette [CLKID_ENC480P] = &gxbb_enc480p.hw, 2815738f66d3SMichael Turquette [CLKID_RNG1] = &gxbb_rng1.hw, 2816738f66d3SMichael Turquette [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 2817738f66d3SMichael Turquette [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 2818738f66d3SMichael Turquette [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 2819738f66d3SMichael Turquette [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 2820738f66d3SMichael Turquette [CLKID_EDP] = &gxbb_edp.hw, 2821738f66d3SMichael Turquette [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 2822738f66d3SMichael Turquette [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 2823738f66d3SMichael Turquette [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 2824738f66d3SMichael Turquette [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 2825738f66d3SMichael Turquette [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 282633608dcdSKevin Hilman [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 282733608dcdSKevin Hilman [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 282833608dcdSKevin Hilman [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 282933d0fcdfSMartin Blumenstingl [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 283033d0fcdfSMartin Blumenstingl [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 283133d0fcdfSMartin Blumenstingl [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 2832fac9a55bSNeil Armstrong [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 2833fac9a55bSNeil Armstrong [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 2834fac9a55bSNeil Armstrong [CLKID_MALI_0] = &gxbb_mali_0.hw, 2835fac9a55bSNeil Armstrong [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 2836fac9a55bSNeil Armstrong [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 2837fac9a55bSNeil Armstrong [CLKID_MALI_1] = &gxbb_mali_1.hw, 2838fac9a55bSNeil Armstrong [CLKID_MALI] = &gxbb_mali.hw, 28394087bd4bSJerome Brunet [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 28404087bd4bSJerome Brunet [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 28414087bd4bSJerome Brunet [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 28423c277c24SJerome Brunet [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 28433c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 28443c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 28457eaa44f6SJerome Brunet [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 284614c735c8SNeil Armstrong [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 284714c735c8SNeil Armstrong [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 284814c735c8SNeil Armstrong [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 2849914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 2850914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 2851914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 2852914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 2853914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 2854914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 2855914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 2856914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 2857914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 2858762a1f20SNeil Armstrong [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 2859762a1f20SNeil Armstrong [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 2860762a1f20SNeil Armstrong [CLKID_VPU_0] = &gxbb_vpu_0.hw, 2861762a1f20SNeil Armstrong [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 2862762a1f20SNeil Armstrong [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 2863762a1f20SNeil Armstrong [CLKID_VPU_1] = &gxbb_vpu_1.hw, 2864762a1f20SNeil Armstrong [CLKID_VPU] = &gxbb_vpu.hw, 2865762a1f20SNeil Armstrong [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 2866762a1f20SNeil Armstrong [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 2867762a1f20SNeil Armstrong [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 2868762a1f20SNeil Armstrong [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 2869762a1f20SNeil Armstrong [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 2870762a1f20SNeil Armstrong [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 2871762a1f20SNeil Armstrong [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 2872762a1f20SNeil Armstrong [CLKID_VAPB] = &gxbb_vapb.hw, 28733c4fe763SJerome Brunet [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw, 2874d610b54fSJerome Brunet [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 2875d610b54fSJerome Brunet [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 2876d610b54fSJerome Brunet [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 2877513b67acSJerome Brunet [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 287805f81440SJerome Brunet [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 287905f81440SJerome Brunet [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 288005f81440SJerome Brunet [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 288105f81440SJerome Brunet [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 288205f81440SJerome Brunet [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 2883a565242eSMaxime Jourdan [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 2884a565242eSMaxime Jourdan [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 2885a565242eSMaxime Jourdan [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 2886a565242eSMaxime Jourdan [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 2887a565242eSMaxime Jourdan [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 2888a565242eSMaxime Jourdan [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 28897df533a7SJerome Brunet [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 28907df533a7SJerome Brunet [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 28917df533a7SJerome Brunet [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 289287173557SJerome Brunet [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 289387173557SJerome Brunet [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw, 289487173557SJerome Brunet [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw, 289587173557SJerome Brunet [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw, 289687173557SJerome Brunet [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 289787173557SJerome Brunet [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw, 2898a8080f24SNeil Armstrong [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 2899a8080f24SNeil Armstrong [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 2900a8080f24SNeil Armstrong [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 2901a8080f24SNeil Armstrong [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 2902a8080f24SNeil Armstrong [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 2903a8080f24SNeil Armstrong [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 2904a8080f24SNeil Armstrong [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 2905a8080f24SNeil Armstrong [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 2906a8080f24SNeil Armstrong [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 2907a8080f24SNeil Armstrong [CLKID_VCLK] = &gxbb_vclk.hw, 2908a8080f24SNeil Armstrong [CLKID_VCLK2] = &gxbb_vclk2.hw, 2909a8080f24SNeil Armstrong [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 2910a8080f24SNeil Armstrong [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 2911a8080f24SNeil Armstrong [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 2912a8080f24SNeil Armstrong [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 2913a8080f24SNeil Armstrong [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 2914a8080f24SNeil Armstrong [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 2915a8080f24SNeil Armstrong [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 2916a8080f24SNeil Armstrong [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 2917a8080f24SNeil Armstrong [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 2918a8080f24SNeil Armstrong [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 2919a8080f24SNeil Armstrong [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 2920a8080f24SNeil Armstrong [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 2921a8080f24SNeil Armstrong [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 2922a8080f24SNeil Armstrong [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 2923a8080f24SNeil Armstrong [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 2924a8080f24SNeil Armstrong [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 2925a8080f24SNeil Armstrong [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 2926a8080f24SNeil Armstrong [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 2927a8080f24SNeil Armstrong [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 2928a8080f24SNeil Armstrong [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 2929a8080f24SNeil Armstrong [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 2930a8080f24SNeil Armstrong [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 2931a8080f24SNeil Armstrong [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 2932a8080f24SNeil Armstrong [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 2933a8080f24SNeil Armstrong [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 2934a8080f24SNeil Armstrong [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 2935a8080f24SNeil Armstrong [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 2936a8080f24SNeil Armstrong [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 2937a8080f24SNeil Armstrong [CLKID_HDMI] = &gxbb_hdmi.hw, 29381f6f1dcbSJerome Brunet [NR_CLKS] = NULL, 2939738f66d3SMichael Turquette }, 2940738f66d3SMichael Turquette .num = NR_CLKS, 2941738f66d3SMichael Turquette }; 2942738f66d3SMichael Turquette 29430d48fc55SNeil Armstrong static struct clk_hw_onecell_data gxl_hw_onecell_data = { 29440d48fc55SNeil Armstrong .hws = { 29450d48fc55SNeil Armstrong [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 294669d92293SJerome Brunet [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw, 29470d48fc55SNeil Armstrong [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 29480d48fc55SNeil Armstrong [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 29490d48fc55SNeil Armstrong [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 29500d48fc55SNeil Armstrong [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 29510d48fc55SNeil Armstrong [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 29520d48fc55SNeil Armstrong [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 295387173557SJerome Brunet [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 29540d48fc55SNeil Armstrong [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 29550d48fc55SNeil Armstrong [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 29560d48fc55SNeil Armstrong [CLKID_CLK81] = &gxbb_clk81.hw, 29570d48fc55SNeil Armstrong [CLKID_MPLL0] = &gxbb_mpll0.hw, 29580d48fc55SNeil Armstrong [CLKID_MPLL1] = &gxbb_mpll1.hw, 29590d48fc55SNeil Armstrong [CLKID_MPLL2] = &gxbb_mpll2.hw, 29600d48fc55SNeil Armstrong [CLKID_DDR] = &gxbb_ddr.hw, 29610d48fc55SNeil Armstrong [CLKID_DOS] = &gxbb_dos.hw, 29620d48fc55SNeil Armstrong [CLKID_ISA] = &gxbb_isa.hw, 29630d48fc55SNeil Armstrong [CLKID_PL301] = &gxbb_pl301.hw, 29640d48fc55SNeil Armstrong [CLKID_PERIPHS] = &gxbb_periphs.hw, 29650d48fc55SNeil Armstrong [CLKID_SPICC] = &gxbb_spicc.hw, 29660d48fc55SNeil Armstrong [CLKID_I2C] = &gxbb_i2c.hw, 29670d48fc55SNeil Armstrong [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 29680d48fc55SNeil Armstrong [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 29690d48fc55SNeil Armstrong [CLKID_RNG0] = &gxbb_rng0.hw, 29700d48fc55SNeil Armstrong [CLKID_UART0] = &gxbb_uart0.hw, 29710d48fc55SNeil Armstrong [CLKID_SDHC] = &gxbb_sdhc.hw, 29720d48fc55SNeil Armstrong [CLKID_STREAM] = &gxbb_stream.hw, 29730d48fc55SNeil Armstrong [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 29740d48fc55SNeil Armstrong [CLKID_SDIO] = &gxbb_sdio.hw, 29750d48fc55SNeil Armstrong [CLKID_ABUF] = &gxbb_abuf.hw, 29760d48fc55SNeil Armstrong [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 29770d48fc55SNeil Armstrong [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 29780d48fc55SNeil Armstrong [CLKID_SPI] = &gxbb_spi.hw, 29790d48fc55SNeil Armstrong [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 29800d48fc55SNeil Armstrong [CLKID_ETH] = &gxbb_eth.hw, 29810d48fc55SNeil Armstrong [CLKID_DEMUX] = &gxbb_demux.hw, 29820d48fc55SNeil Armstrong [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 29830d48fc55SNeil Armstrong [CLKID_IEC958] = &gxbb_iec958.hw, 29840d48fc55SNeil Armstrong [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 29850d48fc55SNeil Armstrong [CLKID_AMCLK] = &gxbb_amclk.hw, 29860d48fc55SNeil Armstrong [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 29870d48fc55SNeil Armstrong [CLKID_MIXER] = &gxbb_mixer.hw, 29880d48fc55SNeil Armstrong [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 29890d48fc55SNeil Armstrong [CLKID_ADC] = &gxbb_adc.hw, 29900d48fc55SNeil Armstrong [CLKID_BLKMV] = &gxbb_blkmv.hw, 29910d48fc55SNeil Armstrong [CLKID_AIU] = &gxbb_aiu.hw, 29920d48fc55SNeil Armstrong [CLKID_UART1] = &gxbb_uart1.hw, 29930d48fc55SNeil Armstrong [CLKID_G2D] = &gxbb_g2d.hw, 29940d48fc55SNeil Armstrong [CLKID_USB0] = &gxbb_usb0.hw, 29950d48fc55SNeil Armstrong [CLKID_USB1] = &gxbb_usb1.hw, 29960d48fc55SNeil Armstrong [CLKID_RESET] = &gxbb_reset.hw, 29970d48fc55SNeil Armstrong [CLKID_NAND] = &gxbb_nand.hw, 29980d48fc55SNeil Armstrong [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 29990d48fc55SNeil Armstrong [CLKID_USB] = &gxbb_usb.hw, 30000d48fc55SNeil Armstrong [CLKID_VDIN1] = &gxbb_vdin1.hw, 30010d48fc55SNeil Armstrong [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 30020d48fc55SNeil Armstrong [CLKID_EFUSE] = &gxbb_efuse.hw, 30030d48fc55SNeil Armstrong [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 30040d48fc55SNeil Armstrong [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 30050d48fc55SNeil Armstrong [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 30060d48fc55SNeil Armstrong [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 30070d48fc55SNeil Armstrong [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 30080d48fc55SNeil Armstrong [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 30090d48fc55SNeil Armstrong [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 30100d48fc55SNeil Armstrong [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 30110d48fc55SNeil Armstrong [CLKID_DVIN] = &gxbb_dvin.hw, 30120d48fc55SNeil Armstrong [CLKID_UART2] = &gxbb_uart2.hw, 30130d48fc55SNeil Armstrong [CLKID_SANA] = &gxbb_sana.hw, 30140d48fc55SNeil Armstrong [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 30150d48fc55SNeil Armstrong [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 30160d48fc55SNeil Armstrong [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 30170d48fc55SNeil Armstrong [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 30180d48fc55SNeil Armstrong [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 30190d48fc55SNeil Armstrong [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 30200d48fc55SNeil Armstrong [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 30210d48fc55SNeil Armstrong [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 30220d48fc55SNeil Armstrong [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 30230d48fc55SNeil Armstrong [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 30240d48fc55SNeil Armstrong [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 30250d48fc55SNeil Armstrong [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 30260d48fc55SNeil Armstrong [CLKID_ENC480P] = &gxbb_enc480p.hw, 30270d48fc55SNeil Armstrong [CLKID_RNG1] = &gxbb_rng1.hw, 30280d48fc55SNeil Armstrong [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 30290d48fc55SNeil Armstrong [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 30300d48fc55SNeil Armstrong [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 30310d48fc55SNeil Armstrong [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 30320d48fc55SNeil Armstrong [CLKID_EDP] = &gxbb_edp.hw, 30330d48fc55SNeil Armstrong [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 30340d48fc55SNeil Armstrong [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 30350d48fc55SNeil Armstrong [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 30360d48fc55SNeil Armstrong [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 30370d48fc55SNeil Armstrong [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 30380d48fc55SNeil Armstrong [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 30390d48fc55SNeil Armstrong [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 30400d48fc55SNeil Armstrong [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 30410d48fc55SNeil Armstrong [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 30420d48fc55SNeil Armstrong [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 30430d48fc55SNeil Armstrong [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 30440d48fc55SNeil Armstrong [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 30450d48fc55SNeil Armstrong [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 30460d48fc55SNeil Armstrong [CLKID_MALI_0] = &gxbb_mali_0.hw, 30470d48fc55SNeil Armstrong [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 30480d48fc55SNeil Armstrong [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 30490d48fc55SNeil Armstrong [CLKID_MALI_1] = &gxbb_mali_1.hw, 30500d48fc55SNeil Armstrong [CLKID_MALI] = &gxbb_mali.hw, 30514087bd4bSJerome Brunet [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 30524087bd4bSJerome Brunet [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 30534087bd4bSJerome Brunet [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 30543c277c24SJerome Brunet [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 30553c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 30563c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 30577eaa44f6SJerome Brunet [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 305814c735c8SNeil Armstrong [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 305914c735c8SNeil Armstrong [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 306014c735c8SNeil Armstrong [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 3061914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 3062914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 3063914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 3064914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 3065914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 3066914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 3067914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 3068914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 3069914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 3070762a1f20SNeil Armstrong [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 3071762a1f20SNeil Armstrong [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 3072762a1f20SNeil Armstrong [CLKID_VPU_0] = &gxbb_vpu_0.hw, 3073762a1f20SNeil Armstrong [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 3074762a1f20SNeil Armstrong [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 3075762a1f20SNeil Armstrong [CLKID_VPU_1] = &gxbb_vpu_1.hw, 3076762a1f20SNeil Armstrong [CLKID_VPU] = &gxbb_vpu.hw, 3077762a1f20SNeil Armstrong [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 3078762a1f20SNeil Armstrong [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 3079762a1f20SNeil Armstrong [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 3080762a1f20SNeil Armstrong [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 3081762a1f20SNeil Armstrong [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 3082762a1f20SNeil Armstrong [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 3083762a1f20SNeil Armstrong [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 3084762a1f20SNeil Armstrong [CLKID_VAPB] = &gxbb_vapb.hw, 3085*ff54938dSMartin Blumenstingl [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw, 3086d610b54fSJerome Brunet [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 3087d610b54fSJerome Brunet [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 3088513b67acSJerome Brunet [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 308905f81440SJerome Brunet [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 309005f81440SJerome Brunet [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 309105f81440SJerome Brunet [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 309205f81440SJerome Brunet [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 309305f81440SJerome Brunet [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 3094a565242eSMaxime Jourdan [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 3095a565242eSMaxime Jourdan [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 3096a565242eSMaxime Jourdan [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 3097a565242eSMaxime Jourdan [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 3098a565242eSMaxime Jourdan [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 3099a565242eSMaxime Jourdan [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 31007df533a7SJerome Brunet [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 31017df533a7SJerome Brunet [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 31027df533a7SJerome Brunet [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 310387173557SJerome Brunet [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 31040058502fSNeil Armstrong [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw, 310587173557SJerome Brunet [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw, 310687173557SJerome Brunet [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw, 310787173557SJerome Brunet [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 310887173557SJerome Brunet [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw, 3109a8080f24SNeil Armstrong [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 3110a8080f24SNeil Armstrong [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 3111a8080f24SNeil Armstrong [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 3112a8080f24SNeil Armstrong [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 3113a8080f24SNeil Armstrong [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 3114a8080f24SNeil Armstrong [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 3115a8080f24SNeil Armstrong [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 3116a8080f24SNeil Armstrong [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 3117a8080f24SNeil Armstrong [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 3118a8080f24SNeil Armstrong [CLKID_VCLK] = &gxbb_vclk.hw, 3119a8080f24SNeil Armstrong [CLKID_VCLK2] = &gxbb_vclk2.hw, 3120a8080f24SNeil Armstrong [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 3121a8080f24SNeil Armstrong [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 3122a8080f24SNeil Armstrong [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 3123a8080f24SNeil Armstrong [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 3124a8080f24SNeil Armstrong [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 3125a8080f24SNeil Armstrong [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 3126a8080f24SNeil Armstrong [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 3127a8080f24SNeil Armstrong [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 3128a8080f24SNeil Armstrong [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 3129a8080f24SNeil Armstrong [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 3130a8080f24SNeil Armstrong [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 3131a8080f24SNeil Armstrong [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 3132a8080f24SNeil Armstrong [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 3133a8080f24SNeil Armstrong [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 3134a8080f24SNeil Armstrong [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 3135a8080f24SNeil Armstrong [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 3136a8080f24SNeil Armstrong [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 3137a8080f24SNeil Armstrong [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 3138a8080f24SNeil Armstrong [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 3139a8080f24SNeil Armstrong [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 3140a8080f24SNeil Armstrong [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 3141a8080f24SNeil Armstrong [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 3142a8080f24SNeil Armstrong [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 3143a8080f24SNeil Armstrong [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 3144a8080f24SNeil Armstrong [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 3145a8080f24SNeil Armstrong [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 3146a8080f24SNeil Armstrong [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 3147a8080f24SNeil Armstrong [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 3148a8080f24SNeil Armstrong [CLKID_HDMI] = &gxbb_hdmi.hw, 314973c7ddd8SJerome Brunet [CLKID_ACODEC] = &gxl_acodec.hw, 31501f6f1dcbSJerome Brunet [NR_CLKS] = NULL, 31510d48fc55SNeil Armstrong }, 31520d48fc55SNeil Armstrong .num = NR_CLKS, 31530d48fc55SNeil Armstrong }; 31540d48fc55SNeil Armstrong 3155722825dcSJerome Brunet static struct clk_regmap *const gxbb_clk_regmaps[] = { 3156738f66d3SMichael Turquette &gxbb_clk81, 3157738f66d3SMichael Turquette &gxbb_ddr, 3158738f66d3SMichael Turquette &gxbb_dos, 3159738f66d3SMichael Turquette &gxbb_isa, 3160738f66d3SMichael Turquette &gxbb_pl301, 3161738f66d3SMichael Turquette &gxbb_periphs, 3162738f66d3SMichael Turquette &gxbb_spicc, 3163738f66d3SMichael Turquette &gxbb_i2c, 3164738f66d3SMichael Turquette &gxbb_sar_adc, 3165738f66d3SMichael Turquette &gxbb_smart_card, 3166738f66d3SMichael Turquette &gxbb_rng0, 3167738f66d3SMichael Turquette &gxbb_uart0, 3168738f66d3SMichael Turquette &gxbb_sdhc, 3169738f66d3SMichael Turquette &gxbb_stream, 3170738f66d3SMichael Turquette &gxbb_async_fifo, 3171738f66d3SMichael Turquette &gxbb_sdio, 3172738f66d3SMichael Turquette &gxbb_abuf, 3173738f66d3SMichael Turquette &gxbb_hiu_iface, 3174738f66d3SMichael Turquette &gxbb_assist_misc, 3175738f66d3SMichael Turquette &gxbb_spi, 3176738f66d3SMichael Turquette &gxbb_i2s_spdif, 3177738f66d3SMichael Turquette &gxbb_eth, 3178738f66d3SMichael Turquette &gxbb_demux, 3179738f66d3SMichael Turquette &gxbb_aiu_glue, 3180738f66d3SMichael Turquette &gxbb_iec958, 3181738f66d3SMichael Turquette &gxbb_i2s_out, 3182738f66d3SMichael Turquette &gxbb_amclk, 3183738f66d3SMichael Turquette &gxbb_aififo2, 3184738f66d3SMichael Turquette &gxbb_mixer, 3185738f66d3SMichael Turquette &gxbb_mixer_iface, 3186738f66d3SMichael Turquette &gxbb_adc, 3187738f66d3SMichael Turquette &gxbb_blkmv, 3188738f66d3SMichael Turquette &gxbb_aiu, 3189738f66d3SMichael Turquette &gxbb_uart1, 3190738f66d3SMichael Turquette &gxbb_g2d, 3191738f66d3SMichael Turquette &gxbb_usb0, 3192738f66d3SMichael Turquette &gxbb_usb1, 3193738f66d3SMichael Turquette &gxbb_reset, 3194738f66d3SMichael Turquette &gxbb_nand, 3195738f66d3SMichael Turquette &gxbb_dos_parser, 3196738f66d3SMichael Turquette &gxbb_usb, 3197738f66d3SMichael Turquette &gxbb_vdin1, 3198738f66d3SMichael Turquette &gxbb_ahb_arb0, 3199738f66d3SMichael Turquette &gxbb_efuse, 3200738f66d3SMichael Turquette &gxbb_boot_rom, 3201738f66d3SMichael Turquette &gxbb_ahb_data_bus, 3202738f66d3SMichael Turquette &gxbb_ahb_ctrl_bus, 3203738f66d3SMichael Turquette &gxbb_hdmi_intr_sync, 3204738f66d3SMichael Turquette &gxbb_hdmi_pclk, 3205738f66d3SMichael Turquette &gxbb_usb1_ddr_bridge, 3206738f66d3SMichael Turquette &gxbb_usb0_ddr_bridge, 3207738f66d3SMichael Turquette &gxbb_mmc_pclk, 3208738f66d3SMichael Turquette &gxbb_dvin, 3209738f66d3SMichael Turquette &gxbb_uart2, 3210738f66d3SMichael Turquette &gxbb_sana, 3211738f66d3SMichael Turquette &gxbb_vpu_intr, 3212738f66d3SMichael Turquette &gxbb_sec_ahb_ahb3_bridge, 3213738f66d3SMichael Turquette &gxbb_clk81_a53, 3214738f66d3SMichael Turquette &gxbb_vclk2_venci0, 3215738f66d3SMichael Turquette &gxbb_vclk2_venci1, 3216738f66d3SMichael Turquette &gxbb_vclk2_vencp0, 3217738f66d3SMichael Turquette &gxbb_vclk2_vencp1, 3218738f66d3SMichael Turquette &gxbb_gclk_venci_int0, 3219738f66d3SMichael Turquette &gxbb_gclk_vencp_int, 3220738f66d3SMichael Turquette &gxbb_dac_clk, 3221738f66d3SMichael Turquette &gxbb_aoclk_gate, 3222738f66d3SMichael Turquette &gxbb_iec958_gate, 3223738f66d3SMichael Turquette &gxbb_enc480p, 3224738f66d3SMichael Turquette &gxbb_rng1, 3225738f66d3SMichael Turquette &gxbb_gclk_venci_int1, 3226738f66d3SMichael Turquette &gxbb_vclk2_venclmcc, 3227738f66d3SMichael Turquette &gxbb_vclk2_vencl, 3228738f66d3SMichael Turquette &gxbb_vclk_other, 3229738f66d3SMichael Turquette &gxbb_edp, 3230738f66d3SMichael Turquette &gxbb_ao_media_cpu, 3231738f66d3SMichael Turquette &gxbb_ao_ahb_sram, 3232738f66d3SMichael Turquette &gxbb_ao_ahb_bus, 3233738f66d3SMichael Turquette &gxbb_ao_iface, 3234738f66d3SMichael Turquette &gxbb_ao_i2c, 323533608dcdSKevin Hilman &gxbb_emmc_a, 323633608dcdSKevin Hilman &gxbb_emmc_b, 323733608dcdSKevin Hilman &gxbb_emmc_c, 323833d0fcdfSMartin Blumenstingl &gxbb_sar_adc_clk, 3239fac9a55bSNeil Armstrong &gxbb_mali_0, 3240fac9a55bSNeil Armstrong &gxbb_mali_1, 32414087bd4bSJerome Brunet &gxbb_cts_amclk, 32423c277c24SJerome Brunet &gxbb_cts_mclk_i958, 324314c735c8SNeil Armstrong &gxbb_32k_clk, 3244914e6e80SJerome Brunet &gxbb_sd_emmc_a_clk0, 3245914e6e80SJerome Brunet &gxbb_sd_emmc_b_clk0, 3246914e6e80SJerome Brunet &gxbb_sd_emmc_c_clk0, 3247762a1f20SNeil Armstrong &gxbb_vpu_0, 3248762a1f20SNeil Armstrong &gxbb_vpu_1, 3249762a1f20SNeil Armstrong &gxbb_vapb_0, 3250762a1f20SNeil Armstrong &gxbb_vapb_1, 3251762a1f20SNeil Armstrong &gxbb_vapb, 3252f06ddd28SJerome Brunet &gxbb_mpeg_clk_div, 3253f06ddd28SJerome Brunet &gxbb_sar_adc_clk_div, 3254f06ddd28SJerome Brunet &gxbb_mali_0_div, 3255f06ddd28SJerome Brunet &gxbb_mali_1_div, 3256f06ddd28SJerome Brunet &gxbb_cts_mclk_i958_div, 3257f06ddd28SJerome Brunet &gxbb_32k_clk_div, 3258f06ddd28SJerome Brunet &gxbb_sd_emmc_a_clk0_div, 3259f06ddd28SJerome Brunet &gxbb_sd_emmc_b_clk0_div, 3260f06ddd28SJerome Brunet &gxbb_sd_emmc_c_clk0_div, 3261f06ddd28SJerome Brunet &gxbb_vpu_0_div, 3262f06ddd28SJerome Brunet &gxbb_vpu_1_div, 3263f06ddd28SJerome Brunet &gxbb_vapb_0_div, 3264f06ddd28SJerome Brunet &gxbb_vapb_1_div, 32652513a28cSJerome Brunet &gxbb_mpeg_clk_sel, 32662513a28cSJerome Brunet &gxbb_sar_adc_clk_sel, 32672513a28cSJerome Brunet &gxbb_mali_0_sel, 32682513a28cSJerome Brunet &gxbb_mali_1_sel, 32692513a28cSJerome Brunet &gxbb_mali, 32702513a28cSJerome Brunet &gxbb_cts_amclk_sel, 32712513a28cSJerome Brunet &gxbb_cts_mclk_i958_sel, 32722513a28cSJerome Brunet &gxbb_cts_i958, 32732513a28cSJerome Brunet &gxbb_32k_clk_sel, 32742513a28cSJerome Brunet &gxbb_sd_emmc_a_clk0_sel, 32752513a28cSJerome Brunet &gxbb_sd_emmc_b_clk0_sel, 32762513a28cSJerome Brunet &gxbb_sd_emmc_c_clk0_sel, 32772513a28cSJerome Brunet &gxbb_vpu_0_sel, 32782513a28cSJerome Brunet &gxbb_vpu_1_sel, 32792513a28cSJerome Brunet &gxbb_vpu, 32802513a28cSJerome Brunet &gxbb_vapb_0_sel, 32812513a28cSJerome Brunet &gxbb_vapb_1_sel, 32822513a28cSJerome Brunet &gxbb_vapb_sel, 3283c763e61aSJerome Brunet &gxbb_mpll0, 3284c763e61aSJerome Brunet &gxbb_mpll1, 3285c763e61aSJerome Brunet &gxbb_mpll2, 3286d610b54fSJerome Brunet &gxbb_mpll0_div, 3287d610b54fSJerome Brunet &gxbb_mpll1_div, 3288d610b54fSJerome Brunet &gxbb_mpll2_div, 328988a4e128SJerome Brunet &gxbb_cts_amclk_div, 3290722825dcSJerome Brunet &gxbb_fixed_pll, 3291722825dcSJerome Brunet &gxbb_sys_pll, 3292513b67acSJerome Brunet &gxbb_mpll_prediv, 329305f81440SJerome Brunet &gxbb_fclk_div2, 329405f81440SJerome Brunet &gxbb_fclk_div3, 329505f81440SJerome Brunet &gxbb_fclk_div4, 329605f81440SJerome Brunet &gxbb_fclk_div5, 329705f81440SJerome Brunet &gxbb_fclk_div7, 3298a565242eSMaxime Jourdan &gxbb_vdec_1_sel, 3299a565242eSMaxime Jourdan &gxbb_vdec_1_div, 3300a565242eSMaxime Jourdan &gxbb_vdec_1, 3301a565242eSMaxime Jourdan &gxbb_vdec_hevc_sel, 3302a565242eSMaxime Jourdan &gxbb_vdec_hevc_div, 3303a565242eSMaxime Jourdan &gxbb_vdec_hevc, 33047df533a7SJerome Brunet &gxbb_gen_clk_sel, 33057df533a7SJerome Brunet &gxbb_gen_clk_div, 33067df533a7SJerome Brunet &gxbb_gen_clk, 330787173557SJerome Brunet &gxbb_fixed_pll_dco, 330887173557SJerome Brunet &gxbb_sys_pll_dco, 330987173557SJerome Brunet &gxbb_gp0_pll, 3310a8080f24SNeil Armstrong &gxbb_vid_pll, 3311a8080f24SNeil Armstrong &gxbb_vid_pll_sel, 3312a8080f24SNeil Armstrong &gxbb_vid_pll_div, 3313a8080f24SNeil Armstrong &gxbb_vclk, 3314a8080f24SNeil Armstrong &gxbb_vclk_sel, 3315a8080f24SNeil Armstrong &gxbb_vclk_div, 3316a8080f24SNeil Armstrong &gxbb_vclk_input, 3317a8080f24SNeil Armstrong &gxbb_vclk_div1, 3318a8080f24SNeil Armstrong &gxbb_vclk_div2_en, 3319a8080f24SNeil Armstrong &gxbb_vclk_div4_en, 3320a8080f24SNeil Armstrong &gxbb_vclk_div6_en, 3321a8080f24SNeil Armstrong &gxbb_vclk_div12_en, 3322a8080f24SNeil Armstrong &gxbb_vclk2, 3323a8080f24SNeil Armstrong &gxbb_vclk2_sel, 3324a8080f24SNeil Armstrong &gxbb_vclk2_div, 3325a8080f24SNeil Armstrong &gxbb_vclk2_input, 3326a8080f24SNeil Armstrong &gxbb_vclk2_div1, 3327a8080f24SNeil Armstrong &gxbb_vclk2_div2_en, 3328a8080f24SNeil Armstrong &gxbb_vclk2_div4_en, 3329a8080f24SNeil Armstrong &gxbb_vclk2_div6_en, 3330a8080f24SNeil Armstrong &gxbb_vclk2_div12_en, 3331a8080f24SNeil Armstrong &gxbb_cts_enci, 3332a8080f24SNeil Armstrong &gxbb_cts_enci_sel, 3333a8080f24SNeil Armstrong &gxbb_cts_encp, 3334a8080f24SNeil Armstrong &gxbb_cts_encp_sel, 3335a8080f24SNeil Armstrong &gxbb_cts_vdac, 3336a8080f24SNeil Armstrong &gxbb_cts_vdac_sel, 3337a8080f24SNeil Armstrong &gxbb_hdmi_tx, 3338a8080f24SNeil Armstrong &gxbb_hdmi_tx_sel, 3339a8080f24SNeil Armstrong &gxbb_hdmi_sel, 3340a8080f24SNeil Armstrong &gxbb_hdmi_div, 3341a8080f24SNeil Armstrong &gxbb_hdmi, 33426682bd4dSJerome Brunet &gxbb_gp0_pll_dco, 33436682bd4dSJerome Brunet &gxbb_hdmi_pll, 33446682bd4dSJerome Brunet &gxbb_hdmi_pll_od, 33456682bd4dSJerome Brunet &gxbb_hdmi_pll_od2, 33466682bd4dSJerome Brunet &gxbb_hdmi_pll_dco, 3347738f66d3SMichael Turquette }; 3348738f66d3SMichael Turquette 33496682bd4dSJerome Brunet static struct clk_regmap *const gxl_clk_regmaps[] = { 33506682bd4dSJerome Brunet &gxbb_clk81, 33516682bd4dSJerome Brunet &gxbb_ddr, 33526682bd4dSJerome Brunet &gxbb_dos, 33536682bd4dSJerome Brunet &gxbb_isa, 33546682bd4dSJerome Brunet &gxbb_pl301, 33556682bd4dSJerome Brunet &gxbb_periphs, 33566682bd4dSJerome Brunet &gxbb_spicc, 33576682bd4dSJerome Brunet &gxbb_i2c, 33586682bd4dSJerome Brunet &gxbb_sar_adc, 33596682bd4dSJerome Brunet &gxbb_smart_card, 33606682bd4dSJerome Brunet &gxbb_rng0, 33616682bd4dSJerome Brunet &gxbb_uart0, 33626682bd4dSJerome Brunet &gxbb_sdhc, 33636682bd4dSJerome Brunet &gxbb_stream, 33646682bd4dSJerome Brunet &gxbb_async_fifo, 33656682bd4dSJerome Brunet &gxbb_sdio, 33666682bd4dSJerome Brunet &gxbb_abuf, 33676682bd4dSJerome Brunet &gxbb_hiu_iface, 33686682bd4dSJerome Brunet &gxbb_assist_misc, 33696682bd4dSJerome Brunet &gxbb_spi, 33706682bd4dSJerome Brunet &gxbb_i2s_spdif, 33716682bd4dSJerome Brunet &gxbb_eth, 33726682bd4dSJerome Brunet &gxbb_demux, 33736682bd4dSJerome Brunet &gxbb_aiu_glue, 33746682bd4dSJerome Brunet &gxbb_iec958, 33756682bd4dSJerome Brunet &gxbb_i2s_out, 33766682bd4dSJerome Brunet &gxbb_amclk, 33776682bd4dSJerome Brunet &gxbb_aififo2, 33786682bd4dSJerome Brunet &gxbb_mixer, 33796682bd4dSJerome Brunet &gxbb_mixer_iface, 33806682bd4dSJerome Brunet &gxbb_adc, 33816682bd4dSJerome Brunet &gxbb_blkmv, 33826682bd4dSJerome Brunet &gxbb_aiu, 33836682bd4dSJerome Brunet &gxbb_uart1, 33846682bd4dSJerome Brunet &gxbb_g2d, 33856682bd4dSJerome Brunet &gxbb_usb0, 33866682bd4dSJerome Brunet &gxbb_usb1, 33876682bd4dSJerome Brunet &gxbb_reset, 33886682bd4dSJerome Brunet &gxbb_nand, 33896682bd4dSJerome Brunet &gxbb_dos_parser, 33906682bd4dSJerome Brunet &gxbb_usb, 33916682bd4dSJerome Brunet &gxbb_vdin1, 33926682bd4dSJerome Brunet &gxbb_ahb_arb0, 33936682bd4dSJerome Brunet &gxbb_efuse, 33946682bd4dSJerome Brunet &gxbb_boot_rom, 33956682bd4dSJerome Brunet &gxbb_ahb_data_bus, 33966682bd4dSJerome Brunet &gxbb_ahb_ctrl_bus, 33976682bd4dSJerome Brunet &gxbb_hdmi_intr_sync, 33986682bd4dSJerome Brunet &gxbb_hdmi_pclk, 33996682bd4dSJerome Brunet &gxbb_usb1_ddr_bridge, 34006682bd4dSJerome Brunet &gxbb_usb0_ddr_bridge, 34016682bd4dSJerome Brunet &gxbb_mmc_pclk, 34026682bd4dSJerome Brunet &gxbb_dvin, 34036682bd4dSJerome Brunet &gxbb_uart2, 34046682bd4dSJerome Brunet &gxbb_sana, 34056682bd4dSJerome Brunet &gxbb_vpu_intr, 34066682bd4dSJerome Brunet &gxbb_sec_ahb_ahb3_bridge, 34076682bd4dSJerome Brunet &gxbb_clk81_a53, 34086682bd4dSJerome Brunet &gxbb_vclk2_venci0, 34096682bd4dSJerome Brunet &gxbb_vclk2_venci1, 34106682bd4dSJerome Brunet &gxbb_vclk2_vencp0, 34116682bd4dSJerome Brunet &gxbb_vclk2_vencp1, 34126682bd4dSJerome Brunet &gxbb_gclk_venci_int0, 34136682bd4dSJerome Brunet &gxbb_gclk_vencp_int, 34146682bd4dSJerome Brunet &gxbb_dac_clk, 34156682bd4dSJerome Brunet &gxbb_aoclk_gate, 34166682bd4dSJerome Brunet &gxbb_iec958_gate, 34176682bd4dSJerome Brunet &gxbb_enc480p, 34186682bd4dSJerome Brunet &gxbb_rng1, 34196682bd4dSJerome Brunet &gxbb_gclk_venci_int1, 34206682bd4dSJerome Brunet &gxbb_vclk2_venclmcc, 34216682bd4dSJerome Brunet &gxbb_vclk2_vencl, 34226682bd4dSJerome Brunet &gxbb_vclk_other, 34236682bd4dSJerome Brunet &gxbb_edp, 34246682bd4dSJerome Brunet &gxbb_ao_media_cpu, 34256682bd4dSJerome Brunet &gxbb_ao_ahb_sram, 34266682bd4dSJerome Brunet &gxbb_ao_ahb_bus, 34276682bd4dSJerome Brunet &gxbb_ao_iface, 34286682bd4dSJerome Brunet &gxbb_ao_i2c, 34296682bd4dSJerome Brunet &gxbb_emmc_a, 34306682bd4dSJerome Brunet &gxbb_emmc_b, 34316682bd4dSJerome Brunet &gxbb_emmc_c, 34326682bd4dSJerome Brunet &gxbb_sar_adc_clk, 34336682bd4dSJerome Brunet &gxbb_mali_0, 34346682bd4dSJerome Brunet &gxbb_mali_1, 34356682bd4dSJerome Brunet &gxbb_cts_amclk, 34366682bd4dSJerome Brunet &gxbb_cts_mclk_i958, 34376682bd4dSJerome Brunet &gxbb_32k_clk, 34386682bd4dSJerome Brunet &gxbb_sd_emmc_a_clk0, 34396682bd4dSJerome Brunet &gxbb_sd_emmc_b_clk0, 34406682bd4dSJerome Brunet &gxbb_sd_emmc_c_clk0, 34416682bd4dSJerome Brunet &gxbb_vpu_0, 34426682bd4dSJerome Brunet &gxbb_vpu_1, 34436682bd4dSJerome Brunet &gxbb_vapb_0, 34446682bd4dSJerome Brunet &gxbb_vapb_1, 34456682bd4dSJerome Brunet &gxbb_vapb, 34466682bd4dSJerome Brunet &gxbb_mpeg_clk_div, 34476682bd4dSJerome Brunet &gxbb_sar_adc_clk_div, 34486682bd4dSJerome Brunet &gxbb_mali_0_div, 34496682bd4dSJerome Brunet &gxbb_mali_1_div, 34506682bd4dSJerome Brunet &gxbb_cts_mclk_i958_div, 34516682bd4dSJerome Brunet &gxbb_32k_clk_div, 34526682bd4dSJerome Brunet &gxbb_sd_emmc_a_clk0_div, 34536682bd4dSJerome Brunet &gxbb_sd_emmc_b_clk0_div, 34546682bd4dSJerome Brunet &gxbb_sd_emmc_c_clk0_div, 34556682bd4dSJerome Brunet &gxbb_vpu_0_div, 34566682bd4dSJerome Brunet &gxbb_vpu_1_div, 34576682bd4dSJerome Brunet &gxbb_vapb_0_div, 34586682bd4dSJerome Brunet &gxbb_vapb_1_div, 34596682bd4dSJerome Brunet &gxbb_mpeg_clk_sel, 34606682bd4dSJerome Brunet &gxbb_sar_adc_clk_sel, 34616682bd4dSJerome Brunet &gxbb_mali_0_sel, 34626682bd4dSJerome Brunet &gxbb_mali_1_sel, 34636682bd4dSJerome Brunet &gxbb_mali, 34646682bd4dSJerome Brunet &gxbb_cts_amclk_sel, 34656682bd4dSJerome Brunet &gxbb_cts_mclk_i958_sel, 34666682bd4dSJerome Brunet &gxbb_cts_i958, 34676682bd4dSJerome Brunet &gxbb_32k_clk_sel, 34686682bd4dSJerome Brunet &gxbb_sd_emmc_a_clk0_sel, 34696682bd4dSJerome Brunet &gxbb_sd_emmc_b_clk0_sel, 34706682bd4dSJerome Brunet &gxbb_sd_emmc_c_clk0_sel, 34716682bd4dSJerome Brunet &gxbb_vpu_0_sel, 34726682bd4dSJerome Brunet &gxbb_vpu_1_sel, 34736682bd4dSJerome Brunet &gxbb_vpu, 34746682bd4dSJerome Brunet &gxbb_vapb_0_sel, 34756682bd4dSJerome Brunet &gxbb_vapb_1_sel, 34766682bd4dSJerome Brunet &gxbb_vapb_sel, 34776682bd4dSJerome Brunet &gxbb_mpll0, 34786682bd4dSJerome Brunet &gxbb_mpll1, 34796682bd4dSJerome Brunet &gxbb_mpll2, 3480*ff54938dSMartin Blumenstingl &gxl_mpll0_div, 34816682bd4dSJerome Brunet &gxbb_mpll1_div, 34826682bd4dSJerome Brunet &gxbb_mpll2_div, 34836682bd4dSJerome Brunet &gxbb_cts_amclk_div, 34846682bd4dSJerome Brunet &gxbb_fixed_pll, 34856682bd4dSJerome Brunet &gxbb_sys_pll, 34866682bd4dSJerome Brunet &gxbb_mpll_prediv, 34876682bd4dSJerome Brunet &gxbb_fclk_div2, 34886682bd4dSJerome Brunet &gxbb_fclk_div3, 34896682bd4dSJerome Brunet &gxbb_fclk_div4, 34906682bd4dSJerome Brunet &gxbb_fclk_div5, 34916682bd4dSJerome Brunet &gxbb_fclk_div7, 34926682bd4dSJerome Brunet &gxbb_vdec_1_sel, 34936682bd4dSJerome Brunet &gxbb_vdec_1_div, 34946682bd4dSJerome Brunet &gxbb_vdec_1, 34956682bd4dSJerome Brunet &gxbb_vdec_hevc_sel, 34966682bd4dSJerome Brunet &gxbb_vdec_hevc_div, 34976682bd4dSJerome Brunet &gxbb_vdec_hevc, 34986682bd4dSJerome Brunet &gxbb_gen_clk_sel, 34996682bd4dSJerome Brunet &gxbb_gen_clk_div, 35006682bd4dSJerome Brunet &gxbb_gen_clk, 35016682bd4dSJerome Brunet &gxbb_fixed_pll_dco, 35026682bd4dSJerome Brunet &gxbb_sys_pll_dco, 35036682bd4dSJerome Brunet &gxbb_gp0_pll, 35046682bd4dSJerome Brunet &gxbb_vid_pll, 35056682bd4dSJerome Brunet &gxbb_vid_pll_sel, 35066682bd4dSJerome Brunet &gxbb_vid_pll_div, 35076682bd4dSJerome Brunet &gxbb_vclk, 35086682bd4dSJerome Brunet &gxbb_vclk_sel, 35096682bd4dSJerome Brunet &gxbb_vclk_div, 35106682bd4dSJerome Brunet &gxbb_vclk_input, 35116682bd4dSJerome Brunet &gxbb_vclk_div1, 35126682bd4dSJerome Brunet &gxbb_vclk_div2_en, 35136682bd4dSJerome Brunet &gxbb_vclk_div4_en, 35146682bd4dSJerome Brunet &gxbb_vclk_div6_en, 35156682bd4dSJerome Brunet &gxbb_vclk_div12_en, 35166682bd4dSJerome Brunet &gxbb_vclk2, 35176682bd4dSJerome Brunet &gxbb_vclk2_sel, 35186682bd4dSJerome Brunet &gxbb_vclk2_div, 35196682bd4dSJerome Brunet &gxbb_vclk2_input, 35206682bd4dSJerome Brunet &gxbb_vclk2_div1, 35216682bd4dSJerome Brunet &gxbb_vclk2_div2_en, 35226682bd4dSJerome Brunet &gxbb_vclk2_div4_en, 35236682bd4dSJerome Brunet &gxbb_vclk2_div6_en, 35246682bd4dSJerome Brunet &gxbb_vclk2_div12_en, 35256682bd4dSJerome Brunet &gxbb_cts_enci, 35266682bd4dSJerome Brunet &gxbb_cts_enci_sel, 35276682bd4dSJerome Brunet &gxbb_cts_encp, 35286682bd4dSJerome Brunet &gxbb_cts_encp_sel, 35296682bd4dSJerome Brunet &gxbb_cts_vdac, 35306682bd4dSJerome Brunet &gxbb_cts_vdac_sel, 35316682bd4dSJerome Brunet &gxbb_hdmi_tx, 35326682bd4dSJerome Brunet &gxbb_hdmi_tx_sel, 35336682bd4dSJerome Brunet &gxbb_hdmi_sel, 35346682bd4dSJerome Brunet &gxbb_hdmi_div, 35356682bd4dSJerome Brunet &gxbb_hdmi, 35366682bd4dSJerome Brunet &gxl_gp0_pll_dco, 35376682bd4dSJerome Brunet &gxl_hdmi_pll, 35386682bd4dSJerome Brunet &gxl_hdmi_pll_od, 35396682bd4dSJerome Brunet &gxl_hdmi_pll_od2, 35406682bd4dSJerome Brunet &gxl_hdmi_pll_dco, 354173c7ddd8SJerome Brunet &gxl_acodec, 35420d48fc55SNeil Armstrong }; 35430d48fc55SNeil Armstrong 35446682bd4dSJerome Brunet static const struct meson_eeclkc_data gxbb_clkc_data = { 3545722825dcSJerome Brunet .regmap_clks = gxbb_clk_regmaps, 35466682bd4dSJerome Brunet .regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps), 35470d48fc55SNeil Armstrong .hw_onecell_data = &gxbb_hw_onecell_data, 35480d48fc55SNeil Armstrong }; 35490d48fc55SNeil Armstrong 35506682bd4dSJerome Brunet static const struct meson_eeclkc_data gxl_clkc_data = { 3551722825dcSJerome Brunet .regmap_clks = gxl_clk_regmaps, 35526682bd4dSJerome Brunet .regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps), 35530d48fc55SNeil Armstrong .hw_onecell_data = &gxl_hw_onecell_data, 35540d48fc55SNeil Armstrong }; 35550d48fc55SNeil Armstrong 35560d48fc55SNeil Armstrong static const struct of_device_id clkc_match_table[] = { 35570d48fc55SNeil Armstrong { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data }, 35580d48fc55SNeil Armstrong { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data }, 35590d48fc55SNeil Armstrong {}, 35600d48fc55SNeil Armstrong }; 356120425f63SKevin Hilman MODULE_DEVICE_TABLE(of, clkc_match_table); 35620d48fc55SNeil Armstrong 3563738f66d3SMichael Turquette static struct platform_driver gxbb_driver = { 35646682bd4dSJerome Brunet .probe = meson_eeclkc_probe, 3565738f66d3SMichael Turquette .driver = { 3566738f66d3SMichael Turquette .name = "gxbb-clkc", 35670d48fc55SNeil Armstrong .of_match_table = clkc_match_table, 3568738f66d3SMichael Turquette }, 3569738f66d3SMichael Turquette }; 3570738f66d3SMichael Turquette 357120425f63SKevin Hilman module_platform_driver(gxbb_driver); 357220425f63SKevin Hilman MODULE_LICENSE("GPL v2"); 3573