122f65a38SJerome Brunet // SPDX-License-Identifier: GPL-2.0 2738f66d3SMichael Turquette /* 3738f66d3SMichael Turquette * Copyright (c) 2016 AmLogic, Inc. 4738f66d3SMichael Turquette * Michael Turquette <mturquette@baylibre.com> 5738f66d3SMichael Turquette */ 6738f66d3SMichael Turquette 7738f66d3SMichael Turquette #include <linux/clk-provider.h> 8161f6e5bSJerome Brunet #include <linux/init.h> 90d48fc55SNeil Armstrong #include <linux/of_device.h> 10738f66d3SMichael Turquette #include <linux/platform_device.h> 11738f66d3SMichael Turquette 12738f66d3SMichael Turquette #include "gxbb.h" 137f9768a5SJerome Brunet #include "clk-regmap.h" 14889c2b7eSJerome Brunet #include "clk-pll.h" 15889c2b7eSJerome Brunet #include "clk-mpll.h" 166682bd4dSJerome Brunet #include "meson-eeclk.h" 17889c2b7eSJerome Brunet #include "vid-pll-div.h" 18738f66d3SMichael Turquette 1927aad905SYixun Lan static DEFINE_SPINLOCK(meson_clk_lock); 20738f66d3SMichael Turquette 21dd601dbcSJerome Brunet static const struct pll_params_table gxbb_gp0_pll_params_table[] = { 22dd601dbcSJerome Brunet PLL_PARAMS(32, 1), 23dd601dbcSJerome Brunet PLL_PARAMS(33, 1), 24dd601dbcSJerome Brunet PLL_PARAMS(34, 1), 25dd601dbcSJerome Brunet PLL_PARAMS(35, 1), 26dd601dbcSJerome Brunet PLL_PARAMS(36, 1), 27dd601dbcSJerome Brunet PLL_PARAMS(37, 1), 28dd601dbcSJerome Brunet PLL_PARAMS(38, 1), 29dd601dbcSJerome Brunet PLL_PARAMS(39, 1), 30dd601dbcSJerome Brunet PLL_PARAMS(40, 1), 31dd601dbcSJerome Brunet PLL_PARAMS(41, 1), 32dd601dbcSJerome Brunet PLL_PARAMS(42, 1), 33dd601dbcSJerome Brunet PLL_PARAMS(43, 1), 34dd601dbcSJerome Brunet PLL_PARAMS(44, 1), 35dd601dbcSJerome Brunet PLL_PARAMS(45, 1), 36dd601dbcSJerome Brunet PLL_PARAMS(46, 1), 37dd601dbcSJerome Brunet PLL_PARAMS(47, 1), 38dd601dbcSJerome Brunet PLL_PARAMS(48, 1), 39dd601dbcSJerome Brunet PLL_PARAMS(49, 1), 40dd601dbcSJerome Brunet PLL_PARAMS(50, 1), 41dd601dbcSJerome Brunet PLL_PARAMS(51, 1), 42dd601dbcSJerome Brunet PLL_PARAMS(52, 1), 43dd601dbcSJerome Brunet PLL_PARAMS(53, 1), 44dd601dbcSJerome Brunet PLL_PARAMS(54, 1), 45dd601dbcSJerome Brunet PLL_PARAMS(55, 1), 46dd601dbcSJerome Brunet PLL_PARAMS(56, 1), 47dd601dbcSJerome Brunet PLL_PARAMS(57, 1), 48dd601dbcSJerome Brunet PLL_PARAMS(58, 1), 49dd601dbcSJerome Brunet PLL_PARAMS(59, 1), 50dd601dbcSJerome Brunet PLL_PARAMS(60, 1), 51dd601dbcSJerome Brunet PLL_PARAMS(61, 1), 52dd601dbcSJerome Brunet PLL_PARAMS(62, 1), 53738f66d3SMichael Turquette { /* sentinel */ }, 54738f66d3SMichael Turquette }; 55738f66d3SMichael Turquette 56dd601dbcSJerome Brunet static const struct pll_params_table gxl_gp0_pll_params_table[] = { 57dd601dbcSJerome Brunet PLL_PARAMS(42, 1), 58dd601dbcSJerome Brunet PLL_PARAMS(43, 1), 59dd601dbcSJerome Brunet PLL_PARAMS(44, 1), 60dd601dbcSJerome Brunet PLL_PARAMS(45, 1), 61dd601dbcSJerome Brunet PLL_PARAMS(46, 1), 62dd601dbcSJerome Brunet PLL_PARAMS(47, 1), 63dd601dbcSJerome Brunet PLL_PARAMS(48, 1), 64dd601dbcSJerome Brunet PLL_PARAMS(49, 1), 65dd601dbcSJerome Brunet PLL_PARAMS(50, 1), 66dd601dbcSJerome Brunet PLL_PARAMS(51, 1), 67dd601dbcSJerome Brunet PLL_PARAMS(52, 1), 68dd601dbcSJerome Brunet PLL_PARAMS(53, 1), 69dd601dbcSJerome Brunet PLL_PARAMS(54, 1), 70dd601dbcSJerome Brunet PLL_PARAMS(55, 1), 71dd601dbcSJerome Brunet PLL_PARAMS(56, 1), 72dd601dbcSJerome Brunet PLL_PARAMS(57, 1), 73dd601dbcSJerome Brunet PLL_PARAMS(58, 1), 74dd601dbcSJerome Brunet PLL_PARAMS(59, 1), 75dd601dbcSJerome Brunet PLL_PARAMS(60, 1), 76dd601dbcSJerome Brunet PLL_PARAMS(61, 1), 77dd601dbcSJerome Brunet PLL_PARAMS(62, 1), 78dd601dbcSJerome Brunet PLL_PARAMS(63, 1), 79dd601dbcSJerome Brunet PLL_PARAMS(64, 1), 80dd601dbcSJerome Brunet PLL_PARAMS(65, 1), 81dd601dbcSJerome Brunet PLL_PARAMS(66, 1), 820d48fc55SNeil Armstrong { /* sentinel */ }, 830d48fc55SNeil Armstrong }; 840d48fc55SNeil Armstrong 8587173557SJerome Brunet static struct clk_regmap gxbb_fixed_pll_dco = { 86722825dcSJerome Brunet .data = &(struct meson_clk_pll_data){ 87e40c7e3cSJerome Brunet .en = { 88e40c7e3cSJerome Brunet .reg_off = HHI_MPLL_CNTL, 89e40c7e3cSJerome Brunet .shift = 30, 90e40c7e3cSJerome Brunet .width = 1, 91e40c7e3cSJerome Brunet }, 92738f66d3SMichael Turquette .m = { 93738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL, 94738f66d3SMichael Turquette .shift = 0, 95738f66d3SMichael Turquette .width = 9, 96738f66d3SMichael Turquette }, 97738f66d3SMichael Turquette .n = { 98738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL, 99738f66d3SMichael Turquette .shift = 9, 100738f66d3SMichael Turquette .width = 5, 101738f66d3SMichael Turquette }, 10207f45e2eSJerome Brunet .frac = { 10307f45e2eSJerome Brunet .reg_off = HHI_MPLL_CNTL2, 10407f45e2eSJerome Brunet .shift = 0, 10507f45e2eSJerome Brunet .width = 12, 10607f45e2eSJerome Brunet }, 107722825dcSJerome Brunet .l = { 108722825dcSJerome Brunet .reg_off = HHI_MPLL_CNTL, 109722825dcSJerome Brunet .shift = 31, 110722825dcSJerome Brunet .width = 1, 111722825dcSJerome Brunet }, 112722825dcSJerome Brunet .rst = { 113722825dcSJerome Brunet .reg_off = HHI_MPLL_CNTL, 114722825dcSJerome Brunet .shift = 29, 115722825dcSJerome Brunet .width = 1, 116722825dcSJerome Brunet }, 117722825dcSJerome Brunet }, 118738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 11987173557SJerome Brunet .name = "fixed_pll_dco", 120738f66d3SMichael Turquette .ops = &meson_clk_pll_ro_ops, 1210dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 1220dea3f35SAlexandre Mergnat .fw_name = "xtal", 1230dea3f35SAlexandre Mergnat }, 124738f66d3SMichael Turquette .num_parents = 1, 125738f66d3SMichael Turquette }, 126738f66d3SMichael Turquette }; 127738f66d3SMichael Turquette 12887173557SJerome Brunet static struct clk_regmap gxbb_fixed_pll = { 12987173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 13087173557SJerome Brunet .offset = HHI_MPLL_CNTL, 13187173557SJerome Brunet .shift = 16, 13287173557SJerome Brunet .width = 2, 13387173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 13487173557SJerome Brunet }, 13587173557SJerome Brunet .hw.init = &(struct clk_init_data){ 13687173557SJerome Brunet .name = "fixed_pll", 13787173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 1380dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 1390dea3f35SAlexandre Mergnat &gxbb_fixed_pll_dco.hw 1400dea3f35SAlexandre Mergnat }, 14187173557SJerome Brunet .num_parents = 1, 14287173557SJerome Brunet /* 14387173557SJerome Brunet * This clock won't ever change at runtime so 14487173557SJerome Brunet * CLK_SET_RATE_PARENT is not required 14587173557SJerome Brunet */ 14687173557SJerome Brunet }, 14787173557SJerome Brunet }; 14887173557SJerome Brunet 1493c4fe763SJerome Brunet static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = { 1503c4fe763SJerome Brunet .mult = 2, 1513c4fe763SJerome Brunet .div = 1, 1523c4fe763SJerome Brunet .hw.init = &(struct clk_init_data){ 1533c4fe763SJerome Brunet .name = "hdmi_pll_pre_mult", 1543c4fe763SJerome Brunet .ops = &clk_fixed_factor_ops, 1550dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 1560dea3f35SAlexandre Mergnat .fw_name = "xtal", 1570dea3f35SAlexandre Mergnat }, 1583c4fe763SJerome Brunet .num_parents = 1, 1593c4fe763SJerome Brunet }, 1603c4fe763SJerome Brunet }; 1613c4fe763SJerome Brunet 16287173557SJerome Brunet static struct clk_regmap gxbb_hdmi_pll_dco = { 163722825dcSJerome Brunet .data = &(struct meson_clk_pll_data){ 164e40c7e3cSJerome Brunet .en = { 165e40c7e3cSJerome Brunet .reg_off = HHI_HDMI_PLL_CNTL, 166e40c7e3cSJerome Brunet .shift = 30, 167e40c7e3cSJerome Brunet .width = 1, 168e40c7e3cSJerome Brunet }, 169738f66d3SMichael Turquette .m = { 170738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL, 171738f66d3SMichael Turquette .shift = 0, 172738f66d3SMichael Turquette .width = 9, 173738f66d3SMichael Turquette }, 174738f66d3SMichael Turquette .n = { 175738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL, 176738f66d3SMichael Turquette .shift = 9, 177738f66d3SMichael Turquette .width = 5, 178738f66d3SMichael Turquette }, 179738f66d3SMichael Turquette .frac = { 180738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL2, 181738f66d3SMichael Turquette .shift = 0, 182738f66d3SMichael Turquette .width = 12, 183738f66d3SMichael Turquette }, 184722825dcSJerome Brunet .l = { 185722825dcSJerome Brunet .reg_off = HHI_HDMI_PLL_CNTL, 186722825dcSJerome Brunet .shift = 31, 187722825dcSJerome Brunet .width = 1, 188722825dcSJerome Brunet }, 189722825dcSJerome Brunet .rst = { 190722825dcSJerome Brunet .reg_off = HHI_HDMI_PLL_CNTL, 191722825dcSJerome Brunet .shift = 28, 192722825dcSJerome Brunet .width = 1, 193722825dcSJerome Brunet }, 194722825dcSJerome Brunet }, 195738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 19687173557SJerome Brunet .name = "hdmi_pll_dco", 197738f66d3SMichael Turquette .ops = &meson_clk_pll_ro_ops, 1980dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 1990dea3f35SAlexandre Mergnat &gxbb_hdmi_pll_pre_mult.hw 2000dea3f35SAlexandre Mergnat }, 201738f66d3SMichael Turquette .num_parents = 1, 2022303a9caSJerome Brunet /* 2032303a9caSJerome Brunet * Display directly handle hdmi pll registers ATM, we need 2042303a9caSJerome Brunet * NOCACHE to keep our view of the clock as accurate as possible 2052303a9caSJerome Brunet */ 206738f66d3SMichael Turquette .flags = CLK_GET_RATE_NOCACHE, 207738f66d3SMichael Turquette }, 208738f66d3SMichael Turquette }; 209738f66d3SMichael Turquette 2100058502fSNeil Armstrong static struct clk_regmap gxl_hdmi_pll_dco = { 2110058502fSNeil Armstrong .data = &(struct meson_clk_pll_data){ 2120058502fSNeil Armstrong .en = { 2130058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL, 2140058502fSNeil Armstrong .shift = 30, 2150058502fSNeil Armstrong .width = 1, 2160058502fSNeil Armstrong }, 2170058502fSNeil Armstrong .m = { 2180058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL, 2190058502fSNeil Armstrong .shift = 0, 2200058502fSNeil Armstrong .width = 9, 2210058502fSNeil Armstrong }, 2220058502fSNeil Armstrong .n = { 2230058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL, 2240058502fSNeil Armstrong .shift = 9, 2250058502fSNeil Armstrong .width = 5, 2260058502fSNeil Armstrong }, 22721310c39SNeil Armstrong /* 22821310c39SNeil Armstrong * On gxl, there is a register shift due to 22921310c39SNeil Armstrong * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb, 23021310c39SNeil Armstrong * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB 23121310c39SNeil Armstrong * instead which is defined at the same offset. 23221310c39SNeil Armstrong */ 2330058502fSNeil Armstrong .frac = { 2340058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL2, 2350058502fSNeil Armstrong .shift = 0, 23621310c39SNeil Armstrong .width = 10, 2370058502fSNeil Armstrong }, 2380058502fSNeil Armstrong .l = { 2390058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL, 2400058502fSNeil Armstrong .shift = 31, 2410058502fSNeil Armstrong .width = 1, 2420058502fSNeil Armstrong }, 2430058502fSNeil Armstrong .rst = { 2440058502fSNeil Armstrong .reg_off = HHI_HDMI_PLL_CNTL, 2450058502fSNeil Armstrong .shift = 28, 2460058502fSNeil Armstrong .width = 1, 2470058502fSNeil Armstrong }, 2480058502fSNeil Armstrong }, 2490058502fSNeil Armstrong .hw.init = &(struct clk_init_data){ 2500058502fSNeil Armstrong .name = "hdmi_pll_dco", 2510058502fSNeil Armstrong .ops = &meson_clk_pll_ro_ops, 2520dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 2530dea3f35SAlexandre Mergnat .fw_name = "xtal", 2540dea3f35SAlexandre Mergnat }, 2550058502fSNeil Armstrong .num_parents = 1, 2560058502fSNeil Armstrong /* 2570058502fSNeil Armstrong * Display directly handle hdmi pll registers ATM, we need 2580058502fSNeil Armstrong * NOCACHE to keep our view of the clock as accurate as possible 2590058502fSNeil Armstrong */ 2600058502fSNeil Armstrong .flags = CLK_GET_RATE_NOCACHE, 2610058502fSNeil Armstrong }, 2620058502fSNeil Armstrong }; 2630058502fSNeil Armstrong 26487173557SJerome Brunet static struct clk_regmap gxbb_hdmi_pll_od = { 26587173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 26687173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL2, 26787173557SJerome Brunet .shift = 16, 26887173557SJerome Brunet .width = 2, 26987173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 27087173557SJerome Brunet }, 27187173557SJerome Brunet .hw.init = &(struct clk_init_data){ 27287173557SJerome Brunet .name = "hdmi_pll_od", 27387173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 2740dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 2750dea3f35SAlexandre Mergnat &gxbb_hdmi_pll_dco.hw 2760dea3f35SAlexandre Mergnat }, 27787173557SJerome Brunet .num_parents = 1, 27887173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 27987173557SJerome Brunet }, 28087173557SJerome Brunet }; 28187173557SJerome Brunet 28287173557SJerome Brunet static struct clk_regmap gxbb_hdmi_pll_od2 = { 28387173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 28487173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL2, 28587173557SJerome Brunet .shift = 22, 28687173557SJerome Brunet .width = 2, 28787173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 28887173557SJerome Brunet }, 28987173557SJerome Brunet .hw.init = &(struct clk_init_data){ 29087173557SJerome Brunet .name = "hdmi_pll_od2", 29187173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 2920dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 2930dea3f35SAlexandre Mergnat &gxbb_hdmi_pll_od.hw 2940dea3f35SAlexandre Mergnat }, 29587173557SJerome Brunet .num_parents = 1, 29687173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 29787173557SJerome Brunet }, 29887173557SJerome Brunet }; 29987173557SJerome Brunet 30087173557SJerome Brunet static struct clk_regmap gxbb_hdmi_pll = { 30187173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 30287173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL2, 30387173557SJerome Brunet .shift = 18, 30487173557SJerome Brunet .width = 2, 30587173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 30687173557SJerome Brunet }, 30787173557SJerome Brunet .hw.init = &(struct clk_init_data){ 30887173557SJerome Brunet .name = "hdmi_pll", 30987173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 3100dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 3110dea3f35SAlexandre Mergnat &gxbb_hdmi_pll_od2.hw 3120dea3f35SAlexandre Mergnat }, 31387173557SJerome Brunet .num_parents = 1, 31487173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 31587173557SJerome Brunet }, 31687173557SJerome Brunet }; 31787173557SJerome Brunet 31887173557SJerome Brunet static struct clk_regmap gxl_hdmi_pll_od = { 31987173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 32087173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL + 8, 32187173557SJerome Brunet .shift = 21, 32287173557SJerome Brunet .width = 2, 32387173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 32487173557SJerome Brunet }, 32587173557SJerome Brunet .hw.init = &(struct clk_init_data){ 32687173557SJerome Brunet .name = "hdmi_pll_od", 32787173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 3280dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 3290dea3f35SAlexandre Mergnat &gxl_hdmi_pll_dco.hw 3300dea3f35SAlexandre Mergnat }, 33187173557SJerome Brunet .num_parents = 1, 33287173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 33387173557SJerome Brunet }, 33487173557SJerome Brunet }; 33587173557SJerome Brunet 33687173557SJerome Brunet static struct clk_regmap gxl_hdmi_pll_od2 = { 33787173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 33887173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL + 8, 33987173557SJerome Brunet .shift = 23, 34087173557SJerome Brunet .width = 2, 34187173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 34287173557SJerome Brunet }, 34387173557SJerome Brunet .hw.init = &(struct clk_init_data){ 34487173557SJerome Brunet .name = "hdmi_pll_od2", 34587173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 3460dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 3470dea3f35SAlexandre Mergnat &gxl_hdmi_pll_od.hw 3480dea3f35SAlexandre Mergnat }, 34987173557SJerome Brunet .num_parents = 1, 35087173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 35187173557SJerome Brunet }, 35287173557SJerome Brunet }; 35387173557SJerome Brunet 354722825dcSJerome Brunet static struct clk_regmap gxl_hdmi_pll = { 35587173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 35687173557SJerome Brunet .offset = HHI_HDMI_PLL_CNTL + 8, 35787173557SJerome Brunet .shift = 19, 35887173557SJerome Brunet .width = 2, 35987173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 36087173557SJerome Brunet }, 36187173557SJerome Brunet .hw.init = &(struct clk_init_data){ 36287173557SJerome Brunet .name = "hdmi_pll", 36387173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 3640dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 3650dea3f35SAlexandre Mergnat &gxl_hdmi_pll_od2.hw 3660dea3f35SAlexandre Mergnat }, 36787173557SJerome Brunet .num_parents = 1, 36887173557SJerome Brunet .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 36987173557SJerome Brunet }, 37087173557SJerome Brunet }; 37187173557SJerome Brunet 37287173557SJerome Brunet static struct clk_regmap gxbb_sys_pll_dco = { 373722825dcSJerome Brunet .data = &(struct meson_clk_pll_data){ 374e40c7e3cSJerome Brunet .en = { 37587173557SJerome Brunet .reg_off = HHI_SYS_PLL_CNTL, 376e40c7e3cSJerome Brunet .shift = 30, 377e40c7e3cSJerome Brunet .width = 1, 378e40c7e3cSJerome Brunet }, 37969d92293SJerome Brunet .m = { 38087173557SJerome Brunet .reg_off = HHI_SYS_PLL_CNTL, 38169d92293SJerome Brunet .shift = 0, 38269d92293SJerome Brunet .width = 9, 38369d92293SJerome Brunet }, 38469d92293SJerome Brunet .n = { 38587173557SJerome Brunet .reg_off = HHI_SYS_PLL_CNTL, 38669d92293SJerome Brunet .shift = 9, 38769d92293SJerome Brunet .width = 5, 38869d92293SJerome Brunet }, 389722825dcSJerome Brunet .l = { 39087173557SJerome Brunet .reg_off = HHI_SYS_PLL_CNTL, 391722825dcSJerome Brunet .shift = 31, 392722825dcSJerome Brunet .width = 1, 393722825dcSJerome Brunet }, 394722825dcSJerome Brunet .rst = { 39587173557SJerome Brunet .reg_off = HHI_SYS_PLL_CNTL, 396722825dcSJerome Brunet .shift = 29, 397722825dcSJerome Brunet .width = 1, 398722825dcSJerome Brunet }, 399722825dcSJerome Brunet }, 40069d92293SJerome Brunet .hw.init = &(struct clk_init_data){ 40187173557SJerome Brunet .name = "sys_pll_dco", 40269d92293SJerome Brunet .ops = &meson_clk_pll_ro_ops, 4030dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 4040dea3f35SAlexandre Mergnat .fw_name = "xtal", 4050dea3f35SAlexandre Mergnat }, 40669d92293SJerome Brunet .num_parents = 1, 40769d92293SJerome Brunet }, 40869d92293SJerome Brunet }; 40969d92293SJerome Brunet 410722825dcSJerome Brunet static struct clk_regmap gxbb_sys_pll = { 41187173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 41287173557SJerome Brunet .offset = HHI_SYS_PLL_CNTL, 413738f66d3SMichael Turquette .shift = 10, 414738f66d3SMichael Turquette .width = 2, 41587173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 416722825dcSJerome Brunet }, 417738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 418738f66d3SMichael Turquette .name = "sys_pll", 41987173557SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 4200dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 4210dea3f35SAlexandre Mergnat &gxbb_sys_pll_dco.hw 4220dea3f35SAlexandre Mergnat }, 423738f66d3SMichael Turquette .num_parents = 1, 42487173557SJerome Brunet .flags = CLK_SET_RATE_PARENT, 425738f66d3SMichael Turquette }, 426738f66d3SMichael Turquette }; 427738f66d3SMichael Turquette 4285d1c04ddSStephen Boyd static const struct reg_sequence gxbb_gp0_init_regs[] = { 429722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 }, 430722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 }, 431722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d }, 432e194401cSNeil Armstrong }; 433e194401cSNeil Armstrong 43487173557SJerome Brunet static struct clk_regmap gxbb_gp0_pll_dco = { 435722825dcSJerome Brunet .data = &(struct meson_clk_pll_data){ 436e40c7e3cSJerome Brunet .en = { 437e40c7e3cSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 438e40c7e3cSJerome Brunet .shift = 30, 439e40c7e3cSJerome Brunet .width = 1, 440e40c7e3cSJerome Brunet }, 441738f66d3SMichael Turquette .m = { 442738f66d3SMichael Turquette .reg_off = HHI_GP0_PLL_CNTL, 443738f66d3SMichael Turquette .shift = 0, 444738f66d3SMichael Turquette .width = 9, 445738f66d3SMichael Turquette }, 446738f66d3SMichael Turquette .n = { 447738f66d3SMichael Turquette .reg_off = HHI_GP0_PLL_CNTL, 448738f66d3SMichael Turquette .shift = 9, 449738f66d3SMichael Turquette .width = 5, 450738f66d3SMichael Turquette }, 451722825dcSJerome Brunet .l = { 452722825dcSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 453722825dcSJerome Brunet .shift = 31, 454722825dcSJerome Brunet .width = 1, 455e194401cSNeil Armstrong }, 456722825dcSJerome Brunet .rst = { 457722825dcSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 458722825dcSJerome Brunet .shift = 29, 459722825dcSJerome Brunet .width = 1, 460722825dcSJerome Brunet }, 461dd601dbcSJerome Brunet .table = gxbb_gp0_pll_params_table, 462722825dcSJerome Brunet .init_regs = gxbb_gp0_init_regs, 463722825dcSJerome Brunet .init_count = ARRAY_SIZE(gxbb_gp0_init_regs), 464722825dcSJerome Brunet }, 4650d48fc55SNeil Armstrong .hw.init = &(struct clk_init_data){ 46687173557SJerome Brunet .name = "gp0_pll_dco", 4670d48fc55SNeil Armstrong .ops = &meson_clk_pll_ops, 4680dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 4690dea3f35SAlexandre Mergnat .fw_name = "xtal", 4700dea3f35SAlexandre Mergnat }, 4710d48fc55SNeil Armstrong .num_parents = 1, 4720d48fc55SNeil Armstrong }, 4730d48fc55SNeil Armstrong }; 4740d48fc55SNeil Armstrong 4755d1c04ddSStephen Boyd static const struct reg_sequence gxl_gp0_init_regs[] = { 476c77de0e5SJerome Brunet { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 }, 477722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, 478722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, 479722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, 480722825dcSJerome Brunet { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, 4810d48fc55SNeil Armstrong }; 4820d48fc55SNeil Armstrong 48387173557SJerome Brunet static struct clk_regmap gxl_gp0_pll_dco = { 484722825dcSJerome Brunet .data = &(struct meson_clk_pll_data){ 485e40c7e3cSJerome Brunet .en = { 486e40c7e3cSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 487e40c7e3cSJerome Brunet .shift = 30, 488e40c7e3cSJerome Brunet .width = 1, 489e40c7e3cSJerome Brunet }, 4900d48fc55SNeil Armstrong .m = { 4910d48fc55SNeil Armstrong .reg_off = HHI_GP0_PLL_CNTL, 4920d48fc55SNeil Armstrong .shift = 0, 4930d48fc55SNeil Armstrong .width = 9, 4940d48fc55SNeil Armstrong }, 4950d48fc55SNeil Armstrong .n = { 4960d48fc55SNeil Armstrong .reg_off = HHI_GP0_PLL_CNTL, 4970d48fc55SNeil Armstrong .shift = 9, 4980d48fc55SNeil Armstrong .width = 5, 4990d48fc55SNeil Armstrong }, 500c77de0e5SJerome Brunet .frac = { 501c77de0e5SJerome Brunet .reg_off = HHI_GP0_PLL_CNTL1, 502c77de0e5SJerome Brunet .shift = 0, 503c77de0e5SJerome Brunet .width = 10, 504c77de0e5SJerome Brunet }, 505722825dcSJerome Brunet .l = { 506722825dcSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 507722825dcSJerome Brunet .shift = 31, 508722825dcSJerome Brunet .width = 1, 5090d48fc55SNeil Armstrong }, 510722825dcSJerome Brunet .rst = { 511722825dcSJerome Brunet .reg_off = HHI_GP0_PLL_CNTL, 512722825dcSJerome Brunet .shift = 29, 513722825dcSJerome Brunet .width = 1, 514722825dcSJerome Brunet }, 515dd601dbcSJerome Brunet .table = gxl_gp0_pll_params_table, 516722825dcSJerome Brunet .init_regs = gxl_gp0_init_regs, 517722825dcSJerome Brunet .init_count = ARRAY_SIZE(gxl_gp0_init_regs), 518722825dcSJerome Brunet }, 519738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 52087173557SJerome Brunet .name = "gp0_pll_dco", 521738f66d3SMichael Turquette .ops = &meson_clk_pll_ops, 5220dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 5230dea3f35SAlexandre Mergnat .fw_name = "xtal", 5240dea3f35SAlexandre Mergnat }, 525738f66d3SMichael Turquette .num_parents = 1, 526738f66d3SMichael Turquette }, 527738f66d3SMichael Turquette }; 528738f66d3SMichael Turquette 52987173557SJerome Brunet static struct clk_regmap gxbb_gp0_pll = { 53087173557SJerome Brunet .data = &(struct clk_regmap_div_data){ 53187173557SJerome Brunet .offset = HHI_GP0_PLL_CNTL, 53287173557SJerome Brunet .shift = 16, 53387173557SJerome Brunet .width = 2, 53487173557SJerome Brunet .flags = CLK_DIVIDER_POWER_OF_TWO, 53587173557SJerome Brunet }, 53687173557SJerome Brunet .hw.init = &(struct clk_init_data){ 53787173557SJerome Brunet .name = "gp0_pll", 53887173557SJerome Brunet .ops = &clk_regmap_divider_ops, 5390dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 5400dea3f35SAlexandre Mergnat /* 5410dea3f35SAlexandre Mergnat * Note: 5420dea3f35SAlexandre Mergnat * GXL and GXBB have different gp0_pll_dco (with 5430dea3f35SAlexandre Mergnat * different struct clk_hw). We fallback to the global 5440dea3f35SAlexandre Mergnat * naming string mechanism so gp0_pll picks up the 5450dea3f35SAlexandre Mergnat * appropriate one. 5460dea3f35SAlexandre Mergnat */ 5470dea3f35SAlexandre Mergnat .name = "gp0_pll_dco", 5480dea3f35SAlexandre Mergnat .index = -1, 5490dea3f35SAlexandre Mergnat }, 55087173557SJerome Brunet .num_parents = 1, 55187173557SJerome Brunet .flags = CLK_SET_RATE_PARENT, 55287173557SJerome Brunet }, 55387173557SJerome Brunet }; 55487173557SJerome Brunet 55505f81440SJerome Brunet static struct clk_fixed_factor gxbb_fclk_div2_div = { 556738f66d3SMichael Turquette .mult = 1, 557738f66d3SMichael Turquette .div = 2, 558738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 55905f81440SJerome Brunet .name = "fclk_div2_div", 560738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 5610dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 5620dea3f35SAlexandre Mergnat &gxbb_fixed_pll.hw 5630dea3f35SAlexandre Mergnat }, 564738f66d3SMichael Turquette .num_parents = 1, 565738f66d3SMichael Turquette }, 566738f66d3SMichael Turquette }; 567738f66d3SMichael Turquette 56805f81440SJerome Brunet static struct clk_regmap gxbb_fclk_div2 = { 56905f81440SJerome Brunet .data = &(struct clk_regmap_gate_data){ 57005f81440SJerome Brunet .offset = HHI_MPLL_CNTL6, 57105f81440SJerome Brunet .bit_idx = 27, 57205f81440SJerome Brunet }, 57305f81440SJerome Brunet .hw.init = &(struct clk_init_data){ 57405f81440SJerome Brunet .name = "fclk_div2", 57505f81440SJerome Brunet .ops = &clk_regmap_gate_ops, 5760dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 5770dea3f35SAlexandre Mergnat &gxbb_fclk_div2_div.hw 5780dea3f35SAlexandre Mergnat }, 57905f81440SJerome Brunet .num_parents = 1, 580c987ac6fSNeil Armstrong .flags = CLK_IS_CRITICAL, 58105f81440SJerome Brunet }, 58205f81440SJerome Brunet }; 58305f81440SJerome Brunet 58405f81440SJerome Brunet static struct clk_fixed_factor gxbb_fclk_div3_div = { 585738f66d3SMichael Turquette .mult = 1, 586738f66d3SMichael Turquette .div = 3, 587738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 58805f81440SJerome Brunet .name = "fclk_div3_div", 589738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 5900dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 591738f66d3SMichael Turquette .num_parents = 1, 592738f66d3SMichael Turquette }, 593738f66d3SMichael Turquette }; 594738f66d3SMichael Turquette 59505f81440SJerome Brunet static struct clk_regmap gxbb_fclk_div3 = { 59605f81440SJerome Brunet .data = &(struct clk_regmap_gate_data){ 59705f81440SJerome Brunet .offset = HHI_MPLL_CNTL6, 59805f81440SJerome Brunet .bit_idx = 28, 59905f81440SJerome Brunet }, 60005f81440SJerome Brunet .hw.init = &(struct clk_init_data){ 60105f81440SJerome Brunet .name = "fclk_div3", 60205f81440SJerome Brunet .ops = &clk_regmap_gate_ops, 6030dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 6040dea3f35SAlexandre Mergnat &gxbb_fclk_div3_div.hw 6050dea3f35SAlexandre Mergnat }, 60605f81440SJerome Brunet .num_parents = 1, 607e2576c8bSChristian Hewitt /* 608e2576c8bSChristian Hewitt * FIXME: 609e2576c8bSChristian Hewitt * This clock, as fdiv2, is used by the SCPI FW and is required 610e2576c8bSChristian Hewitt * by the platform to operate correctly. 611e2576c8bSChristian Hewitt * Until the following condition are met, we need this clock to 612e2576c8bSChristian Hewitt * be marked as critical: 613e2576c8bSChristian Hewitt * a) The SCPI generic driver claims and enable all the clocks 614e2576c8bSChristian Hewitt * it needs 615e2576c8bSChristian Hewitt * b) CCF has a clock hand-off mechanism to make the sure the 616e2576c8bSChristian Hewitt * clock stays on until the proper driver comes along 617e2576c8bSChristian Hewitt */ 618e2576c8bSChristian Hewitt .flags = CLK_IS_CRITICAL, 61905f81440SJerome Brunet }, 62005f81440SJerome Brunet }; 62105f81440SJerome Brunet 62205f81440SJerome Brunet static struct clk_fixed_factor gxbb_fclk_div4_div = { 623738f66d3SMichael Turquette .mult = 1, 624738f66d3SMichael Turquette .div = 4, 625738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 62605f81440SJerome Brunet .name = "fclk_div4_div", 627738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 6280dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 629738f66d3SMichael Turquette .num_parents = 1, 630738f66d3SMichael Turquette }, 631738f66d3SMichael Turquette }; 632738f66d3SMichael Turquette 63305f81440SJerome Brunet static struct clk_regmap gxbb_fclk_div4 = { 63405f81440SJerome Brunet .data = &(struct clk_regmap_gate_data){ 63505f81440SJerome Brunet .offset = HHI_MPLL_CNTL6, 63605f81440SJerome Brunet .bit_idx = 29, 63705f81440SJerome Brunet }, 63805f81440SJerome Brunet .hw.init = &(struct clk_init_data){ 63905f81440SJerome Brunet .name = "fclk_div4", 64005f81440SJerome Brunet .ops = &clk_regmap_gate_ops, 6410dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 6420dea3f35SAlexandre Mergnat &gxbb_fclk_div4_div.hw 6430dea3f35SAlexandre Mergnat }, 64405f81440SJerome Brunet .num_parents = 1, 64505f81440SJerome Brunet }, 64605f81440SJerome Brunet }; 64705f81440SJerome Brunet 64805f81440SJerome Brunet static struct clk_fixed_factor gxbb_fclk_div5_div = { 649738f66d3SMichael Turquette .mult = 1, 650738f66d3SMichael Turquette .div = 5, 651738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 65205f81440SJerome Brunet .name = "fclk_div5_div", 653738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 6540dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 655738f66d3SMichael Turquette .num_parents = 1, 656738f66d3SMichael Turquette }, 657738f66d3SMichael Turquette }; 658738f66d3SMichael Turquette 65905f81440SJerome Brunet static struct clk_regmap gxbb_fclk_div5 = { 66005f81440SJerome Brunet .data = &(struct clk_regmap_gate_data){ 66105f81440SJerome Brunet .offset = HHI_MPLL_CNTL6, 66205f81440SJerome Brunet .bit_idx = 30, 66305f81440SJerome Brunet }, 66405f81440SJerome Brunet .hw.init = &(struct clk_init_data){ 66505f81440SJerome Brunet .name = "fclk_div5", 66605f81440SJerome Brunet .ops = &clk_regmap_gate_ops, 6670dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 6680dea3f35SAlexandre Mergnat &gxbb_fclk_div5_div.hw 6690dea3f35SAlexandre Mergnat }, 67005f81440SJerome Brunet .num_parents = 1, 67105f81440SJerome Brunet }, 67205f81440SJerome Brunet }; 67305f81440SJerome Brunet 67405f81440SJerome Brunet static struct clk_fixed_factor gxbb_fclk_div7_div = { 675738f66d3SMichael Turquette .mult = 1, 676738f66d3SMichael Turquette .div = 7, 677738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 67805f81440SJerome Brunet .name = "fclk_div7_div", 679738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 6800dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 681738f66d3SMichael Turquette .num_parents = 1, 682738f66d3SMichael Turquette }, 683738f66d3SMichael Turquette }; 684738f66d3SMichael Turquette 68505f81440SJerome Brunet static struct clk_regmap gxbb_fclk_div7 = { 68605f81440SJerome Brunet .data = &(struct clk_regmap_gate_data){ 68705f81440SJerome Brunet .offset = HHI_MPLL_CNTL6, 68805f81440SJerome Brunet .bit_idx = 31, 68905f81440SJerome Brunet }, 69005f81440SJerome Brunet .hw.init = &(struct clk_init_data){ 69105f81440SJerome Brunet .name = "fclk_div7", 69205f81440SJerome Brunet .ops = &clk_regmap_gate_ops, 6930dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 6940dea3f35SAlexandre Mergnat &gxbb_fclk_div7_div.hw 6950dea3f35SAlexandre Mergnat }, 69605f81440SJerome Brunet .num_parents = 1, 69705f81440SJerome Brunet }, 69805f81440SJerome Brunet }; 69905f81440SJerome Brunet 700513b67acSJerome Brunet static struct clk_regmap gxbb_mpll_prediv = { 701513b67acSJerome Brunet .data = &(struct clk_regmap_div_data){ 702513b67acSJerome Brunet .offset = HHI_MPLL_CNTL5, 703513b67acSJerome Brunet .shift = 12, 704513b67acSJerome Brunet .width = 1, 705513b67acSJerome Brunet }, 706513b67acSJerome Brunet .hw.init = &(struct clk_init_data){ 707513b67acSJerome Brunet .name = "mpll_prediv", 708513b67acSJerome Brunet .ops = &clk_regmap_divider_ro_ops, 7090dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw }, 710513b67acSJerome Brunet .num_parents = 1, 711513b67acSJerome Brunet }, 712513b67acSJerome Brunet }; 713513b67acSJerome Brunet 714d610b54fSJerome Brunet static struct clk_regmap gxbb_mpll0_div = { 715c763e61aSJerome Brunet .data = &(struct meson_clk_mpll_data){ 716738f66d3SMichael Turquette .sdm = { 717738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL7, 718738f66d3SMichael Turquette .shift = 0, 719738f66d3SMichael Turquette .width = 14, 720738f66d3SMichael Turquette }, 721007e6e5cSJerome Brunet .sdm_en = { 722007e6e5cSJerome Brunet .reg_off = HHI_MPLL_CNTL7, 723007e6e5cSJerome Brunet .shift = 15, 724007e6e5cSJerome Brunet .width = 1, 725007e6e5cSJerome Brunet }, 726738f66d3SMichael Turquette .n2 = { 727738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL7, 728738f66d3SMichael Turquette .shift = 16, 729738f66d3SMichael Turquette .width = 9, 730738f66d3SMichael Turquette }, 73127aad905SYixun Lan .lock = &meson_clk_lock, 732c763e61aSJerome Brunet }, 733738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 734d610b54fSJerome Brunet .name = "mpll0_div", 735d610b54fSJerome Brunet .ops = &meson_clk_mpll_ops, 7360dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 7370dea3f35SAlexandre Mergnat &gxbb_mpll_prediv.hw 7380dea3f35SAlexandre Mergnat }, 739d610b54fSJerome Brunet .num_parents = 1, 740d610b54fSJerome Brunet }, 741d610b54fSJerome Brunet }; 742d610b54fSJerome Brunet 743d610b54fSJerome Brunet static struct clk_regmap gxbb_mpll0 = { 744d610b54fSJerome Brunet .data = &(struct clk_regmap_gate_data){ 745d610b54fSJerome Brunet .offset = HHI_MPLL_CNTL7, 746d610b54fSJerome Brunet .bit_idx = 14, 747d610b54fSJerome Brunet }, 748d610b54fSJerome Brunet .hw.init = &(struct clk_init_data){ 749738f66d3SMichael Turquette .name = "mpll0", 750d610b54fSJerome Brunet .ops = &clk_regmap_gate_ops, 7510dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll0_div.hw }, 752d610b54fSJerome Brunet .num_parents = 1, 753d610b54fSJerome Brunet .flags = CLK_SET_RATE_PARENT, 754d610b54fSJerome Brunet }, 755d610b54fSJerome Brunet }; 756d610b54fSJerome Brunet 757d610b54fSJerome Brunet static struct clk_regmap gxbb_mpll1_div = { 758d610b54fSJerome Brunet .data = &(struct meson_clk_mpll_data){ 759d610b54fSJerome Brunet .sdm = { 760d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL8, 761d610b54fSJerome Brunet .shift = 0, 762d610b54fSJerome Brunet .width = 14, 763d610b54fSJerome Brunet }, 764d610b54fSJerome Brunet .sdm_en = { 765d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL8, 766d610b54fSJerome Brunet .shift = 15, 767d610b54fSJerome Brunet .width = 1, 768d610b54fSJerome Brunet }, 769d610b54fSJerome Brunet .n2 = { 770d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL8, 771d610b54fSJerome Brunet .shift = 16, 772d610b54fSJerome Brunet .width = 9, 773d610b54fSJerome Brunet }, 774d610b54fSJerome Brunet .lock = &meson_clk_lock, 775d610b54fSJerome Brunet }, 776d610b54fSJerome Brunet .hw.init = &(struct clk_init_data){ 777d610b54fSJerome Brunet .name = "mpll1_div", 77805b43aa2SJerome Brunet .ops = &meson_clk_mpll_ops, 7790dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 7800dea3f35SAlexandre Mergnat &gxbb_mpll_prediv.hw 7810dea3f35SAlexandre Mergnat }, 782738f66d3SMichael Turquette .num_parents = 1, 783738f66d3SMichael Turquette }, 784738f66d3SMichael Turquette }; 785738f66d3SMichael Turquette 786c763e61aSJerome Brunet static struct clk_regmap gxbb_mpll1 = { 787d610b54fSJerome Brunet .data = &(struct clk_regmap_gate_data){ 788d610b54fSJerome Brunet .offset = HHI_MPLL_CNTL8, 789d610b54fSJerome Brunet .bit_idx = 14, 790d610b54fSJerome Brunet }, 791d610b54fSJerome Brunet .hw.init = &(struct clk_init_data){ 792d610b54fSJerome Brunet .name = "mpll1", 793d610b54fSJerome Brunet .ops = &clk_regmap_gate_ops, 7940dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw }, 795d610b54fSJerome Brunet .num_parents = 1, 796d610b54fSJerome Brunet .flags = CLK_SET_RATE_PARENT, 797d610b54fSJerome Brunet }, 798d610b54fSJerome Brunet }; 799d610b54fSJerome Brunet 800d610b54fSJerome Brunet static struct clk_regmap gxbb_mpll2_div = { 801c763e61aSJerome Brunet .data = &(struct meson_clk_mpll_data){ 802738f66d3SMichael Turquette .sdm = { 803d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL9, 804738f66d3SMichael Turquette .shift = 0, 805738f66d3SMichael Turquette .width = 14, 806738f66d3SMichael Turquette }, 807007e6e5cSJerome Brunet .sdm_en = { 808d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL9, 809007e6e5cSJerome Brunet .shift = 15, 810007e6e5cSJerome Brunet .width = 1, 811007e6e5cSJerome Brunet }, 812738f66d3SMichael Turquette .n2 = { 813d610b54fSJerome Brunet .reg_off = HHI_MPLL_CNTL9, 814738f66d3SMichael Turquette .shift = 16, 815738f66d3SMichael Turquette .width = 9, 816738f66d3SMichael Turquette }, 81727aad905SYixun Lan .lock = &meson_clk_lock, 818c763e61aSJerome Brunet }, 819738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 820d610b54fSJerome Brunet .name = "mpll2_div", 82105b43aa2SJerome Brunet .ops = &meson_clk_mpll_ops, 8220dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 8230dea3f35SAlexandre Mergnat &gxbb_mpll_prediv.hw 8240dea3f35SAlexandre Mergnat }, 825738f66d3SMichael Turquette .num_parents = 1, 826738f66d3SMichael Turquette }, 827738f66d3SMichael Turquette }; 828738f66d3SMichael Turquette 829c763e61aSJerome Brunet static struct clk_regmap gxbb_mpll2 = { 830d610b54fSJerome Brunet .data = &(struct clk_regmap_gate_data){ 831d610b54fSJerome Brunet .offset = HHI_MPLL_CNTL9, 832d610b54fSJerome Brunet .bit_idx = 14, 833c763e61aSJerome Brunet }, 834738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 835738f66d3SMichael Turquette .name = "mpll2", 836d610b54fSJerome Brunet .ops = &clk_regmap_gate_ops, 8370dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw }, 838738f66d3SMichael Turquette .num_parents = 1, 839d610b54fSJerome Brunet .flags = CLK_SET_RATE_PARENT, 840738f66d3SMichael Turquette }, 841738f66d3SMichael Turquette }; 842738f66d3SMichael Turquette 843215c80a7SJerome Brunet static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 8440dea3f35SAlexandre Mergnat static const struct clk_parent_data clk81_parent_data[] = { 8450dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 8460dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div7.hw }, 8470dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll1.hw }, 8480dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll2.hw }, 8490dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div4.hw }, 8500dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 8510dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 852215c80a7SJerome Brunet }; 853738f66d3SMichael Turquette 8542513a28cSJerome Brunet static struct clk_regmap gxbb_mpeg_clk_sel = { 8552513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 8562513a28cSJerome Brunet .offset = HHI_MPEG_CLK_CNTL, 857738f66d3SMichael Turquette .mask = 0x7, 858738f66d3SMichael Turquette .shift = 12, 859738f66d3SMichael Turquette .table = mux_table_clk81, 8602513a28cSJerome Brunet }, 861738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 862738f66d3SMichael Turquette .name = "mpeg_clk_sel", 8632513a28cSJerome Brunet .ops = &clk_regmap_mux_ro_ops, 864738f66d3SMichael Turquette /* 865215c80a7SJerome Brunet * bits 14:12 selects from 8 possible parents: 866738f66d3SMichael Turquette * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 867738f66d3SMichael Turquette * fclk_div4, fclk_div3, fclk_div5 868738f66d3SMichael Turquette */ 8690dea3f35SAlexandre Mergnat .parent_data = clk81_parent_data, 8700dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(clk81_parent_data), 871738f66d3SMichael Turquette }, 872738f66d3SMichael Turquette }; 873738f66d3SMichael Turquette 874f06ddd28SJerome Brunet static struct clk_regmap gxbb_mpeg_clk_div = { 875f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 876f06ddd28SJerome Brunet .offset = HHI_MPEG_CLK_CNTL, 877738f66d3SMichael Turquette .shift = 0, 878738f66d3SMichael Turquette .width = 7, 879f06ddd28SJerome Brunet }, 880738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 881738f66d3SMichael Turquette .name = "mpeg_clk_div", 8825b13ef64SJerome Brunet .ops = &clk_regmap_divider_ro_ops, 8830dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 8840dea3f35SAlexandre Mergnat &gxbb_mpeg_clk_sel.hw 8850dea3f35SAlexandre Mergnat }, 886738f66d3SMichael Turquette .num_parents = 1, 887738f66d3SMichael Turquette }, 888738f66d3SMichael Turquette }; 889738f66d3SMichael Turquette 8907f9768a5SJerome Brunet /* the mother of dragons gates */ 8917f9768a5SJerome Brunet static struct clk_regmap gxbb_clk81 = { 8927f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 8937f9768a5SJerome Brunet .offset = HHI_MPEG_CLK_CNTL, 894738f66d3SMichael Turquette .bit_idx = 7, 8957f9768a5SJerome Brunet }, 896738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 897738f66d3SMichael Turquette .name = "clk81", 8987f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 8990dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 9000dea3f35SAlexandre Mergnat &gxbb_mpeg_clk_div.hw 9010dea3f35SAlexandre Mergnat }, 902738f66d3SMichael Turquette .num_parents = 1, 9035b13ef64SJerome Brunet .flags = CLK_IS_CRITICAL, 904738f66d3SMichael Turquette }, 905738f66d3SMichael Turquette }; 906738f66d3SMichael Turquette 9072513a28cSJerome Brunet static struct clk_regmap gxbb_sar_adc_clk_sel = { 9082513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 9092513a28cSJerome Brunet .offset = HHI_SAR_CLK_CNTL, 91033d0fcdfSMartin Blumenstingl .mask = 0x3, 91133d0fcdfSMartin Blumenstingl .shift = 9, 9122513a28cSJerome Brunet }, 91333d0fcdfSMartin Blumenstingl .hw.init = &(struct clk_init_data){ 91433d0fcdfSMartin Blumenstingl .name = "sar_adc_clk_sel", 9152513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 91633d0fcdfSMartin Blumenstingl /* NOTE: The datasheet doesn't list the parents for bit 10 */ 9170dea3f35SAlexandre Mergnat .parent_data = (const struct clk_parent_data []) { 9180dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 9190dea3f35SAlexandre Mergnat { .hw = &gxbb_clk81.hw }, 9200dea3f35SAlexandre Mergnat }, 92133d0fcdfSMartin Blumenstingl .num_parents = 2, 92233d0fcdfSMartin Blumenstingl }, 92333d0fcdfSMartin Blumenstingl }; 92433d0fcdfSMartin Blumenstingl 925f06ddd28SJerome Brunet static struct clk_regmap gxbb_sar_adc_clk_div = { 926f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 927f06ddd28SJerome Brunet .offset = HHI_SAR_CLK_CNTL, 92833d0fcdfSMartin Blumenstingl .shift = 0, 92933d0fcdfSMartin Blumenstingl .width = 8, 930f06ddd28SJerome Brunet }, 93133d0fcdfSMartin Blumenstingl .hw.init = &(struct clk_init_data){ 93233d0fcdfSMartin Blumenstingl .name = "sar_adc_clk_div", 933f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 9340dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 9350dea3f35SAlexandre Mergnat &gxbb_sar_adc_clk_sel.hw 9360dea3f35SAlexandre Mergnat }, 93733d0fcdfSMartin Blumenstingl .num_parents = 1, 93844b09b11SMartin Blumenstingl .flags = CLK_SET_RATE_PARENT, 93933d0fcdfSMartin Blumenstingl }, 94033d0fcdfSMartin Blumenstingl }; 94133d0fcdfSMartin Blumenstingl 9427f9768a5SJerome Brunet static struct clk_regmap gxbb_sar_adc_clk = { 9437f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 9447f9768a5SJerome Brunet .offset = HHI_SAR_CLK_CNTL, 94533d0fcdfSMartin Blumenstingl .bit_idx = 8, 9467f9768a5SJerome Brunet }, 94733d0fcdfSMartin Blumenstingl .hw.init = &(struct clk_init_data){ 94833d0fcdfSMartin Blumenstingl .name = "sar_adc_clk", 9497f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 9500dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 9510dea3f35SAlexandre Mergnat &gxbb_sar_adc_clk_div.hw 9520dea3f35SAlexandre Mergnat }, 95333d0fcdfSMartin Blumenstingl .num_parents = 1, 95433d0fcdfSMartin Blumenstingl .flags = CLK_SET_RATE_PARENT, 95533d0fcdfSMartin Blumenstingl }, 95633d0fcdfSMartin Blumenstingl }; 95733d0fcdfSMartin Blumenstingl 958fac9a55bSNeil Armstrong /* 959fac9a55bSNeil Armstrong * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 960fac9a55bSNeil Armstrong * muxed by a glitch-free switch. 961fac9a55bSNeil Armstrong */ 962fac9a55bSNeil Armstrong 9630dea3f35SAlexandre Mergnat static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = { 9640dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 9650dea3f35SAlexandre Mergnat { .hw = &gxbb_gp0_pll.hw }, 9660dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll2.hw }, 9670dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll1.hw }, 9680dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div7.hw }, 9690dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div4.hw }, 9700dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 9710dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 972fac9a55bSNeil Armstrong }; 973fac9a55bSNeil Armstrong 9742513a28cSJerome Brunet static struct clk_regmap gxbb_mali_0_sel = { 9752513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 9762513a28cSJerome Brunet .offset = HHI_MALI_CLK_CNTL, 977fac9a55bSNeil Armstrong .mask = 0x7, 978fac9a55bSNeil Armstrong .shift = 9, 9792513a28cSJerome Brunet }, 980fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 981fac9a55bSNeil Armstrong .name = "mali_0_sel", 9822513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 983fac9a55bSNeil Armstrong /* 984fac9a55bSNeil Armstrong * bits 10:9 selects from 8 possible parents: 985fac9a55bSNeil Armstrong * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 986fac9a55bSNeil Armstrong * fclk_div4, fclk_div3, fclk_div5 987fac9a55bSNeil Armstrong */ 9880dea3f35SAlexandre Mergnat .parent_data = gxbb_mali_0_1_parent_data, 989fac9a55bSNeil Armstrong .num_parents = 8, 990fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 991fac9a55bSNeil Armstrong }, 992fac9a55bSNeil Armstrong }; 993fac9a55bSNeil Armstrong 994f06ddd28SJerome Brunet static struct clk_regmap gxbb_mali_0_div = { 995f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 996f06ddd28SJerome Brunet .offset = HHI_MALI_CLK_CNTL, 997fac9a55bSNeil Armstrong .shift = 0, 998fac9a55bSNeil Armstrong .width = 7, 999f06ddd28SJerome Brunet }, 1000fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1001fac9a55bSNeil Armstrong .name = "mali_0_div", 1002f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 10030dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 10040dea3f35SAlexandre Mergnat &gxbb_mali_0_sel.hw 10050dea3f35SAlexandre Mergnat }, 1006fac9a55bSNeil Armstrong .num_parents = 1, 1007fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1008fac9a55bSNeil Armstrong }, 1009fac9a55bSNeil Armstrong }; 1010fac9a55bSNeil Armstrong 10117f9768a5SJerome Brunet static struct clk_regmap gxbb_mali_0 = { 10127f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 10137f9768a5SJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1014fac9a55bSNeil Armstrong .bit_idx = 8, 10157f9768a5SJerome Brunet }, 1016fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1017fac9a55bSNeil Armstrong .name = "mali_0", 10187f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 10190dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 10200dea3f35SAlexandre Mergnat &gxbb_mali_0_div.hw 10210dea3f35SAlexandre Mergnat }, 1022fac9a55bSNeil Armstrong .num_parents = 1, 1023fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1024fac9a55bSNeil Armstrong }, 1025fac9a55bSNeil Armstrong }; 1026fac9a55bSNeil Armstrong 10272513a28cSJerome Brunet static struct clk_regmap gxbb_mali_1_sel = { 10282513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 10292513a28cSJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1030fac9a55bSNeil Armstrong .mask = 0x7, 1031fac9a55bSNeil Armstrong .shift = 25, 10322513a28cSJerome Brunet }, 1033fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1034fac9a55bSNeil Armstrong .name = "mali_1_sel", 10352513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1036fac9a55bSNeil Armstrong /* 1037fac9a55bSNeil Armstrong * bits 10:9 selects from 8 possible parents: 1038fac9a55bSNeil Armstrong * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 1039fac9a55bSNeil Armstrong * fclk_div4, fclk_div3, fclk_div5 1040fac9a55bSNeil Armstrong */ 10410dea3f35SAlexandre Mergnat .parent_data = gxbb_mali_0_1_parent_data, 1042fac9a55bSNeil Armstrong .num_parents = 8, 1043fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1044fac9a55bSNeil Armstrong }, 1045fac9a55bSNeil Armstrong }; 1046fac9a55bSNeil Armstrong 1047f06ddd28SJerome Brunet static struct clk_regmap gxbb_mali_1_div = { 1048f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1049f06ddd28SJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1050fac9a55bSNeil Armstrong .shift = 16, 1051fac9a55bSNeil Armstrong .width = 7, 1052f06ddd28SJerome Brunet }, 1053fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1054fac9a55bSNeil Armstrong .name = "mali_1_div", 1055f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 10560dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 10570dea3f35SAlexandre Mergnat &gxbb_mali_1_sel.hw 10580dea3f35SAlexandre Mergnat }, 1059fac9a55bSNeil Armstrong .num_parents = 1, 1060fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1061fac9a55bSNeil Armstrong }, 1062fac9a55bSNeil Armstrong }; 1063fac9a55bSNeil Armstrong 10647f9768a5SJerome Brunet static struct clk_regmap gxbb_mali_1 = { 10657f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 10667f9768a5SJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1067fac9a55bSNeil Armstrong .bit_idx = 24, 10687f9768a5SJerome Brunet }, 1069fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1070fac9a55bSNeil Armstrong .name = "mali_1", 10717f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 10720dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 10730dea3f35SAlexandre Mergnat &gxbb_mali_1_div.hw 10740dea3f35SAlexandre Mergnat }, 1075fac9a55bSNeil Armstrong .num_parents = 1, 1076fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1077fac9a55bSNeil Armstrong }, 1078fac9a55bSNeil Armstrong }; 1079fac9a55bSNeil Armstrong 10800dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_mali_parent_hws[] = { 10810dea3f35SAlexandre Mergnat &gxbb_mali_0.hw, 10820dea3f35SAlexandre Mergnat &gxbb_mali_1.hw, 1083fac9a55bSNeil Armstrong }; 1084fac9a55bSNeil Armstrong 10852513a28cSJerome Brunet static struct clk_regmap gxbb_mali = { 10862513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 10872513a28cSJerome Brunet .offset = HHI_MALI_CLK_CNTL, 1088fac9a55bSNeil Armstrong .mask = 1, 1089fac9a55bSNeil Armstrong .shift = 31, 10902513a28cSJerome Brunet }, 1091fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 1092fac9a55bSNeil Armstrong .name = "mali", 10932513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 10940dea3f35SAlexandre Mergnat .parent_hws = gxbb_mali_parent_hws, 1095fac9a55bSNeil Armstrong .num_parents = 2, 1096fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1097fac9a55bSNeil Armstrong }, 1098fac9a55bSNeil Armstrong }; 1099fac9a55bSNeil Armstrong 11002513a28cSJerome Brunet static struct clk_regmap gxbb_cts_amclk_sel = { 11012513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 11022513a28cSJerome Brunet .offset = HHI_AUD_CLK_CNTL, 11034087bd4bSJerome Brunet .mask = 0x3, 11044087bd4bSJerome Brunet .shift = 9, 11054087bd4bSJerome Brunet .table = (u32[]){ 1, 2, 3 }, 11069799d5aeSJerome Brunet .flags = CLK_MUX_ROUND_CLOSEST, 11072513a28cSJerome Brunet }, 11084087bd4bSJerome Brunet .hw.init = &(struct clk_init_data){ 11094087bd4bSJerome Brunet .name = "cts_amclk_sel", 11102513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 11110dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 11120dea3f35SAlexandre Mergnat &gxbb_mpll0.hw, 11130dea3f35SAlexandre Mergnat &gxbb_mpll1.hw, 11140dea3f35SAlexandre Mergnat &gxbb_mpll2.hw, 11150dea3f35SAlexandre Mergnat }, 11164087bd4bSJerome Brunet .num_parents = 3, 11174087bd4bSJerome Brunet }, 11184087bd4bSJerome Brunet }; 11194087bd4bSJerome Brunet 112088a4e128SJerome Brunet static struct clk_regmap gxbb_cts_amclk_div = { 11219799d5aeSJerome Brunet .data = &(struct clk_regmap_div_data) { 11229799d5aeSJerome Brunet .offset = HHI_AUD_CLK_CNTL, 11234087bd4bSJerome Brunet .shift = 0, 11244087bd4bSJerome Brunet .width = 8, 1125004f6f46SJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 112688a4e128SJerome Brunet }, 11274087bd4bSJerome Brunet .hw.init = &(struct clk_init_data){ 11284087bd4bSJerome Brunet .name = "cts_amclk_div", 11299799d5aeSJerome Brunet .ops = &clk_regmap_divider_ops, 11300dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 11310dea3f35SAlexandre Mergnat &gxbb_cts_amclk_sel.hw 11320dea3f35SAlexandre Mergnat }, 11334087bd4bSJerome Brunet .num_parents = 1, 1134004f6f46SJerome Brunet .flags = CLK_SET_RATE_PARENT, 11354087bd4bSJerome Brunet }, 11364087bd4bSJerome Brunet }; 11374087bd4bSJerome Brunet 11387f9768a5SJerome Brunet static struct clk_regmap gxbb_cts_amclk = { 11397f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 11407f9768a5SJerome Brunet .offset = HHI_AUD_CLK_CNTL, 11414087bd4bSJerome Brunet .bit_idx = 8, 11427f9768a5SJerome Brunet }, 11434087bd4bSJerome Brunet .hw.init = &(struct clk_init_data){ 11444087bd4bSJerome Brunet .name = "cts_amclk", 11457f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 11460dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 11470dea3f35SAlexandre Mergnat &gxbb_cts_amclk_div.hw 11480dea3f35SAlexandre Mergnat }, 11494087bd4bSJerome Brunet .num_parents = 1, 11504087bd4bSJerome Brunet .flags = CLK_SET_RATE_PARENT, 11514087bd4bSJerome Brunet }, 11524087bd4bSJerome Brunet }; 11534087bd4bSJerome Brunet 11542513a28cSJerome Brunet static struct clk_regmap gxbb_cts_mclk_i958_sel = { 11552513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 11562513a28cSJerome Brunet .offset = HHI_AUD_CLK_CNTL2, 11573c277c24SJerome Brunet .mask = 0x3, 11583c277c24SJerome Brunet .shift = 25, 11593c277c24SJerome Brunet .table = (u32[]){ 1, 2, 3 }, 11609799d5aeSJerome Brunet .flags = CLK_MUX_ROUND_CLOSEST, 11612513a28cSJerome Brunet }, 11623c277c24SJerome Brunet .hw.init = &(struct clk_init_data) { 11633c277c24SJerome Brunet .name = "cts_mclk_i958_sel", 11642513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 11650dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 11660dea3f35SAlexandre Mergnat &gxbb_mpll0.hw, 11670dea3f35SAlexandre Mergnat &gxbb_mpll1.hw, 11680dea3f35SAlexandre Mergnat &gxbb_mpll2.hw, 11690dea3f35SAlexandre Mergnat }, 11703c277c24SJerome Brunet .num_parents = 3, 11713c277c24SJerome Brunet }, 11723c277c24SJerome Brunet }; 11733c277c24SJerome Brunet 1174f06ddd28SJerome Brunet static struct clk_regmap gxbb_cts_mclk_i958_div = { 1175f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1176f06ddd28SJerome Brunet .offset = HHI_AUD_CLK_CNTL2, 11773c277c24SJerome Brunet .shift = 16, 11783c277c24SJerome Brunet .width = 8, 11797605aa5bSJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 1180f06ddd28SJerome Brunet }, 11813c277c24SJerome Brunet .hw.init = &(struct clk_init_data) { 11823c277c24SJerome Brunet .name = "cts_mclk_i958_div", 1183f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 11840dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 11850dea3f35SAlexandre Mergnat &gxbb_cts_mclk_i958_sel.hw 11860dea3f35SAlexandre Mergnat }, 11873c277c24SJerome Brunet .num_parents = 1, 11887605aa5bSJerome Brunet .flags = CLK_SET_RATE_PARENT, 11893c277c24SJerome Brunet }, 11903c277c24SJerome Brunet }; 11913c277c24SJerome Brunet 11927f9768a5SJerome Brunet static struct clk_regmap gxbb_cts_mclk_i958 = { 11937f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 11947f9768a5SJerome Brunet .offset = HHI_AUD_CLK_CNTL2, 11953c277c24SJerome Brunet .bit_idx = 24, 11967f9768a5SJerome Brunet }, 11973c277c24SJerome Brunet .hw.init = &(struct clk_init_data){ 11983c277c24SJerome Brunet .name = "cts_mclk_i958", 11997f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 12000dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 12010dea3f35SAlexandre Mergnat &gxbb_cts_mclk_i958_div.hw 12020dea3f35SAlexandre Mergnat }, 12033c277c24SJerome Brunet .num_parents = 1, 12043c277c24SJerome Brunet .flags = CLK_SET_RATE_PARENT, 12053c277c24SJerome Brunet }, 12063c277c24SJerome Brunet }; 12073c277c24SJerome Brunet 12082513a28cSJerome Brunet static struct clk_regmap gxbb_cts_i958 = { 12092513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 12102513a28cSJerome Brunet .offset = HHI_AUD_CLK_CNTL2, 12117eaa44f6SJerome Brunet .mask = 0x1, 12127eaa44f6SJerome Brunet .shift = 27, 12132513a28cSJerome Brunet }, 12147eaa44f6SJerome Brunet .hw.init = &(struct clk_init_data){ 12157eaa44f6SJerome Brunet .name = "cts_i958", 12162513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 12170dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 12180dea3f35SAlexandre Mergnat &gxbb_cts_amclk.hw, 12190dea3f35SAlexandre Mergnat &gxbb_cts_mclk_i958.hw 12200dea3f35SAlexandre Mergnat }, 12217eaa44f6SJerome Brunet .num_parents = 2, 12227eaa44f6SJerome Brunet /* 12237eaa44f6SJerome Brunet *The parent is specific to origin of the audio data. Let the 12247eaa44f6SJerome Brunet * consumer choose the appropriate parent 12257eaa44f6SJerome Brunet */ 12267eaa44f6SJerome Brunet .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 12277eaa44f6SJerome Brunet }, 12287eaa44f6SJerome Brunet }; 12297eaa44f6SJerome Brunet 12300dea3f35SAlexandre Mergnat static const struct clk_parent_data gxbb_32k_clk_parent_data[] = { 12310dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 12320dea3f35SAlexandre Mergnat /* 12330dea3f35SAlexandre Mergnat * FIXME: This clock is provided by the ao clock controller but the 12340dea3f35SAlexandre Mergnat * clock is not yet part of the binding of this controller, so string 12350dea3f35SAlexandre Mergnat * name must be use to set this parent. 12360dea3f35SAlexandre Mergnat */ 12370dea3f35SAlexandre Mergnat { .name = "cts_slow_oscin", .index = -1 }, 12380dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 12390dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 12400dea3f35SAlexandre Mergnat }; 12410dea3f35SAlexandre Mergnat 12420dea3f35SAlexandre Mergnat static struct clk_regmap gxbb_32k_clk_sel = { 12430dea3f35SAlexandre Mergnat .data = &(struct clk_regmap_mux_data){ 12440dea3f35SAlexandre Mergnat .offset = HHI_32K_CLK_CNTL, 12450dea3f35SAlexandre Mergnat .mask = 0x3, 12460dea3f35SAlexandre Mergnat .shift = 16, 12470dea3f35SAlexandre Mergnat }, 12480dea3f35SAlexandre Mergnat .hw.init = &(struct clk_init_data){ 12490dea3f35SAlexandre Mergnat .name = "32k_clk_sel", 12500dea3f35SAlexandre Mergnat .ops = &clk_regmap_mux_ops, 12510dea3f35SAlexandre Mergnat .parent_data = gxbb_32k_clk_parent_data, 12520dea3f35SAlexandre Mergnat .num_parents = 4, 12530dea3f35SAlexandre Mergnat .flags = CLK_SET_RATE_PARENT, 12540dea3f35SAlexandre Mergnat }, 12550dea3f35SAlexandre Mergnat }; 12560dea3f35SAlexandre Mergnat 1257f06ddd28SJerome Brunet static struct clk_regmap gxbb_32k_clk_div = { 1258f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1259f06ddd28SJerome Brunet .offset = HHI_32K_CLK_CNTL, 126014c735c8SNeil Armstrong .shift = 0, 126114c735c8SNeil Armstrong .width = 14, 1262f06ddd28SJerome Brunet }, 126314c735c8SNeil Armstrong .hw.init = &(struct clk_init_data){ 126414c735c8SNeil Armstrong .name = "32k_clk_div", 1265f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 12660dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 12670dea3f35SAlexandre Mergnat &gxbb_32k_clk_sel.hw 12680dea3f35SAlexandre Mergnat }, 126914c735c8SNeil Armstrong .num_parents = 1, 127014c735c8SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, 127114c735c8SNeil Armstrong }, 127214c735c8SNeil Armstrong }; 127314c735c8SNeil Armstrong 12747f9768a5SJerome Brunet static struct clk_regmap gxbb_32k_clk = { 12757f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 12767f9768a5SJerome Brunet .offset = HHI_32K_CLK_CNTL, 127714c735c8SNeil Armstrong .bit_idx = 15, 12787f9768a5SJerome Brunet }, 127914c735c8SNeil Armstrong .hw.init = &(struct clk_init_data){ 128014c735c8SNeil Armstrong .name = "32k_clk", 12817f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 12820dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 12830dea3f35SAlexandre Mergnat &gxbb_32k_clk_div.hw 12840dea3f35SAlexandre Mergnat }, 128514c735c8SNeil Armstrong .num_parents = 1, 128614c735c8SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 128714c735c8SNeil Armstrong }, 128814c735c8SNeil Armstrong }; 128914c735c8SNeil Armstrong 12900dea3f35SAlexandre Mergnat static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = { 12910dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 12920dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div2.hw }, 12930dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 12940dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 12950dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div7.hw }, 1296914e6e80SJerome Brunet /* 1297914e6e80SJerome Brunet * Following these parent clocks, we should also have had mpll2, mpll3 1298914e6e80SJerome Brunet * and gp0_pll but these clocks are too precious to be used here. All 1299914e6e80SJerome Brunet * the necessary rates for MMC and NAND operation can be acheived using 1300914e6e80SJerome Brunet * xtal or fclk_div clocks 1301914e6e80SJerome Brunet */ 1302914e6e80SJerome Brunet }; 1303914e6e80SJerome Brunet 1304914e6e80SJerome Brunet /* SDIO clock */ 13052513a28cSJerome Brunet static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = { 13062513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 13072513a28cSJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1308914e6e80SJerome Brunet .mask = 0x7, 1309914e6e80SJerome Brunet .shift = 9, 13102513a28cSJerome Brunet }, 1311914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1312914e6e80SJerome Brunet .name = "sd_emmc_a_clk0_sel", 13132513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 13140dea3f35SAlexandre Mergnat .parent_data = gxbb_sd_emmc_clk0_parent_data, 13150dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data), 1316914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1317914e6e80SJerome Brunet }, 1318914e6e80SJerome Brunet }; 1319914e6e80SJerome Brunet 1320f06ddd28SJerome Brunet static struct clk_regmap gxbb_sd_emmc_a_clk0_div = { 1321f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1322f06ddd28SJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1323914e6e80SJerome Brunet .shift = 0, 1324914e6e80SJerome Brunet .width = 7, 1325914e6e80SJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 1326f06ddd28SJerome Brunet }, 1327914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1328914e6e80SJerome Brunet .name = "sd_emmc_a_clk0_div", 1329f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 13300dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 13310dea3f35SAlexandre Mergnat &gxbb_sd_emmc_a_clk0_sel.hw 13320dea3f35SAlexandre Mergnat }, 1333914e6e80SJerome Brunet .num_parents = 1, 1334914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1335914e6e80SJerome Brunet }, 1336914e6e80SJerome Brunet }; 1337914e6e80SJerome Brunet 13387f9768a5SJerome Brunet static struct clk_regmap gxbb_sd_emmc_a_clk0 = { 13397f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 13407f9768a5SJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1341914e6e80SJerome Brunet .bit_idx = 7, 13427f9768a5SJerome Brunet }, 1343914e6e80SJerome Brunet .hw.init = &(struct clk_init_data){ 1344914e6e80SJerome Brunet .name = "sd_emmc_a_clk0", 13457f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 13460dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 13470dea3f35SAlexandre Mergnat &gxbb_sd_emmc_a_clk0_div.hw 13480dea3f35SAlexandre Mergnat }, 1349914e6e80SJerome Brunet .num_parents = 1, 1350ed3fb5afSJerome Brunet .flags = CLK_SET_RATE_PARENT, 1351914e6e80SJerome Brunet }, 1352914e6e80SJerome Brunet }; 1353914e6e80SJerome Brunet 1354914e6e80SJerome Brunet /* SDcard clock */ 13552513a28cSJerome Brunet static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = { 13562513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 13572513a28cSJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1358914e6e80SJerome Brunet .mask = 0x7, 1359914e6e80SJerome Brunet .shift = 25, 13602513a28cSJerome Brunet }, 1361914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1362914e6e80SJerome Brunet .name = "sd_emmc_b_clk0_sel", 13632513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 13640dea3f35SAlexandre Mergnat .parent_data = gxbb_sd_emmc_clk0_parent_data, 13650dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data), 1366914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1367914e6e80SJerome Brunet }, 1368914e6e80SJerome Brunet }; 1369914e6e80SJerome Brunet 1370f06ddd28SJerome Brunet static struct clk_regmap gxbb_sd_emmc_b_clk0_div = { 1371f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1372f06ddd28SJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1373914e6e80SJerome Brunet .shift = 16, 1374914e6e80SJerome Brunet .width = 7, 1375914e6e80SJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 1376f06ddd28SJerome Brunet }, 1377914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1378914e6e80SJerome Brunet .name = "sd_emmc_b_clk0_div", 1379f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 13800dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 13810dea3f35SAlexandre Mergnat &gxbb_sd_emmc_b_clk0_sel.hw 13820dea3f35SAlexandre Mergnat }, 1383914e6e80SJerome Brunet .num_parents = 1, 1384914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1385914e6e80SJerome Brunet }, 1386914e6e80SJerome Brunet }; 1387914e6e80SJerome Brunet 13887f9768a5SJerome Brunet static struct clk_regmap gxbb_sd_emmc_b_clk0 = { 13897f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 13907f9768a5SJerome Brunet .offset = HHI_SD_EMMC_CLK_CNTL, 1391914e6e80SJerome Brunet .bit_idx = 23, 13927f9768a5SJerome Brunet }, 1393914e6e80SJerome Brunet .hw.init = &(struct clk_init_data){ 1394914e6e80SJerome Brunet .name = "sd_emmc_b_clk0", 13957f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 13960dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 13970dea3f35SAlexandre Mergnat &gxbb_sd_emmc_b_clk0_div.hw 13980dea3f35SAlexandre Mergnat }, 1399914e6e80SJerome Brunet .num_parents = 1, 1400ed3fb5afSJerome Brunet .flags = CLK_SET_RATE_PARENT, 1401914e6e80SJerome Brunet }, 1402914e6e80SJerome Brunet }; 1403914e6e80SJerome Brunet 1404914e6e80SJerome Brunet /* EMMC/NAND clock */ 14052513a28cSJerome Brunet static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = { 14062513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 14072513a28cSJerome Brunet .offset = HHI_NAND_CLK_CNTL, 1408914e6e80SJerome Brunet .mask = 0x7, 1409914e6e80SJerome Brunet .shift = 9, 14102513a28cSJerome Brunet }, 1411914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1412914e6e80SJerome Brunet .name = "sd_emmc_c_clk0_sel", 14132513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 14140dea3f35SAlexandre Mergnat .parent_data = gxbb_sd_emmc_clk0_parent_data, 14150dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data), 1416914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1417914e6e80SJerome Brunet }, 1418914e6e80SJerome Brunet }; 1419914e6e80SJerome Brunet 1420f06ddd28SJerome Brunet static struct clk_regmap gxbb_sd_emmc_c_clk0_div = { 1421f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1422f06ddd28SJerome Brunet .offset = HHI_NAND_CLK_CNTL, 1423914e6e80SJerome Brunet .shift = 0, 1424914e6e80SJerome Brunet .width = 7, 1425914e6e80SJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 1426f06ddd28SJerome Brunet }, 1427914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1428914e6e80SJerome Brunet .name = "sd_emmc_c_clk0_div", 1429f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 14300dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 14310dea3f35SAlexandre Mergnat &gxbb_sd_emmc_c_clk0_sel.hw 14320dea3f35SAlexandre Mergnat }, 1433914e6e80SJerome Brunet .num_parents = 1, 1434914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1435914e6e80SJerome Brunet }, 1436914e6e80SJerome Brunet }; 1437914e6e80SJerome Brunet 14387f9768a5SJerome Brunet static struct clk_regmap gxbb_sd_emmc_c_clk0 = { 14397f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 14407f9768a5SJerome Brunet .offset = HHI_NAND_CLK_CNTL, 1441914e6e80SJerome Brunet .bit_idx = 7, 14427f9768a5SJerome Brunet }, 1443914e6e80SJerome Brunet .hw.init = &(struct clk_init_data){ 1444914e6e80SJerome Brunet .name = "sd_emmc_c_clk0", 14457f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 14460dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 14470dea3f35SAlexandre Mergnat &gxbb_sd_emmc_c_clk0_div.hw 14480dea3f35SAlexandre Mergnat }, 1449914e6e80SJerome Brunet .num_parents = 1, 1450ed3fb5afSJerome Brunet .flags = CLK_SET_RATE_PARENT, 1451914e6e80SJerome Brunet }, 1452914e6e80SJerome Brunet }; 1453914e6e80SJerome Brunet 1454762a1f20SNeil Armstrong /* VPU Clock */ 1455762a1f20SNeil Armstrong 14560dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_vpu_parent_hws[] = { 14570dea3f35SAlexandre Mergnat &gxbb_fclk_div4.hw, 14580dea3f35SAlexandre Mergnat &gxbb_fclk_div3.hw, 14590dea3f35SAlexandre Mergnat &gxbb_fclk_div5.hw, 14600dea3f35SAlexandre Mergnat &gxbb_fclk_div7.hw, 1461762a1f20SNeil Armstrong }; 1462762a1f20SNeil Armstrong 14632513a28cSJerome Brunet static struct clk_regmap gxbb_vpu_0_sel = { 14642513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 14652513a28cSJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1466762a1f20SNeil Armstrong .mask = 0x3, 1467762a1f20SNeil Armstrong .shift = 9, 14682513a28cSJerome Brunet }, 1469762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1470762a1f20SNeil Armstrong .name = "vpu_0_sel", 14712513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1472762a1f20SNeil Armstrong /* 1473762a1f20SNeil Armstrong * bits 9:10 selects from 4 possible parents: 1474762a1f20SNeil Armstrong * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1475762a1f20SNeil Armstrong */ 14760dea3f35SAlexandre Mergnat .parent_hws = gxbb_vpu_parent_hws, 14770dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws), 1478762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1479762a1f20SNeil Armstrong }, 1480762a1f20SNeil Armstrong }; 1481762a1f20SNeil Armstrong 1482f06ddd28SJerome Brunet static struct clk_regmap gxbb_vpu_0_div = { 1483f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1484f06ddd28SJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1485762a1f20SNeil Armstrong .shift = 0, 1486762a1f20SNeil Armstrong .width = 7, 1487f06ddd28SJerome Brunet }, 1488762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1489762a1f20SNeil Armstrong .name = "vpu_0_div", 1490f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 14910dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw }, 1492762a1f20SNeil Armstrong .num_parents = 1, 1493762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1494762a1f20SNeil Armstrong }, 1495762a1f20SNeil Armstrong }; 1496762a1f20SNeil Armstrong 14977f9768a5SJerome Brunet static struct clk_regmap gxbb_vpu_0 = { 14987f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 14997f9768a5SJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1500762a1f20SNeil Armstrong .bit_idx = 8, 15017f9768a5SJerome Brunet }, 1502762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1503762a1f20SNeil Armstrong .name = "vpu_0", 15047f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 15050dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw }, 1506762a1f20SNeil Armstrong .num_parents = 1, 1507762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1508762a1f20SNeil Armstrong }, 1509762a1f20SNeil Armstrong }; 1510762a1f20SNeil Armstrong 15112513a28cSJerome Brunet static struct clk_regmap gxbb_vpu_1_sel = { 15122513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 15132513a28cSJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1514762a1f20SNeil Armstrong .mask = 0x3, 1515762a1f20SNeil Armstrong .shift = 25, 15162513a28cSJerome Brunet }, 1517762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1518762a1f20SNeil Armstrong .name = "vpu_1_sel", 15192513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1520762a1f20SNeil Armstrong /* 1521762a1f20SNeil Armstrong * bits 25:26 selects from 4 possible parents: 1522762a1f20SNeil Armstrong * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1523762a1f20SNeil Armstrong */ 15240dea3f35SAlexandre Mergnat .parent_hws = gxbb_vpu_parent_hws, 15250dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws), 1526762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1527762a1f20SNeil Armstrong }, 1528762a1f20SNeil Armstrong }; 1529762a1f20SNeil Armstrong 1530f06ddd28SJerome Brunet static struct clk_regmap gxbb_vpu_1_div = { 1531f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1532f06ddd28SJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1533762a1f20SNeil Armstrong .shift = 16, 1534762a1f20SNeil Armstrong .width = 7, 1535f06ddd28SJerome Brunet }, 1536762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1537762a1f20SNeil Armstrong .name = "vpu_1_div", 1538f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 15390dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw }, 1540762a1f20SNeil Armstrong .num_parents = 1, 1541762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1542762a1f20SNeil Armstrong }, 1543762a1f20SNeil Armstrong }; 1544762a1f20SNeil Armstrong 15457f9768a5SJerome Brunet static struct clk_regmap gxbb_vpu_1 = { 15467f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 15477f9768a5SJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1548762a1f20SNeil Armstrong .bit_idx = 24, 15497f9768a5SJerome Brunet }, 1550762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1551762a1f20SNeil Armstrong .name = "vpu_1", 15527f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 15530dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw }, 1554762a1f20SNeil Armstrong .num_parents = 1, 1555762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1556762a1f20SNeil Armstrong }, 1557762a1f20SNeil Armstrong }; 1558762a1f20SNeil Armstrong 15592513a28cSJerome Brunet static struct clk_regmap gxbb_vpu = { 15602513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 15612513a28cSJerome Brunet .offset = HHI_VPU_CLK_CNTL, 1562762a1f20SNeil Armstrong .mask = 1, 1563762a1f20SNeil Armstrong .shift = 31, 15642513a28cSJerome Brunet }, 1565762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1566762a1f20SNeil Armstrong .name = "vpu", 15672513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1568762a1f20SNeil Armstrong /* 1569762a1f20SNeil Armstrong * bit 31 selects from 2 possible parents: 1570762a1f20SNeil Armstrong * vpu_0 or vpu_1 1571762a1f20SNeil Armstrong */ 15720dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 15730dea3f35SAlexandre Mergnat &gxbb_vpu_0.hw, 15740dea3f35SAlexandre Mergnat &gxbb_vpu_1.hw 15750dea3f35SAlexandre Mergnat }, 1576762a1f20SNeil Armstrong .num_parents = 2, 1577762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1578762a1f20SNeil Armstrong }, 1579762a1f20SNeil Armstrong }; 1580762a1f20SNeil Armstrong 1581762a1f20SNeil Armstrong /* VAPB Clock */ 1582762a1f20SNeil Armstrong 15830dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_vapb_parent_hws[] = { 15840dea3f35SAlexandre Mergnat &gxbb_fclk_div4.hw, 15850dea3f35SAlexandre Mergnat &gxbb_fclk_div3.hw, 15860dea3f35SAlexandre Mergnat &gxbb_fclk_div5.hw, 15870dea3f35SAlexandre Mergnat &gxbb_fclk_div7.hw, 1588762a1f20SNeil Armstrong }; 1589762a1f20SNeil Armstrong 15902513a28cSJerome Brunet static struct clk_regmap gxbb_vapb_0_sel = { 15912513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 15922513a28cSJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1593762a1f20SNeil Armstrong .mask = 0x3, 1594762a1f20SNeil Armstrong .shift = 9, 15952513a28cSJerome Brunet }, 1596762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1597762a1f20SNeil Armstrong .name = "vapb_0_sel", 15982513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1599762a1f20SNeil Armstrong /* 1600762a1f20SNeil Armstrong * bits 9:10 selects from 4 possible parents: 1601762a1f20SNeil Armstrong * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1602762a1f20SNeil Armstrong */ 16030dea3f35SAlexandre Mergnat .parent_hws = gxbb_vapb_parent_hws, 16040dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws), 1605762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1606762a1f20SNeil Armstrong }, 1607762a1f20SNeil Armstrong }; 1608762a1f20SNeil Armstrong 1609f06ddd28SJerome Brunet static struct clk_regmap gxbb_vapb_0_div = { 1610f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1611f06ddd28SJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1612762a1f20SNeil Armstrong .shift = 0, 1613762a1f20SNeil Armstrong .width = 7, 1614f06ddd28SJerome Brunet }, 1615762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1616762a1f20SNeil Armstrong .name = "vapb_0_div", 1617f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 16180dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 16190dea3f35SAlexandre Mergnat &gxbb_vapb_0_sel.hw 16200dea3f35SAlexandre Mergnat }, 1621762a1f20SNeil Armstrong .num_parents = 1, 1622762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1623762a1f20SNeil Armstrong }, 1624762a1f20SNeil Armstrong }; 1625762a1f20SNeil Armstrong 16267f9768a5SJerome Brunet static struct clk_regmap gxbb_vapb_0 = { 16277f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 16287f9768a5SJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1629762a1f20SNeil Armstrong .bit_idx = 8, 16307f9768a5SJerome Brunet }, 1631762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1632762a1f20SNeil Armstrong .name = "vapb_0", 16337f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 16340dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 16350dea3f35SAlexandre Mergnat &gxbb_vapb_0_div.hw 16360dea3f35SAlexandre Mergnat }, 1637762a1f20SNeil Armstrong .num_parents = 1, 1638762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1639762a1f20SNeil Armstrong }, 1640762a1f20SNeil Armstrong }; 1641762a1f20SNeil Armstrong 16422513a28cSJerome Brunet static struct clk_regmap gxbb_vapb_1_sel = { 16432513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 16442513a28cSJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1645762a1f20SNeil Armstrong .mask = 0x3, 1646762a1f20SNeil Armstrong .shift = 25, 16472513a28cSJerome Brunet }, 1648762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1649762a1f20SNeil Armstrong .name = "vapb_1_sel", 16502513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1651762a1f20SNeil Armstrong /* 1652762a1f20SNeil Armstrong * bits 25:26 selects from 4 possible parents: 1653762a1f20SNeil Armstrong * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1654762a1f20SNeil Armstrong */ 16550dea3f35SAlexandre Mergnat .parent_hws = gxbb_vapb_parent_hws, 16560dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws), 1657762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1658762a1f20SNeil Armstrong }, 1659762a1f20SNeil Armstrong }; 1660762a1f20SNeil Armstrong 1661f06ddd28SJerome Brunet static struct clk_regmap gxbb_vapb_1_div = { 1662f06ddd28SJerome Brunet .data = &(struct clk_regmap_div_data){ 1663f06ddd28SJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1664762a1f20SNeil Armstrong .shift = 16, 1665762a1f20SNeil Armstrong .width = 7, 1666f06ddd28SJerome Brunet }, 1667762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1668762a1f20SNeil Armstrong .name = "vapb_1_div", 1669f06ddd28SJerome Brunet .ops = &clk_regmap_divider_ops, 16700dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 16710dea3f35SAlexandre Mergnat &gxbb_vapb_1_sel.hw 16720dea3f35SAlexandre Mergnat }, 1673762a1f20SNeil Armstrong .num_parents = 1, 1674762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1675762a1f20SNeil Armstrong }, 1676762a1f20SNeil Armstrong }; 1677762a1f20SNeil Armstrong 16787f9768a5SJerome Brunet static struct clk_regmap gxbb_vapb_1 = { 16797f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 16807f9768a5SJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1681762a1f20SNeil Armstrong .bit_idx = 24, 16827f9768a5SJerome Brunet }, 1683762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1684762a1f20SNeil Armstrong .name = "vapb_1", 16857f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 16860dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 16870dea3f35SAlexandre Mergnat &gxbb_vapb_1_div.hw 16880dea3f35SAlexandre Mergnat }, 1689762a1f20SNeil Armstrong .num_parents = 1, 1690762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1691762a1f20SNeil Armstrong }, 1692762a1f20SNeil Armstrong }; 1693762a1f20SNeil Armstrong 16942513a28cSJerome Brunet static struct clk_regmap gxbb_vapb_sel = { 16952513a28cSJerome Brunet .data = &(struct clk_regmap_mux_data){ 16962513a28cSJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1697762a1f20SNeil Armstrong .mask = 1, 1698762a1f20SNeil Armstrong .shift = 31, 16992513a28cSJerome Brunet }, 1700762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1701762a1f20SNeil Armstrong .name = "vapb_sel", 17022513a28cSJerome Brunet .ops = &clk_regmap_mux_ops, 1703762a1f20SNeil Armstrong /* 1704762a1f20SNeil Armstrong * bit 31 selects from 2 possible parents: 1705762a1f20SNeil Armstrong * vapb_0 or vapb_1 1706762a1f20SNeil Armstrong */ 17070dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 17080dea3f35SAlexandre Mergnat &gxbb_vapb_0.hw, 17090dea3f35SAlexandre Mergnat &gxbb_vapb_1.hw 17100dea3f35SAlexandre Mergnat }, 1711762a1f20SNeil Armstrong .num_parents = 2, 1712762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1713762a1f20SNeil Armstrong }, 1714762a1f20SNeil Armstrong }; 1715762a1f20SNeil Armstrong 17167f9768a5SJerome Brunet static struct clk_regmap gxbb_vapb = { 17177f9768a5SJerome Brunet .data = &(struct clk_regmap_gate_data){ 17187f9768a5SJerome Brunet .offset = HHI_VAPBCLK_CNTL, 1719762a1f20SNeil Armstrong .bit_idx = 30, 17207f9768a5SJerome Brunet }, 1721762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1722762a1f20SNeil Armstrong .name = "vapb", 17237f9768a5SJerome Brunet .ops = &clk_regmap_gate_ops, 17240dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw }, 1725762a1f20SNeil Armstrong .num_parents = 1, 1726762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1727762a1f20SNeil Armstrong }, 1728762a1f20SNeil Armstrong }; 1729762a1f20SNeil Armstrong 1730a8080f24SNeil Armstrong /* Video Clocks */ 1731a8080f24SNeil Armstrong 1732a8080f24SNeil Armstrong static struct clk_regmap gxbb_vid_pll_div = { 1733a8080f24SNeil Armstrong .data = &(struct meson_vid_pll_div_data){ 1734a8080f24SNeil Armstrong .val = { 1735a8080f24SNeil Armstrong .reg_off = HHI_VID_PLL_CLK_DIV, 1736a8080f24SNeil Armstrong .shift = 0, 1737a8080f24SNeil Armstrong .width = 15, 1738a8080f24SNeil Armstrong }, 1739a8080f24SNeil Armstrong .sel = { 1740a8080f24SNeil Armstrong .reg_off = HHI_VID_PLL_CLK_DIV, 1741a8080f24SNeil Armstrong .shift = 16, 1742a8080f24SNeil Armstrong .width = 2, 1743a8080f24SNeil Armstrong }, 1744a8080f24SNeil Armstrong }, 1745a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1746a8080f24SNeil Armstrong .name = "vid_pll_div", 1747a8080f24SNeil Armstrong .ops = &meson_vid_pll_div_ro_ops, 17480dea3f35SAlexandre Mergnat .parent_data = &(const struct clk_parent_data) { 17490dea3f35SAlexandre Mergnat /* 17500dea3f35SAlexandre Mergnat * Note: 17510dea3f35SAlexandre Mergnat * GXL and GXBB have different hdmi_plls (with 17520dea3f35SAlexandre Mergnat * different struct clk_hw). We fallback to the global 17530dea3f35SAlexandre Mergnat * naming string mechanism so vid_pll_div picks up the 17540dea3f35SAlexandre Mergnat * appropriate one. 17550dea3f35SAlexandre Mergnat */ 17560dea3f35SAlexandre Mergnat .name = "hdmi_pll", 17570dea3f35SAlexandre Mergnat .index = -1, 17580dea3f35SAlexandre Mergnat }, 1759a8080f24SNeil Armstrong .num_parents = 1, 1760a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 1761a8080f24SNeil Armstrong }, 1762a8080f24SNeil Armstrong }; 1763a8080f24SNeil Armstrong 17640dea3f35SAlexandre Mergnat static const struct clk_parent_data gxbb_vid_pll_parent_data[] = { 17650dea3f35SAlexandre Mergnat { .hw = &gxbb_vid_pll_div.hw }, 17660dea3f35SAlexandre Mergnat /* 17670dea3f35SAlexandre Mergnat * Note: 17680dea3f35SAlexandre Mergnat * GXL and GXBB have different hdmi_plls (with 17690dea3f35SAlexandre Mergnat * different struct clk_hw). We fallback to the global 17700dea3f35SAlexandre Mergnat * naming string mechanism so vid_pll_div picks up the 17710dea3f35SAlexandre Mergnat * appropriate one. 17720dea3f35SAlexandre Mergnat */ 17730dea3f35SAlexandre Mergnat { .name = "hdmi_pll", .index = -1 }, 17740dea3f35SAlexandre Mergnat }; 1775a8080f24SNeil Armstrong 1776a8080f24SNeil Armstrong static struct clk_regmap gxbb_vid_pll_sel = { 1777a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 1778a8080f24SNeil Armstrong .offset = HHI_VID_PLL_CLK_DIV, 1779a8080f24SNeil Armstrong .mask = 0x1, 1780a8080f24SNeil Armstrong .shift = 18, 1781a8080f24SNeil Armstrong }, 1782a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 1783a8080f24SNeil Armstrong .name = "vid_pll_sel", 1784a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 1785a8080f24SNeil Armstrong /* 1786a8080f24SNeil Armstrong * bit 18 selects from 2 possible parents: 1787a8080f24SNeil Armstrong * vid_pll_div or hdmi_pll 1788a8080f24SNeil Armstrong */ 17890dea3f35SAlexandre Mergnat .parent_data = gxbb_vid_pll_parent_data, 17900dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data), 1791a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1792a8080f24SNeil Armstrong }, 1793a8080f24SNeil Armstrong }; 1794a8080f24SNeil Armstrong 1795a8080f24SNeil Armstrong static struct clk_regmap gxbb_vid_pll = { 1796a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1797a8080f24SNeil Armstrong .offset = HHI_VID_PLL_CLK_DIV, 1798a8080f24SNeil Armstrong .bit_idx = 19, 1799a8080f24SNeil Armstrong }, 1800a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1801a8080f24SNeil Armstrong .name = "vid_pll", 1802a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 18030dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 18040dea3f35SAlexandre Mergnat &gxbb_vid_pll_sel.hw 18050dea3f35SAlexandre Mergnat }, 1806a8080f24SNeil Armstrong .num_parents = 1, 1807a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1808a8080f24SNeil Armstrong }, 1809a8080f24SNeil Armstrong }; 1810a8080f24SNeil Armstrong 18110dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_vclk_parent_hws[] = { 18120dea3f35SAlexandre Mergnat &gxbb_vid_pll.hw, 18130dea3f35SAlexandre Mergnat &gxbb_fclk_div4.hw, 18140dea3f35SAlexandre Mergnat &gxbb_fclk_div3.hw, 18150dea3f35SAlexandre Mergnat &gxbb_fclk_div5.hw, 18160dea3f35SAlexandre Mergnat &gxbb_vid_pll.hw, 18170dea3f35SAlexandre Mergnat &gxbb_fclk_div7.hw, 18180dea3f35SAlexandre Mergnat &gxbb_mpll1.hw, 1819a8080f24SNeil Armstrong }; 1820a8080f24SNeil Armstrong 1821a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_sel = { 1822a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 1823a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 1824a8080f24SNeil Armstrong .mask = 0x7, 1825a8080f24SNeil Armstrong .shift = 16, 1826a8080f24SNeil Armstrong }, 1827a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 1828a8080f24SNeil Armstrong .name = "vclk_sel", 1829a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 1830a8080f24SNeil Armstrong /* 1831a8080f24SNeil Armstrong * bits 16:18 selects from 8 possible parents: 1832a8080f24SNeil Armstrong * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1833a8080f24SNeil Armstrong * vid_pll, fclk_div7, mp1 1834a8080f24SNeil Armstrong */ 18350dea3f35SAlexandre Mergnat .parent_hws = gxbb_vclk_parent_hws, 18360dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws), 1837a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1838a8080f24SNeil Armstrong }, 1839a8080f24SNeil Armstrong }; 1840a8080f24SNeil Armstrong 1841a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_sel = { 1842a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 1843a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 1844a8080f24SNeil Armstrong .mask = 0x7, 1845a8080f24SNeil Armstrong .shift = 16, 1846a8080f24SNeil Armstrong }, 1847a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 1848a8080f24SNeil Armstrong .name = "vclk2_sel", 1849a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 1850a8080f24SNeil Armstrong /* 1851a8080f24SNeil Armstrong * bits 16:18 selects from 8 possible parents: 1852a8080f24SNeil Armstrong * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1853a8080f24SNeil Armstrong * vid_pll, fclk_div7, mp1 1854a8080f24SNeil Armstrong */ 18550dea3f35SAlexandre Mergnat .parent_hws = gxbb_vclk_parent_hws, 18560dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws), 1857a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1858a8080f24SNeil Armstrong }, 1859a8080f24SNeil Armstrong }; 1860a8080f24SNeil Armstrong 1861a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_input = { 1862a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1863a8080f24SNeil Armstrong .offset = HHI_VID_CLK_DIV, 1864a8080f24SNeil Armstrong .bit_idx = 16, 1865a8080f24SNeil Armstrong }, 1866a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1867a8080f24SNeil Armstrong .name = "vclk_input", 1868a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 18690dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw }, 1870a8080f24SNeil Armstrong .num_parents = 1, 1871a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1872a8080f24SNeil Armstrong }, 1873a8080f24SNeil Armstrong }; 1874a8080f24SNeil Armstrong 1875a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_input = { 1876a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1877a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_DIV, 1878a8080f24SNeil Armstrong .bit_idx = 16, 1879a8080f24SNeil Armstrong }, 1880a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1881a8080f24SNeil Armstrong .name = "vclk2_input", 1882a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 18830dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw }, 1884a8080f24SNeil Armstrong .num_parents = 1, 1885a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1886a8080f24SNeil Armstrong }, 1887a8080f24SNeil Armstrong }; 1888a8080f24SNeil Armstrong 1889a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div = { 1890a8080f24SNeil Armstrong .data = &(struct clk_regmap_div_data){ 1891a8080f24SNeil Armstrong .offset = HHI_VID_CLK_DIV, 1892a8080f24SNeil Armstrong .shift = 0, 1893a8080f24SNeil Armstrong .width = 8, 1894a8080f24SNeil Armstrong }, 1895a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 1896a8080f24SNeil Armstrong .name = "vclk_div", 1897a8080f24SNeil Armstrong .ops = &clk_regmap_divider_ops, 18980dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 18990dea3f35SAlexandre Mergnat &gxbb_vclk_input.hw 19000dea3f35SAlexandre Mergnat }, 1901a8080f24SNeil Armstrong .num_parents = 1, 1902a8080f24SNeil Armstrong .flags = CLK_GET_RATE_NOCACHE, 1903a8080f24SNeil Armstrong }, 1904a8080f24SNeil Armstrong }; 1905a8080f24SNeil Armstrong 1906a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div = { 1907a8080f24SNeil Armstrong .data = &(struct clk_regmap_div_data){ 1908a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_DIV, 1909a8080f24SNeil Armstrong .shift = 0, 1910a8080f24SNeil Armstrong .width = 8, 1911a8080f24SNeil Armstrong }, 1912a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 1913a8080f24SNeil Armstrong .name = "vclk2_div", 1914a8080f24SNeil Armstrong .ops = &clk_regmap_divider_ops, 19150dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 19160dea3f35SAlexandre Mergnat &gxbb_vclk2_input.hw 19170dea3f35SAlexandre Mergnat }, 1918a8080f24SNeil Armstrong .num_parents = 1, 1919a8080f24SNeil Armstrong .flags = CLK_GET_RATE_NOCACHE, 1920a8080f24SNeil Armstrong }, 1921a8080f24SNeil Armstrong }; 1922a8080f24SNeil Armstrong 1923a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk = { 1924a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1925a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 1926a8080f24SNeil Armstrong .bit_idx = 19, 1927a8080f24SNeil Armstrong }, 1928a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1929a8080f24SNeil Armstrong .name = "vclk", 1930a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 19310dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw }, 1932a8080f24SNeil Armstrong .num_parents = 1, 1933a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1934a8080f24SNeil Armstrong }, 1935a8080f24SNeil Armstrong }; 1936a8080f24SNeil Armstrong 1937a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2 = { 1938a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1939a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 1940a8080f24SNeil Armstrong .bit_idx = 19, 1941a8080f24SNeil Armstrong }, 1942a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1943a8080f24SNeil Armstrong .name = "vclk2", 1944a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 19450dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw }, 1946a8080f24SNeil Armstrong .num_parents = 1, 1947a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1948a8080f24SNeil Armstrong }, 1949a8080f24SNeil Armstrong }; 1950a8080f24SNeil Armstrong 1951a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div1 = { 1952a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1953a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 1954a8080f24SNeil Armstrong .bit_idx = 0, 1955a8080f24SNeil Armstrong }, 1956a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1957a8080f24SNeil Armstrong .name = "vclk_div1", 1958a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 19590dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 1960a8080f24SNeil Armstrong .num_parents = 1, 1961a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1962a8080f24SNeil Armstrong }, 1963a8080f24SNeil Armstrong }; 1964a8080f24SNeil Armstrong 1965a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div2_en = { 1966a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1967a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 1968a8080f24SNeil Armstrong .bit_idx = 1, 1969a8080f24SNeil Armstrong }, 1970a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1971a8080f24SNeil Armstrong .name = "vclk_div2_en", 1972a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 19730dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 1974a8080f24SNeil Armstrong .num_parents = 1, 1975a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1976a8080f24SNeil Armstrong }, 1977a8080f24SNeil Armstrong }; 1978a8080f24SNeil Armstrong 1979a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div4_en = { 1980a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1981a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 1982a8080f24SNeil Armstrong .bit_idx = 2, 1983a8080f24SNeil Armstrong }, 1984a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1985a8080f24SNeil Armstrong .name = "vclk_div4_en", 1986a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 19870dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 1988a8080f24SNeil Armstrong .num_parents = 1, 1989a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1990a8080f24SNeil Armstrong }, 1991a8080f24SNeil Armstrong }; 1992a8080f24SNeil Armstrong 1993a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div6_en = { 1994a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 1995a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 1996a8080f24SNeil Armstrong .bit_idx = 3, 1997a8080f24SNeil Armstrong }, 1998a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 1999a8080f24SNeil Armstrong .name = "vclk_div6_en", 2000a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20010dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2002a8080f24SNeil Armstrong .num_parents = 1, 2003a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2004a8080f24SNeil Armstrong }, 2005a8080f24SNeil Armstrong }; 2006a8080f24SNeil Armstrong 2007a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk_div12_en = { 2008a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2009a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL, 2010a8080f24SNeil Armstrong .bit_idx = 4, 2011a8080f24SNeil Armstrong }, 2012a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2013a8080f24SNeil Armstrong .name = "vclk_div12_en", 2014a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20150dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw }, 2016a8080f24SNeil Armstrong .num_parents = 1, 2017a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2018a8080f24SNeil Armstrong }, 2019a8080f24SNeil Armstrong }; 2020a8080f24SNeil Armstrong 2021a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div1 = { 2022a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2023a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 2024a8080f24SNeil Armstrong .bit_idx = 0, 2025a8080f24SNeil Armstrong }, 2026a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2027a8080f24SNeil Armstrong .name = "vclk2_div1", 2028a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20290dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2030a8080f24SNeil Armstrong .num_parents = 1, 2031a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2032a8080f24SNeil Armstrong }, 2033a8080f24SNeil Armstrong }; 2034a8080f24SNeil Armstrong 2035a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div2_en = { 2036a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2037a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 2038a8080f24SNeil Armstrong .bit_idx = 1, 2039a8080f24SNeil Armstrong }, 2040a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2041a8080f24SNeil Armstrong .name = "vclk2_div2_en", 2042a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20430dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2044a8080f24SNeil Armstrong .num_parents = 1, 2045a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2046a8080f24SNeil Armstrong }, 2047a8080f24SNeil Armstrong }; 2048a8080f24SNeil Armstrong 2049a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div4_en = { 2050a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2051a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 2052a8080f24SNeil Armstrong .bit_idx = 2, 2053a8080f24SNeil Armstrong }, 2054a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2055a8080f24SNeil Armstrong .name = "vclk2_div4_en", 2056a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20570dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2058a8080f24SNeil Armstrong .num_parents = 1, 2059a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2060a8080f24SNeil Armstrong }, 2061a8080f24SNeil Armstrong }; 2062a8080f24SNeil Armstrong 2063a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div6_en = { 2064a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2065a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 2066a8080f24SNeil Armstrong .bit_idx = 3, 2067a8080f24SNeil Armstrong }, 2068a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2069a8080f24SNeil Armstrong .name = "vclk2_div6_en", 2070a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20710dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2072a8080f24SNeil Armstrong .num_parents = 1, 2073a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2074a8080f24SNeil Armstrong }, 2075a8080f24SNeil Armstrong }; 2076a8080f24SNeil Armstrong 2077a8080f24SNeil Armstrong static struct clk_regmap gxbb_vclk2_div12_en = { 2078a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2079a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_CNTL, 2080a8080f24SNeil Armstrong .bit_idx = 4, 2081a8080f24SNeil Armstrong }, 2082a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2083a8080f24SNeil Armstrong .name = "vclk2_div12_en", 2084a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 20850dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw }, 2086a8080f24SNeil Armstrong .num_parents = 1, 2087a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2088a8080f24SNeil Armstrong }, 2089a8080f24SNeil Armstrong }; 2090a8080f24SNeil Armstrong 2091a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk_div2 = { 2092a8080f24SNeil Armstrong .mult = 1, 2093a8080f24SNeil Armstrong .div = 2, 2094a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2095a8080f24SNeil Armstrong .name = "vclk_div2", 2096a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 20970dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 20980dea3f35SAlexandre Mergnat &gxbb_vclk_div2_en.hw 20990dea3f35SAlexandre Mergnat }, 2100a8080f24SNeil Armstrong .num_parents = 1, 2101a8080f24SNeil Armstrong }, 2102a8080f24SNeil Armstrong }; 2103a8080f24SNeil Armstrong 2104a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk_div4 = { 2105a8080f24SNeil Armstrong .mult = 1, 2106a8080f24SNeil Armstrong .div = 4, 2107a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2108a8080f24SNeil Armstrong .name = "vclk_div4", 2109a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 21100dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 21110dea3f35SAlexandre Mergnat &gxbb_vclk_div4_en.hw 21120dea3f35SAlexandre Mergnat }, 2113a8080f24SNeil Armstrong .num_parents = 1, 2114a8080f24SNeil Armstrong }, 2115a8080f24SNeil Armstrong }; 2116a8080f24SNeil Armstrong 2117a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk_div6 = { 2118a8080f24SNeil Armstrong .mult = 1, 2119a8080f24SNeil Armstrong .div = 6, 2120a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2121a8080f24SNeil Armstrong .name = "vclk_div6", 2122a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 21230dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 21240dea3f35SAlexandre Mergnat &gxbb_vclk_div6_en.hw 21250dea3f35SAlexandre Mergnat }, 2126a8080f24SNeil Armstrong .num_parents = 1, 2127a8080f24SNeil Armstrong }, 2128a8080f24SNeil Armstrong }; 2129a8080f24SNeil Armstrong 2130a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk_div12 = { 2131a8080f24SNeil Armstrong .mult = 1, 2132a8080f24SNeil Armstrong .div = 12, 2133a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2134a8080f24SNeil Armstrong .name = "vclk_div12", 2135a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 21360dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 21370dea3f35SAlexandre Mergnat &gxbb_vclk_div12_en.hw 21380dea3f35SAlexandre Mergnat }, 2139a8080f24SNeil Armstrong .num_parents = 1, 2140a8080f24SNeil Armstrong }, 2141a8080f24SNeil Armstrong }; 2142a8080f24SNeil Armstrong 2143a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk2_div2 = { 2144a8080f24SNeil Armstrong .mult = 1, 2145a8080f24SNeil Armstrong .div = 2, 2146a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2147a8080f24SNeil Armstrong .name = "vclk2_div2", 2148a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 21490dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 21500dea3f35SAlexandre Mergnat &gxbb_vclk2_div2_en.hw 21510dea3f35SAlexandre Mergnat }, 2152a8080f24SNeil Armstrong .num_parents = 1, 2153a8080f24SNeil Armstrong }, 2154a8080f24SNeil Armstrong }; 2155a8080f24SNeil Armstrong 2156a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk2_div4 = { 2157a8080f24SNeil Armstrong .mult = 1, 2158a8080f24SNeil Armstrong .div = 4, 2159a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2160a8080f24SNeil Armstrong .name = "vclk2_div4", 2161a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 21620dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 21630dea3f35SAlexandre Mergnat &gxbb_vclk2_div4_en.hw 21640dea3f35SAlexandre Mergnat }, 2165a8080f24SNeil Armstrong .num_parents = 1, 2166a8080f24SNeil Armstrong }, 2167a8080f24SNeil Armstrong }; 2168a8080f24SNeil Armstrong 2169a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk2_div6 = { 2170a8080f24SNeil Armstrong .mult = 1, 2171a8080f24SNeil Armstrong .div = 6, 2172a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2173a8080f24SNeil Armstrong .name = "vclk2_div6", 2174a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 21750dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 21760dea3f35SAlexandre Mergnat &gxbb_vclk2_div6_en.hw 21770dea3f35SAlexandre Mergnat }, 2178a8080f24SNeil Armstrong .num_parents = 1, 2179a8080f24SNeil Armstrong }, 2180a8080f24SNeil Armstrong }; 2181a8080f24SNeil Armstrong 2182a8080f24SNeil Armstrong static struct clk_fixed_factor gxbb_vclk2_div12 = { 2183a8080f24SNeil Armstrong .mult = 1, 2184a8080f24SNeil Armstrong .div = 12, 2185a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2186a8080f24SNeil Armstrong .name = "vclk2_div12", 2187a8080f24SNeil Armstrong .ops = &clk_fixed_factor_ops, 21880dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 21890dea3f35SAlexandre Mergnat &gxbb_vclk2_div12_en.hw 21900dea3f35SAlexandre Mergnat }, 2191a8080f24SNeil Armstrong .num_parents = 1, 2192a8080f24SNeil Armstrong }, 2193a8080f24SNeil Armstrong }; 2194a8080f24SNeil Armstrong 2195a8080f24SNeil Armstrong static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 21960dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_cts_parent_hws[] = { 21970dea3f35SAlexandre Mergnat &gxbb_vclk_div1.hw, 21980dea3f35SAlexandre Mergnat &gxbb_vclk_div2.hw, 21990dea3f35SAlexandre Mergnat &gxbb_vclk_div4.hw, 22000dea3f35SAlexandre Mergnat &gxbb_vclk_div6.hw, 22010dea3f35SAlexandre Mergnat &gxbb_vclk_div12.hw, 22020dea3f35SAlexandre Mergnat &gxbb_vclk2_div1.hw, 22030dea3f35SAlexandre Mergnat &gxbb_vclk2_div2.hw, 22040dea3f35SAlexandre Mergnat &gxbb_vclk2_div4.hw, 22050dea3f35SAlexandre Mergnat &gxbb_vclk2_div6.hw, 22060dea3f35SAlexandre Mergnat &gxbb_vclk2_div12.hw, 2207a8080f24SNeil Armstrong }; 2208a8080f24SNeil Armstrong 2209a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_enci_sel = { 2210a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 2211a8080f24SNeil Armstrong .offset = HHI_VID_CLK_DIV, 2212a8080f24SNeil Armstrong .mask = 0xf, 2213a8080f24SNeil Armstrong .shift = 28, 2214a8080f24SNeil Armstrong .table = mux_table_cts_sel, 2215a8080f24SNeil Armstrong }, 2216a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2217a8080f24SNeil Armstrong .name = "cts_enci_sel", 2218a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 22190dea3f35SAlexandre Mergnat .parent_hws = gxbb_cts_parent_hws, 22200dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws), 2221a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2222a8080f24SNeil Armstrong }, 2223a8080f24SNeil Armstrong }; 2224a8080f24SNeil Armstrong 2225a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_encp_sel = { 2226a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 2227a8080f24SNeil Armstrong .offset = HHI_VID_CLK_DIV, 2228a8080f24SNeil Armstrong .mask = 0xf, 2229a8080f24SNeil Armstrong .shift = 20, 2230a8080f24SNeil Armstrong .table = mux_table_cts_sel, 2231a8080f24SNeil Armstrong }, 2232a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2233a8080f24SNeil Armstrong .name = "cts_encp_sel", 2234a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 22350dea3f35SAlexandre Mergnat .parent_hws = gxbb_cts_parent_hws, 22360dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws), 2237a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2238a8080f24SNeil Armstrong }, 2239a8080f24SNeil Armstrong }; 2240a8080f24SNeil Armstrong 2241a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_vdac_sel = { 2242a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 2243a8080f24SNeil Armstrong .offset = HHI_VIID_CLK_DIV, 2244a8080f24SNeil Armstrong .mask = 0xf, 2245a8080f24SNeil Armstrong .shift = 28, 2246a8080f24SNeil Armstrong .table = mux_table_cts_sel, 2247a8080f24SNeil Armstrong }, 2248a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2249a8080f24SNeil Armstrong .name = "cts_vdac_sel", 2250a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 22510dea3f35SAlexandre Mergnat .parent_hws = gxbb_cts_parent_hws, 22520dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws), 2253a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2254a8080f24SNeil Armstrong }, 2255a8080f24SNeil Armstrong }; 2256a8080f24SNeil Armstrong 2257a8080f24SNeil Armstrong /* TOFIX: add support for cts_tcon */ 2258a8080f24SNeil Armstrong static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 22590dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = { 22600dea3f35SAlexandre Mergnat &gxbb_vclk_div1.hw, 22610dea3f35SAlexandre Mergnat &gxbb_vclk_div2.hw, 22620dea3f35SAlexandre Mergnat &gxbb_vclk_div4.hw, 22630dea3f35SAlexandre Mergnat &gxbb_vclk_div6.hw, 22640dea3f35SAlexandre Mergnat &gxbb_vclk_div12.hw, 22650dea3f35SAlexandre Mergnat &gxbb_vclk2_div1.hw, 22660dea3f35SAlexandre Mergnat &gxbb_vclk2_div2.hw, 22670dea3f35SAlexandre Mergnat &gxbb_vclk2_div4.hw, 22680dea3f35SAlexandre Mergnat &gxbb_vclk2_div6.hw, 22690dea3f35SAlexandre Mergnat &gxbb_vclk2_div12.hw, 2270a8080f24SNeil Armstrong }; 2271a8080f24SNeil Armstrong 2272a8080f24SNeil Armstrong static struct clk_regmap gxbb_hdmi_tx_sel = { 2273a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 2274a8080f24SNeil Armstrong .offset = HHI_HDMI_CLK_CNTL, 2275a8080f24SNeil Armstrong .mask = 0xf, 2276a8080f24SNeil Armstrong .shift = 16, 2277a8080f24SNeil Armstrong .table = mux_table_hdmi_tx_sel, 2278a8080f24SNeil Armstrong }, 2279a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2280a8080f24SNeil Armstrong .name = "hdmi_tx_sel", 2281a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 2282a8080f24SNeil Armstrong /* 2283a8080f24SNeil Armstrong * bits 31:28 selects from 12 possible parents: 2284a8080f24SNeil Armstrong * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12 2285a8080f24SNeil Armstrong * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12, 2286a8080f24SNeil Armstrong * cts_tcon 2287a8080f24SNeil Armstrong */ 22880dea3f35SAlexandre Mergnat .parent_hws = gxbb_cts_hdmi_tx_parent_hws, 22890dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws), 2290a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2291a8080f24SNeil Armstrong }, 2292a8080f24SNeil Armstrong }; 2293a8080f24SNeil Armstrong 2294a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_enci = { 2295a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2296a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL2, 2297a8080f24SNeil Armstrong .bit_idx = 0, 2298a8080f24SNeil Armstrong }, 2299a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2300a8080f24SNeil Armstrong .name = "cts_enci", 2301a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 23020dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 23030dea3f35SAlexandre Mergnat &gxbb_cts_enci_sel.hw 23040dea3f35SAlexandre Mergnat }, 2305a8080f24SNeil Armstrong .num_parents = 1, 2306a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2307a8080f24SNeil Armstrong }, 2308a8080f24SNeil Armstrong }; 2309a8080f24SNeil Armstrong 2310a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_encp = { 2311a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2312a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL2, 2313a8080f24SNeil Armstrong .bit_idx = 2, 2314a8080f24SNeil Armstrong }, 2315a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2316a8080f24SNeil Armstrong .name = "cts_encp", 2317a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 23180dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 23190dea3f35SAlexandre Mergnat &gxbb_cts_encp_sel.hw 23200dea3f35SAlexandre Mergnat }, 2321a8080f24SNeil Armstrong .num_parents = 1, 2322a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2323a8080f24SNeil Armstrong }, 2324a8080f24SNeil Armstrong }; 2325a8080f24SNeil Armstrong 2326a8080f24SNeil Armstrong static struct clk_regmap gxbb_cts_vdac = { 2327a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2328a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL2, 2329a8080f24SNeil Armstrong .bit_idx = 4, 2330a8080f24SNeil Armstrong }, 2331a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2332a8080f24SNeil Armstrong .name = "cts_vdac", 2333a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 23340dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 23350dea3f35SAlexandre Mergnat &gxbb_cts_vdac_sel.hw 23360dea3f35SAlexandre Mergnat }, 2337a8080f24SNeil Armstrong .num_parents = 1, 2338a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2339a8080f24SNeil Armstrong }, 2340a8080f24SNeil Armstrong }; 2341a8080f24SNeil Armstrong 2342a8080f24SNeil Armstrong static struct clk_regmap gxbb_hdmi_tx = { 2343a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2344a8080f24SNeil Armstrong .offset = HHI_VID_CLK_CNTL2, 2345a8080f24SNeil Armstrong .bit_idx = 5, 2346a8080f24SNeil Armstrong }, 2347a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2348a8080f24SNeil Armstrong .name = "hdmi_tx", 2349a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 23500dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 23510dea3f35SAlexandre Mergnat &gxbb_hdmi_tx_sel.hw 23520dea3f35SAlexandre Mergnat }, 2353a8080f24SNeil Armstrong .num_parents = 1, 2354a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2355a8080f24SNeil Armstrong }, 2356a8080f24SNeil Armstrong }; 2357a8080f24SNeil Armstrong 2358a8080f24SNeil Armstrong /* HDMI Clocks */ 2359a8080f24SNeil Armstrong 23600dea3f35SAlexandre Mergnat static const struct clk_parent_data gxbb_hdmi_parent_data[] = { 23610dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 23620dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div4.hw }, 23630dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 23640dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 2365a8080f24SNeil Armstrong }; 2366a8080f24SNeil Armstrong 2367a8080f24SNeil Armstrong static struct clk_regmap gxbb_hdmi_sel = { 2368a8080f24SNeil Armstrong .data = &(struct clk_regmap_mux_data){ 2369a8080f24SNeil Armstrong .offset = HHI_HDMI_CLK_CNTL, 2370a8080f24SNeil Armstrong .mask = 0x3, 2371a8080f24SNeil Armstrong .shift = 9, 2372a8080f24SNeil Armstrong .flags = CLK_MUX_ROUND_CLOSEST, 2373a8080f24SNeil Armstrong }, 2374a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2375a8080f24SNeil Armstrong .name = "hdmi_sel", 2376a8080f24SNeil Armstrong .ops = &clk_regmap_mux_ops, 23770dea3f35SAlexandre Mergnat .parent_data = gxbb_hdmi_parent_data, 23780dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data), 2379a8080f24SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2380a8080f24SNeil Armstrong }, 2381a8080f24SNeil Armstrong }; 2382a8080f24SNeil Armstrong 2383a8080f24SNeil Armstrong static struct clk_regmap gxbb_hdmi_div = { 2384a8080f24SNeil Armstrong .data = &(struct clk_regmap_div_data){ 2385a8080f24SNeil Armstrong .offset = HHI_HDMI_CLK_CNTL, 2386a8080f24SNeil Armstrong .shift = 0, 2387a8080f24SNeil Armstrong .width = 7, 2388a8080f24SNeil Armstrong }, 2389a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data){ 2390a8080f24SNeil Armstrong .name = "hdmi_div", 2391a8080f24SNeil Armstrong .ops = &clk_regmap_divider_ops, 23920dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw }, 2393a8080f24SNeil Armstrong .num_parents = 1, 2394a8080f24SNeil Armstrong .flags = CLK_GET_RATE_NOCACHE, 2395a8080f24SNeil Armstrong }, 2396a8080f24SNeil Armstrong }; 2397a8080f24SNeil Armstrong 2398a8080f24SNeil Armstrong static struct clk_regmap gxbb_hdmi = { 2399a8080f24SNeil Armstrong .data = &(struct clk_regmap_gate_data){ 2400a8080f24SNeil Armstrong .offset = HHI_HDMI_CLK_CNTL, 2401a8080f24SNeil Armstrong .bit_idx = 8, 2402a8080f24SNeil Armstrong }, 2403a8080f24SNeil Armstrong .hw.init = &(struct clk_init_data) { 2404a8080f24SNeil Armstrong .name = "hdmi", 2405a8080f24SNeil Armstrong .ops = &clk_regmap_gate_ops, 24060dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw }, 2407a8080f24SNeil Armstrong .num_parents = 1, 2408a8080f24SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2409a8080f24SNeil Armstrong }, 2410a8080f24SNeil Armstrong }; 2411a8080f24SNeil Armstrong 2412a565242eSMaxime Jourdan /* VDEC clocks */ 2413a565242eSMaxime Jourdan 24140dea3f35SAlexandre Mergnat static const struct clk_hw *gxbb_vdec_parent_hws[] = { 24150dea3f35SAlexandre Mergnat &gxbb_fclk_div4.hw, 24160dea3f35SAlexandre Mergnat &gxbb_fclk_div3.hw, 24170dea3f35SAlexandre Mergnat &gxbb_fclk_div5.hw, 24180dea3f35SAlexandre Mergnat &gxbb_fclk_div7.hw, 2419a565242eSMaxime Jourdan }; 2420a565242eSMaxime Jourdan 2421a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_1_sel = { 2422a565242eSMaxime Jourdan .data = &(struct clk_regmap_mux_data){ 2423a565242eSMaxime Jourdan .offset = HHI_VDEC_CLK_CNTL, 2424a565242eSMaxime Jourdan .mask = 0x3, 2425a565242eSMaxime Jourdan .shift = 9, 2426a565242eSMaxime Jourdan .flags = CLK_MUX_ROUND_CLOSEST, 2427a565242eSMaxime Jourdan }, 2428a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data){ 2429a565242eSMaxime Jourdan .name = "vdec_1_sel", 2430a565242eSMaxime Jourdan .ops = &clk_regmap_mux_ops, 24310dea3f35SAlexandre Mergnat .parent_hws = gxbb_vdec_parent_hws, 24320dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws), 2433a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2434a565242eSMaxime Jourdan }, 2435a565242eSMaxime Jourdan }; 2436a565242eSMaxime Jourdan 2437a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_1_div = { 2438a565242eSMaxime Jourdan .data = &(struct clk_regmap_div_data){ 2439a565242eSMaxime Jourdan .offset = HHI_VDEC_CLK_CNTL, 2440a565242eSMaxime Jourdan .shift = 0, 2441a565242eSMaxime Jourdan .width = 7, 24429b70c697SMaxime Jourdan .flags = CLK_DIVIDER_ROUND_CLOSEST, 2443a565242eSMaxime Jourdan }, 2444a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data){ 2445a565242eSMaxime Jourdan .name = "vdec_1_div", 2446a565242eSMaxime Jourdan .ops = &clk_regmap_divider_ops, 24470dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 24480dea3f35SAlexandre Mergnat &gxbb_vdec_1_sel.hw 24490dea3f35SAlexandre Mergnat }, 2450a565242eSMaxime Jourdan .num_parents = 1, 2451a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2452a565242eSMaxime Jourdan }, 2453a565242eSMaxime Jourdan }; 2454a565242eSMaxime Jourdan 2455a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_1 = { 2456a565242eSMaxime Jourdan .data = &(struct clk_regmap_gate_data){ 2457a565242eSMaxime Jourdan .offset = HHI_VDEC_CLK_CNTL, 2458a565242eSMaxime Jourdan .bit_idx = 8, 2459a565242eSMaxime Jourdan }, 2460a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data) { 2461a565242eSMaxime Jourdan .name = "vdec_1", 2462a565242eSMaxime Jourdan .ops = &clk_regmap_gate_ops, 24630dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 24640dea3f35SAlexandre Mergnat &gxbb_vdec_1_div.hw 24650dea3f35SAlexandre Mergnat }, 2466a565242eSMaxime Jourdan .num_parents = 1, 2467a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2468a565242eSMaxime Jourdan }, 2469a565242eSMaxime Jourdan }; 2470a565242eSMaxime Jourdan 2471a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_hevc_sel = { 2472a565242eSMaxime Jourdan .data = &(struct clk_regmap_mux_data){ 2473a565242eSMaxime Jourdan .offset = HHI_VDEC2_CLK_CNTL, 2474a565242eSMaxime Jourdan .mask = 0x3, 2475a565242eSMaxime Jourdan .shift = 25, 2476a565242eSMaxime Jourdan .flags = CLK_MUX_ROUND_CLOSEST, 2477a565242eSMaxime Jourdan }, 2478a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data){ 2479a565242eSMaxime Jourdan .name = "vdec_hevc_sel", 2480a565242eSMaxime Jourdan .ops = &clk_regmap_mux_ops, 24810dea3f35SAlexandre Mergnat .parent_hws = gxbb_vdec_parent_hws, 24820dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws), 2483a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2484a565242eSMaxime Jourdan }, 2485a565242eSMaxime Jourdan }; 2486a565242eSMaxime Jourdan 2487a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_hevc_div = { 2488a565242eSMaxime Jourdan .data = &(struct clk_regmap_div_data){ 2489a565242eSMaxime Jourdan .offset = HHI_VDEC2_CLK_CNTL, 2490a565242eSMaxime Jourdan .shift = 16, 2491a565242eSMaxime Jourdan .width = 7, 24929b70c697SMaxime Jourdan .flags = CLK_DIVIDER_ROUND_CLOSEST, 2493a565242eSMaxime Jourdan }, 2494a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data){ 2495a565242eSMaxime Jourdan .name = "vdec_hevc_div", 2496a565242eSMaxime Jourdan .ops = &clk_regmap_divider_ops, 24970dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 24980dea3f35SAlexandre Mergnat &gxbb_vdec_hevc_sel.hw 24990dea3f35SAlexandre Mergnat }, 2500a565242eSMaxime Jourdan .num_parents = 1, 2501a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2502a565242eSMaxime Jourdan }, 2503a565242eSMaxime Jourdan }; 2504a565242eSMaxime Jourdan 2505a565242eSMaxime Jourdan static struct clk_regmap gxbb_vdec_hevc = { 2506a565242eSMaxime Jourdan .data = &(struct clk_regmap_gate_data){ 2507a565242eSMaxime Jourdan .offset = HHI_VDEC2_CLK_CNTL, 2508a565242eSMaxime Jourdan .bit_idx = 24, 2509a565242eSMaxime Jourdan }, 2510a565242eSMaxime Jourdan .hw.init = &(struct clk_init_data) { 2511a565242eSMaxime Jourdan .name = "vdec_hevc", 2512a565242eSMaxime Jourdan .ops = &clk_regmap_gate_ops, 25130dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 25140dea3f35SAlexandre Mergnat &gxbb_vdec_hevc_div.hw 25150dea3f35SAlexandre Mergnat }, 2516a565242eSMaxime Jourdan .num_parents = 1, 2517a565242eSMaxime Jourdan .flags = CLK_SET_RATE_PARENT, 2518a565242eSMaxime Jourdan }, 2519a565242eSMaxime Jourdan }; 2520a565242eSMaxime Jourdan 25217df533a7SJerome Brunet static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, 25227df533a7SJerome Brunet 9, 10, 11, 13, 14, }; 25230dea3f35SAlexandre Mergnat static const struct clk_parent_data gen_clk_parent_data[] = { 25240dea3f35SAlexandre Mergnat { .fw_name = "xtal", }, 25250dea3f35SAlexandre Mergnat { .hw = &gxbb_vdec_1.hw }, 25260dea3f35SAlexandre Mergnat { .hw = &gxbb_vdec_hevc.hw }, 25270dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll0.hw }, 25280dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll1.hw }, 25290dea3f35SAlexandre Mergnat { .hw = &gxbb_mpll2.hw }, 25300dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div4.hw }, 25310dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div3.hw }, 25320dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div5.hw }, 25330dea3f35SAlexandre Mergnat { .hw = &gxbb_fclk_div7.hw }, 25340dea3f35SAlexandre Mergnat { .hw = &gxbb_gp0_pll.hw }, 25357df533a7SJerome Brunet }; 25367df533a7SJerome Brunet 25377df533a7SJerome Brunet static struct clk_regmap gxbb_gen_clk_sel = { 25387df533a7SJerome Brunet .data = &(struct clk_regmap_mux_data){ 25397df533a7SJerome Brunet .offset = HHI_GEN_CLK_CNTL, 25407df533a7SJerome Brunet .mask = 0xf, 25417df533a7SJerome Brunet .shift = 12, 25427df533a7SJerome Brunet .table = mux_table_gen_clk, 25437df533a7SJerome Brunet }, 25447df533a7SJerome Brunet .hw.init = &(struct clk_init_data){ 25457df533a7SJerome Brunet .name = "gen_clk_sel", 25467df533a7SJerome Brunet .ops = &clk_regmap_mux_ops, 25477df533a7SJerome Brunet /* 25487df533a7SJerome Brunet * bits 15:12 selects from 14 possible parents: 25497df533a7SJerome Brunet * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt], 25507df533a7SJerome Brunet * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4, 25517df533a7SJerome Brunet * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 25527df533a7SJerome Brunet */ 25530dea3f35SAlexandre Mergnat .parent_data = gen_clk_parent_data, 25540dea3f35SAlexandre Mergnat .num_parents = ARRAY_SIZE(gen_clk_parent_data), 25557df533a7SJerome Brunet }, 25567df533a7SJerome Brunet }; 25577df533a7SJerome Brunet 25587df533a7SJerome Brunet static struct clk_regmap gxbb_gen_clk_div = { 25597df533a7SJerome Brunet .data = &(struct clk_regmap_div_data){ 25607df533a7SJerome Brunet .offset = HHI_GEN_CLK_CNTL, 25617df533a7SJerome Brunet .shift = 0, 25627df533a7SJerome Brunet .width = 11, 25637df533a7SJerome Brunet }, 25647df533a7SJerome Brunet .hw.init = &(struct clk_init_data){ 25657df533a7SJerome Brunet .name = "gen_clk_div", 25667df533a7SJerome Brunet .ops = &clk_regmap_divider_ops, 25670dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 25680dea3f35SAlexandre Mergnat &gxbb_gen_clk_sel.hw 25690dea3f35SAlexandre Mergnat }, 25707df533a7SJerome Brunet .num_parents = 1, 25717df533a7SJerome Brunet .flags = CLK_SET_RATE_PARENT, 25727df533a7SJerome Brunet }, 25737df533a7SJerome Brunet }; 25747df533a7SJerome Brunet 25757df533a7SJerome Brunet static struct clk_regmap gxbb_gen_clk = { 25767df533a7SJerome Brunet .data = &(struct clk_regmap_gate_data){ 25777df533a7SJerome Brunet .offset = HHI_GEN_CLK_CNTL, 25787df533a7SJerome Brunet .bit_idx = 7, 25797df533a7SJerome Brunet }, 25807df533a7SJerome Brunet .hw.init = &(struct clk_init_data){ 25817df533a7SJerome Brunet .name = "gen_clk", 25827df533a7SJerome Brunet .ops = &clk_regmap_gate_ops, 25830dea3f35SAlexandre Mergnat .parent_hws = (const struct clk_hw *[]) { 25840dea3f35SAlexandre Mergnat &gxbb_gen_clk_div.hw 25850dea3f35SAlexandre Mergnat }, 25867df533a7SJerome Brunet .num_parents = 1, 25877df533a7SJerome Brunet .flags = CLK_SET_RATE_PARENT, 25887df533a7SJerome Brunet }, 25897df533a7SJerome Brunet }; 25907df533a7SJerome Brunet 25913a36044eSAlexandre Mergnat #define MESON_GATE(_name, _reg, _bit) \ 25923a36044eSAlexandre Mergnat MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw) 25933a36044eSAlexandre Mergnat 2594738f66d3SMichael Turquette /* Everything Else (EE) domain gates */ 25957ba64d82SAlexander Müller static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 25967ba64d82SAlexander Müller static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); 25977ba64d82SAlexander Müller static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5); 25987ba64d82SAlexander Müller static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6); 25997ba64d82SAlexander Müller static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7); 26007ba64d82SAlexander Müller static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8); 26017ba64d82SAlexander Müller static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9); 260275eccf5eSYixun Lan static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10); 26037ba64d82SAlexander Müller static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11); 26047ba64d82SAlexander Müller static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12); 26057ba64d82SAlexander Müller static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13); 26067ba64d82SAlexander Müller static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14); 26077ba64d82SAlexander Müller static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15); 26087ba64d82SAlexander Müller static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16); 26097ba64d82SAlexander Müller static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17); 26107ba64d82SAlexander Müller static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18); 26117ba64d82SAlexander Müller static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19); 26127ba64d82SAlexander Müller static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); 26137ba64d82SAlexander Müller static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24); 26147ba64d82SAlexander Müller static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25); 26157ba64d82SAlexander Müller static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26); 261673c7ddd8SJerome Brunet static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28); 26177ba64d82SAlexander Müller static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30); 2618738f66d3SMichael Turquette 26197ba64d82SAlexander Müller static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2); 26207ba64d82SAlexander Müller static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3); 26217ba64d82SAlexander Müller static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4); 26227ba64d82SAlexander Müller static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14); 26237ba64d82SAlexander Müller static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15); 26247ba64d82SAlexander Müller static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16); 26257ba64d82SAlexander Müller static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20); 26267ba64d82SAlexander Müller static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21); 26277ba64d82SAlexander Müller static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22); 26287ba64d82SAlexander Müller static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23); 26297ba64d82SAlexander Müller static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24); 26307ba64d82SAlexander Müller static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25); 26317ba64d82SAlexander Müller static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26); 26327ba64d82SAlexander Müller static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28); 26337ba64d82SAlexander Müller static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29); 26347ba64d82SAlexander Müller static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30); 26357ba64d82SAlexander Müller static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31); 2636738f66d3SMichael Turquette 26377ba64d82SAlexander Müller static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1); 26387ba64d82SAlexander Müller static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 26397ba64d82SAlexander Müller static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); 26407ba64d82SAlexander Müller static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4); 26417ba64d82SAlexander Müller static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); 26427ba64d82SAlexander Müller static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); 26437ba64d82SAlexander Müller static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); 26447ba64d82SAlexander Müller static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12); 26457ba64d82SAlexander Müller static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15); 264675eccf5eSYixun Lan static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22); 26477ba64d82SAlexander Müller static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); 26487ba64d82SAlexander Müller static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 26497ba64d82SAlexander Müller static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); 2650738f66d3SMichael Turquette 26517ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1); 26527ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2); 26537ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3); 26547ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4); 26557ba64d82SAlexander Müller static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8); 26567ba64d82SAlexander Müller static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9); 26577ba64d82SAlexander Müller static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10); 26587ba64d82SAlexander Müller static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14); 26597ba64d82SAlexander Müller static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16); 26607ba64d82SAlexander Müller static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20); 26617ba64d82SAlexander Müller static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21); 26627ba64d82SAlexander Müller static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22); 26637ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24); 26647ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25); 26657ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26); 26667ba64d82SAlexander Müller static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31); 2667738f66d3SMichael Turquette 2668738f66d3SMichael Turquette /* Always On (AO) domain gates */ 2669738f66d3SMichael Turquette 26707ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0); 26717ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1); 26727ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2); 26737ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3); 26747ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4); 2675738f66d3SMichael Turquette 267683b89a75SJerome Brunet /* AIU gates */ 267783b89a75SJerome Brunet static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw); 267883b89a75SJerome Brunet static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw); 267983b89a75SJerome Brunet static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw); 268083b89a75SJerome Brunet static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw); 268183b89a75SJerome Brunet static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw); 268283b89a75SJerome Brunet static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw); 268383b89a75SJerome Brunet static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw); 268483b89a75SJerome Brunet static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw); 268583b89a75SJerome Brunet 2686738f66d3SMichael Turquette /* Array of all clocks provided by this provider */ 2687738f66d3SMichael Turquette 2688738f66d3SMichael Turquette static struct clk_hw_onecell_data gxbb_hw_onecell_data = { 2689738f66d3SMichael Turquette .hws = { 2690738f66d3SMichael Turquette [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 2691738f66d3SMichael Turquette [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 2692738f66d3SMichael Turquette [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 2693738f66d3SMichael Turquette [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 2694738f66d3SMichael Turquette [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 2695738f66d3SMichael Turquette [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 2696738f66d3SMichael Turquette [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 2697738f66d3SMichael Turquette [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 2698738f66d3SMichael Turquette [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 2699738f66d3SMichael Turquette [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 2700738f66d3SMichael Turquette [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 2701738f66d3SMichael Turquette [CLKID_CLK81] = &gxbb_clk81.hw, 2702738f66d3SMichael Turquette [CLKID_MPLL0] = &gxbb_mpll0.hw, 2703738f66d3SMichael Turquette [CLKID_MPLL1] = &gxbb_mpll1.hw, 2704738f66d3SMichael Turquette [CLKID_MPLL2] = &gxbb_mpll2.hw, 2705738f66d3SMichael Turquette [CLKID_DDR] = &gxbb_ddr.hw, 2706738f66d3SMichael Turquette [CLKID_DOS] = &gxbb_dos.hw, 2707738f66d3SMichael Turquette [CLKID_ISA] = &gxbb_isa.hw, 2708738f66d3SMichael Turquette [CLKID_PL301] = &gxbb_pl301.hw, 2709738f66d3SMichael Turquette [CLKID_PERIPHS] = &gxbb_periphs.hw, 2710738f66d3SMichael Turquette [CLKID_SPICC] = &gxbb_spicc.hw, 2711738f66d3SMichael Turquette [CLKID_I2C] = &gxbb_i2c.hw, 2712738f66d3SMichael Turquette [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 2713738f66d3SMichael Turquette [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 2714738f66d3SMichael Turquette [CLKID_RNG0] = &gxbb_rng0.hw, 2715738f66d3SMichael Turquette [CLKID_UART0] = &gxbb_uart0.hw, 2716738f66d3SMichael Turquette [CLKID_SDHC] = &gxbb_sdhc.hw, 2717738f66d3SMichael Turquette [CLKID_STREAM] = &gxbb_stream.hw, 2718738f66d3SMichael Turquette [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 2719738f66d3SMichael Turquette [CLKID_SDIO] = &gxbb_sdio.hw, 2720738f66d3SMichael Turquette [CLKID_ABUF] = &gxbb_abuf.hw, 2721738f66d3SMichael Turquette [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 2722738f66d3SMichael Turquette [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 2723738f66d3SMichael Turquette [CLKID_SPI] = &gxbb_spi.hw, 2724738f66d3SMichael Turquette [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 2725738f66d3SMichael Turquette [CLKID_ETH] = &gxbb_eth.hw, 2726738f66d3SMichael Turquette [CLKID_DEMUX] = &gxbb_demux.hw, 2727738f66d3SMichael Turquette [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 2728738f66d3SMichael Turquette [CLKID_IEC958] = &gxbb_iec958.hw, 2729738f66d3SMichael Turquette [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 2730738f66d3SMichael Turquette [CLKID_AMCLK] = &gxbb_amclk.hw, 2731738f66d3SMichael Turquette [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 2732738f66d3SMichael Turquette [CLKID_MIXER] = &gxbb_mixer.hw, 2733738f66d3SMichael Turquette [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 2734738f66d3SMichael Turquette [CLKID_ADC] = &gxbb_adc.hw, 2735738f66d3SMichael Turquette [CLKID_BLKMV] = &gxbb_blkmv.hw, 2736738f66d3SMichael Turquette [CLKID_AIU] = &gxbb_aiu.hw, 2737738f66d3SMichael Turquette [CLKID_UART1] = &gxbb_uart1.hw, 2738738f66d3SMichael Turquette [CLKID_G2D] = &gxbb_g2d.hw, 2739738f66d3SMichael Turquette [CLKID_USB0] = &gxbb_usb0.hw, 2740738f66d3SMichael Turquette [CLKID_USB1] = &gxbb_usb1.hw, 2741738f66d3SMichael Turquette [CLKID_RESET] = &gxbb_reset.hw, 2742738f66d3SMichael Turquette [CLKID_NAND] = &gxbb_nand.hw, 2743738f66d3SMichael Turquette [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 2744738f66d3SMichael Turquette [CLKID_USB] = &gxbb_usb.hw, 2745738f66d3SMichael Turquette [CLKID_VDIN1] = &gxbb_vdin1.hw, 2746738f66d3SMichael Turquette [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 2747738f66d3SMichael Turquette [CLKID_EFUSE] = &gxbb_efuse.hw, 2748738f66d3SMichael Turquette [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 2749738f66d3SMichael Turquette [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 2750738f66d3SMichael Turquette [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 2751738f66d3SMichael Turquette [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 2752738f66d3SMichael Turquette [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 2753738f66d3SMichael Turquette [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 2754738f66d3SMichael Turquette [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 2755738f66d3SMichael Turquette [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 2756738f66d3SMichael Turquette [CLKID_DVIN] = &gxbb_dvin.hw, 2757738f66d3SMichael Turquette [CLKID_UART2] = &gxbb_uart2.hw, 2758738f66d3SMichael Turquette [CLKID_SANA] = &gxbb_sana.hw, 2759738f66d3SMichael Turquette [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 2760738f66d3SMichael Turquette [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 2761738f66d3SMichael Turquette [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 2762738f66d3SMichael Turquette [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 2763738f66d3SMichael Turquette [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 2764738f66d3SMichael Turquette [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 2765738f66d3SMichael Turquette [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 2766738f66d3SMichael Turquette [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 2767738f66d3SMichael Turquette [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 2768738f66d3SMichael Turquette [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 2769738f66d3SMichael Turquette [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 2770738f66d3SMichael Turquette [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 2771738f66d3SMichael Turquette [CLKID_ENC480P] = &gxbb_enc480p.hw, 2772738f66d3SMichael Turquette [CLKID_RNG1] = &gxbb_rng1.hw, 2773738f66d3SMichael Turquette [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 2774738f66d3SMichael Turquette [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 2775738f66d3SMichael Turquette [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 2776738f66d3SMichael Turquette [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 2777738f66d3SMichael Turquette [CLKID_EDP] = &gxbb_edp.hw, 2778738f66d3SMichael Turquette [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 2779738f66d3SMichael Turquette [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 2780738f66d3SMichael Turquette [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 2781738f66d3SMichael Turquette [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 2782738f66d3SMichael Turquette [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 278333608dcdSKevin Hilman [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 278433608dcdSKevin Hilman [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 278533608dcdSKevin Hilman [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 278633d0fcdfSMartin Blumenstingl [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 278733d0fcdfSMartin Blumenstingl [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 278833d0fcdfSMartin Blumenstingl [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 2789fac9a55bSNeil Armstrong [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 2790fac9a55bSNeil Armstrong [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 2791fac9a55bSNeil Armstrong [CLKID_MALI_0] = &gxbb_mali_0.hw, 2792fac9a55bSNeil Armstrong [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 2793fac9a55bSNeil Armstrong [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 2794fac9a55bSNeil Armstrong [CLKID_MALI_1] = &gxbb_mali_1.hw, 2795fac9a55bSNeil Armstrong [CLKID_MALI] = &gxbb_mali.hw, 27964087bd4bSJerome Brunet [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 27974087bd4bSJerome Brunet [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 27984087bd4bSJerome Brunet [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 27993c277c24SJerome Brunet [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 28003c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 28013c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 28027eaa44f6SJerome Brunet [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 280314c735c8SNeil Armstrong [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 280414c735c8SNeil Armstrong [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 280514c735c8SNeil Armstrong [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 2806914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 2807914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 2808914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 2809914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 2810914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 2811914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 2812914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 2813914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 2814914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 2815762a1f20SNeil Armstrong [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 2816762a1f20SNeil Armstrong [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 2817762a1f20SNeil Armstrong [CLKID_VPU_0] = &gxbb_vpu_0.hw, 2818762a1f20SNeil Armstrong [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 2819762a1f20SNeil Armstrong [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 2820762a1f20SNeil Armstrong [CLKID_VPU_1] = &gxbb_vpu_1.hw, 2821762a1f20SNeil Armstrong [CLKID_VPU] = &gxbb_vpu.hw, 2822762a1f20SNeil Armstrong [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 2823762a1f20SNeil Armstrong [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 2824762a1f20SNeil Armstrong [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 2825762a1f20SNeil Armstrong [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 2826762a1f20SNeil Armstrong [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 2827762a1f20SNeil Armstrong [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 2828762a1f20SNeil Armstrong [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 2829762a1f20SNeil Armstrong [CLKID_VAPB] = &gxbb_vapb.hw, 28303c4fe763SJerome Brunet [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw, 2831d610b54fSJerome Brunet [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 2832d610b54fSJerome Brunet [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 2833d610b54fSJerome Brunet [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 2834513b67acSJerome Brunet [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 283505f81440SJerome Brunet [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 283605f81440SJerome Brunet [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 283705f81440SJerome Brunet [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 283805f81440SJerome Brunet [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 283905f81440SJerome Brunet [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 2840a565242eSMaxime Jourdan [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 2841a565242eSMaxime Jourdan [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 2842a565242eSMaxime Jourdan [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 2843a565242eSMaxime Jourdan [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 2844a565242eSMaxime Jourdan [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 2845a565242eSMaxime Jourdan [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 28467df533a7SJerome Brunet [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 28477df533a7SJerome Brunet [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 28487df533a7SJerome Brunet [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 284987173557SJerome Brunet [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 285087173557SJerome Brunet [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw, 285187173557SJerome Brunet [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw, 285287173557SJerome Brunet [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw, 285387173557SJerome Brunet [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 285487173557SJerome Brunet [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw, 2855a8080f24SNeil Armstrong [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 2856a8080f24SNeil Armstrong [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 2857a8080f24SNeil Armstrong [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 2858a8080f24SNeil Armstrong [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 2859a8080f24SNeil Armstrong [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 2860a8080f24SNeil Armstrong [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 2861a8080f24SNeil Armstrong [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 2862a8080f24SNeil Armstrong [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 2863a8080f24SNeil Armstrong [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 2864a8080f24SNeil Armstrong [CLKID_VCLK] = &gxbb_vclk.hw, 2865a8080f24SNeil Armstrong [CLKID_VCLK2] = &gxbb_vclk2.hw, 2866a8080f24SNeil Armstrong [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 2867a8080f24SNeil Armstrong [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 2868a8080f24SNeil Armstrong [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 2869a8080f24SNeil Armstrong [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 2870a8080f24SNeil Armstrong [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 2871a8080f24SNeil Armstrong [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 2872a8080f24SNeil Armstrong [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 2873a8080f24SNeil Armstrong [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 2874a8080f24SNeil Armstrong [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 2875a8080f24SNeil Armstrong [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 2876a8080f24SNeil Armstrong [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 2877a8080f24SNeil Armstrong [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 2878a8080f24SNeil Armstrong [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 2879a8080f24SNeil Armstrong [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 2880a8080f24SNeil Armstrong [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 2881a8080f24SNeil Armstrong [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 2882a8080f24SNeil Armstrong [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 2883a8080f24SNeil Armstrong [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 2884a8080f24SNeil Armstrong [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 2885a8080f24SNeil Armstrong [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 2886a8080f24SNeil Armstrong [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 2887a8080f24SNeil Armstrong [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 2888a8080f24SNeil Armstrong [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 2889a8080f24SNeil Armstrong [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 2890a8080f24SNeil Armstrong [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 2891a8080f24SNeil Armstrong [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 2892a8080f24SNeil Armstrong [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 2893a8080f24SNeil Armstrong [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 2894a8080f24SNeil Armstrong [CLKID_HDMI] = &gxbb_hdmi.hw, 28951f6f1dcbSJerome Brunet [NR_CLKS] = NULL, 2896738f66d3SMichael Turquette }, 2897738f66d3SMichael Turquette .num = NR_CLKS, 2898738f66d3SMichael Turquette }; 2899738f66d3SMichael Turquette 29000d48fc55SNeil Armstrong static struct clk_hw_onecell_data gxl_hw_onecell_data = { 29010d48fc55SNeil Armstrong .hws = { 29020d48fc55SNeil Armstrong [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 290369d92293SJerome Brunet [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw, 29040d48fc55SNeil Armstrong [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 29050d48fc55SNeil Armstrong [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 29060d48fc55SNeil Armstrong [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 29070d48fc55SNeil Armstrong [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 29080d48fc55SNeil Armstrong [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 29090d48fc55SNeil Armstrong [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 291087173557SJerome Brunet [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 29110d48fc55SNeil Armstrong [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 29120d48fc55SNeil Armstrong [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 29130d48fc55SNeil Armstrong [CLKID_CLK81] = &gxbb_clk81.hw, 29140d48fc55SNeil Armstrong [CLKID_MPLL0] = &gxbb_mpll0.hw, 29150d48fc55SNeil Armstrong [CLKID_MPLL1] = &gxbb_mpll1.hw, 29160d48fc55SNeil Armstrong [CLKID_MPLL2] = &gxbb_mpll2.hw, 29170d48fc55SNeil Armstrong [CLKID_DDR] = &gxbb_ddr.hw, 29180d48fc55SNeil Armstrong [CLKID_DOS] = &gxbb_dos.hw, 29190d48fc55SNeil Armstrong [CLKID_ISA] = &gxbb_isa.hw, 29200d48fc55SNeil Armstrong [CLKID_PL301] = &gxbb_pl301.hw, 29210d48fc55SNeil Armstrong [CLKID_PERIPHS] = &gxbb_periphs.hw, 29220d48fc55SNeil Armstrong [CLKID_SPICC] = &gxbb_spicc.hw, 29230d48fc55SNeil Armstrong [CLKID_I2C] = &gxbb_i2c.hw, 29240d48fc55SNeil Armstrong [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 29250d48fc55SNeil Armstrong [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 29260d48fc55SNeil Armstrong [CLKID_RNG0] = &gxbb_rng0.hw, 29270d48fc55SNeil Armstrong [CLKID_UART0] = &gxbb_uart0.hw, 29280d48fc55SNeil Armstrong [CLKID_SDHC] = &gxbb_sdhc.hw, 29290d48fc55SNeil Armstrong [CLKID_STREAM] = &gxbb_stream.hw, 29300d48fc55SNeil Armstrong [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 29310d48fc55SNeil Armstrong [CLKID_SDIO] = &gxbb_sdio.hw, 29320d48fc55SNeil Armstrong [CLKID_ABUF] = &gxbb_abuf.hw, 29330d48fc55SNeil Armstrong [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 29340d48fc55SNeil Armstrong [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 29350d48fc55SNeil Armstrong [CLKID_SPI] = &gxbb_spi.hw, 29360d48fc55SNeil Armstrong [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 29370d48fc55SNeil Armstrong [CLKID_ETH] = &gxbb_eth.hw, 29380d48fc55SNeil Armstrong [CLKID_DEMUX] = &gxbb_demux.hw, 29390d48fc55SNeil Armstrong [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 29400d48fc55SNeil Armstrong [CLKID_IEC958] = &gxbb_iec958.hw, 29410d48fc55SNeil Armstrong [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 29420d48fc55SNeil Armstrong [CLKID_AMCLK] = &gxbb_amclk.hw, 29430d48fc55SNeil Armstrong [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 29440d48fc55SNeil Armstrong [CLKID_MIXER] = &gxbb_mixer.hw, 29450d48fc55SNeil Armstrong [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 29460d48fc55SNeil Armstrong [CLKID_ADC] = &gxbb_adc.hw, 29470d48fc55SNeil Armstrong [CLKID_BLKMV] = &gxbb_blkmv.hw, 29480d48fc55SNeil Armstrong [CLKID_AIU] = &gxbb_aiu.hw, 29490d48fc55SNeil Armstrong [CLKID_UART1] = &gxbb_uart1.hw, 29500d48fc55SNeil Armstrong [CLKID_G2D] = &gxbb_g2d.hw, 29510d48fc55SNeil Armstrong [CLKID_USB0] = &gxbb_usb0.hw, 29520d48fc55SNeil Armstrong [CLKID_USB1] = &gxbb_usb1.hw, 29530d48fc55SNeil Armstrong [CLKID_RESET] = &gxbb_reset.hw, 29540d48fc55SNeil Armstrong [CLKID_NAND] = &gxbb_nand.hw, 29550d48fc55SNeil Armstrong [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 29560d48fc55SNeil Armstrong [CLKID_USB] = &gxbb_usb.hw, 29570d48fc55SNeil Armstrong [CLKID_VDIN1] = &gxbb_vdin1.hw, 29580d48fc55SNeil Armstrong [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 29590d48fc55SNeil Armstrong [CLKID_EFUSE] = &gxbb_efuse.hw, 29600d48fc55SNeil Armstrong [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 29610d48fc55SNeil Armstrong [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 29620d48fc55SNeil Armstrong [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 29630d48fc55SNeil Armstrong [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 29640d48fc55SNeil Armstrong [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 29650d48fc55SNeil Armstrong [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 29660d48fc55SNeil Armstrong [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 29670d48fc55SNeil Armstrong [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 29680d48fc55SNeil Armstrong [CLKID_DVIN] = &gxbb_dvin.hw, 29690d48fc55SNeil Armstrong [CLKID_UART2] = &gxbb_uart2.hw, 29700d48fc55SNeil Armstrong [CLKID_SANA] = &gxbb_sana.hw, 29710d48fc55SNeil Armstrong [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 29720d48fc55SNeil Armstrong [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 29730d48fc55SNeil Armstrong [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 29740d48fc55SNeil Armstrong [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 29750d48fc55SNeil Armstrong [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 29760d48fc55SNeil Armstrong [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 29770d48fc55SNeil Armstrong [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 29780d48fc55SNeil Armstrong [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 29790d48fc55SNeil Armstrong [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 29800d48fc55SNeil Armstrong [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 29810d48fc55SNeil Armstrong [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 29820d48fc55SNeil Armstrong [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 29830d48fc55SNeil Armstrong [CLKID_ENC480P] = &gxbb_enc480p.hw, 29840d48fc55SNeil Armstrong [CLKID_RNG1] = &gxbb_rng1.hw, 29850d48fc55SNeil Armstrong [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 29860d48fc55SNeil Armstrong [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 29870d48fc55SNeil Armstrong [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 29880d48fc55SNeil Armstrong [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 29890d48fc55SNeil Armstrong [CLKID_EDP] = &gxbb_edp.hw, 29900d48fc55SNeil Armstrong [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 29910d48fc55SNeil Armstrong [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 29920d48fc55SNeil Armstrong [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 29930d48fc55SNeil Armstrong [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 29940d48fc55SNeil Armstrong [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 29950d48fc55SNeil Armstrong [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 29960d48fc55SNeil Armstrong [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 29970d48fc55SNeil Armstrong [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 29980d48fc55SNeil Armstrong [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 29990d48fc55SNeil Armstrong [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 30000d48fc55SNeil Armstrong [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 30010d48fc55SNeil Armstrong [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 30020d48fc55SNeil Armstrong [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 30030d48fc55SNeil Armstrong [CLKID_MALI_0] = &gxbb_mali_0.hw, 30040d48fc55SNeil Armstrong [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 30050d48fc55SNeil Armstrong [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 30060d48fc55SNeil Armstrong [CLKID_MALI_1] = &gxbb_mali_1.hw, 30070d48fc55SNeil Armstrong [CLKID_MALI] = &gxbb_mali.hw, 30084087bd4bSJerome Brunet [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 30094087bd4bSJerome Brunet [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 30104087bd4bSJerome Brunet [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 30113c277c24SJerome Brunet [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 30123c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 30133c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 30147eaa44f6SJerome Brunet [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 301514c735c8SNeil Armstrong [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 301614c735c8SNeil Armstrong [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 301714c735c8SNeil Armstrong [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 3018914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 3019914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 3020914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 3021914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 3022914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 3023914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 3024914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 3025914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 3026914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 3027762a1f20SNeil Armstrong [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 3028762a1f20SNeil Armstrong [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 3029762a1f20SNeil Armstrong [CLKID_VPU_0] = &gxbb_vpu_0.hw, 3030762a1f20SNeil Armstrong [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 3031762a1f20SNeil Armstrong [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 3032762a1f20SNeil Armstrong [CLKID_VPU_1] = &gxbb_vpu_1.hw, 3033762a1f20SNeil Armstrong [CLKID_VPU] = &gxbb_vpu.hw, 3034762a1f20SNeil Armstrong [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 3035762a1f20SNeil Armstrong [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 3036762a1f20SNeil Armstrong [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 3037762a1f20SNeil Armstrong [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 3038762a1f20SNeil Armstrong [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 3039762a1f20SNeil Armstrong [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 3040762a1f20SNeil Armstrong [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 3041762a1f20SNeil Armstrong [CLKID_VAPB] = &gxbb_vapb.hw, 3042d610b54fSJerome Brunet [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, 3043d610b54fSJerome Brunet [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, 3044d610b54fSJerome Brunet [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, 3045513b67acSJerome Brunet [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw, 304605f81440SJerome Brunet [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw, 304705f81440SJerome Brunet [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw, 304805f81440SJerome Brunet [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw, 304905f81440SJerome Brunet [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw, 305005f81440SJerome Brunet [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw, 3051a565242eSMaxime Jourdan [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw, 3052a565242eSMaxime Jourdan [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw, 3053a565242eSMaxime Jourdan [CLKID_VDEC_1] = &gxbb_vdec_1.hw, 3054a565242eSMaxime Jourdan [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw, 3055a565242eSMaxime Jourdan [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw, 3056a565242eSMaxime Jourdan [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw, 30577df533a7SJerome Brunet [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw, 30587df533a7SJerome Brunet [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw, 30597df533a7SJerome Brunet [CLKID_GEN_CLK] = &gxbb_gen_clk.hw, 306087173557SJerome Brunet [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw, 30610058502fSNeil Armstrong [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw, 306287173557SJerome Brunet [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw, 306387173557SJerome Brunet [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw, 306487173557SJerome Brunet [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw, 306587173557SJerome Brunet [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw, 3066a8080f24SNeil Armstrong [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw, 3067a8080f24SNeil Armstrong [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw, 3068a8080f24SNeil Armstrong [CLKID_VID_PLL] = &gxbb_vid_pll.hw, 3069a8080f24SNeil Armstrong [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw, 3070a8080f24SNeil Armstrong [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw, 3071a8080f24SNeil Armstrong [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw, 3072a8080f24SNeil Armstrong [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw, 3073a8080f24SNeil Armstrong [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw, 3074a8080f24SNeil Armstrong [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw, 3075a8080f24SNeil Armstrong [CLKID_VCLK] = &gxbb_vclk.hw, 3076a8080f24SNeil Armstrong [CLKID_VCLK2] = &gxbb_vclk2.hw, 3077a8080f24SNeil Armstrong [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw, 3078a8080f24SNeil Armstrong [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw, 3079a8080f24SNeil Armstrong [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw, 3080a8080f24SNeil Armstrong [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw, 3081a8080f24SNeil Armstrong [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw, 3082a8080f24SNeil Armstrong [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw, 3083a8080f24SNeil Armstrong [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw, 3084a8080f24SNeil Armstrong [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw, 3085a8080f24SNeil Armstrong [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw, 3086a8080f24SNeil Armstrong [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw, 3087a8080f24SNeil Armstrong [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw, 3088a8080f24SNeil Armstrong [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw, 3089a8080f24SNeil Armstrong [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw, 3090a8080f24SNeil Armstrong [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw, 3091a8080f24SNeil Armstrong [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw, 3092a8080f24SNeil Armstrong [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw, 3093a8080f24SNeil Armstrong [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw, 3094a8080f24SNeil Armstrong [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw, 3095a8080f24SNeil Armstrong [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw, 3096a8080f24SNeil Armstrong [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw, 3097a8080f24SNeil Armstrong [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw, 3098a8080f24SNeil Armstrong [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw, 3099a8080f24SNeil Armstrong [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw, 3100a8080f24SNeil Armstrong [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw, 3101a8080f24SNeil Armstrong [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw, 3102a8080f24SNeil Armstrong [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw, 3103a8080f24SNeil Armstrong [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw, 3104a8080f24SNeil Armstrong [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw, 3105a8080f24SNeil Armstrong [CLKID_HDMI] = &gxbb_hdmi.hw, 310673c7ddd8SJerome Brunet [CLKID_ACODEC] = &gxl_acodec.hw, 31071f6f1dcbSJerome Brunet [NR_CLKS] = NULL, 31080d48fc55SNeil Armstrong }, 31090d48fc55SNeil Armstrong .num = NR_CLKS, 31100d48fc55SNeil Armstrong }; 31110d48fc55SNeil Armstrong 3112722825dcSJerome Brunet static struct clk_regmap *const gxbb_clk_regmaps[] = { 3113738f66d3SMichael Turquette &gxbb_clk81, 3114738f66d3SMichael Turquette &gxbb_ddr, 3115738f66d3SMichael Turquette &gxbb_dos, 3116738f66d3SMichael Turquette &gxbb_isa, 3117738f66d3SMichael Turquette &gxbb_pl301, 3118738f66d3SMichael Turquette &gxbb_periphs, 3119738f66d3SMichael Turquette &gxbb_spicc, 3120738f66d3SMichael Turquette &gxbb_i2c, 3121738f66d3SMichael Turquette &gxbb_sar_adc, 3122738f66d3SMichael Turquette &gxbb_smart_card, 3123738f66d3SMichael Turquette &gxbb_rng0, 3124738f66d3SMichael Turquette &gxbb_uart0, 3125738f66d3SMichael Turquette &gxbb_sdhc, 3126738f66d3SMichael Turquette &gxbb_stream, 3127738f66d3SMichael Turquette &gxbb_async_fifo, 3128738f66d3SMichael Turquette &gxbb_sdio, 3129738f66d3SMichael Turquette &gxbb_abuf, 3130738f66d3SMichael Turquette &gxbb_hiu_iface, 3131738f66d3SMichael Turquette &gxbb_assist_misc, 3132738f66d3SMichael Turquette &gxbb_spi, 3133738f66d3SMichael Turquette &gxbb_i2s_spdif, 3134738f66d3SMichael Turquette &gxbb_eth, 3135738f66d3SMichael Turquette &gxbb_demux, 3136738f66d3SMichael Turquette &gxbb_aiu_glue, 3137738f66d3SMichael Turquette &gxbb_iec958, 3138738f66d3SMichael Turquette &gxbb_i2s_out, 3139738f66d3SMichael Turquette &gxbb_amclk, 3140738f66d3SMichael Turquette &gxbb_aififo2, 3141738f66d3SMichael Turquette &gxbb_mixer, 3142738f66d3SMichael Turquette &gxbb_mixer_iface, 3143738f66d3SMichael Turquette &gxbb_adc, 3144738f66d3SMichael Turquette &gxbb_blkmv, 3145738f66d3SMichael Turquette &gxbb_aiu, 3146738f66d3SMichael Turquette &gxbb_uart1, 3147738f66d3SMichael Turquette &gxbb_g2d, 3148738f66d3SMichael Turquette &gxbb_usb0, 3149738f66d3SMichael Turquette &gxbb_usb1, 3150738f66d3SMichael Turquette &gxbb_reset, 3151738f66d3SMichael Turquette &gxbb_nand, 3152738f66d3SMichael Turquette &gxbb_dos_parser, 3153738f66d3SMichael Turquette &gxbb_usb, 3154738f66d3SMichael Turquette &gxbb_vdin1, 3155738f66d3SMichael Turquette &gxbb_ahb_arb0, 3156738f66d3SMichael Turquette &gxbb_efuse, 3157738f66d3SMichael Turquette &gxbb_boot_rom, 3158738f66d3SMichael Turquette &gxbb_ahb_data_bus, 3159738f66d3SMichael Turquette &gxbb_ahb_ctrl_bus, 3160738f66d3SMichael Turquette &gxbb_hdmi_intr_sync, 3161738f66d3SMichael Turquette &gxbb_hdmi_pclk, 3162738f66d3SMichael Turquette &gxbb_usb1_ddr_bridge, 3163738f66d3SMichael Turquette &gxbb_usb0_ddr_bridge, 3164738f66d3SMichael Turquette &gxbb_mmc_pclk, 3165738f66d3SMichael Turquette &gxbb_dvin, 3166738f66d3SMichael Turquette &gxbb_uart2, 3167738f66d3SMichael Turquette &gxbb_sana, 3168738f66d3SMichael Turquette &gxbb_vpu_intr, 3169738f66d3SMichael Turquette &gxbb_sec_ahb_ahb3_bridge, 3170738f66d3SMichael Turquette &gxbb_clk81_a53, 3171738f66d3SMichael Turquette &gxbb_vclk2_venci0, 3172738f66d3SMichael Turquette &gxbb_vclk2_venci1, 3173738f66d3SMichael Turquette &gxbb_vclk2_vencp0, 3174738f66d3SMichael Turquette &gxbb_vclk2_vencp1, 3175738f66d3SMichael Turquette &gxbb_gclk_venci_int0, 3176738f66d3SMichael Turquette &gxbb_gclk_vencp_int, 3177738f66d3SMichael Turquette &gxbb_dac_clk, 3178738f66d3SMichael Turquette &gxbb_aoclk_gate, 3179738f66d3SMichael Turquette &gxbb_iec958_gate, 3180738f66d3SMichael Turquette &gxbb_enc480p, 3181738f66d3SMichael Turquette &gxbb_rng1, 3182738f66d3SMichael Turquette &gxbb_gclk_venci_int1, 3183738f66d3SMichael Turquette &gxbb_vclk2_venclmcc, 3184738f66d3SMichael Turquette &gxbb_vclk2_vencl, 3185738f66d3SMichael Turquette &gxbb_vclk_other, 3186738f66d3SMichael Turquette &gxbb_edp, 3187738f66d3SMichael Turquette &gxbb_ao_media_cpu, 3188738f66d3SMichael Turquette &gxbb_ao_ahb_sram, 3189738f66d3SMichael Turquette &gxbb_ao_ahb_bus, 3190738f66d3SMichael Turquette &gxbb_ao_iface, 3191738f66d3SMichael Turquette &gxbb_ao_i2c, 319233608dcdSKevin Hilman &gxbb_emmc_a, 319333608dcdSKevin Hilman &gxbb_emmc_b, 319433608dcdSKevin Hilman &gxbb_emmc_c, 319533d0fcdfSMartin Blumenstingl &gxbb_sar_adc_clk, 3196fac9a55bSNeil Armstrong &gxbb_mali_0, 3197fac9a55bSNeil Armstrong &gxbb_mali_1, 31984087bd4bSJerome Brunet &gxbb_cts_amclk, 31993c277c24SJerome Brunet &gxbb_cts_mclk_i958, 320014c735c8SNeil Armstrong &gxbb_32k_clk, 3201914e6e80SJerome Brunet &gxbb_sd_emmc_a_clk0, 3202914e6e80SJerome Brunet &gxbb_sd_emmc_b_clk0, 3203914e6e80SJerome Brunet &gxbb_sd_emmc_c_clk0, 3204762a1f20SNeil Armstrong &gxbb_vpu_0, 3205762a1f20SNeil Armstrong &gxbb_vpu_1, 3206762a1f20SNeil Armstrong &gxbb_vapb_0, 3207762a1f20SNeil Armstrong &gxbb_vapb_1, 3208762a1f20SNeil Armstrong &gxbb_vapb, 3209f06ddd28SJerome Brunet &gxbb_mpeg_clk_div, 3210f06ddd28SJerome Brunet &gxbb_sar_adc_clk_div, 3211f06ddd28SJerome Brunet &gxbb_mali_0_div, 3212f06ddd28SJerome Brunet &gxbb_mali_1_div, 3213f06ddd28SJerome Brunet &gxbb_cts_mclk_i958_div, 3214f06ddd28SJerome Brunet &gxbb_32k_clk_div, 3215f06ddd28SJerome Brunet &gxbb_sd_emmc_a_clk0_div, 3216f06ddd28SJerome Brunet &gxbb_sd_emmc_b_clk0_div, 3217f06ddd28SJerome Brunet &gxbb_sd_emmc_c_clk0_div, 3218f06ddd28SJerome Brunet &gxbb_vpu_0_div, 3219f06ddd28SJerome Brunet &gxbb_vpu_1_div, 3220f06ddd28SJerome Brunet &gxbb_vapb_0_div, 3221f06ddd28SJerome Brunet &gxbb_vapb_1_div, 32222513a28cSJerome Brunet &gxbb_mpeg_clk_sel, 32232513a28cSJerome Brunet &gxbb_sar_adc_clk_sel, 32242513a28cSJerome Brunet &gxbb_mali_0_sel, 32252513a28cSJerome Brunet &gxbb_mali_1_sel, 32262513a28cSJerome Brunet &gxbb_mali, 32272513a28cSJerome Brunet &gxbb_cts_amclk_sel, 32282513a28cSJerome Brunet &gxbb_cts_mclk_i958_sel, 32292513a28cSJerome Brunet &gxbb_cts_i958, 32302513a28cSJerome Brunet &gxbb_32k_clk_sel, 32312513a28cSJerome Brunet &gxbb_sd_emmc_a_clk0_sel, 32322513a28cSJerome Brunet &gxbb_sd_emmc_b_clk0_sel, 32332513a28cSJerome Brunet &gxbb_sd_emmc_c_clk0_sel, 32342513a28cSJerome Brunet &gxbb_vpu_0_sel, 32352513a28cSJerome Brunet &gxbb_vpu_1_sel, 32362513a28cSJerome Brunet &gxbb_vpu, 32372513a28cSJerome Brunet &gxbb_vapb_0_sel, 32382513a28cSJerome Brunet &gxbb_vapb_1_sel, 32392513a28cSJerome Brunet &gxbb_vapb_sel, 3240c763e61aSJerome Brunet &gxbb_mpll0, 3241c763e61aSJerome Brunet &gxbb_mpll1, 3242c763e61aSJerome Brunet &gxbb_mpll2, 3243d610b54fSJerome Brunet &gxbb_mpll0_div, 3244d610b54fSJerome Brunet &gxbb_mpll1_div, 3245d610b54fSJerome Brunet &gxbb_mpll2_div, 324688a4e128SJerome Brunet &gxbb_cts_amclk_div, 3247722825dcSJerome Brunet &gxbb_fixed_pll, 3248722825dcSJerome Brunet &gxbb_sys_pll, 3249513b67acSJerome Brunet &gxbb_mpll_prediv, 325005f81440SJerome Brunet &gxbb_fclk_div2, 325105f81440SJerome Brunet &gxbb_fclk_div3, 325205f81440SJerome Brunet &gxbb_fclk_div4, 325305f81440SJerome Brunet &gxbb_fclk_div5, 325405f81440SJerome Brunet &gxbb_fclk_div7, 3255a565242eSMaxime Jourdan &gxbb_vdec_1_sel, 3256a565242eSMaxime Jourdan &gxbb_vdec_1_div, 3257a565242eSMaxime Jourdan &gxbb_vdec_1, 3258a565242eSMaxime Jourdan &gxbb_vdec_hevc_sel, 3259a565242eSMaxime Jourdan &gxbb_vdec_hevc_div, 3260a565242eSMaxime Jourdan &gxbb_vdec_hevc, 32617df533a7SJerome Brunet &gxbb_gen_clk_sel, 32627df533a7SJerome Brunet &gxbb_gen_clk_div, 32637df533a7SJerome Brunet &gxbb_gen_clk, 326487173557SJerome Brunet &gxbb_fixed_pll_dco, 326587173557SJerome Brunet &gxbb_sys_pll_dco, 326687173557SJerome Brunet &gxbb_gp0_pll, 3267a8080f24SNeil Armstrong &gxbb_vid_pll, 3268a8080f24SNeil Armstrong &gxbb_vid_pll_sel, 3269a8080f24SNeil Armstrong &gxbb_vid_pll_div, 3270a8080f24SNeil Armstrong &gxbb_vclk, 3271a8080f24SNeil Armstrong &gxbb_vclk_sel, 3272a8080f24SNeil Armstrong &gxbb_vclk_div, 3273a8080f24SNeil Armstrong &gxbb_vclk_input, 3274a8080f24SNeil Armstrong &gxbb_vclk_div1, 3275a8080f24SNeil Armstrong &gxbb_vclk_div2_en, 3276a8080f24SNeil Armstrong &gxbb_vclk_div4_en, 3277a8080f24SNeil Armstrong &gxbb_vclk_div6_en, 3278a8080f24SNeil Armstrong &gxbb_vclk_div12_en, 3279a8080f24SNeil Armstrong &gxbb_vclk2, 3280a8080f24SNeil Armstrong &gxbb_vclk2_sel, 3281a8080f24SNeil Armstrong &gxbb_vclk2_div, 3282a8080f24SNeil Armstrong &gxbb_vclk2_input, 3283a8080f24SNeil Armstrong &gxbb_vclk2_div1, 3284a8080f24SNeil Armstrong &gxbb_vclk2_div2_en, 3285a8080f24SNeil Armstrong &gxbb_vclk2_div4_en, 3286a8080f24SNeil Armstrong &gxbb_vclk2_div6_en, 3287a8080f24SNeil Armstrong &gxbb_vclk2_div12_en, 3288a8080f24SNeil Armstrong &gxbb_cts_enci, 3289a8080f24SNeil Armstrong &gxbb_cts_enci_sel, 3290a8080f24SNeil Armstrong &gxbb_cts_encp, 3291a8080f24SNeil Armstrong &gxbb_cts_encp_sel, 3292a8080f24SNeil Armstrong &gxbb_cts_vdac, 3293a8080f24SNeil Armstrong &gxbb_cts_vdac_sel, 3294a8080f24SNeil Armstrong &gxbb_hdmi_tx, 3295a8080f24SNeil Armstrong &gxbb_hdmi_tx_sel, 3296a8080f24SNeil Armstrong &gxbb_hdmi_sel, 3297a8080f24SNeil Armstrong &gxbb_hdmi_div, 3298a8080f24SNeil Armstrong &gxbb_hdmi, 32996682bd4dSJerome Brunet &gxbb_gp0_pll_dco, 33006682bd4dSJerome Brunet &gxbb_hdmi_pll, 33016682bd4dSJerome Brunet &gxbb_hdmi_pll_od, 33026682bd4dSJerome Brunet &gxbb_hdmi_pll_od2, 33036682bd4dSJerome Brunet &gxbb_hdmi_pll_dco, 3304738f66d3SMichael Turquette }; 3305738f66d3SMichael Turquette 33066682bd4dSJerome Brunet static struct clk_regmap *const gxl_clk_regmaps[] = { 33076682bd4dSJerome Brunet &gxbb_clk81, 33086682bd4dSJerome Brunet &gxbb_ddr, 33096682bd4dSJerome Brunet &gxbb_dos, 33106682bd4dSJerome Brunet &gxbb_isa, 33116682bd4dSJerome Brunet &gxbb_pl301, 33126682bd4dSJerome Brunet &gxbb_periphs, 33136682bd4dSJerome Brunet &gxbb_spicc, 33146682bd4dSJerome Brunet &gxbb_i2c, 33156682bd4dSJerome Brunet &gxbb_sar_adc, 33166682bd4dSJerome Brunet &gxbb_smart_card, 33176682bd4dSJerome Brunet &gxbb_rng0, 33186682bd4dSJerome Brunet &gxbb_uart0, 33196682bd4dSJerome Brunet &gxbb_sdhc, 33206682bd4dSJerome Brunet &gxbb_stream, 33216682bd4dSJerome Brunet &gxbb_async_fifo, 33226682bd4dSJerome Brunet &gxbb_sdio, 33236682bd4dSJerome Brunet &gxbb_abuf, 33246682bd4dSJerome Brunet &gxbb_hiu_iface, 33256682bd4dSJerome Brunet &gxbb_assist_misc, 33266682bd4dSJerome Brunet &gxbb_spi, 33276682bd4dSJerome Brunet &gxbb_i2s_spdif, 33286682bd4dSJerome Brunet &gxbb_eth, 33296682bd4dSJerome Brunet &gxbb_demux, 33306682bd4dSJerome Brunet &gxbb_aiu_glue, 33316682bd4dSJerome Brunet &gxbb_iec958, 33326682bd4dSJerome Brunet &gxbb_i2s_out, 33336682bd4dSJerome Brunet &gxbb_amclk, 33346682bd4dSJerome Brunet &gxbb_aififo2, 33356682bd4dSJerome Brunet &gxbb_mixer, 33366682bd4dSJerome Brunet &gxbb_mixer_iface, 33376682bd4dSJerome Brunet &gxbb_adc, 33386682bd4dSJerome Brunet &gxbb_blkmv, 33396682bd4dSJerome Brunet &gxbb_aiu, 33406682bd4dSJerome Brunet &gxbb_uart1, 33416682bd4dSJerome Brunet &gxbb_g2d, 33426682bd4dSJerome Brunet &gxbb_usb0, 33436682bd4dSJerome Brunet &gxbb_usb1, 33446682bd4dSJerome Brunet &gxbb_reset, 33456682bd4dSJerome Brunet &gxbb_nand, 33466682bd4dSJerome Brunet &gxbb_dos_parser, 33476682bd4dSJerome Brunet &gxbb_usb, 33486682bd4dSJerome Brunet &gxbb_vdin1, 33496682bd4dSJerome Brunet &gxbb_ahb_arb0, 33506682bd4dSJerome Brunet &gxbb_efuse, 33516682bd4dSJerome Brunet &gxbb_boot_rom, 33526682bd4dSJerome Brunet &gxbb_ahb_data_bus, 33536682bd4dSJerome Brunet &gxbb_ahb_ctrl_bus, 33546682bd4dSJerome Brunet &gxbb_hdmi_intr_sync, 33556682bd4dSJerome Brunet &gxbb_hdmi_pclk, 33566682bd4dSJerome Brunet &gxbb_usb1_ddr_bridge, 33576682bd4dSJerome Brunet &gxbb_usb0_ddr_bridge, 33586682bd4dSJerome Brunet &gxbb_mmc_pclk, 33596682bd4dSJerome Brunet &gxbb_dvin, 33606682bd4dSJerome Brunet &gxbb_uart2, 33616682bd4dSJerome Brunet &gxbb_sana, 33626682bd4dSJerome Brunet &gxbb_vpu_intr, 33636682bd4dSJerome Brunet &gxbb_sec_ahb_ahb3_bridge, 33646682bd4dSJerome Brunet &gxbb_clk81_a53, 33656682bd4dSJerome Brunet &gxbb_vclk2_venci0, 33666682bd4dSJerome Brunet &gxbb_vclk2_venci1, 33676682bd4dSJerome Brunet &gxbb_vclk2_vencp0, 33686682bd4dSJerome Brunet &gxbb_vclk2_vencp1, 33696682bd4dSJerome Brunet &gxbb_gclk_venci_int0, 33706682bd4dSJerome Brunet &gxbb_gclk_vencp_int, 33716682bd4dSJerome Brunet &gxbb_dac_clk, 33726682bd4dSJerome Brunet &gxbb_aoclk_gate, 33736682bd4dSJerome Brunet &gxbb_iec958_gate, 33746682bd4dSJerome Brunet &gxbb_enc480p, 33756682bd4dSJerome Brunet &gxbb_rng1, 33766682bd4dSJerome Brunet &gxbb_gclk_venci_int1, 33776682bd4dSJerome Brunet &gxbb_vclk2_venclmcc, 33786682bd4dSJerome Brunet &gxbb_vclk2_vencl, 33796682bd4dSJerome Brunet &gxbb_vclk_other, 33806682bd4dSJerome Brunet &gxbb_edp, 33816682bd4dSJerome Brunet &gxbb_ao_media_cpu, 33826682bd4dSJerome Brunet &gxbb_ao_ahb_sram, 33836682bd4dSJerome Brunet &gxbb_ao_ahb_bus, 33846682bd4dSJerome Brunet &gxbb_ao_iface, 33856682bd4dSJerome Brunet &gxbb_ao_i2c, 33866682bd4dSJerome Brunet &gxbb_emmc_a, 33876682bd4dSJerome Brunet &gxbb_emmc_b, 33886682bd4dSJerome Brunet &gxbb_emmc_c, 33896682bd4dSJerome Brunet &gxbb_sar_adc_clk, 33906682bd4dSJerome Brunet &gxbb_mali_0, 33916682bd4dSJerome Brunet &gxbb_mali_1, 33926682bd4dSJerome Brunet &gxbb_cts_amclk, 33936682bd4dSJerome Brunet &gxbb_cts_mclk_i958, 33946682bd4dSJerome Brunet &gxbb_32k_clk, 33956682bd4dSJerome Brunet &gxbb_sd_emmc_a_clk0, 33966682bd4dSJerome Brunet &gxbb_sd_emmc_b_clk0, 33976682bd4dSJerome Brunet &gxbb_sd_emmc_c_clk0, 33986682bd4dSJerome Brunet &gxbb_vpu_0, 33996682bd4dSJerome Brunet &gxbb_vpu_1, 34006682bd4dSJerome Brunet &gxbb_vapb_0, 34016682bd4dSJerome Brunet &gxbb_vapb_1, 34026682bd4dSJerome Brunet &gxbb_vapb, 34036682bd4dSJerome Brunet &gxbb_mpeg_clk_div, 34046682bd4dSJerome Brunet &gxbb_sar_adc_clk_div, 34056682bd4dSJerome Brunet &gxbb_mali_0_div, 34066682bd4dSJerome Brunet &gxbb_mali_1_div, 34076682bd4dSJerome Brunet &gxbb_cts_mclk_i958_div, 34086682bd4dSJerome Brunet &gxbb_32k_clk_div, 34096682bd4dSJerome Brunet &gxbb_sd_emmc_a_clk0_div, 34106682bd4dSJerome Brunet &gxbb_sd_emmc_b_clk0_div, 34116682bd4dSJerome Brunet &gxbb_sd_emmc_c_clk0_div, 34126682bd4dSJerome Brunet &gxbb_vpu_0_div, 34136682bd4dSJerome Brunet &gxbb_vpu_1_div, 34146682bd4dSJerome Brunet &gxbb_vapb_0_div, 34156682bd4dSJerome Brunet &gxbb_vapb_1_div, 34166682bd4dSJerome Brunet &gxbb_mpeg_clk_sel, 34176682bd4dSJerome Brunet &gxbb_sar_adc_clk_sel, 34186682bd4dSJerome Brunet &gxbb_mali_0_sel, 34196682bd4dSJerome Brunet &gxbb_mali_1_sel, 34206682bd4dSJerome Brunet &gxbb_mali, 34216682bd4dSJerome Brunet &gxbb_cts_amclk_sel, 34226682bd4dSJerome Brunet &gxbb_cts_mclk_i958_sel, 34236682bd4dSJerome Brunet &gxbb_cts_i958, 34246682bd4dSJerome Brunet &gxbb_32k_clk_sel, 34256682bd4dSJerome Brunet &gxbb_sd_emmc_a_clk0_sel, 34266682bd4dSJerome Brunet &gxbb_sd_emmc_b_clk0_sel, 34276682bd4dSJerome Brunet &gxbb_sd_emmc_c_clk0_sel, 34286682bd4dSJerome Brunet &gxbb_vpu_0_sel, 34296682bd4dSJerome Brunet &gxbb_vpu_1_sel, 34306682bd4dSJerome Brunet &gxbb_vpu, 34316682bd4dSJerome Brunet &gxbb_vapb_0_sel, 34326682bd4dSJerome Brunet &gxbb_vapb_1_sel, 34336682bd4dSJerome Brunet &gxbb_vapb_sel, 34346682bd4dSJerome Brunet &gxbb_mpll0, 34356682bd4dSJerome Brunet &gxbb_mpll1, 34366682bd4dSJerome Brunet &gxbb_mpll2, 34376682bd4dSJerome Brunet &gxbb_mpll0_div, 34386682bd4dSJerome Brunet &gxbb_mpll1_div, 34396682bd4dSJerome Brunet &gxbb_mpll2_div, 34406682bd4dSJerome Brunet &gxbb_cts_amclk_div, 34416682bd4dSJerome Brunet &gxbb_fixed_pll, 34426682bd4dSJerome Brunet &gxbb_sys_pll, 34436682bd4dSJerome Brunet &gxbb_mpll_prediv, 34446682bd4dSJerome Brunet &gxbb_fclk_div2, 34456682bd4dSJerome Brunet &gxbb_fclk_div3, 34466682bd4dSJerome Brunet &gxbb_fclk_div4, 34476682bd4dSJerome Brunet &gxbb_fclk_div5, 34486682bd4dSJerome Brunet &gxbb_fclk_div7, 34496682bd4dSJerome Brunet &gxbb_vdec_1_sel, 34506682bd4dSJerome Brunet &gxbb_vdec_1_div, 34516682bd4dSJerome Brunet &gxbb_vdec_1, 34526682bd4dSJerome Brunet &gxbb_vdec_hevc_sel, 34536682bd4dSJerome Brunet &gxbb_vdec_hevc_div, 34546682bd4dSJerome Brunet &gxbb_vdec_hevc, 34556682bd4dSJerome Brunet &gxbb_gen_clk_sel, 34566682bd4dSJerome Brunet &gxbb_gen_clk_div, 34576682bd4dSJerome Brunet &gxbb_gen_clk, 34586682bd4dSJerome Brunet &gxbb_fixed_pll_dco, 34596682bd4dSJerome Brunet &gxbb_sys_pll_dco, 34606682bd4dSJerome Brunet &gxbb_gp0_pll, 34616682bd4dSJerome Brunet &gxbb_vid_pll, 34626682bd4dSJerome Brunet &gxbb_vid_pll_sel, 34636682bd4dSJerome Brunet &gxbb_vid_pll_div, 34646682bd4dSJerome Brunet &gxbb_vclk, 34656682bd4dSJerome Brunet &gxbb_vclk_sel, 34666682bd4dSJerome Brunet &gxbb_vclk_div, 34676682bd4dSJerome Brunet &gxbb_vclk_input, 34686682bd4dSJerome Brunet &gxbb_vclk_div1, 34696682bd4dSJerome Brunet &gxbb_vclk_div2_en, 34706682bd4dSJerome Brunet &gxbb_vclk_div4_en, 34716682bd4dSJerome Brunet &gxbb_vclk_div6_en, 34726682bd4dSJerome Brunet &gxbb_vclk_div12_en, 34736682bd4dSJerome Brunet &gxbb_vclk2, 34746682bd4dSJerome Brunet &gxbb_vclk2_sel, 34756682bd4dSJerome Brunet &gxbb_vclk2_div, 34766682bd4dSJerome Brunet &gxbb_vclk2_input, 34776682bd4dSJerome Brunet &gxbb_vclk2_div1, 34786682bd4dSJerome Brunet &gxbb_vclk2_div2_en, 34796682bd4dSJerome Brunet &gxbb_vclk2_div4_en, 34806682bd4dSJerome Brunet &gxbb_vclk2_div6_en, 34816682bd4dSJerome Brunet &gxbb_vclk2_div12_en, 34826682bd4dSJerome Brunet &gxbb_cts_enci, 34836682bd4dSJerome Brunet &gxbb_cts_enci_sel, 34846682bd4dSJerome Brunet &gxbb_cts_encp, 34856682bd4dSJerome Brunet &gxbb_cts_encp_sel, 34866682bd4dSJerome Brunet &gxbb_cts_vdac, 34876682bd4dSJerome Brunet &gxbb_cts_vdac_sel, 34886682bd4dSJerome Brunet &gxbb_hdmi_tx, 34896682bd4dSJerome Brunet &gxbb_hdmi_tx_sel, 34906682bd4dSJerome Brunet &gxbb_hdmi_sel, 34916682bd4dSJerome Brunet &gxbb_hdmi_div, 34926682bd4dSJerome Brunet &gxbb_hdmi, 34936682bd4dSJerome Brunet &gxl_gp0_pll_dco, 34946682bd4dSJerome Brunet &gxl_hdmi_pll, 34956682bd4dSJerome Brunet &gxl_hdmi_pll_od, 34966682bd4dSJerome Brunet &gxl_hdmi_pll_od2, 34976682bd4dSJerome Brunet &gxl_hdmi_pll_dco, 349873c7ddd8SJerome Brunet &gxl_acodec, 34990d48fc55SNeil Armstrong }; 35000d48fc55SNeil Armstrong 35016682bd4dSJerome Brunet static const struct meson_eeclkc_data gxbb_clkc_data = { 3502722825dcSJerome Brunet .regmap_clks = gxbb_clk_regmaps, 35036682bd4dSJerome Brunet .regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps), 35040d48fc55SNeil Armstrong .hw_onecell_data = &gxbb_hw_onecell_data, 35050d48fc55SNeil Armstrong }; 35060d48fc55SNeil Armstrong 35076682bd4dSJerome Brunet static const struct meson_eeclkc_data gxl_clkc_data = { 3508722825dcSJerome Brunet .regmap_clks = gxl_clk_regmaps, 35096682bd4dSJerome Brunet .regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps), 35100d48fc55SNeil Armstrong .hw_onecell_data = &gxl_hw_onecell_data, 35110d48fc55SNeil Armstrong }; 35120d48fc55SNeil Armstrong 35130d48fc55SNeil Armstrong static const struct of_device_id clkc_match_table[] = { 35140d48fc55SNeil Armstrong { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data }, 35150d48fc55SNeil Armstrong { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data }, 35160d48fc55SNeil Armstrong {}, 35170d48fc55SNeil Armstrong }; 35180d48fc55SNeil Armstrong 3519738f66d3SMichael Turquette static struct platform_driver gxbb_driver = { 35206682bd4dSJerome Brunet .probe = meson_eeclkc_probe, 3521738f66d3SMichael Turquette .driver = { 3522738f66d3SMichael Turquette .name = "gxbb-clkc", 35230d48fc55SNeil Armstrong .of_match_table = clkc_match_table, 3524738f66d3SMichael Turquette }, 3525738f66d3SMichael Turquette }; 3526738f66d3SMichael Turquette 352700746f10SWei Yongjun builtin_platform_driver(gxbb_driver); 3528