1738f66d3SMichael Turquette /* 21f501d63SPaul Gortmaker * AmLogic S905 / GXBB Clock Controller Driver 31f501d63SPaul Gortmaker * 4738f66d3SMichael Turquette * Copyright (c) 2016 AmLogic, Inc. 5738f66d3SMichael Turquette * Michael Turquette <mturquette@baylibre.com> 6738f66d3SMichael Turquette * 7738f66d3SMichael Turquette * This program is free software; you can redistribute it and/or modify it 8738f66d3SMichael Turquette * under the terms and conditions of the GNU General Public License, 9738f66d3SMichael Turquette * version 2, as published by the Free Software Foundation. 10738f66d3SMichael Turquette * 11738f66d3SMichael Turquette * This program is distributed in the hope it will be useful, but WITHOUT 12738f66d3SMichael Turquette * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13738f66d3SMichael Turquette * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14738f66d3SMichael Turquette * more details. 15738f66d3SMichael Turquette * 16738f66d3SMichael Turquette * You should have received a copy of the GNU General Public License along with 17738f66d3SMichael Turquette * this program. If not, see <http://www.gnu.org/licenses/>. 18738f66d3SMichael Turquette */ 19738f66d3SMichael Turquette 20738f66d3SMichael Turquette #include <linux/clk.h> 21738f66d3SMichael Turquette #include <linux/clk-provider.h> 22738f66d3SMichael Turquette #include <linux/of_address.h> 230d48fc55SNeil Armstrong #include <linux/of_device.h> 24738f66d3SMichael Turquette #include <linux/platform_device.h> 251f501d63SPaul Gortmaker #include <linux/init.h> 26738f66d3SMichael Turquette 27738f66d3SMichael Turquette #include "clkc.h" 28738f66d3SMichael Turquette #include "gxbb.h" 29738f66d3SMichael Turquette 30738f66d3SMichael Turquette static DEFINE_SPINLOCK(clk_lock); 31738f66d3SMichael Turquette 32738f66d3SMichael Turquette static const struct pll_rate_table sys_pll_rate_table[] = { 33738f66d3SMichael Turquette PLL_RATE(24000000, 56, 1, 2), 34738f66d3SMichael Turquette PLL_RATE(48000000, 64, 1, 2), 35738f66d3SMichael Turquette PLL_RATE(72000000, 72, 1, 2), 36738f66d3SMichael Turquette PLL_RATE(96000000, 64, 1, 2), 37738f66d3SMichael Turquette PLL_RATE(120000000, 80, 1, 2), 38738f66d3SMichael Turquette PLL_RATE(144000000, 96, 1, 2), 39738f66d3SMichael Turquette PLL_RATE(168000000, 56, 1, 1), 40738f66d3SMichael Turquette PLL_RATE(192000000, 64, 1, 1), 41738f66d3SMichael Turquette PLL_RATE(216000000, 72, 1, 1), 42738f66d3SMichael Turquette PLL_RATE(240000000, 80, 1, 1), 43738f66d3SMichael Turquette PLL_RATE(264000000, 88, 1, 1), 44738f66d3SMichael Turquette PLL_RATE(288000000, 96, 1, 1), 45738f66d3SMichael Turquette PLL_RATE(312000000, 52, 1, 2), 46738f66d3SMichael Turquette PLL_RATE(336000000, 56, 1, 2), 47738f66d3SMichael Turquette PLL_RATE(360000000, 60, 1, 2), 48738f66d3SMichael Turquette PLL_RATE(384000000, 64, 1, 2), 49738f66d3SMichael Turquette PLL_RATE(408000000, 68, 1, 2), 50738f66d3SMichael Turquette PLL_RATE(432000000, 72, 1, 2), 51738f66d3SMichael Turquette PLL_RATE(456000000, 76, 1, 2), 52738f66d3SMichael Turquette PLL_RATE(480000000, 80, 1, 2), 53738f66d3SMichael Turquette PLL_RATE(504000000, 84, 1, 2), 54738f66d3SMichael Turquette PLL_RATE(528000000, 88, 1, 2), 55738f66d3SMichael Turquette PLL_RATE(552000000, 92, 1, 2), 56738f66d3SMichael Turquette PLL_RATE(576000000, 96, 1, 2), 57738f66d3SMichael Turquette PLL_RATE(600000000, 50, 1, 1), 58738f66d3SMichael Turquette PLL_RATE(624000000, 52, 1, 1), 59738f66d3SMichael Turquette PLL_RATE(648000000, 54, 1, 1), 60738f66d3SMichael Turquette PLL_RATE(672000000, 56, 1, 1), 61738f66d3SMichael Turquette PLL_RATE(696000000, 58, 1, 1), 62738f66d3SMichael Turquette PLL_RATE(720000000, 60, 1, 1), 63738f66d3SMichael Turquette PLL_RATE(744000000, 62, 1, 1), 64738f66d3SMichael Turquette PLL_RATE(768000000, 64, 1, 1), 65738f66d3SMichael Turquette PLL_RATE(792000000, 66, 1, 1), 66738f66d3SMichael Turquette PLL_RATE(816000000, 68, 1, 1), 67738f66d3SMichael Turquette PLL_RATE(840000000, 70, 1, 1), 68738f66d3SMichael Turquette PLL_RATE(864000000, 72, 1, 1), 69738f66d3SMichael Turquette PLL_RATE(888000000, 74, 1, 1), 70738f66d3SMichael Turquette PLL_RATE(912000000, 76, 1, 1), 71738f66d3SMichael Turquette PLL_RATE(936000000, 78, 1, 1), 72738f66d3SMichael Turquette PLL_RATE(960000000, 80, 1, 1), 73738f66d3SMichael Turquette PLL_RATE(984000000, 82, 1, 1), 74738f66d3SMichael Turquette PLL_RATE(1008000000, 84, 1, 1), 75738f66d3SMichael Turquette PLL_RATE(1032000000, 86, 1, 1), 76738f66d3SMichael Turquette PLL_RATE(1056000000, 88, 1, 1), 77738f66d3SMichael Turquette PLL_RATE(1080000000, 90, 1, 1), 78738f66d3SMichael Turquette PLL_RATE(1104000000, 92, 1, 1), 79738f66d3SMichael Turquette PLL_RATE(1128000000, 94, 1, 1), 80738f66d3SMichael Turquette PLL_RATE(1152000000, 96, 1, 1), 81738f66d3SMichael Turquette PLL_RATE(1176000000, 98, 1, 1), 82738f66d3SMichael Turquette PLL_RATE(1200000000, 50, 1, 0), 83738f66d3SMichael Turquette PLL_RATE(1224000000, 51, 1, 0), 84738f66d3SMichael Turquette PLL_RATE(1248000000, 52, 1, 0), 85738f66d3SMichael Turquette PLL_RATE(1272000000, 53, 1, 0), 86738f66d3SMichael Turquette PLL_RATE(1296000000, 54, 1, 0), 87738f66d3SMichael Turquette PLL_RATE(1320000000, 55, 1, 0), 88738f66d3SMichael Turquette PLL_RATE(1344000000, 56, 1, 0), 89738f66d3SMichael Turquette PLL_RATE(1368000000, 57, 1, 0), 90738f66d3SMichael Turquette PLL_RATE(1392000000, 58, 1, 0), 91738f66d3SMichael Turquette PLL_RATE(1416000000, 59, 1, 0), 92738f66d3SMichael Turquette PLL_RATE(1440000000, 60, 1, 0), 93738f66d3SMichael Turquette PLL_RATE(1464000000, 61, 1, 0), 94738f66d3SMichael Turquette PLL_RATE(1488000000, 62, 1, 0), 95738f66d3SMichael Turquette PLL_RATE(1512000000, 63, 1, 0), 96738f66d3SMichael Turquette PLL_RATE(1536000000, 64, 1, 0), 97738f66d3SMichael Turquette PLL_RATE(1560000000, 65, 1, 0), 98738f66d3SMichael Turquette PLL_RATE(1584000000, 66, 1, 0), 99738f66d3SMichael Turquette PLL_RATE(1608000000, 67, 1, 0), 100738f66d3SMichael Turquette PLL_RATE(1632000000, 68, 1, 0), 101738f66d3SMichael Turquette PLL_RATE(1656000000, 68, 1, 0), 102738f66d3SMichael Turquette PLL_RATE(1680000000, 68, 1, 0), 103738f66d3SMichael Turquette PLL_RATE(1704000000, 68, 1, 0), 104738f66d3SMichael Turquette PLL_RATE(1728000000, 69, 1, 0), 105738f66d3SMichael Turquette PLL_RATE(1752000000, 69, 1, 0), 106738f66d3SMichael Turquette PLL_RATE(1776000000, 69, 1, 0), 107738f66d3SMichael Turquette PLL_RATE(1800000000, 69, 1, 0), 108738f66d3SMichael Turquette PLL_RATE(1824000000, 70, 1, 0), 109738f66d3SMichael Turquette PLL_RATE(1848000000, 70, 1, 0), 110738f66d3SMichael Turquette PLL_RATE(1872000000, 70, 1, 0), 111738f66d3SMichael Turquette PLL_RATE(1896000000, 70, 1, 0), 112738f66d3SMichael Turquette PLL_RATE(1920000000, 71, 1, 0), 113738f66d3SMichael Turquette PLL_RATE(1944000000, 71, 1, 0), 114738f66d3SMichael Turquette PLL_RATE(1968000000, 71, 1, 0), 115738f66d3SMichael Turquette PLL_RATE(1992000000, 71, 1, 0), 116738f66d3SMichael Turquette PLL_RATE(2016000000, 72, 1, 0), 117738f66d3SMichael Turquette PLL_RATE(2040000000, 72, 1, 0), 118738f66d3SMichael Turquette PLL_RATE(2064000000, 72, 1, 0), 119738f66d3SMichael Turquette PLL_RATE(2088000000, 72, 1, 0), 120738f66d3SMichael Turquette PLL_RATE(2112000000, 73, 1, 0), 121738f66d3SMichael Turquette { /* sentinel */ }, 122738f66d3SMichael Turquette }; 123738f66d3SMichael Turquette 1240d48fc55SNeil Armstrong static const struct pll_rate_table gxbb_gp0_pll_rate_table[] = { 125738f66d3SMichael Turquette PLL_RATE(96000000, 32, 1, 3), 126738f66d3SMichael Turquette PLL_RATE(99000000, 33, 1, 3), 127738f66d3SMichael Turquette PLL_RATE(102000000, 34, 1, 3), 128738f66d3SMichael Turquette PLL_RATE(105000000, 35, 1, 3), 129738f66d3SMichael Turquette PLL_RATE(108000000, 36, 1, 3), 130738f66d3SMichael Turquette PLL_RATE(111000000, 37, 1, 3), 131738f66d3SMichael Turquette PLL_RATE(114000000, 38, 1, 3), 132738f66d3SMichael Turquette PLL_RATE(117000000, 39, 1, 3), 133738f66d3SMichael Turquette PLL_RATE(120000000, 40, 1, 3), 134738f66d3SMichael Turquette PLL_RATE(123000000, 41, 1, 3), 135738f66d3SMichael Turquette PLL_RATE(126000000, 42, 1, 3), 136738f66d3SMichael Turquette PLL_RATE(129000000, 43, 1, 3), 137738f66d3SMichael Turquette PLL_RATE(132000000, 44, 1, 3), 138738f66d3SMichael Turquette PLL_RATE(135000000, 45, 1, 3), 139738f66d3SMichael Turquette PLL_RATE(138000000, 46, 1, 3), 140738f66d3SMichael Turquette PLL_RATE(141000000, 47, 1, 3), 141738f66d3SMichael Turquette PLL_RATE(144000000, 48, 1, 3), 142738f66d3SMichael Turquette PLL_RATE(147000000, 49, 1, 3), 143738f66d3SMichael Turquette PLL_RATE(150000000, 50, 1, 3), 144738f66d3SMichael Turquette PLL_RATE(153000000, 51, 1, 3), 145738f66d3SMichael Turquette PLL_RATE(156000000, 52, 1, 3), 146738f66d3SMichael Turquette PLL_RATE(159000000, 53, 1, 3), 147738f66d3SMichael Turquette PLL_RATE(162000000, 54, 1, 3), 148738f66d3SMichael Turquette PLL_RATE(165000000, 55, 1, 3), 149738f66d3SMichael Turquette PLL_RATE(168000000, 56, 1, 3), 150738f66d3SMichael Turquette PLL_RATE(171000000, 57, 1, 3), 151738f66d3SMichael Turquette PLL_RATE(174000000, 58, 1, 3), 152738f66d3SMichael Turquette PLL_RATE(177000000, 59, 1, 3), 153738f66d3SMichael Turquette PLL_RATE(180000000, 60, 1, 3), 154738f66d3SMichael Turquette PLL_RATE(183000000, 61, 1, 3), 155738f66d3SMichael Turquette PLL_RATE(186000000, 62, 1, 3), 156738f66d3SMichael Turquette PLL_RATE(192000000, 32, 1, 2), 157738f66d3SMichael Turquette PLL_RATE(198000000, 33, 1, 2), 158738f66d3SMichael Turquette PLL_RATE(204000000, 34, 1, 2), 159738f66d3SMichael Turquette PLL_RATE(210000000, 35, 1, 2), 160738f66d3SMichael Turquette PLL_RATE(216000000, 36, 1, 2), 161738f66d3SMichael Turquette PLL_RATE(222000000, 37, 1, 2), 162738f66d3SMichael Turquette PLL_RATE(228000000, 38, 1, 2), 163738f66d3SMichael Turquette PLL_RATE(234000000, 39, 1, 2), 164738f66d3SMichael Turquette PLL_RATE(240000000, 40, 1, 2), 165738f66d3SMichael Turquette PLL_RATE(246000000, 41, 1, 2), 166738f66d3SMichael Turquette PLL_RATE(252000000, 42, 1, 2), 167738f66d3SMichael Turquette PLL_RATE(258000000, 43, 1, 2), 168738f66d3SMichael Turquette PLL_RATE(264000000, 44, 1, 2), 169738f66d3SMichael Turquette PLL_RATE(270000000, 45, 1, 2), 170738f66d3SMichael Turquette PLL_RATE(276000000, 46, 1, 2), 171738f66d3SMichael Turquette PLL_RATE(282000000, 47, 1, 2), 172738f66d3SMichael Turquette PLL_RATE(288000000, 48, 1, 2), 173738f66d3SMichael Turquette PLL_RATE(294000000, 49, 1, 2), 174738f66d3SMichael Turquette PLL_RATE(300000000, 50, 1, 2), 175738f66d3SMichael Turquette PLL_RATE(306000000, 51, 1, 2), 176738f66d3SMichael Turquette PLL_RATE(312000000, 52, 1, 2), 177738f66d3SMichael Turquette PLL_RATE(318000000, 53, 1, 2), 178738f66d3SMichael Turquette PLL_RATE(324000000, 54, 1, 2), 179738f66d3SMichael Turquette PLL_RATE(330000000, 55, 1, 2), 180738f66d3SMichael Turquette PLL_RATE(336000000, 56, 1, 2), 181738f66d3SMichael Turquette PLL_RATE(342000000, 57, 1, 2), 182738f66d3SMichael Turquette PLL_RATE(348000000, 58, 1, 2), 183738f66d3SMichael Turquette PLL_RATE(354000000, 59, 1, 2), 184738f66d3SMichael Turquette PLL_RATE(360000000, 60, 1, 2), 185738f66d3SMichael Turquette PLL_RATE(366000000, 61, 1, 2), 186738f66d3SMichael Turquette PLL_RATE(372000000, 62, 1, 2), 187738f66d3SMichael Turquette PLL_RATE(384000000, 32, 1, 1), 188738f66d3SMichael Turquette PLL_RATE(396000000, 33, 1, 1), 189738f66d3SMichael Turquette PLL_RATE(408000000, 34, 1, 1), 190738f66d3SMichael Turquette PLL_RATE(420000000, 35, 1, 1), 191738f66d3SMichael Turquette PLL_RATE(432000000, 36, 1, 1), 192738f66d3SMichael Turquette PLL_RATE(444000000, 37, 1, 1), 193738f66d3SMichael Turquette PLL_RATE(456000000, 38, 1, 1), 194738f66d3SMichael Turquette PLL_RATE(468000000, 39, 1, 1), 195738f66d3SMichael Turquette PLL_RATE(480000000, 40, 1, 1), 196738f66d3SMichael Turquette PLL_RATE(492000000, 41, 1, 1), 197738f66d3SMichael Turquette PLL_RATE(504000000, 42, 1, 1), 198738f66d3SMichael Turquette PLL_RATE(516000000, 43, 1, 1), 199738f66d3SMichael Turquette PLL_RATE(528000000, 44, 1, 1), 200738f66d3SMichael Turquette PLL_RATE(540000000, 45, 1, 1), 201738f66d3SMichael Turquette PLL_RATE(552000000, 46, 1, 1), 202738f66d3SMichael Turquette PLL_RATE(564000000, 47, 1, 1), 203738f66d3SMichael Turquette PLL_RATE(576000000, 48, 1, 1), 204738f66d3SMichael Turquette PLL_RATE(588000000, 49, 1, 1), 205738f66d3SMichael Turquette PLL_RATE(600000000, 50, 1, 1), 206738f66d3SMichael Turquette PLL_RATE(612000000, 51, 1, 1), 207738f66d3SMichael Turquette PLL_RATE(624000000, 52, 1, 1), 208738f66d3SMichael Turquette PLL_RATE(636000000, 53, 1, 1), 209738f66d3SMichael Turquette PLL_RATE(648000000, 54, 1, 1), 210738f66d3SMichael Turquette PLL_RATE(660000000, 55, 1, 1), 211738f66d3SMichael Turquette PLL_RATE(672000000, 56, 1, 1), 212738f66d3SMichael Turquette PLL_RATE(684000000, 57, 1, 1), 213738f66d3SMichael Turquette PLL_RATE(696000000, 58, 1, 1), 214738f66d3SMichael Turquette PLL_RATE(708000000, 59, 1, 1), 215738f66d3SMichael Turquette PLL_RATE(720000000, 60, 1, 1), 216738f66d3SMichael Turquette PLL_RATE(732000000, 61, 1, 1), 217738f66d3SMichael Turquette PLL_RATE(744000000, 62, 1, 1), 218738f66d3SMichael Turquette PLL_RATE(768000000, 32, 1, 0), 219738f66d3SMichael Turquette PLL_RATE(792000000, 33, 1, 0), 220738f66d3SMichael Turquette PLL_RATE(816000000, 34, 1, 0), 221738f66d3SMichael Turquette PLL_RATE(840000000, 35, 1, 0), 222738f66d3SMichael Turquette PLL_RATE(864000000, 36, 1, 0), 223738f66d3SMichael Turquette PLL_RATE(888000000, 37, 1, 0), 224738f66d3SMichael Turquette PLL_RATE(912000000, 38, 1, 0), 225738f66d3SMichael Turquette PLL_RATE(936000000, 39, 1, 0), 226738f66d3SMichael Turquette PLL_RATE(960000000, 40, 1, 0), 227738f66d3SMichael Turquette PLL_RATE(984000000, 41, 1, 0), 228738f66d3SMichael Turquette PLL_RATE(1008000000, 42, 1, 0), 229738f66d3SMichael Turquette PLL_RATE(1032000000, 43, 1, 0), 230738f66d3SMichael Turquette PLL_RATE(1056000000, 44, 1, 0), 231738f66d3SMichael Turquette PLL_RATE(1080000000, 45, 1, 0), 232738f66d3SMichael Turquette PLL_RATE(1104000000, 46, 1, 0), 233738f66d3SMichael Turquette PLL_RATE(1128000000, 47, 1, 0), 234738f66d3SMichael Turquette PLL_RATE(1152000000, 48, 1, 0), 235738f66d3SMichael Turquette PLL_RATE(1176000000, 49, 1, 0), 236738f66d3SMichael Turquette PLL_RATE(1200000000, 50, 1, 0), 237738f66d3SMichael Turquette PLL_RATE(1224000000, 51, 1, 0), 238738f66d3SMichael Turquette PLL_RATE(1248000000, 52, 1, 0), 239738f66d3SMichael Turquette PLL_RATE(1272000000, 53, 1, 0), 240738f66d3SMichael Turquette PLL_RATE(1296000000, 54, 1, 0), 241738f66d3SMichael Turquette PLL_RATE(1320000000, 55, 1, 0), 242738f66d3SMichael Turquette PLL_RATE(1344000000, 56, 1, 0), 243738f66d3SMichael Turquette PLL_RATE(1368000000, 57, 1, 0), 244738f66d3SMichael Turquette PLL_RATE(1392000000, 58, 1, 0), 245738f66d3SMichael Turquette PLL_RATE(1416000000, 59, 1, 0), 246738f66d3SMichael Turquette PLL_RATE(1440000000, 60, 1, 0), 247738f66d3SMichael Turquette PLL_RATE(1464000000, 61, 1, 0), 248738f66d3SMichael Turquette PLL_RATE(1488000000, 62, 1, 0), 249738f66d3SMichael Turquette { /* sentinel */ }, 250738f66d3SMichael Turquette }; 251738f66d3SMichael Turquette 2520d48fc55SNeil Armstrong static const struct pll_rate_table gxl_gp0_pll_rate_table[] = { 2530d48fc55SNeil Armstrong PLL_RATE(504000000, 42, 1, 1), 2540d48fc55SNeil Armstrong PLL_RATE(516000000, 43, 1, 1), 2550d48fc55SNeil Armstrong PLL_RATE(528000000, 44, 1, 1), 2560d48fc55SNeil Armstrong PLL_RATE(540000000, 45, 1, 1), 2570d48fc55SNeil Armstrong PLL_RATE(552000000, 46, 1, 1), 2580d48fc55SNeil Armstrong PLL_RATE(564000000, 47, 1, 1), 2590d48fc55SNeil Armstrong PLL_RATE(576000000, 48, 1, 1), 2600d48fc55SNeil Armstrong PLL_RATE(588000000, 49, 1, 1), 2610d48fc55SNeil Armstrong PLL_RATE(600000000, 50, 1, 1), 2620d48fc55SNeil Armstrong PLL_RATE(612000000, 51, 1, 1), 2630d48fc55SNeil Armstrong PLL_RATE(624000000, 52, 1, 1), 2640d48fc55SNeil Armstrong PLL_RATE(636000000, 53, 1, 1), 2650d48fc55SNeil Armstrong PLL_RATE(648000000, 54, 1, 1), 2660d48fc55SNeil Armstrong PLL_RATE(660000000, 55, 1, 1), 2670d48fc55SNeil Armstrong PLL_RATE(672000000, 56, 1, 1), 2680d48fc55SNeil Armstrong PLL_RATE(684000000, 57, 1, 1), 2690d48fc55SNeil Armstrong PLL_RATE(696000000, 58, 1, 1), 2700d48fc55SNeil Armstrong PLL_RATE(708000000, 59, 1, 1), 2710d48fc55SNeil Armstrong PLL_RATE(720000000, 60, 1, 1), 2720d48fc55SNeil Armstrong PLL_RATE(732000000, 61, 1, 1), 2730d48fc55SNeil Armstrong PLL_RATE(744000000, 62, 1, 1), 2740d48fc55SNeil Armstrong PLL_RATE(756000000, 63, 1, 1), 2750d48fc55SNeil Armstrong PLL_RATE(768000000, 64, 1, 1), 2760d48fc55SNeil Armstrong PLL_RATE(780000000, 65, 1, 1), 2770d48fc55SNeil Armstrong PLL_RATE(792000000, 66, 1, 1), 2780d48fc55SNeil Armstrong { /* sentinel */ }, 2790d48fc55SNeil Armstrong }; 2800d48fc55SNeil Armstrong 281738f66d3SMichael Turquette static const struct clk_div_table cpu_div_table[] = { 282738f66d3SMichael Turquette { .val = 1, .div = 1 }, 283738f66d3SMichael Turquette { .val = 2, .div = 2 }, 284738f66d3SMichael Turquette { .val = 3, .div = 3 }, 285738f66d3SMichael Turquette { .val = 2, .div = 4 }, 286738f66d3SMichael Turquette { .val = 3, .div = 6 }, 287738f66d3SMichael Turquette { .val = 4, .div = 8 }, 288738f66d3SMichael Turquette { .val = 5, .div = 10 }, 289738f66d3SMichael Turquette { .val = 6, .div = 12 }, 290738f66d3SMichael Turquette { .val = 7, .div = 14 }, 291738f66d3SMichael Turquette { .val = 8, .div = 16 }, 292738f66d3SMichael Turquette { /* sentinel */ }, 293738f66d3SMichael Turquette }; 294738f66d3SMichael Turquette 295738f66d3SMichael Turquette static struct meson_clk_pll gxbb_fixed_pll = { 296738f66d3SMichael Turquette .m = { 297738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL, 298738f66d3SMichael Turquette .shift = 0, 299738f66d3SMichael Turquette .width = 9, 300738f66d3SMichael Turquette }, 301738f66d3SMichael Turquette .n = { 302738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL, 303738f66d3SMichael Turquette .shift = 9, 304738f66d3SMichael Turquette .width = 5, 305738f66d3SMichael Turquette }, 306738f66d3SMichael Turquette .od = { 307738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL, 308738f66d3SMichael Turquette .shift = 16, 309738f66d3SMichael Turquette .width = 2, 310738f66d3SMichael Turquette }, 311738f66d3SMichael Turquette .lock = &clk_lock, 312738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 313738f66d3SMichael Turquette .name = "fixed_pll", 314738f66d3SMichael Turquette .ops = &meson_clk_pll_ro_ops, 315738f66d3SMichael Turquette .parent_names = (const char *[]){ "xtal" }, 316738f66d3SMichael Turquette .num_parents = 1, 317738f66d3SMichael Turquette .flags = CLK_GET_RATE_NOCACHE, 318738f66d3SMichael Turquette }, 319738f66d3SMichael Turquette }; 320738f66d3SMichael Turquette 321738f66d3SMichael Turquette static struct meson_clk_pll gxbb_hdmi_pll = { 322738f66d3SMichael Turquette .m = { 323738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL, 324738f66d3SMichael Turquette .shift = 0, 325738f66d3SMichael Turquette .width = 9, 326738f66d3SMichael Turquette }, 327738f66d3SMichael Turquette .n = { 328738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL, 329738f66d3SMichael Turquette .shift = 9, 330738f66d3SMichael Turquette .width = 5, 331738f66d3SMichael Turquette }, 332738f66d3SMichael Turquette .frac = { 333738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL2, 334738f66d3SMichael Turquette .shift = 0, 335738f66d3SMichael Turquette .width = 12, 336738f66d3SMichael Turquette }, 337738f66d3SMichael Turquette .od = { 338738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL2, 339738f66d3SMichael Turquette .shift = 16, 340738f66d3SMichael Turquette .width = 2, 341738f66d3SMichael Turquette }, 342738f66d3SMichael Turquette .od2 = { 343738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL2, 344738f66d3SMichael Turquette .shift = 22, 345738f66d3SMichael Turquette .width = 2, 346738f66d3SMichael Turquette }, 347738f66d3SMichael Turquette .lock = &clk_lock, 348738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 349738f66d3SMichael Turquette .name = "hdmi_pll", 350738f66d3SMichael Turquette .ops = &meson_clk_pll_ro_ops, 351738f66d3SMichael Turquette .parent_names = (const char *[]){ "xtal" }, 352738f66d3SMichael Turquette .num_parents = 1, 353738f66d3SMichael Turquette .flags = CLK_GET_RATE_NOCACHE, 354738f66d3SMichael Turquette }, 355738f66d3SMichael Turquette }; 356738f66d3SMichael Turquette 357738f66d3SMichael Turquette static struct meson_clk_pll gxbb_sys_pll = { 358738f66d3SMichael Turquette .m = { 359738f66d3SMichael Turquette .reg_off = HHI_SYS_PLL_CNTL, 360738f66d3SMichael Turquette .shift = 0, 361738f66d3SMichael Turquette .width = 9, 362738f66d3SMichael Turquette }, 363738f66d3SMichael Turquette .n = { 364738f66d3SMichael Turquette .reg_off = HHI_SYS_PLL_CNTL, 365738f66d3SMichael Turquette .shift = 9, 366738f66d3SMichael Turquette .width = 5, 367738f66d3SMichael Turquette }, 368738f66d3SMichael Turquette .od = { 369738f66d3SMichael Turquette .reg_off = HHI_SYS_PLL_CNTL, 370738f66d3SMichael Turquette .shift = 10, 371738f66d3SMichael Turquette .width = 2, 372738f66d3SMichael Turquette }, 373738f66d3SMichael Turquette .rate_table = sys_pll_rate_table, 374738f66d3SMichael Turquette .rate_count = ARRAY_SIZE(sys_pll_rate_table), 375738f66d3SMichael Turquette .lock = &clk_lock, 376738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 377738f66d3SMichael Turquette .name = "sys_pll", 378738f66d3SMichael Turquette .ops = &meson_clk_pll_ro_ops, 379738f66d3SMichael Turquette .parent_names = (const char *[]){ "xtal" }, 380738f66d3SMichael Turquette .num_parents = 1, 381738f66d3SMichael Turquette .flags = CLK_GET_RATE_NOCACHE, 382738f66d3SMichael Turquette }, 383738f66d3SMichael Turquette }; 384738f66d3SMichael Turquette 385e194401cSNeil Armstrong struct pll_params_table gxbb_gp0_params_table[] = { 386e194401cSNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL, 0x6a000228), 387e194401cSNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL2, 0x69c80000), 388e194401cSNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a5590c4), 389e194401cSNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL4, 0x0000500d), 390e194401cSNeil Armstrong }; 391e194401cSNeil Armstrong 392738f66d3SMichael Turquette static struct meson_clk_pll gxbb_gp0_pll = { 393738f66d3SMichael Turquette .m = { 394738f66d3SMichael Turquette .reg_off = HHI_GP0_PLL_CNTL, 395738f66d3SMichael Turquette .shift = 0, 396738f66d3SMichael Turquette .width = 9, 397738f66d3SMichael Turquette }, 398738f66d3SMichael Turquette .n = { 399738f66d3SMichael Turquette .reg_off = HHI_GP0_PLL_CNTL, 400738f66d3SMichael Turquette .shift = 9, 401738f66d3SMichael Turquette .width = 5, 402738f66d3SMichael Turquette }, 403738f66d3SMichael Turquette .od = { 404738f66d3SMichael Turquette .reg_off = HHI_GP0_PLL_CNTL, 405738f66d3SMichael Turquette .shift = 16, 406738f66d3SMichael Turquette .width = 2, 407738f66d3SMichael Turquette }, 408e194401cSNeil Armstrong .params = { 409e194401cSNeil Armstrong .params_table = gxbb_gp0_params_table, 410e194401cSNeil Armstrong .params_count = ARRAY_SIZE(gxbb_gp0_params_table), 411e194401cSNeil Armstrong .no_init_reset = true, 412e194401cSNeil Armstrong .clear_reset_for_lock = true, 413e194401cSNeil Armstrong }, 4140d48fc55SNeil Armstrong .rate_table = gxbb_gp0_pll_rate_table, 4150d48fc55SNeil Armstrong .rate_count = ARRAY_SIZE(gxbb_gp0_pll_rate_table), 4160d48fc55SNeil Armstrong .lock = &clk_lock, 4170d48fc55SNeil Armstrong .hw.init = &(struct clk_init_data){ 4180d48fc55SNeil Armstrong .name = "gp0_pll", 4190d48fc55SNeil Armstrong .ops = &meson_clk_pll_ops, 4200d48fc55SNeil Armstrong .parent_names = (const char *[]){ "xtal" }, 4210d48fc55SNeil Armstrong .num_parents = 1, 4220d48fc55SNeil Armstrong .flags = CLK_GET_RATE_NOCACHE, 4230d48fc55SNeil Armstrong }, 4240d48fc55SNeil Armstrong }; 4250d48fc55SNeil Armstrong 4260d48fc55SNeil Armstrong struct pll_params_table gxl_gp0_params_table[] = { 4270d48fc55SNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250), 4280d48fc55SNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000), 4290d48fc55SNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be), 4300d48fc55SNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288), 4310d48fc55SNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d), 4320d48fc55SNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000), 4330d48fc55SNeil Armstrong }; 4340d48fc55SNeil Armstrong 4350d48fc55SNeil Armstrong static struct meson_clk_pll gxl_gp0_pll = { 4360d48fc55SNeil Armstrong .m = { 4370d48fc55SNeil Armstrong .reg_off = HHI_GP0_PLL_CNTL, 4380d48fc55SNeil Armstrong .shift = 0, 4390d48fc55SNeil Armstrong .width = 9, 4400d48fc55SNeil Armstrong }, 4410d48fc55SNeil Armstrong .n = { 4420d48fc55SNeil Armstrong .reg_off = HHI_GP0_PLL_CNTL, 4430d48fc55SNeil Armstrong .shift = 9, 4440d48fc55SNeil Armstrong .width = 5, 4450d48fc55SNeil Armstrong }, 4460d48fc55SNeil Armstrong .od = { 4470d48fc55SNeil Armstrong .reg_off = HHI_GP0_PLL_CNTL, 4480d48fc55SNeil Armstrong .shift = 16, 4490d48fc55SNeil Armstrong .width = 2, 4500d48fc55SNeil Armstrong }, 4510d48fc55SNeil Armstrong .params = { 4520d48fc55SNeil Armstrong .params_table = gxl_gp0_params_table, 4530d48fc55SNeil Armstrong .params_count = ARRAY_SIZE(gxl_gp0_params_table), 4540d48fc55SNeil Armstrong .no_init_reset = true, 4550d48fc55SNeil Armstrong .reset_lock_loop = true, 4560d48fc55SNeil Armstrong }, 4570d48fc55SNeil Armstrong .rate_table = gxl_gp0_pll_rate_table, 4580d48fc55SNeil Armstrong .rate_count = ARRAY_SIZE(gxl_gp0_pll_rate_table), 459738f66d3SMichael Turquette .lock = &clk_lock, 460738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 461738f66d3SMichael Turquette .name = "gp0_pll", 462738f66d3SMichael Turquette .ops = &meson_clk_pll_ops, 463738f66d3SMichael Turquette .parent_names = (const char *[]){ "xtal" }, 464738f66d3SMichael Turquette .num_parents = 1, 465738f66d3SMichael Turquette .flags = CLK_GET_RATE_NOCACHE, 466738f66d3SMichael Turquette }, 467738f66d3SMichael Turquette }; 468738f66d3SMichael Turquette 469738f66d3SMichael Turquette static struct clk_fixed_factor gxbb_fclk_div2 = { 470738f66d3SMichael Turquette .mult = 1, 471738f66d3SMichael Turquette .div = 2, 472738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 473738f66d3SMichael Turquette .name = "fclk_div2", 474738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 475738f66d3SMichael Turquette .parent_names = (const char *[]){ "fixed_pll" }, 476738f66d3SMichael Turquette .num_parents = 1, 477738f66d3SMichael Turquette }, 478738f66d3SMichael Turquette }; 479738f66d3SMichael Turquette 480738f66d3SMichael Turquette static struct clk_fixed_factor gxbb_fclk_div3 = { 481738f66d3SMichael Turquette .mult = 1, 482738f66d3SMichael Turquette .div = 3, 483738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 484738f66d3SMichael Turquette .name = "fclk_div3", 485738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 486738f66d3SMichael Turquette .parent_names = (const char *[]){ "fixed_pll" }, 487738f66d3SMichael Turquette .num_parents = 1, 488738f66d3SMichael Turquette }, 489738f66d3SMichael Turquette }; 490738f66d3SMichael Turquette 491738f66d3SMichael Turquette static struct clk_fixed_factor gxbb_fclk_div4 = { 492738f66d3SMichael Turquette .mult = 1, 493738f66d3SMichael Turquette .div = 4, 494738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 495738f66d3SMichael Turquette .name = "fclk_div4", 496738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 497738f66d3SMichael Turquette .parent_names = (const char *[]){ "fixed_pll" }, 498738f66d3SMichael Turquette .num_parents = 1, 499738f66d3SMichael Turquette }, 500738f66d3SMichael Turquette }; 501738f66d3SMichael Turquette 502738f66d3SMichael Turquette static struct clk_fixed_factor gxbb_fclk_div5 = { 503738f66d3SMichael Turquette .mult = 1, 504738f66d3SMichael Turquette .div = 5, 505738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 506738f66d3SMichael Turquette .name = "fclk_div5", 507738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 508738f66d3SMichael Turquette .parent_names = (const char *[]){ "fixed_pll" }, 509738f66d3SMichael Turquette .num_parents = 1, 510738f66d3SMichael Turquette }, 511738f66d3SMichael Turquette }; 512738f66d3SMichael Turquette 513738f66d3SMichael Turquette static struct clk_fixed_factor gxbb_fclk_div7 = { 514738f66d3SMichael Turquette .mult = 1, 515738f66d3SMichael Turquette .div = 7, 516738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 517738f66d3SMichael Turquette .name = "fclk_div7", 518738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 519738f66d3SMichael Turquette .parent_names = (const char *[]){ "fixed_pll" }, 520738f66d3SMichael Turquette .num_parents = 1, 521738f66d3SMichael Turquette }, 522738f66d3SMichael Turquette }; 523738f66d3SMichael Turquette 524738f66d3SMichael Turquette static struct meson_clk_mpll gxbb_mpll0 = { 525738f66d3SMichael Turquette .sdm = { 526738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL7, 527738f66d3SMichael Turquette .shift = 0, 528738f66d3SMichael Turquette .width = 14, 529738f66d3SMichael Turquette }, 530007e6e5cSJerome Brunet .sdm_en = { 531007e6e5cSJerome Brunet .reg_off = HHI_MPLL_CNTL7, 532007e6e5cSJerome Brunet .shift = 15, 533007e6e5cSJerome Brunet .width = 1, 534007e6e5cSJerome Brunet }, 535738f66d3SMichael Turquette .n2 = { 536738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL7, 537738f66d3SMichael Turquette .shift = 16, 538738f66d3SMichael Turquette .width = 9, 539738f66d3SMichael Turquette }, 540007e6e5cSJerome Brunet .en = { 541007e6e5cSJerome Brunet .reg_off = HHI_MPLL_CNTL7, 542007e6e5cSJerome Brunet .shift = 14, 543007e6e5cSJerome Brunet .width = 1, 544007e6e5cSJerome Brunet }, 545738f66d3SMichael Turquette .lock = &clk_lock, 546738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 547738f66d3SMichael Turquette .name = "mpll0", 54805b43aa2SJerome Brunet .ops = &meson_clk_mpll_ops, 549738f66d3SMichael Turquette .parent_names = (const char *[]){ "fixed_pll" }, 550738f66d3SMichael Turquette .num_parents = 1, 551738f66d3SMichael Turquette }, 552738f66d3SMichael Turquette }; 553738f66d3SMichael Turquette 554738f66d3SMichael Turquette static struct meson_clk_mpll gxbb_mpll1 = { 555738f66d3SMichael Turquette .sdm = { 556738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL8, 557738f66d3SMichael Turquette .shift = 0, 558738f66d3SMichael Turquette .width = 14, 559738f66d3SMichael Turquette }, 560007e6e5cSJerome Brunet .sdm_en = { 561007e6e5cSJerome Brunet .reg_off = HHI_MPLL_CNTL8, 562007e6e5cSJerome Brunet .shift = 15, 563007e6e5cSJerome Brunet .width = 1, 564007e6e5cSJerome Brunet }, 565738f66d3SMichael Turquette .n2 = { 566738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL8, 567738f66d3SMichael Turquette .shift = 16, 568738f66d3SMichael Turquette .width = 9, 569738f66d3SMichael Turquette }, 570007e6e5cSJerome Brunet .en = { 571007e6e5cSJerome Brunet .reg_off = HHI_MPLL_CNTL8, 572007e6e5cSJerome Brunet .shift = 14, 573007e6e5cSJerome Brunet .width = 1, 574007e6e5cSJerome Brunet }, 575738f66d3SMichael Turquette .lock = &clk_lock, 576738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 577738f66d3SMichael Turquette .name = "mpll1", 57805b43aa2SJerome Brunet .ops = &meson_clk_mpll_ops, 579738f66d3SMichael Turquette .parent_names = (const char *[]){ "fixed_pll" }, 580738f66d3SMichael Turquette .num_parents = 1, 581738f66d3SMichael Turquette }, 582738f66d3SMichael Turquette }; 583738f66d3SMichael Turquette 584738f66d3SMichael Turquette static struct meson_clk_mpll gxbb_mpll2 = { 585738f66d3SMichael Turquette .sdm = { 586738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL9, 587738f66d3SMichael Turquette .shift = 0, 588738f66d3SMichael Turquette .width = 14, 589738f66d3SMichael Turquette }, 590007e6e5cSJerome Brunet .sdm_en = { 591007e6e5cSJerome Brunet .reg_off = HHI_MPLL_CNTL9, 592007e6e5cSJerome Brunet .shift = 15, 593007e6e5cSJerome Brunet .width = 1, 594007e6e5cSJerome Brunet }, 595738f66d3SMichael Turquette .n2 = { 596738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL9, 597738f66d3SMichael Turquette .shift = 16, 598738f66d3SMichael Turquette .width = 9, 599738f66d3SMichael Turquette }, 600007e6e5cSJerome Brunet .en = { 601007e6e5cSJerome Brunet .reg_off = HHI_MPLL_CNTL9, 602007e6e5cSJerome Brunet .shift = 14, 603007e6e5cSJerome Brunet .width = 1, 604007e6e5cSJerome Brunet }, 605738f66d3SMichael Turquette .lock = &clk_lock, 606738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 607738f66d3SMichael Turquette .name = "mpll2", 60805b43aa2SJerome Brunet .ops = &meson_clk_mpll_ops, 609738f66d3SMichael Turquette .parent_names = (const char *[]){ "fixed_pll" }, 610738f66d3SMichael Turquette .num_parents = 1, 611738f66d3SMichael Turquette }, 612738f66d3SMichael Turquette }; 613738f66d3SMichael Turquette 614738f66d3SMichael Turquette /* 615738f66d3SMichael Turquette * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL 616738f66d3SMichael Turquette * post-dividers and should be modeled with their respective PLLs via the 617738f66d3SMichael Turquette * forthcoming coordinated clock rates feature 618738f66d3SMichael Turquette */ 619738f66d3SMichael Turquette static struct meson_clk_cpu gxbb_cpu_clk = { 620738f66d3SMichael Turquette .reg_off = HHI_SYS_CPU_CLK_CNTL1, 621738f66d3SMichael Turquette .div_table = cpu_div_table, 622738f66d3SMichael Turquette .clk_nb.notifier_call = meson_clk_cpu_notifier_cb, 623738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 624738f66d3SMichael Turquette .name = "cpu_clk", 625738f66d3SMichael Turquette .ops = &meson_clk_cpu_ops, 626738f66d3SMichael Turquette .parent_names = (const char *[]){ "sys_pll" }, 627738f66d3SMichael Turquette .num_parents = 1, 628738f66d3SMichael Turquette }, 629738f66d3SMichael Turquette }; 630738f66d3SMichael Turquette 631738f66d3SMichael Turquette static u32 mux_table_clk81[] = { 6, 5, 7 }; 632738f66d3SMichael Turquette 633738f66d3SMichael Turquette static struct clk_mux gxbb_mpeg_clk_sel = { 634738f66d3SMichael Turquette .reg = (void *)HHI_MPEG_CLK_CNTL, 635738f66d3SMichael Turquette .mask = 0x7, 636738f66d3SMichael Turquette .shift = 12, 637738f66d3SMichael Turquette .flags = CLK_MUX_READ_ONLY, 638738f66d3SMichael Turquette .table = mux_table_clk81, 639738f66d3SMichael Turquette .lock = &clk_lock, 640738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 641738f66d3SMichael Turquette .name = "mpeg_clk_sel", 642738f66d3SMichael Turquette .ops = &clk_mux_ro_ops, 643738f66d3SMichael Turquette /* 644738f66d3SMichael Turquette * FIXME bits 14:12 selects from 8 possible parents: 645738f66d3SMichael Turquette * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 646738f66d3SMichael Turquette * fclk_div4, fclk_div3, fclk_div5 647738f66d3SMichael Turquette */ 648738f66d3SMichael Turquette .parent_names = (const char *[]){ "fclk_div3", "fclk_div4", 649738f66d3SMichael Turquette "fclk_div5" }, 650738f66d3SMichael Turquette .num_parents = 3, 651738f66d3SMichael Turquette .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED), 652738f66d3SMichael Turquette }, 653738f66d3SMichael Turquette }; 654738f66d3SMichael Turquette 655738f66d3SMichael Turquette static struct clk_divider gxbb_mpeg_clk_div = { 656738f66d3SMichael Turquette .reg = (void *)HHI_MPEG_CLK_CNTL, 657738f66d3SMichael Turquette .shift = 0, 658738f66d3SMichael Turquette .width = 7, 659738f66d3SMichael Turquette .lock = &clk_lock, 660738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 661738f66d3SMichael Turquette .name = "mpeg_clk_div", 662738f66d3SMichael Turquette .ops = &clk_divider_ops, 663738f66d3SMichael Turquette .parent_names = (const char *[]){ "mpeg_clk_sel" }, 664738f66d3SMichael Turquette .num_parents = 1, 665738f66d3SMichael Turquette .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), 666738f66d3SMichael Turquette }, 667738f66d3SMichael Turquette }; 668738f66d3SMichael Turquette 669738f66d3SMichael Turquette /* the mother of dragons^W gates */ 670738f66d3SMichael Turquette static struct clk_gate gxbb_clk81 = { 671738f66d3SMichael Turquette .reg = (void *)HHI_MPEG_CLK_CNTL, 672738f66d3SMichael Turquette .bit_idx = 7, 673738f66d3SMichael Turquette .lock = &clk_lock, 674738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 675738f66d3SMichael Turquette .name = "clk81", 676738f66d3SMichael Turquette .ops = &clk_gate_ops, 677738f66d3SMichael Turquette .parent_names = (const char *[]){ "mpeg_clk_div" }, 678738f66d3SMichael Turquette .num_parents = 1, 679738f66d3SMichael Turquette .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL), 680738f66d3SMichael Turquette }, 681738f66d3SMichael Turquette }; 682738f66d3SMichael Turquette 68333d0fcdfSMartin Blumenstingl static struct clk_mux gxbb_sar_adc_clk_sel = { 68433d0fcdfSMartin Blumenstingl .reg = (void *)HHI_SAR_CLK_CNTL, 68533d0fcdfSMartin Blumenstingl .mask = 0x3, 68633d0fcdfSMartin Blumenstingl .shift = 9, 68733d0fcdfSMartin Blumenstingl .lock = &clk_lock, 68833d0fcdfSMartin Blumenstingl .hw.init = &(struct clk_init_data){ 68933d0fcdfSMartin Blumenstingl .name = "sar_adc_clk_sel", 69033d0fcdfSMartin Blumenstingl .ops = &clk_mux_ops, 69133d0fcdfSMartin Blumenstingl /* NOTE: The datasheet doesn't list the parents for bit 10 */ 69233d0fcdfSMartin Blumenstingl .parent_names = (const char *[]){ "xtal", "clk81", }, 69333d0fcdfSMartin Blumenstingl .num_parents = 2, 69433d0fcdfSMartin Blumenstingl }, 69533d0fcdfSMartin Blumenstingl }; 69633d0fcdfSMartin Blumenstingl 69733d0fcdfSMartin Blumenstingl static struct clk_divider gxbb_sar_adc_clk_div = { 69833d0fcdfSMartin Blumenstingl .reg = (void *)HHI_SAR_CLK_CNTL, 69933d0fcdfSMartin Blumenstingl .shift = 0, 70033d0fcdfSMartin Blumenstingl .width = 8, 70133d0fcdfSMartin Blumenstingl .lock = &clk_lock, 70233d0fcdfSMartin Blumenstingl .hw.init = &(struct clk_init_data){ 70333d0fcdfSMartin Blumenstingl .name = "sar_adc_clk_div", 70433d0fcdfSMartin Blumenstingl .ops = &clk_divider_ops, 70533d0fcdfSMartin Blumenstingl .parent_names = (const char *[]){ "sar_adc_clk_sel" }, 70633d0fcdfSMartin Blumenstingl .num_parents = 1, 70733d0fcdfSMartin Blumenstingl }, 70833d0fcdfSMartin Blumenstingl }; 70933d0fcdfSMartin Blumenstingl 71033d0fcdfSMartin Blumenstingl static struct clk_gate gxbb_sar_adc_clk = { 71133d0fcdfSMartin Blumenstingl .reg = (void *)HHI_SAR_CLK_CNTL, 71233d0fcdfSMartin Blumenstingl .bit_idx = 8, 71333d0fcdfSMartin Blumenstingl .lock = &clk_lock, 71433d0fcdfSMartin Blumenstingl .hw.init = &(struct clk_init_data){ 71533d0fcdfSMartin Blumenstingl .name = "sar_adc_clk", 71633d0fcdfSMartin Blumenstingl .ops = &clk_gate_ops, 71733d0fcdfSMartin Blumenstingl .parent_names = (const char *[]){ "sar_adc_clk_div" }, 71833d0fcdfSMartin Blumenstingl .num_parents = 1, 71933d0fcdfSMartin Blumenstingl .flags = CLK_SET_RATE_PARENT, 72033d0fcdfSMartin Blumenstingl }, 72133d0fcdfSMartin Blumenstingl }; 72233d0fcdfSMartin Blumenstingl 723fac9a55bSNeil Armstrong /* 724fac9a55bSNeil Armstrong * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 725fac9a55bSNeil Armstrong * muxed by a glitch-free switch. 726fac9a55bSNeil Armstrong */ 727fac9a55bSNeil Armstrong 728fac9a55bSNeil Armstrong static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7}; 729fac9a55bSNeil Armstrong static const char *gxbb_mali_0_1_parent_names[] = { 730fac9a55bSNeil Armstrong "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7", 731fac9a55bSNeil Armstrong "fclk_div4", "fclk_div3", "fclk_div5" 732fac9a55bSNeil Armstrong }; 733fac9a55bSNeil Armstrong 734fac9a55bSNeil Armstrong static struct clk_mux gxbb_mali_0_sel = { 735fac9a55bSNeil Armstrong .reg = (void *)HHI_MALI_CLK_CNTL, 736fac9a55bSNeil Armstrong .mask = 0x7, 737fac9a55bSNeil Armstrong .shift = 9, 738fac9a55bSNeil Armstrong .table = mux_table_mali_0_1, 739fac9a55bSNeil Armstrong .lock = &clk_lock, 740fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 741fac9a55bSNeil Armstrong .name = "mali_0_sel", 742fac9a55bSNeil Armstrong .ops = &clk_mux_ops, 743fac9a55bSNeil Armstrong /* 744fac9a55bSNeil Armstrong * bits 10:9 selects from 8 possible parents: 745fac9a55bSNeil Armstrong * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 746fac9a55bSNeil Armstrong * fclk_div4, fclk_div3, fclk_div5 747fac9a55bSNeil Armstrong */ 748fac9a55bSNeil Armstrong .parent_names = gxbb_mali_0_1_parent_names, 749fac9a55bSNeil Armstrong .num_parents = 8, 750fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 751fac9a55bSNeil Armstrong }, 752fac9a55bSNeil Armstrong }; 753fac9a55bSNeil Armstrong 754fac9a55bSNeil Armstrong static struct clk_divider gxbb_mali_0_div = { 755fac9a55bSNeil Armstrong .reg = (void *)HHI_MALI_CLK_CNTL, 756fac9a55bSNeil Armstrong .shift = 0, 757fac9a55bSNeil Armstrong .width = 7, 758fac9a55bSNeil Armstrong .lock = &clk_lock, 759fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 760fac9a55bSNeil Armstrong .name = "mali_0_div", 761fac9a55bSNeil Armstrong .ops = &clk_divider_ops, 762fac9a55bSNeil Armstrong .parent_names = (const char *[]){ "mali_0_sel" }, 763fac9a55bSNeil Armstrong .num_parents = 1, 764fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 765fac9a55bSNeil Armstrong }, 766fac9a55bSNeil Armstrong }; 767fac9a55bSNeil Armstrong 768fac9a55bSNeil Armstrong static struct clk_gate gxbb_mali_0 = { 769fac9a55bSNeil Armstrong .reg = (void *)HHI_MALI_CLK_CNTL, 770fac9a55bSNeil Armstrong .bit_idx = 8, 771fac9a55bSNeil Armstrong .lock = &clk_lock, 772fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 773fac9a55bSNeil Armstrong .name = "mali_0", 774fac9a55bSNeil Armstrong .ops = &clk_gate_ops, 775fac9a55bSNeil Armstrong .parent_names = (const char *[]){ "mali_0_div" }, 776fac9a55bSNeil Armstrong .num_parents = 1, 777fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_PARENT, 778fac9a55bSNeil Armstrong }, 779fac9a55bSNeil Armstrong }; 780fac9a55bSNeil Armstrong 781fac9a55bSNeil Armstrong static struct clk_mux gxbb_mali_1_sel = { 782fac9a55bSNeil Armstrong .reg = (void *)HHI_MALI_CLK_CNTL, 783fac9a55bSNeil Armstrong .mask = 0x7, 784fac9a55bSNeil Armstrong .shift = 25, 785fac9a55bSNeil Armstrong .table = mux_table_mali_0_1, 786fac9a55bSNeil Armstrong .lock = &clk_lock, 787fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 788fac9a55bSNeil Armstrong .name = "mali_1_sel", 789fac9a55bSNeil Armstrong .ops = &clk_mux_ops, 790fac9a55bSNeil Armstrong /* 791fac9a55bSNeil Armstrong * bits 10:9 selects from 8 possible parents: 792fac9a55bSNeil Armstrong * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 793fac9a55bSNeil Armstrong * fclk_div4, fclk_div3, fclk_div5 794fac9a55bSNeil Armstrong */ 795fac9a55bSNeil Armstrong .parent_names = gxbb_mali_0_1_parent_names, 796fac9a55bSNeil Armstrong .num_parents = 8, 797fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 798fac9a55bSNeil Armstrong }, 799fac9a55bSNeil Armstrong }; 800fac9a55bSNeil Armstrong 801fac9a55bSNeil Armstrong static struct clk_divider gxbb_mali_1_div = { 802fac9a55bSNeil Armstrong .reg = (void *)HHI_MALI_CLK_CNTL, 803fac9a55bSNeil Armstrong .shift = 16, 804fac9a55bSNeil Armstrong .width = 7, 805fac9a55bSNeil Armstrong .lock = &clk_lock, 806fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 807fac9a55bSNeil Armstrong .name = "mali_1_div", 808fac9a55bSNeil Armstrong .ops = &clk_divider_ops, 809fac9a55bSNeil Armstrong .parent_names = (const char *[]){ "mali_1_sel" }, 810fac9a55bSNeil Armstrong .num_parents = 1, 811fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 812fac9a55bSNeil Armstrong }, 813fac9a55bSNeil Armstrong }; 814fac9a55bSNeil Armstrong 815fac9a55bSNeil Armstrong static struct clk_gate gxbb_mali_1 = { 816fac9a55bSNeil Armstrong .reg = (void *)HHI_MALI_CLK_CNTL, 817fac9a55bSNeil Armstrong .bit_idx = 24, 818fac9a55bSNeil Armstrong .lock = &clk_lock, 819fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 820fac9a55bSNeil Armstrong .name = "mali_1", 821fac9a55bSNeil Armstrong .ops = &clk_gate_ops, 822fac9a55bSNeil Armstrong .parent_names = (const char *[]){ "mali_1_div" }, 823fac9a55bSNeil Armstrong .num_parents = 1, 824fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_PARENT, 825fac9a55bSNeil Armstrong }, 826fac9a55bSNeil Armstrong }; 827fac9a55bSNeil Armstrong 828fac9a55bSNeil Armstrong static u32 mux_table_mali[] = {0, 1}; 829fac9a55bSNeil Armstrong static const char *gxbb_mali_parent_names[] = { 830fac9a55bSNeil Armstrong "mali_0", "mali_1" 831fac9a55bSNeil Armstrong }; 832fac9a55bSNeil Armstrong 833fac9a55bSNeil Armstrong static struct clk_mux gxbb_mali = { 834fac9a55bSNeil Armstrong .reg = (void *)HHI_MALI_CLK_CNTL, 835fac9a55bSNeil Armstrong .mask = 1, 836fac9a55bSNeil Armstrong .shift = 31, 837fac9a55bSNeil Armstrong .table = mux_table_mali, 838fac9a55bSNeil Armstrong .lock = &clk_lock, 839fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 840fac9a55bSNeil Armstrong .name = "mali", 841fac9a55bSNeil Armstrong .ops = &clk_mux_ops, 842fac9a55bSNeil Armstrong .parent_names = gxbb_mali_parent_names, 843fac9a55bSNeil Armstrong .num_parents = 2, 844fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 845fac9a55bSNeil Armstrong }, 846fac9a55bSNeil Armstrong }; 847fac9a55bSNeil Armstrong 8484087bd4bSJerome Brunet static struct clk_mux gxbb_cts_amclk_sel = { 8494087bd4bSJerome Brunet .reg = (void *) HHI_AUD_CLK_CNTL, 8504087bd4bSJerome Brunet .mask = 0x3, 8514087bd4bSJerome Brunet .shift = 9, 8524087bd4bSJerome Brunet /* Default parent unknown (register reset value: 0) */ 8534087bd4bSJerome Brunet .table = (u32[]){ 1, 2, 3 }, 8544087bd4bSJerome Brunet .lock = &clk_lock, 8554087bd4bSJerome Brunet .hw.init = &(struct clk_init_data){ 8564087bd4bSJerome Brunet .name = "cts_amclk_sel", 8574087bd4bSJerome Brunet .ops = &clk_mux_ops, 8584087bd4bSJerome Brunet .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 8594087bd4bSJerome Brunet .num_parents = 3, 8604087bd4bSJerome Brunet .flags = CLK_SET_RATE_PARENT, 8614087bd4bSJerome Brunet }, 8624087bd4bSJerome Brunet }; 8634087bd4bSJerome Brunet 8644087bd4bSJerome Brunet static struct meson_clk_audio_divider gxbb_cts_amclk_div = { 8654087bd4bSJerome Brunet .div = { 8664087bd4bSJerome Brunet .reg_off = HHI_AUD_CLK_CNTL, 8674087bd4bSJerome Brunet .shift = 0, 8684087bd4bSJerome Brunet .width = 8, 8694087bd4bSJerome Brunet }, 8704087bd4bSJerome Brunet .lock = &clk_lock, 8714087bd4bSJerome Brunet .hw.init = &(struct clk_init_data){ 8724087bd4bSJerome Brunet .name = "cts_amclk_div", 8734087bd4bSJerome Brunet .ops = &meson_clk_audio_divider_ops, 8744087bd4bSJerome Brunet .parent_names = (const char *[]){ "cts_amclk_sel" }, 8754087bd4bSJerome Brunet .num_parents = 1, 8764087bd4bSJerome Brunet .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, 8774087bd4bSJerome Brunet }, 8784087bd4bSJerome Brunet }; 8794087bd4bSJerome Brunet 8804087bd4bSJerome Brunet static struct clk_gate gxbb_cts_amclk = { 8814087bd4bSJerome Brunet .reg = (void *) HHI_AUD_CLK_CNTL, 8824087bd4bSJerome Brunet .bit_idx = 8, 8834087bd4bSJerome Brunet .lock = &clk_lock, 8844087bd4bSJerome Brunet .hw.init = &(struct clk_init_data){ 8854087bd4bSJerome Brunet .name = "cts_amclk", 8864087bd4bSJerome Brunet .ops = &clk_gate_ops, 8874087bd4bSJerome Brunet .parent_names = (const char *[]){ "cts_amclk_div" }, 8884087bd4bSJerome Brunet .num_parents = 1, 8894087bd4bSJerome Brunet .flags = CLK_SET_RATE_PARENT, 8904087bd4bSJerome Brunet }, 8914087bd4bSJerome Brunet }; 8924087bd4bSJerome Brunet 8933c277c24SJerome Brunet static struct clk_mux gxbb_cts_mclk_i958_sel = { 8943c277c24SJerome Brunet .reg = (void *)HHI_AUD_CLK_CNTL2, 8953c277c24SJerome Brunet .mask = 0x3, 8963c277c24SJerome Brunet .shift = 25, 8973c277c24SJerome Brunet /* Default parent unknown (register reset value: 0) */ 8983c277c24SJerome Brunet .table = (u32[]){ 1, 2, 3 }, 8993c277c24SJerome Brunet .lock = &clk_lock, 9003c277c24SJerome Brunet .hw.init = &(struct clk_init_data){ 9013c277c24SJerome Brunet .name = "cts_mclk_i958_sel", 9023c277c24SJerome Brunet .ops = &clk_mux_ops, 9033c277c24SJerome Brunet .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 9043c277c24SJerome Brunet .num_parents = 3, 9053c277c24SJerome Brunet .flags = CLK_SET_RATE_PARENT, 9063c277c24SJerome Brunet }, 9073c277c24SJerome Brunet }; 9083c277c24SJerome Brunet 9093c277c24SJerome Brunet static struct clk_divider gxbb_cts_mclk_i958_div = { 9103c277c24SJerome Brunet .reg = (void *)HHI_AUD_CLK_CNTL2, 9113c277c24SJerome Brunet .shift = 16, 9123c277c24SJerome Brunet .width = 8, 9133c277c24SJerome Brunet .lock = &clk_lock, 9143c277c24SJerome Brunet .hw.init = &(struct clk_init_data){ 9153c277c24SJerome Brunet .name = "cts_mclk_i958_div", 9163c277c24SJerome Brunet .ops = &clk_divider_ops, 9173c277c24SJerome Brunet .parent_names = (const char *[]){ "cts_mclk_i958_sel" }, 9183c277c24SJerome Brunet .num_parents = 1, 9193c277c24SJerome Brunet .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, 9203c277c24SJerome Brunet }, 9213c277c24SJerome Brunet }; 9223c277c24SJerome Brunet 9233c277c24SJerome Brunet static struct clk_gate gxbb_cts_mclk_i958 = { 9243c277c24SJerome Brunet .reg = (void *)HHI_AUD_CLK_CNTL2, 9253c277c24SJerome Brunet .bit_idx = 24, 9263c277c24SJerome Brunet .lock = &clk_lock, 9273c277c24SJerome Brunet .hw.init = &(struct clk_init_data){ 9283c277c24SJerome Brunet .name = "cts_mclk_i958", 9293c277c24SJerome Brunet .ops = &clk_gate_ops, 9303c277c24SJerome Brunet .parent_names = (const char *[]){ "cts_mclk_i958_div" }, 9313c277c24SJerome Brunet .num_parents = 1, 9323c277c24SJerome Brunet .flags = CLK_SET_RATE_PARENT, 9333c277c24SJerome Brunet }, 9343c277c24SJerome Brunet }; 9353c277c24SJerome Brunet 9367eaa44f6SJerome Brunet static struct clk_mux gxbb_cts_i958 = { 9377eaa44f6SJerome Brunet .reg = (void *)HHI_AUD_CLK_CNTL2, 9387eaa44f6SJerome Brunet .mask = 0x1, 9397eaa44f6SJerome Brunet .shift = 27, 9407eaa44f6SJerome Brunet .lock = &clk_lock, 9417eaa44f6SJerome Brunet .hw.init = &(struct clk_init_data){ 9427eaa44f6SJerome Brunet .name = "cts_i958", 9437eaa44f6SJerome Brunet .ops = &clk_mux_ops, 9447eaa44f6SJerome Brunet .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" }, 9457eaa44f6SJerome Brunet .num_parents = 2, 9467eaa44f6SJerome Brunet /* 9477eaa44f6SJerome Brunet *The parent is specific to origin of the audio data. Let the 9487eaa44f6SJerome Brunet * consumer choose the appropriate parent 9497eaa44f6SJerome Brunet */ 9507eaa44f6SJerome Brunet .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 9517eaa44f6SJerome Brunet }, 9527eaa44f6SJerome Brunet }; 9537eaa44f6SJerome Brunet 954738f66d3SMichael Turquette /* Everything Else (EE) domain gates */ 9557ba64d82SAlexander Müller static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 9567ba64d82SAlexander Müller static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); 9577ba64d82SAlexander Müller static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5); 9587ba64d82SAlexander Müller static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6); 9597ba64d82SAlexander Müller static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7); 9607ba64d82SAlexander Müller static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8); 9617ba64d82SAlexander Müller static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9); 9627ba64d82SAlexander Müller static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10); 9637ba64d82SAlexander Müller static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11); 9647ba64d82SAlexander Müller static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12); 9657ba64d82SAlexander Müller static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13); 9667ba64d82SAlexander Müller static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14); 9677ba64d82SAlexander Müller static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15); 9687ba64d82SAlexander Müller static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16); 9697ba64d82SAlexander Müller static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17); 9707ba64d82SAlexander Müller static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18); 9717ba64d82SAlexander Müller static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19); 9727ba64d82SAlexander Müller static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); 9737ba64d82SAlexander Müller static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24); 9747ba64d82SAlexander Müller static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25); 9757ba64d82SAlexander Müller static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26); 9767ba64d82SAlexander Müller static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30); 977738f66d3SMichael Turquette 9787ba64d82SAlexander Müller static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2); 9797ba64d82SAlexander Müller static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3); 9807ba64d82SAlexander Müller static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4); 9817ba64d82SAlexander Müller static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6); 9827ba64d82SAlexander Müller static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7); 9837ba64d82SAlexander Müller static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8); 9847ba64d82SAlexander Müller static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9); 9857ba64d82SAlexander Müller static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10); 9867ba64d82SAlexander Müller static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11); 9877ba64d82SAlexander Müller static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12); 9887ba64d82SAlexander Müller static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13); 9897ba64d82SAlexander Müller static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14); 9907ba64d82SAlexander Müller static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15); 9917ba64d82SAlexander Müller static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16); 9927ba64d82SAlexander Müller static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20); 9937ba64d82SAlexander Müller static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21); 9947ba64d82SAlexander Müller static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22); 9957ba64d82SAlexander Müller static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23); 9967ba64d82SAlexander Müller static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24); 9977ba64d82SAlexander Müller static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25); 9987ba64d82SAlexander Müller static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26); 9997ba64d82SAlexander Müller static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28); 10007ba64d82SAlexander Müller static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29); 10017ba64d82SAlexander Müller static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30); 10027ba64d82SAlexander Müller static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31); 1003738f66d3SMichael Turquette 10047ba64d82SAlexander Müller static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1); 10057ba64d82SAlexander Müller static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 10067ba64d82SAlexander Müller static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); 10077ba64d82SAlexander Müller static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4); 10087ba64d82SAlexander Müller static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); 10097ba64d82SAlexander Müller static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); 10107ba64d82SAlexander Müller static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); 10117ba64d82SAlexander Müller static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12); 10127ba64d82SAlexander Müller static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15); 10137ba64d82SAlexander Müller static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22); 10147ba64d82SAlexander Müller static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); 10157ba64d82SAlexander Müller static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 10167ba64d82SAlexander Müller static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); 1017738f66d3SMichael Turquette 10187ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1); 10197ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2); 10207ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3); 10217ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4); 10227ba64d82SAlexander Müller static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8); 10237ba64d82SAlexander Müller static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9); 10247ba64d82SAlexander Müller static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10); 10257ba64d82SAlexander Müller static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14); 10267ba64d82SAlexander Müller static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16); 10277ba64d82SAlexander Müller static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20); 10287ba64d82SAlexander Müller static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21); 10297ba64d82SAlexander Müller static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22); 10307ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24); 10317ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25); 10327ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26); 10337ba64d82SAlexander Müller static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31); 1034738f66d3SMichael Turquette 1035738f66d3SMichael Turquette /* Always On (AO) domain gates */ 1036738f66d3SMichael Turquette 10377ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0); 10387ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1); 10397ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2); 10407ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3); 10417ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4); 1042738f66d3SMichael Turquette 1043738f66d3SMichael Turquette /* Array of all clocks provided by this provider */ 1044738f66d3SMichael Turquette 1045738f66d3SMichael Turquette static struct clk_hw_onecell_data gxbb_hw_onecell_data = { 1046738f66d3SMichael Turquette .hws = { 1047738f66d3SMichael Turquette [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 1048738f66d3SMichael Turquette [CLKID_CPUCLK] = &gxbb_cpu_clk.hw, 1049738f66d3SMichael Turquette [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 1050738f66d3SMichael Turquette [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 1051738f66d3SMichael Turquette [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 1052738f66d3SMichael Turquette [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 1053738f66d3SMichael Turquette [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 1054738f66d3SMichael Turquette [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 1055738f66d3SMichael Turquette [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 1056738f66d3SMichael Turquette [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 1057738f66d3SMichael Turquette [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 1058738f66d3SMichael Turquette [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 1059738f66d3SMichael Turquette [CLKID_CLK81] = &gxbb_clk81.hw, 1060738f66d3SMichael Turquette [CLKID_MPLL0] = &gxbb_mpll0.hw, 1061738f66d3SMichael Turquette [CLKID_MPLL1] = &gxbb_mpll1.hw, 1062738f66d3SMichael Turquette [CLKID_MPLL2] = &gxbb_mpll2.hw, 1063738f66d3SMichael Turquette [CLKID_DDR] = &gxbb_ddr.hw, 1064738f66d3SMichael Turquette [CLKID_DOS] = &gxbb_dos.hw, 1065738f66d3SMichael Turquette [CLKID_ISA] = &gxbb_isa.hw, 1066738f66d3SMichael Turquette [CLKID_PL301] = &gxbb_pl301.hw, 1067738f66d3SMichael Turquette [CLKID_PERIPHS] = &gxbb_periphs.hw, 1068738f66d3SMichael Turquette [CLKID_SPICC] = &gxbb_spicc.hw, 1069738f66d3SMichael Turquette [CLKID_I2C] = &gxbb_i2c.hw, 1070738f66d3SMichael Turquette [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 1071738f66d3SMichael Turquette [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 1072738f66d3SMichael Turquette [CLKID_RNG0] = &gxbb_rng0.hw, 1073738f66d3SMichael Turquette [CLKID_UART0] = &gxbb_uart0.hw, 1074738f66d3SMichael Turquette [CLKID_SDHC] = &gxbb_sdhc.hw, 1075738f66d3SMichael Turquette [CLKID_STREAM] = &gxbb_stream.hw, 1076738f66d3SMichael Turquette [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 1077738f66d3SMichael Turquette [CLKID_SDIO] = &gxbb_sdio.hw, 1078738f66d3SMichael Turquette [CLKID_ABUF] = &gxbb_abuf.hw, 1079738f66d3SMichael Turquette [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 1080738f66d3SMichael Turquette [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 1081738f66d3SMichael Turquette [CLKID_SPI] = &gxbb_spi.hw, 1082738f66d3SMichael Turquette [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 1083738f66d3SMichael Turquette [CLKID_ETH] = &gxbb_eth.hw, 1084738f66d3SMichael Turquette [CLKID_DEMUX] = &gxbb_demux.hw, 1085738f66d3SMichael Turquette [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 1086738f66d3SMichael Turquette [CLKID_IEC958] = &gxbb_iec958.hw, 1087738f66d3SMichael Turquette [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 1088738f66d3SMichael Turquette [CLKID_AMCLK] = &gxbb_amclk.hw, 1089738f66d3SMichael Turquette [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 1090738f66d3SMichael Turquette [CLKID_MIXER] = &gxbb_mixer.hw, 1091738f66d3SMichael Turquette [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 1092738f66d3SMichael Turquette [CLKID_ADC] = &gxbb_adc.hw, 1093738f66d3SMichael Turquette [CLKID_BLKMV] = &gxbb_blkmv.hw, 1094738f66d3SMichael Turquette [CLKID_AIU] = &gxbb_aiu.hw, 1095738f66d3SMichael Turquette [CLKID_UART1] = &gxbb_uart1.hw, 1096738f66d3SMichael Turquette [CLKID_G2D] = &gxbb_g2d.hw, 1097738f66d3SMichael Turquette [CLKID_USB0] = &gxbb_usb0.hw, 1098738f66d3SMichael Turquette [CLKID_USB1] = &gxbb_usb1.hw, 1099738f66d3SMichael Turquette [CLKID_RESET] = &gxbb_reset.hw, 1100738f66d3SMichael Turquette [CLKID_NAND] = &gxbb_nand.hw, 1101738f66d3SMichael Turquette [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 1102738f66d3SMichael Turquette [CLKID_USB] = &gxbb_usb.hw, 1103738f66d3SMichael Turquette [CLKID_VDIN1] = &gxbb_vdin1.hw, 1104738f66d3SMichael Turquette [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 1105738f66d3SMichael Turquette [CLKID_EFUSE] = &gxbb_efuse.hw, 1106738f66d3SMichael Turquette [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 1107738f66d3SMichael Turquette [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 1108738f66d3SMichael Turquette [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 1109738f66d3SMichael Turquette [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 1110738f66d3SMichael Turquette [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 1111738f66d3SMichael Turquette [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 1112738f66d3SMichael Turquette [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 1113738f66d3SMichael Turquette [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 1114738f66d3SMichael Turquette [CLKID_DVIN] = &gxbb_dvin.hw, 1115738f66d3SMichael Turquette [CLKID_UART2] = &gxbb_uart2.hw, 1116738f66d3SMichael Turquette [CLKID_SANA] = &gxbb_sana.hw, 1117738f66d3SMichael Turquette [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 1118738f66d3SMichael Turquette [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 1119738f66d3SMichael Turquette [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 1120738f66d3SMichael Turquette [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 1121738f66d3SMichael Turquette [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 1122738f66d3SMichael Turquette [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 1123738f66d3SMichael Turquette [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 1124738f66d3SMichael Turquette [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 1125738f66d3SMichael Turquette [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 1126738f66d3SMichael Turquette [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 1127738f66d3SMichael Turquette [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 1128738f66d3SMichael Turquette [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 1129738f66d3SMichael Turquette [CLKID_ENC480P] = &gxbb_enc480p.hw, 1130738f66d3SMichael Turquette [CLKID_RNG1] = &gxbb_rng1.hw, 1131738f66d3SMichael Turquette [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 1132738f66d3SMichael Turquette [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 1133738f66d3SMichael Turquette [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 1134738f66d3SMichael Turquette [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 1135738f66d3SMichael Turquette [CLKID_EDP] = &gxbb_edp.hw, 1136738f66d3SMichael Turquette [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 1137738f66d3SMichael Turquette [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 1138738f66d3SMichael Turquette [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 1139738f66d3SMichael Turquette [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 1140738f66d3SMichael Turquette [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 114133608dcdSKevin Hilman [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 114233608dcdSKevin Hilman [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 114333608dcdSKevin Hilman [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 114433d0fcdfSMartin Blumenstingl [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 114533d0fcdfSMartin Blumenstingl [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 114633d0fcdfSMartin Blumenstingl [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 1147fac9a55bSNeil Armstrong [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 1148fac9a55bSNeil Armstrong [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 1149fac9a55bSNeil Armstrong [CLKID_MALI_0] = &gxbb_mali_0.hw, 1150fac9a55bSNeil Armstrong [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 1151fac9a55bSNeil Armstrong [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 1152fac9a55bSNeil Armstrong [CLKID_MALI_1] = &gxbb_mali_1.hw, 1153fac9a55bSNeil Armstrong [CLKID_MALI] = &gxbb_mali.hw, 11544087bd4bSJerome Brunet [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 11554087bd4bSJerome Brunet [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 11564087bd4bSJerome Brunet [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 11573c277c24SJerome Brunet [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 11583c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 11593c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 11607eaa44f6SJerome Brunet [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 1161738f66d3SMichael Turquette }, 1162738f66d3SMichael Turquette .num = NR_CLKS, 1163738f66d3SMichael Turquette }; 1164738f66d3SMichael Turquette 11650d48fc55SNeil Armstrong static struct clk_hw_onecell_data gxl_hw_onecell_data = { 11660d48fc55SNeil Armstrong .hws = { 11670d48fc55SNeil Armstrong [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 11680d48fc55SNeil Armstrong [CLKID_CPUCLK] = &gxbb_cpu_clk.hw, 11690d48fc55SNeil Armstrong [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 11700d48fc55SNeil Armstrong [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 11710d48fc55SNeil Armstrong [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 11720d48fc55SNeil Armstrong [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 11730d48fc55SNeil Armstrong [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 11740d48fc55SNeil Armstrong [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 11750d48fc55SNeil Armstrong [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 11760d48fc55SNeil Armstrong [CLKID_GP0_PLL] = &gxl_gp0_pll.hw, 11770d48fc55SNeil Armstrong [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 11780d48fc55SNeil Armstrong [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 11790d48fc55SNeil Armstrong [CLKID_CLK81] = &gxbb_clk81.hw, 11800d48fc55SNeil Armstrong [CLKID_MPLL0] = &gxbb_mpll0.hw, 11810d48fc55SNeil Armstrong [CLKID_MPLL1] = &gxbb_mpll1.hw, 11820d48fc55SNeil Armstrong [CLKID_MPLL2] = &gxbb_mpll2.hw, 11830d48fc55SNeil Armstrong [CLKID_DDR] = &gxbb_ddr.hw, 11840d48fc55SNeil Armstrong [CLKID_DOS] = &gxbb_dos.hw, 11850d48fc55SNeil Armstrong [CLKID_ISA] = &gxbb_isa.hw, 11860d48fc55SNeil Armstrong [CLKID_PL301] = &gxbb_pl301.hw, 11870d48fc55SNeil Armstrong [CLKID_PERIPHS] = &gxbb_periphs.hw, 11880d48fc55SNeil Armstrong [CLKID_SPICC] = &gxbb_spicc.hw, 11890d48fc55SNeil Armstrong [CLKID_I2C] = &gxbb_i2c.hw, 11900d48fc55SNeil Armstrong [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 11910d48fc55SNeil Armstrong [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 11920d48fc55SNeil Armstrong [CLKID_RNG0] = &gxbb_rng0.hw, 11930d48fc55SNeil Armstrong [CLKID_UART0] = &gxbb_uart0.hw, 11940d48fc55SNeil Armstrong [CLKID_SDHC] = &gxbb_sdhc.hw, 11950d48fc55SNeil Armstrong [CLKID_STREAM] = &gxbb_stream.hw, 11960d48fc55SNeil Armstrong [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 11970d48fc55SNeil Armstrong [CLKID_SDIO] = &gxbb_sdio.hw, 11980d48fc55SNeil Armstrong [CLKID_ABUF] = &gxbb_abuf.hw, 11990d48fc55SNeil Armstrong [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 12000d48fc55SNeil Armstrong [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 12010d48fc55SNeil Armstrong [CLKID_SPI] = &gxbb_spi.hw, 12020d48fc55SNeil Armstrong [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 12030d48fc55SNeil Armstrong [CLKID_ETH] = &gxbb_eth.hw, 12040d48fc55SNeil Armstrong [CLKID_DEMUX] = &gxbb_demux.hw, 12050d48fc55SNeil Armstrong [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 12060d48fc55SNeil Armstrong [CLKID_IEC958] = &gxbb_iec958.hw, 12070d48fc55SNeil Armstrong [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 12080d48fc55SNeil Armstrong [CLKID_AMCLK] = &gxbb_amclk.hw, 12090d48fc55SNeil Armstrong [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 12100d48fc55SNeil Armstrong [CLKID_MIXER] = &gxbb_mixer.hw, 12110d48fc55SNeil Armstrong [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 12120d48fc55SNeil Armstrong [CLKID_ADC] = &gxbb_adc.hw, 12130d48fc55SNeil Armstrong [CLKID_BLKMV] = &gxbb_blkmv.hw, 12140d48fc55SNeil Armstrong [CLKID_AIU] = &gxbb_aiu.hw, 12150d48fc55SNeil Armstrong [CLKID_UART1] = &gxbb_uart1.hw, 12160d48fc55SNeil Armstrong [CLKID_G2D] = &gxbb_g2d.hw, 12170d48fc55SNeil Armstrong [CLKID_USB0] = &gxbb_usb0.hw, 12180d48fc55SNeil Armstrong [CLKID_USB1] = &gxbb_usb1.hw, 12190d48fc55SNeil Armstrong [CLKID_RESET] = &gxbb_reset.hw, 12200d48fc55SNeil Armstrong [CLKID_NAND] = &gxbb_nand.hw, 12210d48fc55SNeil Armstrong [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 12220d48fc55SNeil Armstrong [CLKID_USB] = &gxbb_usb.hw, 12230d48fc55SNeil Armstrong [CLKID_VDIN1] = &gxbb_vdin1.hw, 12240d48fc55SNeil Armstrong [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 12250d48fc55SNeil Armstrong [CLKID_EFUSE] = &gxbb_efuse.hw, 12260d48fc55SNeil Armstrong [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 12270d48fc55SNeil Armstrong [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 12280d48fc55SNeil Armstrong [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 12290d48fc55SNeil Armstrong [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 12300d48fc55SNeil Armstrong [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 12310d48fc55SNeil Armstrong [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 12320d48fc55SNeil Armstrong [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 12330d48fc55SNeil Armstrong [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 12340d48fc55SNeil Armstrong [CLKID_DVIN] = &gxbb_dvin.hw, 12350d48fc55SNeil Armstrong [CLKID_UART2] = &gxbb_uart2.hw, 12360d48fc55SNeil Armstrong [CLKID_SANA] = &gxbb_sana.hw, 12370d48fc55SNeil Armstrong [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 12380d48fc55SNeil Armstrong [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 12390d48fc55SNeil Armstrong [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 12400d48fc55SNeil Armstrong [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 12410d48fc55SNeil Armstrong [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 12420d48fc55SNeil Armstrong [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 12430d48fc55SNeil Armstrong [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 12440d48fc55SNeil Armstrong [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 12450d48fc55SNeil Armstrong [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 12460d48fc55SNeil Armstrong [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 12470d48fc55SNeil Armstrong [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 12480d48fc55SNeil Armstrong [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 12490d48fc55SNeil Armstrong [CLKID_ENC480P] = &gxbb_enc480p.hw, 12500d48fc55SNeil Armstrong [CLKID_RNG1] = &gxbb_rng1.hw, 12510d48fc55SNeil Armstrong [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 12520d48fc55SNeil Armstrong [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 12530d48fc55SNeil Armstrong [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 12540d48fc55SNeil Armstrong [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 12550d48fc55SNeil Armstrong [CLKID_EDP] = &gxbb_edp.hw, 12560d48fc55SNeil Armstrong [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 12570d48fc55SNeil Armstrong [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 12580d48fc55SNeil Armstrong [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 12590d48fc55SNeil Armstrong [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 12600d48fc55SNeil Armstrong [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 12610d48fc55SNeil Armstrong [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 12620d48fc55SNeil Armstrong [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 12630d48fc55SNeil Armstrong [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 12640d48fc55SNeil Armstrong [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 12650d48fc55SNeil Armstrong [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 12660d48fc55SNeil Armstrong [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 12670d48fc55SNeil Armstrong [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 12680d48fc55SNeil Armstrong [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 12690d48fc55SNeil Armstrong [CLKID_MALI_0] = &gxbb_mali_0.hw, 12700d48fc55SNeil Armstrong [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 12710d48fc55SNeil Armstrong [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 12720d48fc55SNeil Armstrong [CLKID_MALI_1] = &gxbb_mali_1.hw, 12730d48fc55SNeil Armstrong [CLKID_MALI] = &gxbb_mali.hw, 12744087bd4bSJerome Brunet [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 12754087bd4bSJerome Brunet [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 12764087bd4bSJerome Brunet [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 12773c277c24SJerome Brunet [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 12783c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 12793c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 12807eaa44f6SJerome Brunet [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 12810d48fc55SNeil Armstrong }, 12820d48fc55SNeil Armstrong .num = NR_CLKS, 12830d48fc55SNeil Armstrong }; 12840d48fc55SNeil Armstrong 1285738f66d3SMichael Turquette /* Convenience tables to populate base addresses in .probe */ 1286738f66d3SMichael Turquette 1287738f66d3SMichael Turquette static struct meson_clk_pll *const gxbb_clk_plls[] = { 1288738f66d3SMichael Turquette &gxbb_fixed_pll, 1289738f66d3SMichael Turquette &gxbb_hdmi_pll, 1290738f66d3SMichael Turquette &gxbb_sys_pll, 1291738f66d3SMichael Turquette &gxbb_gp0_pll, 1292738f66d3SMichael Turquette }; 1293738f66d3SMichael Turquette 12940d48fc55SNeil Armstrong static struct meson_clk_pll *const gxl_clk_plls[] = { 12950d48fc55SNeil Armstrong &gxbb_fixed_pll, 12960d48fc55SNeil Armstrong &gxbb_hdmi_pll, 12970d48fc55SNeil Armstrong &gxbb_sys_pll, 12980d48fc55SNeil Armstrong &gxl_gp0_pll, 12990d48fc55SNeil Armstrong }; 13000d48fc55SNeil Armstrong 1301738f66d3SMichael Turquette static struct meson_clk_mpll *const gxbb_clk_mplls[] = { 1302738f66d3SMichael Turquette &gxbb_mpll0, 1303738f66d3SMichael Turquette &gxbb_mpll1, 1304738f66d3SMichael Turquette &gxbb_mpll2, 1305738f66d3SMichael Turquette }; 1306738f66d3SMichael Turquette 1307f7e3a826SJerome Brunet static struct clk_gate *const gxbb_clk_gates[] = { 1308738f66d3SMichael Turquette &gxbb_clk81, 1309738f66d3SMichael Turquette &gxbb_ddr, 1310738f66d3SMichael Turquette &gxbb_dos, 1311738f66d3SMichael Turquette &gxbb_isa, 1312738f66d3SMichael Turquette &gxbb_pl301, 1313738f66d3SMichael Turquette &gxbb_periphs, 1314738f66d3SMichael Turquette &gxbb_spicc, 1315738f66d3SMichael Turquette &gxbb_i2c, 1316738f66d3SMichael Turquette &gxbb_sar_adc, 1317738f66d3SMichael Turquette &gxbb_smart_card, 1318738f66d3SMichael Turquette &gxbb_rng0, 1319738f66d3SMichael Turquette &gxbb_uart0, 1320738f66d3SMichael Turquette &gxbb_sdhc, 1321738f66d3SMichael Turquette &gxbb_stream, 1322738f66d3SMichael Turquette &gxbb_async_fifo, 1323738f66d3SMichael Turquette &gxbb_sdio, 1324738f66d3SMichael Turquette &gxbb_abuf, 1325738f66d3SMichael Turquette &gxbb_hiu_iface, 1326738f66d3SMichael Turquette &gxbb_assist_misc, 1327738f66d3SMichael Turquette &gxbb_spi, 1328738f66d3SMichael Turquette &gxbb_i2s_spdif, 1329738f66d3SMichael Turquette &gxbb_eth, 1330738f66d3SMichael Turquette &gxbb_demux, 1331738f66d3SMichael Turquette &gxbb_aiu_glue, 1332738f66d3SMichael Turquette &gxbb_iec958, 1333738f66d3SMichael Turquette &gxbb_i2s_out, 1334738f66d3SMichael Turquette &gxbb_amclk, 1335738f66d3SMichael Turquette &gxbb_aififo2, 1336738f66d3SMichael Turquette &gxbb_mixer, 1337738f66d3SMichael Turquette &gxbb_mixer_iface, 1338738f66d3SMichael Turquette &gxbb_adc, 1339738f66d3SMichael Turquette &gxbb_blkmv, 1340738f66d3SMichael Turquette &gxbb_aiu, 1341738f66d3SMichael Turquette &gxbb_uart1, 1342738f66d3SMichael Turquette &gxbb_g2d, 1343738f66d3SMichael Turquette &gxbb_usb0, 1344738f66d3SMichael Turquette &gxbb_usb1, 1345738f66d3SMichael Turquette &gxbb_reset, 1346738f66d3SMichael Turquette &gxbb_nand, 1347738f66d3SMichael Turquette &gxbb_dos_parser, 1348738f66d3SMichael Turquette &gxbb_usb, 1349738f66d3SMichael Turquette &gxbb_vdin1, 1350738f66d3SMichael Turquette &gxbb_ahb_arb0, 1351738f66d3SMichael Turquette &gxbb_efuse, 1352738f66d3SMichael Turquette &gxbb_boot_rom, 1353738f66d3SMichael Turquette &gxbb_ahb_data_bus, 1354738f66d3SMichael Turquette &gxbb_ahb_ctrl_bus, 1355738f66d3SMichael Turquette &gxbb_hdmi_intr_sync, 1356738f66d3SMichael Turquette &gxbb_hdmi_pclk, 1357738f66d3SMichael Turquette &gxbb_usb1_ddr_bridge, 1358738f66d3SMichael Turquette &gxbb_usb0_ddr_bridge, 1359738f66d3SMichael Turquette &gxbb_mmc_pclk, 1360738f66d3SMichael Turquette &gxbb_dvin, 1361738f66d3SMichael Turquette &gxbb_uart2, 1362738f66d3SMichael Turquette &gxbb_sana, 1363738f66d3SMichael Turquette &gxbb_vpu_intr, 1364738f66d3SMichael Turquette &gxbb_sec_ahb_ahb3_bridge, 1365738f66d3SMichael Turquette &gxbb_clk81_a53, 1366738f66d3SMichael Turquette &gxbb_vclk2_venci0, 1367738f66d3SMichael Turquette &gxbb_vclk2_venci1, 1368738f66d3SMichael Turquette &gxbb_vclk2_vencp0, 1369738f66d3SMichael Turquette &gxbb_vclk2_vencp1, 1370738f66d3SMichael Turquette &gxbb_gclk_venci_int0, 1371738f66d3SMichael Turquette &gxbb_gclk_vencp_int, 1372738f66d3SMichael Turquette &gxbb_dac_clk, 1373738f66d3SMichael Turquette &gxbb_aoclk_gate, 1374738f66d3SMichael Turquette &gxbb_iec958_gate, 1375738f66d3SMichael Turquette &gxbb_enc480p, 1376738f66d3SMichael Turquette &gxbb_rng1, 1377738f66d3SMichael Turquette &gxbb_gclk_venci_int1, 1378738f66d3SMichael Turquette &gxbb_vclk2_venclmcc, 1379738f66d3SMichael Turquette &gxbb_vclk2_vencl, 1380738f66d3SMichael Turquette &gxbb_vclk_other, 1381738f66d3SMichael Turquette &gxbb_edp, 1382738f66d3SMichael Turquette &gxbb_ao_media_cpu, 1383738f66d3SMichael Turquette &gxbb_ao_ahb_sram, 1384738f66d3SMichael Turquette &gxbb_ao_ahb_bus, 1385738f66d3SMichael Turquette &gxbb_ao_iface, 1386738f66d3SMichael Turquette &gxbb_ao_i2c, 138733608dcdSKevin Hilman &gxbb_emmc_a, 138833608dcdSKevin Hilman &gxbb_emmc_b, 138933608dcdSKevin Hilman &gxbb_emmc_c, 139033d0fcdfSMartin Blumenstingl &gxbb_sar_adc_clk, 1391fac9a55bSNeil Armstrong &gxbb_mali_0, 1392fac9a55bSNeil Armstrong &gxbb_mali_1, 13934087bd4bSJerome Brunet &gxbb_cts_amclk, 13943c277c24SJerome Brunet &gxbb_cts_mclk_i958, 1395738f66d3SMichael Turquette }; 1396738f66d3SMichael Turquette 1397b92332eeSJerome Brunet static struct clk_mux *const gxbb_clk_muxes[] = { 1398b92332eeSJerome Brunet &gxbb_mpeg_clk_sel, 1399b92332eeSJerome Brunet &gxbb_sar_adc_clk_sel, 1400fac9a55bSNeil Armstrong &gxbb_mali_0_sel, 1401fac9a55bSNeil Armstrong &gxbb_mali_1_sel, 1402fac9a55bSNeil Armstrong &gxbb_mali, 14034087bd4bSJerome Brunet &gxbb_cts_amclk_sel, 14043c277c24SJerome Brunet &gxbb_cts_mclk_i958_sel, 14057eaa44f6SJerome Brunet &gxbb_cts_i958, 1406b92332eeSJerome Brunet }; 1407b92332eeSJerome Brunet 1408b92332eeSJerome Brunet static struct clk_divider *const gxbb_clk_dividers[] = { 1409b92332eeSJerome Brunet &gxbb_mpeg_clk_div, 1410b92332eeSJerome Brunet &gxbb_sar_adc_clk_div, 1411fac9a55bSNeil Armstrong &gxbb_mali_0_div, 1412fac9a55bSNeil Armstrong &gxbb_mali_1_div, 14133c277c24SJerome Brunet &gxbb_cts_mclk_i958_div, 1414b92332eeSJerome Brunet }; 1415b92332eeSJerome Brunet 14164087bd4bSJerome Brunet static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = { 14174087bd4bSJerome Brunet &gxbb_cts_amclk_div, 14184087bd4bSJerome Brunet }; 14194087bd4bSJerome Brunet 14200d48fc55SNeil Armstrong struct clkc_data { 14210d48fc55SNeil Armstrong struct clk_gate *const *clk_gates; 14220d48fc55SNeil Armstrong unsigned int clk_gates_count; 14230d48fc55SNeil Armstrong struct meson_clk_mpll *const *clk_mplls; 14240d48fc55SNeil Armstrong unsigned int clk_mplls_count; 14250d48fc55SNeil Armstrong struct meson_clk_pll *const *clk_plls; 14260d48fc55SNeil Armstrong unsigned int clk_plls_count; 14270d48fc55SNeil Armstrong struct clk_mux *const *clk_muxes; 14280d48fc55SNeil Armstrong unsigned int clk_muxes_count; 14290d48fc55SNeil Armstrong struct clk_divider *const *clk_dividers; 14300d48fc55SNeil Armstrong unsigned int clk_dividers_count; 14314087bd4bSJerome Brunet struct meson_clk_audio_divider *const *clk_audio_dividers; 14324087bd4bSJerome Brunet unsigned int clk_audio_dividers_count; 14330d48fc55SNeil Armstrong struct meson_clk_cpu *cpu_clk; 14340d48fc55SNeil Armstrong struct clk_hw_onecell_data *hw_onecell_data; 14350d48fc55SNeil Armstrong }; 14360d48fc55SNeil Armstrong 14370d48fc55SNeil Armstrong static const struct clkc_data gxbb_clkc_data = { 14380d48fc55SNeil Armstrong .clk_gates = gxbb_clk_gates, 14390d48fc55SNeil Armstrong .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates), 14400d48fc55SNeil Armstrong .clk_mplls = gxbb_clk_mplls, 14410d48fc55SNeil Armstrong .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls), 14420d48fc55SNeil Armstrong .clk_plls = gxbb_clk_plls, 14430d48fc55SNeil Armstrong .clk_plls_count = ARRAY_SIZE(gxbb_clk_plls), 14440d48fc55SNeil Armstrong .clk_muxes = gxbb_clk_muxes, 14450d48fc55SNeil Armstrong .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes), 14460d48fc55SNeil Armstrong .clk_dividers = gxbb_clk_dividers, 14470d48fc55SNeil Armstrong .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), 14484087bd4bSJerome Brunet .clk_audio_dividers = gxbb_audio_dividers, 14494087bd4bSJerome Brunet .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), 14500d48fc55SNeil Armstrong .cpu_clk = &gxbb_cpu_clk, 14510d48fc55SNeil Armstrong .hw_onecell_data = &gxbb_hw_onecell_data, 14520d48fc55SNeil Armstrong }; 14530d48fc55SNeil Armstrong 14540d48fc55SNeil Armstrong static const struct clkc_data gxl_clkc_data = { 14550d48fc55SNeil Armstrong .clk_gates = gxbb_clk_gates, 14560d48fc55SNeil Armstrong .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates), 14570d48fc55SNeil Armstrong .clk_mplls = gxbb_clk_mplls, 14580d48fc55SNeil Armstrong .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls), 14590d48fc55SNeil Armstrong .clk_plls = gxl_clk_plls, 14600d48fc55SNeil Armstrong .clk_plls_count = ARRAY_SIZE(gxl_clk_plls), 14610d48fc55SNeil Armstrong .clk_muxes = gxbb_clk_muxes, 14620d48fc55SNeil Armstrong .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes), 14630d48fc55SNeil Armstrong .clk_dividers = gxbb_clk_dividers, 14640d48fc55SNeil Armstrong .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), 14654087bd4bSJerome Brunet .clk_audio_dividers = gxbb_audio_dividers, 14664087bd4bSJerome Brunet .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), 14670d48fc55SNeil Armstrong .cpu_clk = &gxbb_cpu_clk, 14680d48fc55SNeil Armstrong .hw_onecell_data = &gxl_hw_onecell_data, 14690d48fc55SNeil Armstrong }; 14700d48fc55SNeil Armstrong 14710d48fc55SNeil Armstrong static const struct of_device_id clkc_match_table[] = { 14720d48fc55SNeil Armstrong { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data }, 14730d48fc55SNeil Armstrong { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data }, 14740d48fc55SNeil Armstrong {}, 14750d48fc55SNeil Armstrong }; 14760d48fc55SNeil Armstrong 1477738f66d3SMichael Turquette static int gxbb_clkc_probe(struct platform_device *pdev) 1478738f66d3SMichael Turquette { 14790d48fc55SNeil Armstrong const struct clkc_data *clkc_data; 1480738f66d3SMichael Turquette void __iomem *clk_base; 1481738f66d3SMichael Turquette int ret, clkid, i; 1482738f66d3SMichael Turquette struct clk_hw *parent_hw; 1483738f66d3SMichael Turquette struct clk *parent_clk; 1484738f66d3SMichael Turquette struct device *dev = &pdev->dev; 1485738f66d3SMichael Turquette 14860d48fc55SNeil Armstrong clkc_data = of_device_get_match_data(&pdev->dev); 14870d48fc55SNeil Armstrong if (!clkc_data) 14880d48fc55SNeil Armstrong return -EINVAL; 14890d48fc55SNeil Armstrong 1490738f66d3SMichael Turquette /* Generic clocks and PLLs */ 1491738f66d3SMichael Turquette clk_base = of_iomap(dev->of_node, 0); 1492738f66d3SMichael Turquette if (!clk_base) { 1493738f66d3SMichael Turquette pr_err("%s: Unable to map clk base\n", __func__); 1494738f66d3SMichael Turquette return -ENXIO; 1495738f66d3SMichael Turquette } 1496738f66d3SMichael Turquette 1497738f66d3SMichael Turquette /* Populate base address for PLLs */ 14980d48fc55SNeil Armstrong for (i = 0; i < clkc_data->clk_plls_count; i++) 14990d48fc55SNeil Armstrong clkc_data->clk_plls[i]->base = clk_base; 1500738f66d3SMichael Turquette 1501738f66d3SMichael Turquette /* Populate base address for MPLLs */ 15020d48fc55SNeil Armstrong for (i = 0; i < clkc_data->clk_mplls_count; i++) 15030d48fc55SNeil Armstrong clkc_data->clk_mplls[i]->base = clk_base; 1504738f66d3SMichael Turquette 1505738f66d3SMichael Turquette /* Populate the base address for CPU clk */ 15060d48fc55SNeil Armstrong clkc_data->cpu_clk->base = clk_base; 1507738f66d3SMichael Turquette 1508738f66d3SMichael Turquette /* Populate base address for gates */ 15090d48fc55SNeil Armstrong for (i = 0; i < clkc_data->clk_gates_count; i++) 15100d48fc55SNeil Armstrong clkc_data->clk_gates[i]->reg = clk_base + 15110d48fc55SNeil Armstrong (u64)clkc_data->clk_gates[i]->reg; 1512738f66d3SMichael Turquette 1513b92332eeSJerome Brunet /* Populate base address for muxes */ 15140d48fc55SNeil Armstrong for (i = 0; i < clkc_data->clk_muxes_count; i++) 15150d48fc55SNeil Armstrong clkc_data->clk_muxes[i]->reg = clk_base + 15160d48fc55SNeil Armstrong (u64)clkc_data->clk_muxes[i]->reg; 1517b92332eeSJerome Brunet 1518b92332eeSJerome Brunet /* Populate base address for dividers */ 15190d48fc55SNeil Armstrong for (i = 0; i < clkc_data->clk_dividers_count; i++) 15200d48fc55SNeil Armstrong clkc_data->clk_dividers[i]->reg = clk_base + 15210d48fc55SNeil Armstrong (u64)clkc_data->clk_dividers[i]->reg; 1522b92332eeSJerome Brunet 15234087bd4bSJerome Brunet /* Populate base address for the audio dividers */ 15244087bd4bSJerome Brunet for (i = 0; i < clkc_data->clk_audio_dividers_count; i++) 15254087bd4bSJerome Brunet clkc_data->clk_audio_dividers[i]->base = clk_base; 15264087bd4bSJerome Brunet 1527738f66d3SMichael Turquette /* 1528738f66d3SMichael Turquette * register all clks 1529738f66d3SMichael Turquette */ 15300d48fc55SNeil Armstrong for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) { 1531a70c6e06SJerome Brunet /* array might be sparse */ 1532a70c6e06SJerome Brunet if (!clkc_data->hw_onecell_data->hws[clkid]) 1533a70c6e06SJerome Brunet continue; 1534a70c6e06SJerome Brunet 15350d48fc55SNeil Armstrong ret = devm_clk_hw_register(dev, 15360d48fc55SNeil Armstrong clkc_data->hw_onecell_data->hws[clkid]); 1537738f66d3SMichael Turquette if (ret) 1538738f66d3SMichael Turquette goto iounmap; 1539738f66d3SMichael Turquette } 1540738f66d3SMichael Turquette 1541738f66d3SMichael Turquette /* 1542738f66d3SMichael Turquette * Register CPU clk notifier 1543738f66d3SMichael Turquette * 1544738f66d3SMichael Turquette * FIXME this is wrong for a lot of reasons. First, the muxes should be 1545738f66d3SMichael Turquette * struct clk_hw objects. Second, we shouldn't program the muxes in 1546738f66d3SMichael Turquette * notifier handlers. The tricky programming sequence will be handled 1547738f66d3SMichael Turquette * by the forthcoming coordinated clock rates mechanism once that 1548738f66d3SMichael Turquette * feature is released. 1549738f66d3SMichael Turquette * 1550738f66d3SMichael Turquette * Furthermore, looking up the parent this way is terrible. At some 1551738f66d3SMichael Turquette * point we will stop allocating a default struct clk when registering 1552738f66d3SMichael Turquette * a new clk_hw, and this hack will no longer work. Releasing the ccr 1553738f66d3SMichael Turquette * feature before that time solves the problem :-) 1554738f66d3SMichael Turquette */ 15550d48fc55SNeil Armstrong parent_hw = clk_hw_get_parent(&clkc_data->cpu_clk->hw); 1556738f66d3SMichael Turquette parent_clk = parent_hw->clk; 15570d48fc55SNeil Armstrong ret = clk_notifier_register(parent_clk, &clkc_data->cpu_clk->clk_nb); 1558738f66d3SMichael Turquette if (ret) { 1559738f66d3SMichael Turquette pr_err("%s: failed to register clock notifier for cpu_clk\n", 1560738f66d3SMichael Turquette __func__); 1561738f66d3SMichael Turquette goto iounmap; 1562738f66d3SMichael Turquette } 1563738f66d3SMichael Turquette 1564738f66d3SMichael Turquette return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, 15650d48fc55SNeil Armstrong clkc_data->hw_onecell_data); 1566738f66d3SMichael Turquette 1567738f66d3SMichael Turquette iounmap: 1568738f66d3SMichael Turquette iounmap(clk_base); 1569738f66d3SMichael Turquette return ret; 1570738f66d3SMichael Turquette } 1571738f66d3SMichael Turquette 1572738f66d3SMichael Turquette static struct platform_driver gxbb_driver = { 1573738f66d3SMichael Turquette .probe = gxbb_clkc_probe, 1574738f66d3SMichael Turquette .driver = { 1575738f66d3SMichael Turquette .name = "gxbb-clkc", 15760d48fc55SNeil Armstrong .of_match_table = clkc_match_table, 1577738f66d3SMichael Turquette }, 1578738f66d3SMichael Turquette }; 1579738f66d3SMichael Turquette 158000746f10SWei Yongjun builtin_platform_driver(gxbb_driver); 1581