1738f66d3SMichael Turquette /* 21f501d63SPaul Gortmaker * AmLogic S905 / GXBB Clock Controller Driver 31f501d63SPaul Gortmaker * 4738f66d3SMichael Turquette * Copyright (c) 2016 AmLogic, Inc. 5738f66d3SMichael Turquette * Michael Turquette <mturquette@baylibre.com> 6738f66d3SMichael Turquette * 7738f66d3SMichael Turquette * This program is free software; you can redistribute it and/or modify it 8738f66d3SMichael Turquette * under the terms and conditions of the GNU General Public License, 9738f66d3SMichael Turquette * version 2, as published by the Free Software Foundation. 10738f66d3SMichael Turquette * 11738f66d3SMichael Turquette * This program is distributed in the hope it will be useful, but WITHOUT 12738f66d3SMichael Turquette * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13738f66d3SMichael Turquette * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14738f66d3SMichael Turquette * more details. 15738f66d3SMichael Turquette * 16738f66d3SMichael Turquette * You should have received a copy of the GNU General Public License along with 17738f66d3SMichael Turquette * this program. If not, see <http://www.gnu.org/licenses/>. 18738f66d3SMichael Turquette */ 19738f66d3SMichael Turquette 20738f66d3SMichael Turquette #include <linux/clk.h> 21738f66d3SMichael Turquette #include <linux/clk-provider.h> 22738f66d3SMichael Turquette #include <linux/of_address.h> 230d48fc55SNeil Armstrong #include <linux/of_device.h> 24738f66d3SMichael Turquette #include <linux/platform_device.h> 251f501d63SPaul Gortmaker #include <linux/init.h> 26738f66d3SMichael Turquette 27738f66d3SMichael Turquette #include "clkc.h" 28738f66d3SMichael Turquette #include "gxbb.h" 29738f66d3SMichael Turquette 3027aad905SYixun Lan static DEFINE_SPINLOCK(meson_clk_lock); 31738f66d3SMichael Turquette 32738f66d3SMichael Turquette static const struct pll_rate_table sys_pll_rate_table[] = { 33738f66d3SMichael Turquette PLL_RATE(24000000, 56, 1, 2), 34738f66d3SMichael Turquette PLL_RATE(48000000, 64, 1, 2), 35738f66d3SMichael Turquette PLL_RATE(72000000, 72, 1, 2), 36738f66d3SMichael Turquette PLL_RATE(96000000, 64, 1, 2), 37738f66d3SMichael Turquette PLL_RATE(120000000, 80, 1, 2), 38738f66d3SMichael Turquette PLL_RATE(144000000, 96, 1, 2), 39738f66d3SMichael Turquette PLL_RATE(168000000, 56, 1, 1), 40738f66d3SMichael Turquette PLL_RATE(192000000, 64, 1, 1), 41738f66d3SMichael Turquette PLL_RATE(216000000, 72, 1, 1), 42738f66d3SMichael Turquette PLL_RATE(240000000, 80, 1, 1), 43738f66d3SMichael Turquette PLL_RATE(264000000, 88, 1, 1), 44738f66d3SMichael Turquette PLL_RATE(288000000, 96, 1, 1), 45738f66d3SMichael Turquette PLL_RATE(312000000, 52, 1, 2), 46738f66d3SMichael Turquette PLL_RATE(336000000, 56, 1, 2), 47738f66d3SMichael Turquette PLL_RATE(360000000, 60, 1, 2), 48738f66d3SMichael Turquette PLL_RATE(384000000, 64, 1, 2), 49738f66d3SMichael Turquette PLL_RATE(408000000, 68, 1, 2), 50738f66d3SMichael Turquette PLL_RATE(432000000, 72, 1, 2), 51738f66d3SMichael Turquette PLL_RATE(456000000, 76, 1, 2), 52738f66d3SMichael Turquette PLL_RATE(480000000, 80, 1, 2), 53738f66d3SMichael Turquette PLL_RATE(504000000, 84, 1, 2), 54738f66d3SMichael Turquette PLL_RATE(528000000, 88, 1, 2), 55738f66d3SMichael Turquette PLL_RATE(552000000, 92, 1, 2), 56738f66d3SMichael Turquette PLL_RATE(576000000, 96, 1, 2), 57738f66d3SMichael Turquette PLL_RATE(600000000, 50, 1, 1), 58738f66d3SMichael Turquette PLL_RATE(624000000, 52, 1, 1), 59738f66d3SMichael Turquette PLL_RATE(648000000, 54, 1, 1), 60738f66d3SMichael Turquette PLL_RATE(672000000, 56, 1, 1), 61738f66d3SMichael Turquette PLL_RATE(696000000, 58, 1, 1), 62738f66d3SMichael Turquette PLL_RATE(720000000, 60, 1, 1), 63738f66d3SMichael Turquette PLL_RATE(744000000, 62, 1, 1), 64738f66d3SMichael Turquette PLL_RATE(768000000, 64, 1, 1), 65738f66d3SMichael Turquette PLL_RATE(792000000, 66, 1, 1), 66738f66d3SMichael Turquette PLL_RATE(816000000, 68, 1, 1), 67738f66d3SMichael Turquette PLL_RATE(840000000, 70, 1, 1), 68738f66d3SMichael Turquette PLL_RATE(864000000, 72, 1, 1), 69738f66d3SMichael Turquette PLL_RATE(888000000, 74, 1, 1), 70738f66d3SMichael Turquette PLL_RATE(912000000, 76, 1, 1), 71738f66d3SMichael Turquette PLL_RATE(936000000, 78, 1, 1), 72738f66d3SMichael Turquette PLL_RATE(960000000, 80, 1, 1), 73738f66d3SMichael Turquette PLL_RATE(984000000, 82, 1, 1), 74738f66d3SMichael Turquette PLL_RATE(1008000000, 84, 1, 1), 75738f66d3SMichael Turquette PLL_RATE(1032000000, 86, 1, 1), 76738f66d3SMichael Turquette PLL_RATE(1056000000, 88, 1, 1), 77738f66d3SMichael Turquette PLL_RATE(1080000000, 90, 1, 1), 78738f66d3SMichael Turquette PLL_RATE(1104000000, 92, 1, 1), 79738f66d3SMichael Turquette PLL_RATE(1128000000, 94, 1, 1), 80738f66d3SMichael Turquette PLL_RATE(1152000000, 96, 1, 1), 81738f66d3SMichael Turquette PLL_RATE(1176000000, 98, 1, 1), 82738f66d3SMichael Turquette PLL_RATE(1200000000, 50, 1, 0), 83738f66d3SMichael Turquette PLL_RATE(1224000000, 51, 1, 0), 84738f66d3SMichael Turquette PLL_RATE(1248000000, 52, 1, 0), 85738f66d3SMichael Turquette PLL_RATE(1272000000, 53, 1, 0), 86738f66d3SMichael Turquette PLL_RATE(1296000000, 54, 1, 0), 87738f66d3SMichael Turquette PLL_RATE(1320000000, 55, 1, 0), 88738f66d3SMichael Turquette PLL_RATE(1344000000, 56, 1, 0), 89738f66d3SMichael Turquette PLL_RATE(1368000000, 57, 1, 0), 90738f66d3SMichael Turquette PLL_RATE(1392000000, 58, 1, 0), 91738f66d3SMichael Turquette PLL_RATE(1416000000, 59, 1, 0), 92738f66d3SMichael Turquette PLL_RATE(1440000000, 60, 1, 0), 93738f66d3SMichael Turquette PLL_RATE(1464000000, 61, 1, 0), 94738f66d3SMichael Turquette PLL_RATE(1488000000, 62, 1, 0), 95738f66d3SMichael Turquette PLL_RATE(1512000000, 63, 1, 0), 96738f66d3SMichael Turquette PLL_RATE(1536000000, 64, 1, 0), 97738f66d3SMichael Turquette PLL_RATE(1560000000, 65, 1, 0), 98738f66d3SMichael Turquette PLL_RATE(1584000000, 66, 1, 0), 99738f66d3SMichael Turquette PLL_RATE(1608000000, 67, 1, 0), 100738f66d3SMichael Turquette PLL_RATE(1632000000, 68, 1, 0), 101738f66d3SMichael Turquette PLL_RATE(1656000000, 68, 1, 0), 102738f66d3SMichael Turquette PLL_RATE(1680000000, 68, 1, 0), 103738f66d3SMichael Turquette PLL_RATE(1704000000, 68, 1, 0), 104738f66d3SMichael Turquette PLL_RATE(1728000000, 69, 1, 0), 105738f66d3SMichael Turquette PLL_RATE(1752000000, 69, 1, 0), 106738f66d3SMichael Turquette PLL_RATE(1776000000, 69, 1, 0), 107738f66d3SMichael Turquette PLL_RATE(1800000000, 69, 1, 0), 108738f66d3SMichael Turquette PLL_RATE(1824000000, 70, 1, 0), 109738f66d3SMichael Turquette PLL_RATE(1848000000, 70, 1, 0), 110738f66d3SMichael Turquette PLL_RATE(1872000000, 70, 1, 0), 111738f66d3SMichael Turquette PLL_RATE(1896000000, 70, 1, 0), 112738f66d3SMichael Turquette PLL_RATE(1920000000, 71, 1, 0), 113738f66d3SMichael Turquette PLL_RATE(1944000000, 71, 1, 0), 114738f66d3SMichael Turquette PLL_RATE(1968000000, 71, 1, 0), 115738f66d3SMichael Turquette PLL_RATE(1992000000, 71, 1, 0), 116738f66d3SMichael Turquette PLL_RATE(2016000000, 72, 1, 0), 117738f66d3SMichael Turquette PLL_RATE(2040000000, 72, 1, 0), 118738f66d3SMichael Turquette PLL_RATE(2064000000, 72, 1, 0), 119738f66d3SMichael Turquette PLL_RATE(2088000000, 72, 1, 0), 120738f66d3SMichael Turquette PLL_RATE(2112000000, 73, 1, 0), 121738f66d3SMichael Turquette { /* sentinel */ }, 122738f66d3SMichael Turquette }; 123738f66d3SMichael Turquette 1240d48fc55SNeil Armstrong static const struct pll_rate_table gxbb_gp0_pll_rate_table[] = { 125738f66d3SMichael Turquette PLL_RATE(96000000, 32, 1, 3), 126738f66d3SMichael Turquette PLL_RATE(99000000, 33, 1, 3), 127738f66d3SMichael Turquette PLL_RATE(102000000, 34, 1, 3), 128738f66d3SMichael Turquette PLL_RATE(105000000, 35, 1, 3), 129738f66d3SMichael Turquette PLL_RATE(108000000, 36, 1, 3), 130738f66d3SMichael Turquette PLL_RATE(111000000, 37, 1, 3), 131738f66d3SMichael Turquette PLL_RATE(114000000, 38, 1, 3), 132738f66d3SMichael Turquette PLL_RATE(117000000, 39, 1, 3), 133738f66d3SMichael Turquette PLL_RATE(120000000, 40, 1, 3), 134738f66d3SMichael Turquette PLL_RATE(123000000, 41, 1, 3), 135738f66d3SMichael Turquette PLL_RATE(126000000, 42, 1, 3), 136738f66d3SMichael Turquette PLL_RATE(129000000, 43, 1, 3), 137738f66d3SMichael Turquette PLL_RATE(132000000, 44, 1, 3), 138738f66d3SMichael Turquette PLL_RATE(135000000, 45, 1, 3), 139738f66d3SMichael Turquette PLL_RATE(138000000, 46, 1, 3), 140738f66d3SMichael Turquette PLL_RATE(141000000, 47, 1, 3), 141738f66d3SMichael Turquette PLL_RATE(144000000, 48, 1, 3), 142738f66d3SMichael Turquette PLL_RATE(147000000, 49, 1, 3), 143738f66d3SMichael Turquette PLL_RATE(150000000, 50, 1, 3), 144738f66d3SMichael Turquette PLL_RATE(153000000, 51, 1, 3), 145738f66d3SMichael Turquette PLL_RATE(156000000, 52, 1, 3), 146738f66d3SMichael Turquette PLL_RATE(159000000, 53, 1, 3), 147738f66d3SMichael Turquette PLL_RATE(162000000, 54, 1, 3), 148738f66d3SMichael Turquette PLL_RATE(165000000, 55, 1, 3), 149738f66d3SMichael Turquette PLL_RATE(168000000, 56, 1, 3), 150738f66d3SMichael Turquette PLL_RATE(171000000, 57, 1, 3), 151738f66d3SMichael Turquette PLL_RATE(174000000, 58, 1, 3), 152738f66d3SMichael Turquette PLL_RATE(177000000, 59, 1, 3), 153738f66d3SMichael Turquette PLL_RATE(180000000, 60, 1, 3), 154738f66d3SMichael Turquette PLL_RATE(183000000, 61, 1, 3), 155738f66d3SMichael Turquette PLL_RATE(186000000, 62, 1, 3), 156738f66d3SMichael Turquette PLL_RATE(192000000, 32, 1, 2), 157738f66d3SMichael Turquette PLL_RATE(198000000, 33, 1, 2), 158738f66d3SMichael Turquette PLL_RATE(204000000, 34, 1, 2), 159738f66d3SMichael Turquette PLL_RATE(210000000, 35, 1, 2), 160738f66d3SMichael Turquette PLL_RATE(216000000, 36, 1, 2), 161738f66d3SMichael Turquette PLL_RATE(222000000, 37, 1, 2), 162738f66d3SMichael Turquette PLL_RATE(228000000, 38, 1, 2), 163738f66d3SMichael Turquette PLL_RATE(234000000, 39, 1, 2), 164738f66d3SMichael Turquette PLL_RATE(240000000, 40, 1, 2), 165738f66d3SMichael Turquette PLL_RATE(246000000, 41, 1, 2), 166738f66d3SMichael Turquette PLL_RATE(252000000, 42, 1, 2), 167738f66d3SMichael Turquette PLL_RATE(258000000, 43, 1, 2), 168738f66d3SMichael Turquette PLL_RATE(264000000, 44, 1, 2), 169738f66d3SMichael Turquette PLL_RATE(270000000, 45, 1, 2), 170738f66d3SMichael Turquette PLL_RATE(276000000, 46, 1, 2), 171738f66d3SMichael Turquette PLL_RATE(282000000, 47, 1, 2), 172738f66d3SMichael Turquette PLL_RATE(288000000, 48, 1, 2), 173738f66d3SMichael Turquette PLL_RATE(294000000, 49, 1, 2), 174738f66d3SMichael Turquette PLL_RATE(300000000, 50, 1, 2), 175738f66d3SMichael Turquette PLL_RATE(306000000, 51, 1, 2), 176738f66d3SMichael Turquette PLL_RATE(312000000, 52, 1, 2), 177738f66d3SMichael Turquette PLL_RATE(318000000, 53, 1, 2), 178738f66d3SMichael Turquette PLL_RATE(324000000, 54, 1, 2), 179738f66d3SMichael Turquette PLL_RATE(330000000, 55, 1, 2), 180738f66d3SMichael Turquette PLL_RATE(336000000, 56, 1, 2), 181738f66d3SMichael Turquette PLL_RATE(342000000, 57, 1, 2), 182738f66d3SMichael Turquette PLL_RATE(348000000, 58, 1, 2), 183738f66d3SMichael Turquette PLL_RATE(354000000, 59, 1, 2), 184738f66d3SMichael Turquette PLL_RATE(360000000, 60, 1, 2), 185738f66d3SMichael Turquette PLL_RATE(366000000, 61, 1, 2), 186738f66d3SMichael Turquette PLL_RATE(372000000, 62, 1, 2), 187738f66d3SMichael Turquette PLL_RATE(384000000, 32, 1, 1), 188738f66d3SMichael Turquette PLL_RATE(396000000, 33, 1, 1), 189738f66d3SMichael Turquette PLL_RATE(408000000, 34, 1, 1), 190738f66d3SMichael Turquette PLL_RATE(420000000, 35, 1, 1), 191738f66d3SMichael Turquette PLL_RATE(432000000, 36, 1, 1), 192738f66d3SMichael Turquette PLL_RATE(444000000, 37, 1, 1), 193738f66d3SMichael Turquette PLL_RATE(456000000, 38, 1, 1), 194738f66d3SMichael Turquette PLL_RATE(468000000, 39, 1, 1), 195738f66d3SMichael Turquette PLL_RATE(480000000, 40, 1, 1), 196738f66d3SMichael Turquette PLL_RATE(492000000, 41, 1, 1), 197738f66d3SMichael Turquette PLL_RATE(504000000, 42, 1, 1), 198738f66d3SMichael Turquette PLL_RATE(516000000, 43, 1, 1), 199738f66d3SMichael Turquette PLL_RATE(528000000, 44, 1, 1), 200738f66d3SMichael Turquette PLL_RATE(540000000, 45, 1, 1), 201738f66d3SMichael Turquette PLL_RATE(552000000, 46, 1, 1), 202738f66d3SMichael Turquette PLL_RATE(564000000, 47, 1, 1), 203738f66d3SMichael Turquette PLL_RATE(576000000, 48, 1, 1), 204738f66d3SMichael Turquette PLL_RATE(588000000, 49, 1, 1), 205738f66d3SMichael Turquette PLL_RATE(600000000, 50, 1, 1), 206738f66d3SMichael Turquette PLL_RATE(612000000, 51, 1, 1), 207738f66d3SMichael Turquette PLL_RATE(624000000, 52, 1, 1), 208738f66d3SMichael Turquette PLL_RATE(636000000, 53, 1, 1), 209738f66d3SMichael Turquette PLL_RATE(648000000, 54, 1, 1), 210738f66d3SMichael Turquette PLL_RATE(660000000, 55, 1, 1), 211738f66d3SMichael Turquette PLL_RATE(672000000, 56, 1, 1), 212738f66d3SMichael Turquette PLL_RATE(684000000, 57, 1, 1), 213738f66d3SMichael Turquette PLL_RATE(696000000, 58, 1, 1), 214738f66d3SMichael Turquette PLL_RATE(708000000, 59, 1, 1), 215738f66d3SMichael Turquette PLL_RATE(720000000, 60, 1, 1), 216738f66d3SMichael Turquette PLL_RATE(732000000, 61, 1, 1), 217738f66d3SMichael Turquette PLL_RATE(744000000, 62, 1, 1), 218738f66d3SMichael Turquette PLL_RATE(768000000, 32, 1, 0), 219738f66d3SMichael Turquette PLL_RATE(792000000, 33, 1, 0), 220738f66d3SMichael Turquette PLL_RATE(816000000, 34, 1, 0), 221738f66d3SMichael Turquette PLL_RATE(840000000, 35, 1, 0), 222738f66d3SMichael Turquette PLL_RATE(864000000, 36, 1, 0), 223738f66d3SMichael Turquette PLL_RATE(888000000, 37, 1, 0), 224738f66d3SMichael Turquette PLL_RATE(912000000, 38, 1, 0), 225738f66d3SMichael Turquette PLL_RATE(936000000, 39, 1, 0), 226738f66d3SMichael Turquette PLL_RATE(960000000, 40, 1, 0), 227738f66d3SMichael Turquette PLL_RATE(984000000, 41, 1, 0), 228738f66d3SMichael Turquette PLL_RATE(1008000000, 42, 1, 0), 229738f66d3SMichael Turquette PLL_RATE(1032000000, 43, 1, 0), 230738f66d3SMichael Turquette PLL_RATE(1056000000, 44, 1, 0), 231738f66d3SMichael Turquette PLL_RATE(1080000000, 45, 1, 0), 232738f66d3SMichael Turquette PLL_RATE(1104000000, 46, 1, 0), 233738f66d3SMichael Turquette PLL_RATE(1128000000, 47, 1, 0), 234738f66d3SMichael Turquette PLL_RATE(1152000000, 48, 1, 0), 235738f66d3SMichael Turquette PLL_RATE(1176000000, 49, 1, 0), 236738f66d3SMichael Turquette PLL_RATE(1200000000, 50, 1, 0), 237738f66d3SMichael Turquette PLL_RATE(1224000000, 51, 1, 0), 238738f66d3SMichael Turquette PLL_RATE(1248000000, 52, 1, 0), 239738f66d3SMichael Turquette PLL_RATE(1272000000, 53, 1, 0), 240738f66d3SMichael Turquette PLL_RATE(1296000000, 54, 1, 0), 241738f66d3SMichael Turquette PLL_RATE(1320000000, 55, 1, 0), 242738f66d3SMichael Turquette PLL_RATE(1344000000, 56, 1, 0), 243738f66d3SMichael Turquette PLL_RATE(1368000000, 57, 1, 0), 244738f66d3SMichael Turquette PLL_RATE(1392000000, 58, 1, 0), 245738f66d3SMichael Turquette PLL_RATE(1416000000, 59, 1, 0), 246738f66d3SMichael Turquette PLL_RATE(1440000000, 60, 1, 0), 247738f66d3SMichael Turquette PLL_RATE(1464000000, 61, 1, 0), 248738f66d3SMichael Turquette PLL_RATE(1488000000, 62, 1, 0), 249738f66d3SMichael Turquette { /* sentinel */ }, 250738f66d3SMichael Turquette }; 251738f66d3SMichael Turquette 2520d48fc55SNeil Armstrong static const struct pll_rate_table gxl_gp0_pll_rate_table[] = { 2530d48fc55SNeil Armstrong PLL_RATE(504000000, 42, 1, 1), 2540d48fc55SNeil Armstrong PLL_RATE(516000000, 43, 1, 1), 2550d48fc55SNeil Armstrong PLL_RATE(528000000, 44, 1, 1), 2560d48fc55SNeil Armstrong PLL_RATE(540000000, 45, 1, 1), 2570d48fc55SNeil Armstrong PLL_RATE(552000000, 46, 1, 1), 2580d48fc55SNeil Armstrong PLL_RATE(564000000, 47, 1, 1), 2590d48fc55SNeil Armstrong PLL_RATE(576000000, 48, 1, 1), 2600d48fc55SNeil Armstrong PLL_RATE(588000000, 49, 1, 1), 2610d48fc55SNeil Armstrong PLL_RATE(600000000, 50, 1, 1), 2620d48fc55SNeil Armstrong PLL_RATE(612000000, 51, 1, 1), 2630d48fc55SNeil Armstrong PLL_RATE(624000000, 52, 1, 1), 2640d48fc55SNeil Armstrong PLL_RATE(636000000, 53, 1, 1), 2650d48fc55SNeil Armstrong PLL_RATE(648000000, 54, 1, 1), 2660d48fc55SNeil Armstrong PLL_RATE(660000000, 55, 1, 1), 2670d48fc55SNeil Armstrong PLL_RATE(672000000, 56, 1, 1), 2680d48fc55SNeil Armstrong PLL_RATE(684000000, 57, 1, 1), 2690d48fc55SNeil Armstrong PLL_RATE(696000000, 58, 1, 1), 2700d48fc55SNeil Armstrong PLL_RATE(708000000, 59, 1, 1), 2710d48fc55SNeil Armstrong PLL_RATE(720000000, 60, 1, 1), 2720d48fc55SNeil Armstrong PLL_RATE(732000000, 61, 1, 1), 2730d48fc55SNeil Armstrong PLL_RATE(744000000, 62, 1, 1), 2740d48fc55SNeil Armstrong PLL_RATE(756000000, 63, 1, 1), 2750d48fc55SNeil Armstrong PLL_RATE(768000000, 64, 1, 1), 2760d48fc55SNeil Armstrong PLL_RATE(780000000, 65, 1, 1), 2770d48fc55SNeil Armstrong PLL_RATE(792000000, 66, 1, 1), 2780d48fc55SNeil Armstrong { /* sentinel */ }, 2790d48fc55SNeil Armstrong }; 2800d48fc55SNeil Armstrong 281738f66d3SMichael Turquette static struct meson_clk_pll gxbb_fixed_pll = { 282738f66d3SMichael Turquette .m = { 283738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL, 284738f66d3SMichael Turquette .shift = 0, 285738f66d3SMichael Turquette .width = 9, 286738f66d3SMichael Turquette }, 287738f66d3SMichael Turquette .n = { 288738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL, 289738f66d3SMichael Turquette .shift = 9, 290738f66d3SMichael Turquette .width = 5, 291738f66d3SMichael Turquette }, 292738f66d3SMichael Turquette .od = { 293738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL, 294738f66d3SMichael Turquette .shift = 16, 295738f66d3SMichael Turquette .width = 2, 296738f66d3SMichael Turquette }, 29727aad905SYixun Lan .lock = &meson_clk_lock, 298738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 299738f66d3SMichael Turquette .name = "fixed_pll", 300738f66d3SMichael Turquette .ops = &meson_clk_pll_ro_ops, 301738f66d3SMichael Turquette .parent_names = (const char *[]){ "xtal" }, 302738f66d3SMichael Turquette .num_parents = 1, 303738f66d3SMichael Turquette .flags = CLK_GET_RATE_NOCACHE, 304738f66d3SMichael Turquette }, 305738f66d3SMichael Turquette }; 306738f66d3SMichael Turquette 307738f66d3SMichael Turquette static struct meson_clk_pll gxbb_hdmi_pll = { 308738f66d3SMichael Turquette .m = { 309738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL, 310738f66d3SMichael Turquette .shift = 0, 311738f66d3SMichael Turquette .width = 9, 312738f66d3SMichael Turquette }, 313738f66d3SMichael Turquette .n = { 314738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL, 315738f66d3SMichael Turquette .shift = 9, 316738f66d3SMichael Turquette .width = 5, 317738f66d3SMichael Turquette }, 318738f66d3SMichael Turquette .frac = { 319738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL2, 320738f66d3SMichael Turquette .shift = 0, 321738f66d3SMichael Turquette .width = 12, 322738f66d3SMichael Turquette }, 323738f66d3SMichael Turquette .od = { 324738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL2, 325738f66d3SMichael Turquette .shift = 16, 326738f66d3SMichael Turquette .width = 2, 327738f66d3SMichael Turquette }, 328738f66d3SMichael Turquette .od2 = { 329738f66d3SMichael Turquette .reg_off = HHI_HDMI_PLL_CNTL2, 330738f66d3SMichael Turquette .shift = 22, 331738f66d3SMichael Turquette .width = 2, 332738f66d3SMichael Turquette }, 33327aad905SYixun Lan .lock = &meson_clk_lock, 334738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 335738f66d3SMichael Turquette .name = "hdmi_pll", 336738f66d3SMichael Turquette .ops = &meson_clk_pll_ro_ops, 337738f66d3SMichael Turquette .parent_names = (const char *[]){ "xtal" }, 338738f66d3SMichael Turquette .num_parents = 1, 339738f66d3SMichael Turquette .flags = CLK_GET_RATE_NOCACHE, 340738f66d3SMichael Turquette }, 341738f66d3SMichael Turquette }; 342738f66d3SMichael Turquette 343738f66d3SMichael Turquette static struct meson_clk_pll gxbb_sys_pll = { 344738f66d3SMichael Turquette .m = { 345738f66d3SMichael Turquette .reg_off = HHI_SYS_PLL_CNTL, 346738f66d3SMichael Turquette .shift = 0, 347738f66d3SMichael Turquette .width = 9, 348738f66d3SMichael Turquette }, 349738f66d3SMichael Turquette .n = { 350738f66d3SMichael Turquette .reg_off = HHI_SYS_PLL_CNTL, 351738f66d3SMichael Turquette .shift = 9, 352738f66d3SMichael Turquette .width = 5, 353738f66d3SMichael Turquette }, 354738f66d3SMichael Turquette .od = { 355738f66d3SMichael Turquette .reg_off = HHI_SYS_PLL_CNTL, 356738f66d3SMichael Turquette .shift = 10, 357738f66d3SMichael Turquette .width = 2, 358738f66d3SMichael Turquette }, 359738f66d3SMichael Turquette .rate_table = sys_pll_rate_table, 360738f66d3SMichael Turquette .rate_count = ARRAY_SIZE(sys_pll_rate_table), 36127aad905SYixun Lan .lock = &meson_clk_lock, 362738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 363738f66d3SMichael Turquette .name = "sys_pll", 364738f66d3SMichael Turquette .ops = &meson_clk_pll_ro_ops, 365738f66d3SMichael Turquette .parent_names = (const char *[]){ "xtal" }, 366738f66d3SMichael Turquette .num_parents = 1, 367738f66d3SMichael Turquette .flags = CLK_GET_RATE_NOCACHE, 368738f66d3SMichael Turquette }, 369738f66d3SMichael Turquette }; 370738f66d3SMichael Turquette 371e194401cSNeil Armstrong struct pll_params_table gxbb_gp0_params_table[] = { 372e194401cSNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL, 0x6a000228), 373e194401cSNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL2, 0x69c80000), 374e194401cSNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a5590c4), 375e194401cSNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL4, 0x0000500d), 376e194401cSNeil Armstrong }; 377e194401cSNeil Armstrong 378738f66d3SMichael Turquette static struct meson_clk_pll gxbb_gp0_pll = { 379738f66d3SMichael Turquette .m = { 380738f66d3SMichael Turquette .reg_off = HHI_GP0_PLL_CNTL, 381738f66d3SMichael Turquette .shift = 0, 382738f66d3SMichael Turquette .width = 9, 383738f66d3SMichael Turquette }, 384738f66d3SMichael Turquette .n = { 385738f66d3SMichael Turquette .reg_off = HHI_GP0_PLL_CNTL, 386738f66d3SMichael Turquette .shift = 9, 387738f66d3SMichael Turquette .width = 5, 388738f66d3SMichael Turquette }, 389738f66d3SMichael Turquette .od = { 390738f66d3SMichael Turquette .reg_off = HHI_GP0_PLL_CNTL, 391738f66d3SMichael Turquette .shift = 16, 392738f66d3SMichael Turquette .width = 2, 393738f66d3SMichael Turquette }, 394e194401cSNeil Armstrong .params = { 395e194401cSNeil Armstrong .params_table = gxbb_gp0_params_table, 396e194401cSNeil Armstrong .params_count = ARRAY_SIZE(gxbb_gp0_params_table), 397e194401cSNeil Armstrong .no_init_reset = true, 398e194401cSNeil Armstrong .clear_reset_for_lock = true, 399e194401cSNeil Armstrong }, 4000d48fc55SNeil Armstrong .rate_table = gxbb_gp0_pll_rate_table, 4010d48fc55SNeil Armstrong .rate_count = ARRAY_SIZE(gxbb_gp0_pll_rate_table), 40227aad905SYixun Lan .lock = &meson_clk_lock, 4030d48fc55SNeil Armstrong .hw.init = &(struct clk_init_data){ 4040d48fc55SNeil Armstrong .name = "gp0_pll", 4050d48fc55SNeil Armstrong .ops = &meson_clk_pll_ops, 4060d48fc55SNeil Armstrong .parent_names = (const char *[]){ "xtal" }, 4070d48fc55SNeil Armstrong .num_parents = 1, 4080d48fc55SNeil Armstrong .flags = CLK_GET_RATE_NOCACHE, 4090d48fc55SNeil Armstrong }, 4100d48fc55SNeil Armstrong }; 4110d48fc55SNeil Armstrong 4120d48fc55SNeil Armstrong struct pll_params_table gxl_gp0_params_table[] = { 4130d48fc55SNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250), 4140d48fc55SNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000), 4150d48fc55SNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be), 4160d48fc55SNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288), 4170d48fc55SNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d), 4180d48fc55SNeil Armstrong PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000), 4190d48fc55SNeil Armstrong }; 4200d48fc55SNeil Armstrong 4210d48fc55SNeil Armstrong static struct meson_clk_pll gxl_gp0_pll = { 4220d48fc55SNeil Armstrong .m = { 4230d48fc55SNeil Armstrong .reg_off = HHI_GP0_PLL_CNTL, 4240d48fc55SNeil Armstrong .shift = 0, 4250d48fc55SNeil Armstrong .width = 9, 4260d48fc55SNeil Armstrong }, 4270d48fc55SNeil Armstrong .n = { 4280d48fc55SNeil Armstrong .reg_off = HHI_GP0_PLL_CNTL, 4290d48fc55SNeil Armstrong .shift = 9, 4300d48fc55SNeil Armstrong .width = 5, 4310d48fc55SNeil Armstrong }, 4320d48fc55SNeil Armstrong .od = { 4330d48fc55SNeil Armstrong .reg_off = HHI_GP0_PLL_CNTL, 4340d48fc55SNeil Armstrong .shift = 16, 4350d48fc55SNeil Armstrong .width = 2, 4360d48fc55SNeil Armstrong }, 4370d48fc55SNeil Armstrong .params = { 4380d48fc55SNeil Armstrong .params_table = gxl_gp0_params_table, 4390d48fc55SNeil Armstrong .params_count = ARRAY_SIZE(gxl_gp0_params_table), 4400d48fc55SNeil Armstrong .no_init_reset = true, 4410d48fc55SNeil Armstrong .reset_lock_loop = true, 4420d48fc55SNeil Armstrong }, 4430d48fc55SNeil Armstrong .rate_table = gxl_gp0_pll_rate_table, 4440d48fc55SNeil Armstrong .rate_count = ARRAY_SIZE(gxl_gp0_pll_rate_table), 44527aad905SYixun Lan .lock = &meson_clk_lock, 446738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 447738f66d3SMichael Turquette .name = "gp0_pll", 448738f66d3SMichael Turquette .ops = &meson_clk_pll_ops, 449738f66d3SMichael Turquette .parent_names = (const char *[]){ "xtal" }, 450738f66d3SMichael Turquette .num_parents = 1, 451738f66d3SMichael Turquette .flags = CLK_GET_RATE_NOCACHE, 452738f66d3SMichael Turquette }, 453738f66d3SMichael Turquette }; 454738f66d3SMichael Turquette 455738f66d3SMichael Turquette static struct clk_fixed_factor gxbb_fclk_div2 = { 456738f66d3SMichael Turquette .mult = 1, 457738f66d3SMichael Turquette .div = 2, 458738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 459738f66d3SMichael Turquette .name = "fclk_div2", 460738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 461738f66d3SMichael Turquette .parent_names = (const char *[]){ "fixed_pll" }, 462738f66d3SMichael Turquette .num_parents = 1, 463738f66d3SMichael Turquette }, 464738f66d3SMichael Turquette }; 465738f66d3SMichael Turquette 466738f66d3SMichael Turquette static struct clk_fixed_factor gxbb_fclk_div3 = { 467738f66d3SMichael Turquette .mult = 1, 468738f66d3SMichael Turquette .div = 3, 469738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 470738f66d3SMichael Turquette .name = "fclk_div3", 471738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 472738f66d3SMichael Turquette .parent_names = (const char *[]){ "fixed_pll" }, 473738f66d3SMichael Turquette .num_parents = 1, 474738f66d3SMichael Turquette }, 475738f66d3SMichael Turquette }; 476738f66d3SMichael Turquette 477738f66d3SMichael Turquette static struct clk_fixed_factor gxbb_fclk_div4 = { 478738f66d3SMichael Turquette .mult = 1, 479738f66d3SMichael Turquette .div = 4, 480738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 481738f66d3SMichael Turquette .name = "fclk_div4", 482738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 483738f66d3SMichael Turquette .parent_names = (const char *[]){ "fixed_pll" }, 484738f66d3SMichael Turquette .num_parents = 1, 485738f66d3SMichael Turquette }, 486738f66d3SMichael Turquette }; 487738f66d3SMichael Turquette 488738f66d3SMichael Turquette static struct clk_fixed_factor gxbb_fclk_div5 = { 489738f66d3SMichael Turquette .mult = 1, 490738f66d3SMichael Turquette .div = 5, 491738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 492738f66d3SMichael Turquette .name = "fclk_div5", 493738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 494738f66d3SMichael Turquette .parent_names = (const char *[]){ "fixed_pll" }, 495738f66d3SMichael Turquette .num_parents = 1, 496738f66d3SMichael Turquette }, 497738f66d3SMichael Turquette }; 498738f66d3SMichael Turquette 499738f66d3SMichael Turquette static struct clk_fixed_factor gxbb_fclk_div7 = { 500738f66d3SMichael Turquette .mult = 1, 501738f66d3SMichael Turquette .div = 7, 502738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 503738f66d3SMichael Turquette .name = "fclk_div7", 504738f66d3SMichael Turquette .ops = &clk_fixed_factor_ops, 505738f66d3SMichael Turquette .parent_names = (const char *[]){ "fixed_pll" }, 506738f66d3SMichael Turquette .num_parents = 1, 507738f66d3SMichael Turquette }, 508738f66d3SMichael Turquette }; 509738f66d3SMichael Turquette 510738f66d3SMichael Turquette static struct meson_clk_mpll gxbb_mpll0 = { 511738f66d3SMichael Turquette .sdm = { 512738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL7, 513738f66d3SMichael Turquette .shift = 0, 514738f66d3SMichael Turquette .width = 14, 515738f66d3SMichael Turquette }, 516007e6e5cSJerome Brunet .sdm_en = { 517007e6e5cSJerome Brunet .reg_off = HHI_MPLL_CNTL7, 518007e6e5cSJerome Brunet .shift = 15, 519007e6e5cSJerome Brunet .width = 1, 520007e6e5cSJerome Brunet }, 521738f66d3SMichael Turquette .n2 = { 522738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL7, 523738f66d3SMichael Turquette .shift = 16, 524738f66d3SMichael Turquette .width = 9, 525738f66d3SMichael Turquette }, 526007e6e5cSJerome Brunet .en = { 527007e6e5cSJerome Brunet .reg_off = HHI_MPLL_CNTL7, 528007e6e5cSJerome Brunet .shift = 14, 529007e6e5cSJerome Brunet .width = 1, 530007e6e5cSJerome Brunet }, 5311f737ffaSJerome Brunet .ssen = { 5321f737ffaSJerome Brunet .reg_off = HHI_MPLL_CNTL, 5331f737ffaSJerome Brunet .shift = 25, 5341f737ffaSJerome Brunet .width = 1, 5351f737ffaSJerome Brunet }, 53627aad905SYixun Lan .lock = &meson_clk_lock, 537738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 538738f66d3SMichael Turquette .name = "mpll0", 53905b43aa2SJerome Brunet .ops = &meson_clk_mpll_ops, 540738f66d3SMichael Turquette .parent_names = (const char *[]){ "fixed_pll" }, 541738f66d3SMichael Turquette .num_parents = 1, 542738f66d3SMichael Turquette }, 543738f66d3SMichael Turquette }; 544738f66d3SMichael Turquette 545738f66d3SMichael Turquette static struct meson_clk_mpll gxbb_mpll1 = { 546738f66d3SMichael Turquette .sdm = { 547738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL8, 548738f66d3SMichael Turquette .shift = 0, 549738f66d3SMichael Turquette .width = 14, 550738f66d3SMichael Turquette }, 551007e6e5cSJerome Brunet .sdm_en = { 552007e6e5cSJerome Brunet .reg_off = HHI_MPLL_CNTL8, 553007e6e5cSJerome Brunet .shift = 15, 554007e6e5cSJerome Brunet .width = 1, 555007e6e5cSJerome Brunet }, 556738f66d3SMichael Turquette .n2 = { 557738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL8, 558738f66d3SMichael Turquette .shift = 16, 559738f66d3SMichael Turquette .width = 9, 560738f66d3SMichael Turquette }, 561007e6e5cSJerome Brunet .en = { 562007e6e5cSJerome Brunet .reg_off = HHI_MPLL_CNTL8, 563007e6e5cSJerome Brunet .shift = 14, 564007e6e5cSJerome Brunet .width = 1, 565007e6e5cSJerome Brunet }, 56627aad905SYixun Lan .lock = &meson_clk_lock, 567738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 568738f66d3SMichael Turquette .name = "mpll1", 56905b43aa2SJerome Brunet .ops = &meson_clk_mpll_ops, 570738f66d3SMichael Turquette .parent_names = (const char *[]){ "fixed_pll" }, 571738f66d3SMichael Turquette .num_parents = 1, 572738f66d3SMichael Turquette }, 573738f66d3SMichael Turquette }; 574738f66d3SMichael Turquette 575738f66d3SMichael Turquette static struct meson_clk_mpll gxbb_mpll2 = { 576738f66d3SMichael Turquette .sdm = { 577738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL9, 578738f66d3SMichael Turquette .shift = 0, 579738f66d3SMichael Turquette .width = 14, 580738f66d3SMichael Turquette }, 581007e6e5cSJerome Brunet .sdm_en = { 582007e6e5cSJerome Brunet .reg_off = HHI_MPLL_CNTL9, 583007e6e5cSJerome Brunet .shift = 15, 584007e6e5cSJerome Brunet .width = 1, 585007e6e5cSJerome Brunet }, 586738f66d3SMichael Turquette .n2 = { 587738f66d3SMichael Turquette .reg_off = HHI_MPLL_CNTL9, 588738f66d3SMichael Turquette .shift = 16, 589738f66d3SMichael Turquette .width = 9, 590738f66d3SMichael Turquette }, 591007e6e5cSJerome Brunet .en = { 592007e6e5cSJerome Brunet .reg_off = HHI_MPLL_CNTL9, 593007e6e5cSJerome Brunet .shift = 14, 594007e6e5cSJerome Brunet .width = 1, 595007e6e5cSJerome Brunet }, 59627aad905SYixun Lan .lock = &meson_clk_lock, 597738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 598738f66d3SMichael Turquette .name = "mpll2", 59905b43aa2SJerome Brunet .ops = &meson_clk_mpll_ops, 600738f66d3SMichael Turquette .parent_names = (const char *[]){ "fixed_pll" }, 601738f66d3SMichael Turquette .num_parents = 1, 602738f66d3SMichael Turquette }, 603738f66d3SMichael Turquette }; 604738f66d3SMichael Turquette 605738f66d3SMichael Turquette /* 60696b61c8dSMartin Blumenstingl * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers 60796b61c8dSMartin Blumenstingl * and should be modeled with their respective PLLs via the forthcoming 60896b61c8dSMartin Blumenstingl * coordinated clock rates feature 609738f66d3SMichael Turquette */ 610738f66d3SMichael Turquette 611215c80a7SJerome Brunet static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 612215c80a7SJerome Brunet static const char * const clk81_parent_names[] = { 613215c80a7SJerome Brunet "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", 614215c80a7SJerome Brunet "fclk_div3", "fclk_div5" 615215c80a7SJerome Brunet }; 616738f66d3SMichael Turquette 617738f66d3SMichael Turquette static struct clk_mux gxbb_mpeg_clk_sel = { 618738f66d3SMichael Turquette .reg = (void *)HHI_MPEG_CLK_CNTL, 619738f66d3SMichael Turquette .mask = 0x7, 620738f66d3SMichael Turquette .shift = 12, 621738f66d3SMichael Turquette .flags = CLK_MUX_READ_ONLY, 622738f66d3SMichael Turquette .table = mux_table_clk81, 62327aad905SYixun Lan .lock = &meson_clk_lock, 624738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 625738f66d3SMichael Turquette .name = "mpeg_clk_sel", 626738f66d3SMichael Turquette .ops = &clk_mux_ro_ops, 627738f66d3SMichael Turquette /* 628215c80a7SJerome Brunet * bits 14:12 selects from 8 possible parents: 629738f66d3SMichael Turquette * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 630738f66d3SMichael Turquette * fclk_div4, fclk_div3, fclk_div5 631738f66d3SMichael Turquette */ 632215c80a7SJerome Brunet .parent_names = clk81_parent_names, 633215c80a7SJerome Brunet .num_parents = ARRAY_SIZE(clk81_parent_names), 634738f66d3SMichael Turquette .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED), 635738f66d3SMichael Turquette }, 636738f66d3SMichael Turquette }; 637738f66d3SMichael Turquette 638738f66d3SMichael Turquette static struct clk_divider gxbb_mpeg_clk_div = { 639738f66d3SMichael Turquette .reg = (void *)HHI_MPEG_CLK_CNTL, 640738f66d3SMichael Turquette .shift = 0, 641738f66d3SMichael Turquette .width = 7, 64227aad905SYixun Lan .lock = &meson_clk_lock, 643738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 644738f66d3SMichael Turquette .name = "mpeg_clk_div", 645738f66d3SMichael Turquette .ops = &clk_divider_ops, 646738f66d3SMichael Turquette .parent_names = (const char *[]){ "mpeg_clk_sel" }, 647738f66d3SMichael Turquette .num_parents = 1, 648738f66d3SMichael Turquette .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), 649738f66d3SMichael Turquette }, 650738f66d3SMichael Turquette }; 651738f66d3SMichael Turquette 652738f66d3SMichael Turquette /* the mother of dragons^W gates */ 653738f66d3SMichael Turquette static struct clk_gate gxbb_clk81 = { 654738f66d3SMichael Turquette .reg = (void *)HHI_MPEG_CLK_CNTL, 655738f66d3SMichael Turquette .bit_idx = 7, 65627aad905SYixun Lan .lock = &meson_clk_lock, 657738f66d3SMichael Turquette .hw.init = &(struct clk_init_data){ 658738f66d3SMichael Turquette .name = "clk81", 659738f66d3SMichael Turquette .ops = &clk_gate_ops, 660738f66d3SMichael Turquette .parent_names = (const char *[]){ "mpeg_clk_div" }, 661738f66d3SMichael Turquette .num_parents = 1, 66239c42ca9SJerome Brunet .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 663738f66d3SMichael Turquette }, 664738f66d3SMichael Turquette }; 665738f66d3SMichael Turquette 66633d0fcdfSMartin Blumenstingl static struct clk_mux gxbb_sar_adc_clk_sel = { 66733d0fcdfSMartin Blumenstingl .reg = (void *)HHI_SAR_CLK_CNTL, 66833d0fcdfSMartin Blumenstingl .mask = 0x3, 66933d0fcdfSMartin Blumenstingl .shift = 9, 67027aad905SYixun Lan .lock = &meson_clk_lock, 67133d0fcdfSMartin Blumenstingl .hw.init = &(struct clk_init_data){ 67233d0fcdfSMartin Blumenstingl .name = "sar_adc_clk_sel", 67333d0fcdfSMartin Blumenstingl .ops = &clk_mux_ops, 67433d0fcdfSMartin Blumenstingl /* NOTE: The datasheet doesn't list the parents for bit 10 */ 67533d0fcdfSMartin Blumenstingl .parent_names = (const char *[]){ "xtal", "clk81", }, 67633d0fcdfSMartin Blumenstingl .num_parents = 2, 67733d0fcdfSMartin Blumenstingl }, 67833d0fcdfSMartin Blumenstingl }; 67933d0fcdfSMartin Blumenstingl 68033d0fcdfSMartin Blumenstingl static struct clk_divider gxbb_sar_adc_clk_div = { 68133d0fcdfSMartin Blumenstingl .reg = (void *)HHI_SAR_CLK_CNTL, 68233d0fcdfSMartin Blumenstingl .shift = 0, 68333d0fcdfSMartin Blumenstingl .width = 8, 68427aad905SYixun Lan .lock = &meson_clk_lock, 68533d0fcdfSMartin Blumenstingl .hw.init = &(struct clk_init_data){ 68633d0fcdfSMartin Blumenstingl .name = "sar_adc_clk_div", 68733d0fcdfSMartin Blumenstingl .ops = &clk_divider_ops, 68833d0fcdfSMartin Blumenstingl .parent_names = (const char *[]){ "sar_adc_clk_sel" }, 68933d0fcdfSMartin Blumenstingl .num_parents = 1, 69033d0fcdfSMartin Blumenstingl }, 69133d0fcdfSMartin Blumenstingl }; 69233d0fcdfSMartin Blumenstingl 69333d0fcdfSMartin Blumenstingl static struct clk_gate gxbb_sar_adc_clk = { 69433d0fcdfSMartin Blumenstingl .reg = (void *)HHI_SAR_CLK_CNTL, 69533d0fcdfSMartin Blumenstingl .bit_idx = 8, 69627aad905SYixun Lan .lock = &meson_clk_lock, 69733d0fcdfSMartin Blumenstingl .hw.init = &(struct clk_init_data){ 69833d0fcdfSMartin Blumenstingl .name = "sar_adc_clk", 69933d0fcdfSMartin Blumenstingl .ops = &clk_gate_ops, 70033d0fcdfSMartin Blumenstingl .parent_names = (const char *[]){ "sar_adc_clk_div" }, 70133d0fcdfSMartin Blumenstingl .num_parents = 1, 70233d0fcdfSMartin Blumenstingl .flags = CLK_SET_RATE_PARENT, 70333d0fcdfSMartin Blumenstingl }, 70433d0fcdfSMartin Blumenstingl }; 70533d0fcdfSMartin Blumenstingl 706fac9a55bSNeil Armstrong /* 707fac9a55bSNeil Armstrong * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 708fac9a55bSNeil Armstrong * muxed by a glitch-free switch. 709fac9a55bSNeil Armstrong */ 710fac9a55bSNeil Armstrong 711fac9a55bSNeil Armstrong static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7}; 712c3c4cb8dSStephen Boyd static const char * const gxbb_mali_0_1_parent_names[] = { 713fac9a55bSNeil Armstrong "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7", 714fac9a55bSNeil Armstrong "fclk_div4", "fclk_div3", "fclk_div5" 715fac9a55bSNeil Armstrong }; 716fac9a55bSNeil Armstrong 717fac9a55bSNeil Armstrong static struct clk_mux gxbb_mali_0_sel = { 718fac9a55bSNeil Armstrong .reg = (void *)HHI_MALI_CLK_CNTL, 719fac9a55bSNeil Armstrong .mask = 0x7, 720fac9a55bSNeil Armstrong .shift = 9, 721fac9a55bSNeil Armstrong .table = mux_table_mali_0_1, 72227aad905SYixun Lan .lock = &meson_clk_lock, 723fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 724fac9a55bSNeil Armstrong .name = "mali_0_sel", 725fac9a55bSNeil Armstrong .ops = &clk_mux_ops, 726fac9a55bSNeil Armstrong /* 727fac9a55bSNeil Armstrong * bits 10:9 selects from 8 possible parents: 728fac9a55bSNeil Armstrong * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 729fac9a55bSNeil Armstrong * fclk_div4, fclk_div3, fclk_div5 730fac9a55bSNeil Armstrong */ 731fac9a55bSNeil Armstrong .parent_names = gxbb_mali_0_1_parent_names, 732fac9a55bSNeil Armstrong .num_parents = 8, 733fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 734fac9a55bSNeil Armstrong }, 735fac9a55bSNeil Armstrong }; 736fac9a55bSNeil Armstrong 737fac9a55bSNeil Armstrong static struct clk_divider gxbb_mali_0_div = { 738fac9a55bSNeil Armstrong .reg = (void *)HHI_MALI_CLK_CNTL, 739fac9a55bSNeil Armstrong .shift = 0, 740fac9a55bSNeil Armstrong .width = 7, 74127aad905SYixun Lan .lock = &meson_clk_lock, 742fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 743fac9a55bSNeil Armstrong .name = "mali_0_div", 744fac9a55bSNeil Armstrong .ops = &clk_divider_ops, 745fac9a55bSNeil Armstrong .parent_names = (const char *[]){ "mali_0_sel" }, 746fac9a55bSNeil Armstrong .num_parents = 1, 747fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 748fac9a55bSNeil Armstrong }, 749fac9a55bSNeil Armstrong }; 750fac9a55bSNeil Armstrong 751fac9a55bSNeil Armstrong static struct clk_gate gxbb_mali_0 = { 752fac9a55bSNeil Armstrong .reg = (void *)HHI_MALI_CLK_CNTL, 753fac9a55bSNeil Armstrong .bit_idx = 8, 75427aad905SYixun Lan .lock = &meson_clk_lock, 755fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 756fac9a55bSNeil Armstrong .name = "mali_0", 757fac9a55bSNeil Armstrong .ops = &clk_gate_ops, 758fac9a55bSNeil Armstrong .parent_names = (const char *[]){ "mali_0_div" }, 759fac9a55bSNeil Armstrong .num_parents = 1, 760fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_PARENT, 761fac9a55bSNeil Armstrong }, 762fac9a55bSNeil Armstrong }; 763fac9a55bSNeil Armstrong 764fac9a55bSNeil Armstrong static struct clk_mux gxbb_mali_1_sel = { 765fac9a55bSNeil Armstrong .reg = (void *)HHI_MALI_CLK_CNTL, 766fac9a55bSNeil Armstrong .mask = 0x7, 767fac9a55bSNeil Armstrong .shift = 25, 768fac9a55bSNeil Armstrong .table = mux_table_mali_0_1, 76927aad905SYixun Lan .lock = &meson_clk_lock, 770fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 771fac9a55bSNeil Armstrong .name = "mali_1_sel", 772fac9a55bSNeil Armstrong .ops = &clk_mux_ops, 773fac9a55bSNeil Armstrong /* 774fac9a55bSNeil Armstrong * bits 10:9 selects from 8 possible parents: 775fac9a55bSNeil Armstrong * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 776fac9a55bSNeil Armstrong * fclk_div4, fclk_div3, fclk_div5 777fac9a55bSNeil Armstrong */ 778fac9a55bSNeil Armstrong .parent_names = gxbb_mali_0_1_parent_names, 779fac9a55bSNeil Armstrong .num_parents = 8, 780fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 781fac9a55bSNeil Armstrong }, 782fac9a55bSNeil Armstrong }; 783fac9a55bSNeil Armstrong 784fac9a55bSNeil Armstrong static struct clk_divider gxbb_mali_1_div = { 785fac9a55bSNeil Armstrong .reg = (void *)HHI_MALI_CLK_CNTL, 786fac9a55bSNeil Armstrong .shift = 16, 787fac9a55bSNeil Armstrong .width = 7, 78827aad905SYixun Lan .lock = &meson_clk_lock, 789fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 790fac9a55bSNeil Armstrong .name = "mali_1_div", 791fac9a55bSNeil Armstrong .ops = &clk_divider_ops, 792fac9a55bSNeil Armstrong .parent_names = (const char *[]){ "mali_1_sel" }, 793fac9a55bSNeil Armstrong .num_parents = 1, 794fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 795fac9a55bSNeil Armstrong }, 796fac9a55bSNeil Armstrong }; 797fac9a55bSNeil Armstrong 798fac9a55bSNeil Armstrong static struct clk_gate gxbb_mali_1 = { 799fac9a55bSNeil Armstrong .reg = (void *)HHI_MALI_CLK_CNTL, 800fac9a55bSNeil Armstrong .bit_idx = 24, 80127aad905SYixun Lan .lock = &meson_clk_lock, 802fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 803fac9a55bSNeil Armstrong .name = "mali_1", 804fac9a55bSNeil Armstrong .ops = &clk_gate_ops, 805fac9a55bSNeil Armstrong .parent_names = (const char *[]){ "mali_1_div" }, 806fac9a55bSNeil Armstrong .num_parents = 1, 807fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_PARENT, 808fac9a55bSNeil Armstrong }, 809fac9a55bSNeil Armstrong }; 810fac9a55bSNeil Armstrong 811fac9a55bSNeil Armstrong static u32 mux_table_mali[] = {0, 1}; 812c3c4cb8dSStephen Boyd static const char * const gxbb_mali_parent_names[] = { 813fac9a55bSNeil Armstrong "mali_0", "mali_1" 814fac9a55bSNeil Armstrong }; 815fac9a55bSNeil Armstrong 816fac9a55bSNeil Armstrong static struct clk_mux gxbb_mali = { 817fac9a55bSNeil Armstrong .reg = (void *)HHI_MALI_CLK_CNTL, 818fac9a55bSNeil Armstrong .mask = 1, 819fac9a55bSNeil Armstrong .shift = 31, 820fac9a55bSNeil Armstrong .table = mux_table_mali, 82127aad905SYixun Lan .lock = &meson_clk_lock, 822fac9a55bSNeil Armstrong .hw.init = &(struct clk_init_data){ 823fac9a55bSNeil Armstrong .name = "mali", 824fac9a55bSNeil Armstrong .ops = &clk_mux_ops, 825fac9a55bSNeil Armstrong .parent_names = gxbb_mali_parent_names, 826fac9a55bSNeil Armstrong .num_parents = 2, 827fac9a55bSNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 828fac9a55bSNeil Armstrong }, 829fac9a55bSNeil Armstrong }; 830fac9a55bSNeil Armstrong 8314087bd4bSJerome Brunet static struct clk_mux gxbb_cts_amclk_sel = { 8324087bd4bSJerome Brunet .reg = (void *) HHI_AUD_CLK_CNTL, 8334087bd4bSJerome Brunet .mask = 0x3, 8344087bd4bSJerome Brunet .shift = 9, 8354087bd4bSJerome Brunet /* Default parent unknown (register reset value: 0) */ 8364087bd4bSJerome Brunet .table = (u32[]){ 1, 2, 3 }, 83727aad905SYixun Lan .lock = &meson_clk_lock, 8384087bd4bSJerome Brunet .hw.init = &(struct clk_init_data){ 8394087bd4bSJerome Brunet .name = "cts_amclk_sel", 8404087bd4bSJerome Brunet .ops = &clk_mux_ops, 8414087bd4bSJerome Brunet .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 8424087bd4bSJerome Brunet .num_parents = 3, 8434087bd4bSJerome Brunet .flags = CLK_SET_RATE_PARENT, 8444087bd4bSJerome Brunet }, 8454087bd4bSJerome Brunet }; 8464087bd4bSJerome Brunet 8474087bd4bSJerome Brunet static struct meson_clk_audio_divider gxbb_cts_amclk_div = { 8484087bd4bSJerome Brunet .div = { 8494087bd4bSJerome Brunet .reg_off = HHI_AUD_CLK_CNTL, 8504087bd4bSJerome Brunet .shift = 0, 8514087bd4bSJerome Brunet .width = 8, 8524087bd4bSJerome Brunet }, 853004f6f46SJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 85427aad905SYixun Lan .lock = &meson_clk_lock, 8554087bd4bSJerome Brunet .hw.init = &(struct clk_init_data){ 8564087bd4bSJerome Brunet .name = "cts_amclk_div", 8574087bd4bSJerome Brunet .ops = &meson_clk_audio_divider_ops, 8584087bd4bSJerome Brunet .parent_names = (const char *[]){ "cts_amclk_sel" }, 8594087bd4bSJerome Brunet .num_parents = 1, 860004f6f46SJerome Brunet .flags = CLK_SET_RATE_PARENT, 8614087bd4bSJerome Brunet }, 8624087bd4bSJerome Brunet }; 8634087bd4bSJerome Brunet 8644087bd4bSJerome Brunet static struct clk_gate gxbb_cts_amclk = { 8654087bd4bSJerome Brunet .reg = (void *) HHI_AUD_CLK_CNTL, 8664087bd4bSJerome Brunet .bit_idx = 8, 86727aad905SYixun Lan .lock = &meson_clk_lock, 8684087bd4bSJerome Brunet .hw.init = &(struct clk_init_data){ 8694087bd4bSJerome Brunet .name = "cts_amclk", 8704087bd4bSJerome Brunet .ops = &clk_gate_ops, 8714087bd4bSJerome Brunet .parent_names = (const char *[]){ "cts_amclk_div" }, 8724087bd4bSJerome Brunet .num_parents = 1, 8734087bd4bSJerome Brunet .flags = CLK_SET_RATE_PARENT, 8744087bd4bSJerome Brunet }, 8754087bd4bSJerome Brunet }; 8764087bd4bSJerome Brunet 8773c277c24SJerome Brunet static struct clk_mux gxbb_cts_mclk_i958_sel = { 8783c277c24SJerome Brunet .reg = (void *)HHI_AUD_CLK_CNTL2, 8793c277c24SJerome Brunet .mask = 0x3, 8803c277c24SJerome Brunet .shift = 25, 8813c277c24SJerome Brunet /* Default parent unknown (register reset value: 0) */ 8823c277c24SJerome Brunet .table = (u32[]){ 1, 2, 3 }, 88327aad905SYixun Lan .lock = &meson_clk_lock, 8843c277c24SJerome Brunet .hw.init = &(struct clk_init_data) { 8853c277c24SJerome Brunet .name = "cts_mclk_i958_sel", 8863c277c24SJerome Brunet .ops = &clk_mux_ops, 8873c277c24SJerome Brunet .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 8883c277c24SJerome Brunet .num_parents = 3, 8893c277c24SJerome Brunet .flags = CLK_SET_RATE_PARENT, 8903c277c24SJerome Brunet }, 8913c277c24SJerome Brunet }; 8923c277c24SJerome Brunet 8933c277c24SJerome Brunet static struct clk_divider gxbb_cts_mclk_i958_div = { 8943c277c24SJerome Brunet .reg = (void *)HHI_AUD_CLK_CNTL2, 8953c277c24SJerome Brunet .shift = 16, 8963c277c24SJerome Brunet .width = 8, 89727aad905SYixun Lan .lock = &meson_clk_lock, 8987605aa5bSJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 8993c277c24SJerome Brunet .hw.init = &(struct clk_init_data) { 9003c277c24SJerome Brunet .name = "cts_mclk_i958_div", 9013c277c24SJerome Brunet .ops = &clk_divider_ops, 9023c277c24SJerome Brunet .parent_names = (const char *[]){ "cts_mclk_i958_sel" }, 9033c277c24SJerome Brunet .num_parents = 1, 9047605aa5bSJerome Brunet .flags = CLK_SET_RATE_PARENT, 9053c277c24SJerome Brunet }, 9063c277c24SJerome Brunet }; 9073c277c24SJerome Brunet 9083c277c24SJerome Brunet static struct clk_gate gxbb_cts_mclk_i958 = { 9093c277c24SJerome Brunet .reg = (void *)HHI_AUD_CLK_CNTL2, 9103c277c24SJerome Brunet .bit_idx = 24, 91127aad905SYixun Lan .lock = &meson_clk_lock, 9123c277c24SJerome Brunet .hw.init = &(struct clk_init_data){ 9133c277c24SJerome Brunet .name = "cts_mclk_i958", 9143c277c24SJerome Brunet .ops = &clk_gate_ops, 9153c277c24SJerome Brunet .parent_names = (const char *[]){ "cts_mclk_i958_div" }, 9163c277c24SJerome Brunet .num_parents = 1, 9173c277c24SJerome Brunet .flags = CLK_SET_RATE_PARENT, 9183c277c24SJerome Brunet }, 9193c277c24SJerome Brunet }; 9203c277c24SJerome Brunet 9217eaa44f6SJerome Brunet static struct clk_mux gxbb_cts_i958 = { 9227eaa44f6SJerome Brunet .reg = (void *)HHI_AUD_CLK_CNTL2, 9237eaa44f6SJerome Brunet .mask = 0x1, 9247eaa44f6SJerome Brunet .shift = 27, 92527aad905SYixun Lan .lock = &meson_clk_lock, 9267eaa44f6SJerome Brunet .hw.init = &(struct clk_init_data){ 9277eaa44f6SJerome Brunet .name = "cts_i958", 9287eaa44f6SJerome Brunet .ops = &clk_mux_ops, 9297eaa44f6SJerome Brunet .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" }, 9307eaa44f6SJerome Brunet .num_parents = 2, 9317eaa44f6SJerome Brunet /* 9327eaa44f6SJerome Brunet *The parent is specific to origin of the audio data. Let the 9337eaa44f6SJerome Brunet * consumer choose the appropriate parent 9347eaa44f6SJerome Brunet */ 9357eaa44f6SJerome Brunet .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 9367eaa44f6SJerome Brunet }, 9377eaa44f6SJerome Brunet }; 9387eaa44f6SJerome Brunet 93914c735c8SNeil Armstrong static struct clk_divider gxbb_32k_clk_div = { 94014c735c8SNeil Armstrong .reg = (void *)HHI_32K_CLK_CNTL, 94114c735c8SNeil Armstrong .shift = 0, 94214c735c8SNeil Armstrong .width = 14, 94327aad905SYixun Lan .lock = &meson_clk_lock, 94414c735c8SNeil Armstrong .hw.init = &(struct clk_init_data){ 94514c735c8SNeil Armstrong .name = "32k_clk_div", 94614c735c8SNeil Armstrong .ops = &clk_divider_ops, 94714c735c8SNeil Armstrong .parent_names = (const char *[]){ "32k_clk_sel" }, 94814c735c8SNeil Armstrong .num_parents = 1, 94914c735c8SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, 95014c735c8SNeil Armstrong }, 95114c735c8SNeil Armstrong }; 95214c735c8SNeil Armstrong 95314c735c8SNeil Armstrong static struct clk_gate gxbb_32k_clk = { 95414c735c8SNeil Armstrong .reg = (void *)HHI_32K_CLK_CNTL, 95514c735c8SNeil Armstrong .bit_idx = 15, 95627aad905SYixun Lan .lock = &meson_clk_lock, 95714c735c8SNeil Armstrong .hw.init = &(struct clk_init_data){ 95814c735c8SNeil Armstrong .name = "32k_clk", 95914c735c8SNeil Armstrong .ops = &clk_gate_ops, 96014c735c8SNeil Armstrong .parent_names = (const char *[]){ "32k_clk_div" }, 96114c735c8SNeil Armstrong .num_parents = 1, 96214c735c8SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 96314c735c8SNeil Armstrong }, 96414c735c8SNeil Armstrong }; 96514c735c8SNeil Armstrong 966c3c4cb8dSStephen Boyd static const char * const gxbb_32k_clk_parent_names[] = { 96714c735c8SNeil Armstrong "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5" 96814c735c8SNeil Armstrong }; 96914c735c8SNeil Armstrong 97014c735c8SNeil Armstrong static struct clk_mux gxbb_32k_clk_sel = { 97114c735c8SNeil Armstrong .reg = (void *)HHI_32K_CLK_CNTL, 97214c735c8SNeil Armstrong .mask = 0x3, 97314c735c8SNeil Armstrong .shift = 16, 97427aad905SYixun Lan .lock = &meson_clk_lock, 97514c735c8SNeil Armstrong .hw.init = &(struct clk_init_data){ 97614c735c8SNeil Armstrong .name = "32k_clk_sel", 97714c735c8SNeil Armstrong .ops = &clk_mux_ops, 97814c735c8SNeil Armstrong .parent_names = gxbb_32k_clk_parent_names, 97914c735c8SNeil Armstrong .num_parents = 4, 98014c735c8SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 98114c735c8SNeil Armstrong }, 98214c735c8SNeil Armstrong }; 98314c735c8SNeil Armstrong 984914e6e80SJerome Brunet static const char * const gxbb_sd_emmc_clk0_parent_names[] = { 985914e6e80SJerome Brunet "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", 986914e6e80SJerome Brunet 987914e6e80SJerome Brunet /* 988914e6e80SJerome Brunet * Following these parent clocks, we should also have had mpll2, mpll3 989914e6e80SJerome Brunet * and gp0_pll but these clocks are too precious to be used here. All 990914e6e80SJerome Brunet * the necessary rates for MMC and NAND operation can be acheived using 991914e6e80SJerome Brunet * xtal or fclk_div clocks 992914e6e80SJerome Brunet */ 993914e6e80SJerome Brunet }; 994914e6e80SJerome Brunet 995914e6e80SJerome Brunet /* SDIO clock */ 996914e6e80SJerome Brunet static struct clk_mux gxbb_sd_emmc_a_clk0_sel = { 997914e6e80SJerome Brunet .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 998914e6e80SJerome Brunet .mask = 0x7, 999914e6e80SJerome Brunet .shift = 9, 100027aad905SYixun Lan .lock = &meson_clk_lock, 1001914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1002914e6e80SJerome Brunet .name = "sd_emmc_a_clk0_sel", 1003914e6e80SJerome Brunet .ops = &clk_mux_ops, 1004914e6e80SJerome Brunet .parent_names = gxbb_sd_emmc_clk0_parent_names, 1005914e6e80SJerome Brunet .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1006914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1007914e6e80SJerome Brunet }, 1008914e6e80SJerome Brunet }; 1009914e6e80SJerome Brunet 1010914e6e80SJerome Brunet static struct clk_divider gxbb_sd_emmc_a_clk0_div = { 1011914e6e80SJerome Brunet .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 1012914e6e80SJerome Brunet .shift = 0, 1013914e6e80SJerome Brunet .width = 7, 101427aad905SYixun Lan .lock = &meson_clk_lock, 1015914e6e80SJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 1016914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1017914e6e80SJerome Brunet .name = "sd_emmc_a_clk0_div", 1018914e6e80SJerome Brunet .ops = &clk_divider_ops, 1019914e6e80SJerome Brunet .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" }, 1020914e6e80SJerome Brunet .num_parents = 1, 1021914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1022914e6e80SJerome Brunet }, 1023914e6e80SJerome Brunet }; 1024914e6e80SJerome Brunet 1025914e6e80SJerome Brunet static struct clk_gate gxbb_sd_emmc_a_clk0 = { 1026914e6e80SJerome Brunet .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 1027914e6e80SJerome Brunet .bit_idx = 7, 102827aad905SYixun Lan .lock = &meson_clk_lock, 1029914e6e80SJerome Brunet .hw.init = &(struct clk_init_data){ 1030914e6e80SJerome Brunet .name = "sd_emmc_a_clk0", 1031914e6e80SJerome Brunet .ops = &clk_gate_ops, 1032914e6e80SJerome Brunet .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" }, 1033914e6e80SJerome Brunet .num_parents = 1, 1034ed3fb5afSJerome Brunet .flags = CLK_SET_RATE_PARENT, 1035914e6e80SJerome Brunet }, 1036914e6e80SJerome Brunet }; 1037914e6e80SJerome Brunet 1038914e6e80SJerome Brunet /* SDcard clock */ 1039914e6e80SJerome Brunet static struct clk_mux gxbb_sd_emmc_b_clk0_sel = { 1040914e6e80SJerome Brunet .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 1041914e6e80SJerome Brunet .mask = 0x7, 1042914e6e80SJerome Brunet .shift = 25, 104327aad905SYixun Lan .lock = &meson_clk_lock, 1044914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1045914e6e80SJerome Brunet .name = "sd_emmc_b_clk0_sel", 1046914e6e80SJerome Brunet .ops = &clk_mux_ops, 1047914e6e80SJerome Brunet .parent_names = gxbb_sd_emmc_clk0_parent_names, 1048914e6e80SJerome Brunet .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1049914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1050914e6e80SJerome Brunet }, 1051914e6e80SJerome Brunet }; 1052914e6e80SJerome Brunet 1053914e6e80SJerome Brunet static struct clk_divider gxbb_sd_emmc_b_clk0_div = { 1054914e6e80SJerome Brunet .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 1055914e6e80SJerome Brunet .shift = 16, 1056914e6e80SJerome Brunet .width = 7, 105727aad905SYixun Lan .lock = &meson_clk_lock, 1058914e6e80SJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 1059914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1060914e6e80SJerome Brunet .name = "sd_emmc_b_clk0_div", 1061914e6e80SJerome Brunet .ops = &clk_divider_ops, 1062914e6e80SJerome Brunet .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, 1063914e6e80SJerome Brunet .num_parents = 1, 1064914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1065914e6e80SJerome Brunet }, 1066914e6e80SJerome Brunet }; 1067914e6e80SJerome Brunet 1068914e6e80SJerome Brunet static struct clk_gate gxbb_sd_emmc_b_clk0 = { 1069914e6e80SJerome Brunet .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 1070914e6e80SJerome Brunet .bit_idx = 23, 107127aad905SYixun Lan .lock = &meson_clk_lock, 1072914e6e80SJerome Brunet .hw.init = &(struct clk_init_data){ 1073914e6e80SJerome Brunet .name = "sd_emmc_b_clk0", 1074914e6e80SJerome Brunet .ops = &clk_gate_ops, 1075914e6e80SJerome Brunet .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, 1076914e6e80SJerome Brunet .num_parents = 1, 1077ed3fb5afSJerome Brunet .flags = CLK_SET_RATE_PARENT, 1078914e6e80SJerome Brunet }, 1079914e6e80SJerome Brunet }; 1080914e6e80SJerome Brunet 1081914e6e80SJerome Brunet /* EMMC/NAND clock */ 1082914e6e80SJerome Brunet static struct clk_mux gxbb_sd_emmc_c_clk0_sel = { 1083914e6e80SJerome Brunet .reg = (void *)HHI_NAND_CLK_CNTL, 1084914e6e80SJerome Brunet .mask = 0x7, 1085914e6e80SJerome Brunet .shift = 9, 108627aad905SYixun Lan .lock = &meson_clk_lock, 1087914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1088914e6e80SJerome Brunet .name = "sd_emmc_c_clk0_sel", 1089914e6e80SJerome Brunet .ops = &clk_mux_ops, 1090914e6e80SJerome Brunet .parent_names = gxbb_sd_emmc_clk0_parent_names, 1091914e6e80SJerome Brunet .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1092914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1093914e6e80SJerome Brunet }, 1094914e6e80SJerome Brunet }; 1095914e6e80SJerome Brunet 1096914e6e80SJerome Brunet static struct clk_divider gxbb_sd_emmc_c_clk0_div = { 1097914e6e80SJerome Brunet .reg = (void *)HHI_NAND_CLK_CNTL, 1098914e6e80SJerome Brunet .shift = 0, 1099914e6e80SJerome Brunet .width = 7, 110027aad905SYixun Lan .lock = &meson_clk_lock, 1101914e6e80SJerome Brunet .flags = CLK_DIVIDER_ROUND_CLOSEST, 1102914e6e80SJerome Brunet .hw.init = &(struct clk_init_data) { 1103914e6e80SJerome Brunet .name = "sd_emmc_c_clk0_div", 1104914e6e80SJerome Brunet .ops = &clk_divider_ops, 1105914e6e80SJerome Brunet .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, 1106914e6e80SJerome Brunet .num_parents = 1, 1107914e6e80SJerome Brunet .flags = CLK_SET_RATE_PARENT, 1108914e6e80SJerome Brunet }, 1109914e6e80SJerome Brunet }; 1110914e6e80SJerome Brunet 1111914e6e80SJerome Brunet static struct clk_gate gxbb_sd_emmc_c_clk0 = { 1112914e6e80SJerome Brunet .reg = (void *)HHI_NAND_CLK_CNTL, 1113914e6e80SJerome Brunet .bit_idx = 7, 111427aad905SYixun Lan .lock = &meson_clk_lock, 1115914e6e80SJerome Brunet .hw.init = &(struct clk_init_data){ 1116914e6e80SJerome Brunet .name = "sd_emmc_c_clk0", 1117914e6e80SJerome Brunet .ops = &clk_gate_ops, 1118914e6e80SJerome Brunet .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, 1119914e6e80SJerome Brunet .num_parents = 1, 1120ed3fb5afSJerome Brunet .flags = CLK_SET_RATE_PARENT, 1121914e6e80SJerome Brunet }, 1122914e6e80SJerome Brunet }; 1123914e6e80SJerome Brunet 1124762a1f20SNeil Armstrong /* VPU Clock */ 1125762a1f20SNeil Armstrong 1126762a1f20SNeil Armstrong static u32 mux_table_vpu[] = {0, 1, 2, 3}; 1127762a1f20SNeil Armstrong static const char * const gxbb_vpu_parent_names[] = { 1128762a1f20SNeil Armstrong "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1129762a1f20SNeil Armstrong }; 1130762a1f20SNeil Armstrong 1131762a1f20SNeil Armstrong static struct clk_mux gxbb_vpu_0_sel = { 1132762a1f20SNeil Armstrong .reg = (void *)HHI_VPU_CLK_CNTL, 1133762a1f20SNeil Armstrong .mask = 0x3, 1134762a1f20SNeil Armstrong .shift = 9, 113527aad905SYixun Lan .lock = &meson_clk_lock, 1136762a1f20SNeil Armstrong .table = mux_table_vpu, 1137762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1138762a1f20SNeil Armstrong .name = "vpu_0_sel", 1139762a1f20SNeil Armstrong .ops = &clk_mux_ops, 1140762a1f20SNeil Armstrong /* 1141762a1f20SNeil Armstrong * bits 9:10 selects from 4 possible parents: 1142762a1f20SNeil Armstrong * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1143762a1f20SNeil Armstrong */ 1144762a1f20SNeil Armstrong .parent_names = gxbb_vpu_parent_names, 1145762a1f20SNeil Armstrong .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names), 1146762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1147762a1f20SNeil Armstrong }, 1148762a1f20SNeil Armstrong }; 1149762a1f20SNeil Armstrong 1150762a1f20SNeil Armstrong static struct clk_divider gxbb_vpu_0_div = { 1151762a1f20SNeil Armstrong .reg = (void *)HHI_VPU_CLK_CNTL, 1152762a1f20SNeil Armstrong .shift = 0, 1153762a1f20SNeil Armstrong .width = 7, 115427aad905SYixun Lan .lock = &meson_clk_lock, 1155762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1156762a1f20SNeil Armstrong .name = "vpu_0_div", 1157762a1f20SNeil Armstrong .ops = &clk_divider_ops, 1158762a1f20SNeil Armstrong .parent_names = (const char *[]){ "vpu_0_sel" }, 1159762a1f20SNeil Armstrong .num_parents = 1, 1160762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1161762a1f20SNeil Armstrong }, 1162762a1f20SNeil Armstrong }; 1163762a1f20SNeil Armstrong 1164762a1f20SNeil Armstrong static struct clk_gate gxbb_vpu_0 = { 1165762a1f20SNeil Armstrong .reg = (void *)HHI_VPU_CLK_CNTL, 1166762a1f20SNeil Armstrong .bit_idx = 8, 116727aad905SYixun Lan .lock = &meson_clk_lock, 1168762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1169762a1f20SNeil Armstrong .name = "vpu_0", 1170762a1f20SNeil Armstrong .ops = &clk_gate_ops, 1171762a1f20SNeil Armstrong .parent_names = (const char *[]){ "vpu_0_div" }, 1172762a1f20SNeil Armstrong .num_parents = 1, 1173762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1174762a1f20SNeil Armstrong }, 1175762a1f20SNeil Armstrong }; 1176762a1f20SNeil Armstrong 1177762a1f20SNeil Armstrong static struct clk_mux gxbb_vpu_1_sel = { 1178762a1f20SNeil Armstrong .reg = (void *)HHI_VPU_CLK_CNTL, 1179762a1f20SNeil Armstrong .mask = 0x3, 1180762a1f20SNeil Armstrong .shift = 25, 118127aad905SYixun Lan .lock = &meson_clk_lock, 1182762a1f20SNeil Armstrong .table = mux_table_vpu, 1183762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1184762a1f20SNeil Armstrong .name = "vpu_1_sel", 1185762a1f20SNeil Armstrong .ops = &clk_mux_ops, 1186762a1f20SNeil Armstrong /* 1187762a1f20SNeil Armstrong * bits 25:26 selects from 4 possible parents: 1188762a1f20SNeil Armstrong * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1189762a1f20SNeil Armstrong */ 1190762a1f20SNeil Armstrong .parent_names = gxbb_vpu_parent_names, 1191762a1f20SNeil Armstrong .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names), 1192762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1193762a1f20SNeil Armstrong }, 1194762a1f20SNeil Armstrong }; 1195762a1f20SNeil Armstrong 1196762a1f20SNeil Armstrong static struct clk_divider gxbb_vpu_1_div = { 1197762a1f20SNeil Armstrong .reg = (void *)HHI_VPU_CLK_CNTL, 1198762a1f20SNeil Armstrong .shift = 16, 1199762a1f20SNeil Armstrong .width = 7, 120027aad905SYixun Lan .lock = &meson_clk_lock, 1201762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1202762a1f20SNeil Armstrong .name = "vpu_1_div", 1203762a1f20SNeil Armstrong .ops = &clk_divider_ops, 1204762a1f20SNeil Armstrong .parent_names = (const char *[]){ "vpu_1_sel" }, 1205762a1f20SNeil Armstrong .num_parents = 1, 1206762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1207762a1f20SNeil Armstrong }, 1208762a1f20SNeil Armstrong }; 1209762a1f20SNeil Armstrong 1210762a1f20SNeil Armstrong static struct clk_gate gxbb_vpu_1 = { 1211762a1f20SNeil Armstrong .reg = (void *)HHI_VPU_CLK_CNTL, 1212762a1f20SNeil Armstrong .bit_idx = 24, 121327aad905SYixun Lan .lock = &meson_clk_lock, 1214762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1215762a1f20SNeil Armstrong .name = "vpu_1", 1216762a1f20SNeil Armstrong .ops = &clk_gate_ops, 1217762a1f20SNeil Armstrong .parent_names = (const char *[]){ "vpu_1_div" }, 1218762a1f20SNeil Armstrong .num_parents = 1, 1219762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1220762a1f20SNeil Armstrong }, 1221762a1f20SNeil Armstrong }; 1222762a1f20SNeil Armstrong 1223762a1f20SNeil Armstrong static struct clk_mux gxbb_vpu = { 1224762a1f20SNeil Armstrong .reg = (void *)HHI_VPU_CLK_CNTL, 1225762a1f20SNeil Armstrong .mask = 1, 1226762a1f20SNeil Armstrong .shift = 31, 122727aad905SYixun Lan .lock = &meson_clk_lock, 1228762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1229762a1f20SNeil Armstrong .name = "vpu", 1230762a1f20SNeil Armstrong .ops = &clk_mux_ops, 1231762a1f20SNeil Armstrong /* 1232762a1f20SNeil Armstrong * bit 31 selects from 2 possible parents: 1233762a1f20SNeil Armstrong * vpu_0 or vpu_1 1234762a1f20SNeil Armstrong */ 1235762a1f20SNeil Armstrong .parent_names = (const char *[]){ "vpu_0", "vpu_1" }, 1236762a1f20SNeil Armstrong .num_parents = 2, 1237762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1238762a1f20SNeil Armstrong }, 1239762a1f20SNeil Armstrong }; 1240762a1f20SNeil Armstrong 1241762a1f20SNeil Armstrong /* VAPB Clock */ 1242762a1f20SNeil Armstrong 1243762a1f20SNeil Armstrong static u32 mux_table_vapb[] = {0, 1, 2, 3}; 1244762a1f20SNeil Armstrong static const char * const gxbb_vapb_parent_names[] = { 1245762a1f20SNeil Armstrong "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1246762a1f20SNeil Armstrong }; 1247762a1f20SNeil Armstrong 1248762a1f20SNeil Armstrong static struct clk_mux gxbb_vapb_0_sel = { 1249762a1f20SNeil Armstrong .reg = (void *)HHI_VAPBCLK_CNTL, 1250762a1f20SNeil Armstrong .mask = 0x3, 1251762a1f20SNeil Armstrong .shift = 9, 125227aad905SYixun Lan .lock = &meson_clk_lock, 1253762a1f20SNeil Armstrong .table = mux_table_vapb, 1254762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1255762a1f20SNeil Armstrong .name = "vapb_0_sel", 1256762a1f20SNeil Armstrong .ops = &clk_mux_ops, 1257762a1f20SNeil Armstrong /* 1258762a1f20SNeil Armstrong * bits 9:10 selects from 4 possible parents: 1259762a1f20SNeil Armstrong * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1260762a1f20SNeil Armstrong */ 1261762a1f20SNeil Armstrong .parent_names = gxbb_vapb_parent_names, 1262762a1f20SNeil Armstrong .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names), 1263762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1264762a1f20SNeil Armstrong }, 1265762a1f20SNeil Armstrong }; 1266762a1f20SNeil Armstrong 1267762a1f20SNeil Armstrong static struct clk_divider gxbb_vapb_0_div = { 1268762a1f20SNeil Armstrong .reg = (void *)HHI_VAPBCLK_CNTL, 1269762a1f20SNeil Armstrong .shift = 0, 1270762a1f20SNeil Armstrong .width = 7, 127127aad905SYixun Lan .lock = &meson_clk_lock, 1272762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1273762a1f20SNeil Armstrong .name = "vapb_0_div", 1274762a1f20SNeil Armstrong .ops = &clk_divider_ops, 1275762a1f20SNeil Armstrong .parent_names = (const char *[]){ "vapb_0_sel" }, 1276762a1f20SNeil Armstrong .num_parents = 1, 1277762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1278762a1f20SNeil Armstrong }, 1279762a1f20SNeil Armstrong }; 1280762a1f20SNeil Armstrong 1281762a1f20SNeil Armstrong static struct clk_gate gxbb_vapb_0 = { 1282762a1f20SNeil Armstrong .reg = (void *)HHI_VAPBCLK_CNTL, 1283762a1f20SNeil Armstrong .bit_idx = 8, 128427aad905SYixun Lan .lock = &meson_clk_lock, 1285762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1286762a1f20SNeil Armstrong .name = "vapb_0", 1287762a1f20SNeil Armstrong .ops = &clk_gate_ops, 1288762a1f20SNeil Armstrong .parent_names = (const char *[]){ "vapb_0_div" }, 1289762a1f20SNeil Armstrong .num_parents = 1, 1290762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1291762a1f20SNeil Armstrong }, 1292762a1f20SNeil Armstrong }; 1293762a1f20SNeil Armstrong 1294762a1f20SNeil Armstrong static struct clk_mux gxbb_vapb_1_sel = { 1295762a1f20SNeil Armstrong .reg = (void *)HHI_VAPBCLK_CNTL, 1296762a1f20SNeil Armstrong .mask = 0x3, 1297762a1f20SNeil Armstrong .shift = 25, 129827aad905SYixun Lan .lock = &meson_clk_lock, 1299762a1f20SNeil Armstrong .table = mux_table_vapb, 1300762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1301762a1f20SNeil Armstrong .name = "vapb_1_sel", 1302762a1f20SNeil Armstrong .ops = &clk_mux_ops, 1303762a1f20SNeil Armstrong /* 1304762a1f20SNeil Armstrong * bits 25:26 selects from 4 possible parents: 1305762a1f20SNeil Armstrong * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1306762a1f20SNeil Armstrong */ 1307762a1f20SNeil Armstrong .parent_names = gxbb_vapb_parent_names, 1308762a1f20SNeil Armstrong .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names), 1309762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1310762a1f20SNeil Armstrong }, 1311762a1f20SNeil Armstrong }; 1312762a1f20SNeil Armstrong 1313762a1f20SNeil Armstrong static struct clk_divider gxbb_vapb_1_div = { 1314762a1f20SNeil Armstrong .reg = (void *)HHI_VAPBCLK_CNTL, 1315762a1f20SNeil Armstrong .shift = 16, 1316762a1f20SNeil Armstrong .width = 7, 131727aad905SYixun Lan .lock = &meson_clk_lock, 1318762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1319762a1f20SNeil Armstrong .name = "vapb_1_div", 1320762a1f20SNeil Armstrong .ops = &clk_divider_ops, 1321762a1f20SNeil Armstrong .parent_names = (const char *[]){ "vapb_1_sel" }, 1322762a1f20SNeil Armstrong .num_parents = 1, 1323762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT, 1324762a1f20SNeil Armstrong }, 1325762a1f20SNeil Armstrong }; 1326762a1f20SNeil Armstrong 1327762a1f20SNeil Armstrong static struct clk_gate gxbb_vapb_1 = { 1328762a1f20SNeil Armstrong .reg = (void *)HHI_VAPBCLK_CNTL, 1329762a1f20SNeil Armstrong .bit_idx = 24, 133027aad905SYixun Lan .lock = &meson_clk_lock, 1331762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1332762a1f20SNeil Armstrong .name = "vapb_1", 1333762a1f20SNeil Armstrong .ops = &clk_gate_ops, 1334762a1f20SNeil Armstrong .parent_names = (const char *[]){ "vapb_1_div" }, 1335762a1f20SNeil Armstrong .num_parents = 1, 1336762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1337762a1f20SNeil Armstrong }, 1338762a1f20SNeil Armstrong }; 1339762a1f20SNeil Armstrong 1340762a1f20SNeil Armstrong static struct clk_mux gxbb_vapb_sel = { 1341762a1f20SNeil Armstrong .reg = (void *)HHI_VAPBCLK_CNTL, 1342762a1f20SNeil Armstrong .mask = 1, 1343762a1f20SNeil Armstrong .shift = 31, 134427aad905SYixun Lan .lock = &meson_clk_lock, 1345762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data){ 1346762a1f20SNeil Armstrong .name = "vapb_sel", 1347762a1f20SNeil Armstrong .ops = &clk_mux_ops, 1348762a1f20SNeil Armstrong /* 1349762a1f20SNeil Armstrong * bit 31 selects from 2 possible parents: 1350762a1f20SNeil Armstrong * vapb_0 or vapb_1 1351762a1f20SNeil Armstrong */ 1352762a1f20SNeil Armstrong .parent_names = (const char *[]){ "vapb_0", "vapb_1" }, 1353762a1f20SNeil Armstrong .num_parents = 2, 1354762a1f20SNeil Armstrong .flags = CLK_SET_RATE_NO_REPARENT, 1355762a1f20SNeil Armstrong }, 1356762a1f20SNeil Armstrong }; 1357762a1f20SNeil Armstrong 1358762a1f20SNeil Armstrong static struct clk_gate gxbb_vapb = { 1359762a1f20SNeil Armstrong .reg = (void *)HHI_VAPBCLK_CNTL, 1360762a1f20SNeil Armstrong .bit_idx = 30, 136127aad905SYixun Lan .lock = &meson_clk_lock, 1362762a1f20SNeil Armstrong .hw.init = &(struct clk_init_data) { 1363762a1f20SNeil Armstrong .name = "vapb", 1364762a1f20SNeil Armstrong .ops = &clk_gate_ops, 1365762a1f20SNeil Armstrong .parent_names = (const char *[]){ "vapb_sel" }, 1366762a1f20SNeil Armstrong .num_parents = 1, 1367762a1f20SNeil Armstrong .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1368762a1f20SNeil Armstrong }, 1369762a1f20SNeil Armstrong }; 1370762a1f20SNeil Armstrong 1371738f66d3SMichael Turquette /* Everything Else (EE) domain gates */ 13727ba64d82SAlexander Müller static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 13737ba64d82SAlexander Müller static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); 13747ba64d82SAlexander Müller static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5); 13757ba64d82SAlexander Müller static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6); 13767ba64d82SAlexander Müller static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7); 13777ba64d82SAlexander Müller static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8); 13787ba64d82SAlexander Müller static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9); 137975eccf5eSYixun Lan static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10); 13807ba64d82SAlexander Müller static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11); 13817ba64d82SAlexander Müller static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12); 13827ba64d82SAlexander Müller static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13); 13837ba64d82SAlexander Müller static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14); 13847ba64d82SAlexander Müller static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15); 13857ba64d82SAlexander Müller static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16); 13867ba64d82SAlexander Müller static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17); 13877ba64d82SAlexander Müller static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18); 13887ba64d82SAlexander Müller static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19); 13897ba64d82SAlexander Müller static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); 13907ba64d82SAlexander Müller static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24); 13917ba64d82SAlexander Müller static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25); 13927ba64d82SAlexander Müller static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26); 13937ba64d82SAlexander Müller static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30); 1394738f66d3SMichael Turquette 13957ba64d82SAlexander Müller static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2); 13967ba64d82SAlexander Müller static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3); 13977ba64d82SAlexander Müller static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4); 13987ba64d82SAlexander Müller static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6); 13997ba64d82SAlexander Müller static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7); 14007ba64d82SAlexander Müller static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8); 14017ba64d82SAlexander Müller static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9); 14027ba64d82SAlexander Müller static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10); 14037ba64d82SAlexander Müller static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11); 14047ba64d82SAlexander Müller static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12); 14057ba64d82SAlexander Müller static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13); 14067ba64d82SAlexander Müller static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14); 14077ba64d82SAlexander Müller static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15); 14087ba64d82SAlexander Müller static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16); 14097ba64d82SAlexander Müller static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20); 14107ba64d82SAlexander Müller static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21); 14117ba64d82SAlexander Müller static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22); 14127ba64d82SAlexander Müller static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23); 14137ba64d82SAlexander Müller static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24); 14147ba64d82SAlexander Müller static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25); 14157ba64d82SAlexander Müller static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26); 14167ba64d82SAlexander Müller static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28); 14177ba64d82SAlexander Müller static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29); 14187ba64d82SAlexander Müller static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30); 14197ba64d82SAlexander Müller static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31); 1420738f66d3SMichael Turquette 14217ba64d82SAlexander Müller static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1); 14227ba64d82SAlexander Müller static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 14237ba64d82SAlexander Müller static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); 14247ba64d82SAlexander Müller static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4); 14257ba64d82SAlexander Müller static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); 14267ba64d82SAlexander Müller static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); 14277ba64d82SAlexander Müller static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); 14287ba64d82SAlexander Müller static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12); 14297ba64d82SAlexander Müller static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15); 143075eccf5eSYixun Lan static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22); 14317ba64d82SAlexander Müller static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); 14327ba64d82SAlexander Müller static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 14337ba64d82SAlexander Müller static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); 1434738f66d3SMichael Turquette 14357ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1); 14367ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2); 14377ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3); 14387ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4); 14397ba64d82SAlexander Müller static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8); 14407ba64d82SAlexander Müller static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9); 14417ba64d82SAlexander Müller static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10); 14427ba64d82SAlexander Müller static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14); 14437ba64d82SAlexander Müller static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16); 14447ba64d82SAlexander Müller static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20); 14457ba64d82SAlexander Müller static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21); 14467ba64d82SAlexander Müller static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22); 14477ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24); 14487ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25); 14497ba64d82SAlexander Müller static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26); 14507ba64d82SAlexander Müller static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31); 1451738f66d3SMichael Turquette 1452738f66d3SMichael Turquette /* Always On (AO) domain gates */ 1453738f66d3SMichael Turquette 14547ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0); 14557ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1); 14567ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2); 14577ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3); 14587ba64d82SAlexander Müller static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4); 1459738f66d3SMichael Turquette 1460738f66d3SMichael Turquette /* Array of all clocks provided by this provider */ 1461738f66d3SMichael Turquette 1462738f66d3SMichael Turquette static struct clk_hw_onecell_data gxbb_hw_onecell_data = { 1463738f66d3SMichael Turquette .hws = { 1464738f66d3SMichael Turquette [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 1465738f66d3SMichael Turquette [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 1466738f66d3SMichael Turquette [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 1467738f66d3SMichael Turquette [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 1468738f66d3SMichael Turquette [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 1469738f66d3SMichael Turquette [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 1470738f66d3SMichael Turquette [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 1471738f66d3SMichael Turquette [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 1472738f66d3SMichael Turquette [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw, 1473738f66d3SMichael Turquette [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 1474738f66d3SMichael Turquette [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 1475738f66d3SMichael Turquette [CLKID_CLK81] = &gxbb_clk81.hw, 1476738f66d3SMichael Turquette [CLKID_MPLL0] = &gxbb_mpll0.hw, 1477738f66d3SMichael Turquette [CLKID_MPLL1] = &gxbb_mpll1.hw, 1478738f66d3SMichael Turquette [CLKID_MPLL2] = &gxbb_mpll2.hw, 1479738f66d3SMichael Turquette [CLKID_DDR] = &gxbb_ddr.hw, 1480738f66d3SMichael Turquette [CLKID_DOS] = &gxbb_dos.hw, 1481738f66d3SMichael Turquette [CLKID_ISA] = &gxbb_isa.hw, 1482738f66d3SMichael Turquette [CLKID_PL301] = &gxbb_pl301.hw, 1483738f66d3SMichael Turquette [CLKID_PERIPHS] = &gxbb_periphs.hw, 1484738f66d3SMichael Turquette [CLKID_SPICC] = &gxbb_spicc.hw, 1485738f66d3SMichael Turquette [CLKID_I2C] = &gxbb_i2c.hw, 1486738f66d3SMichael Turquette [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 1487738f66d3SMichael Turquette [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 1488738f66d3SMichael Turquette [CLKID_RNG0] = &gxbb_rng0.hw, 1489738f66d3SMichael Turquette [CLKID_UART0] = &gxbb_uart0.hw, 1490738f66d3SMichael Turquette [CLKID_SDHC] = &gxbb_sdhc.hw, 1491738f66d3SMichael Turquette [CLKID_STREAM] = &gxbb_stream.hw, 1492738f66d3SMichael Turquette [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 1493738f66d3SMichael Turquette [CLKID_SDIO] = &gxbb_sdio.hw, 1494738f66d3SMichael Turquette [CLKID_ABUF] = &gxbb_abuf.hw, 1495738f66d3SMichael Turquette [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 1496738f66d3SMichael Turquette [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 1497738f66d3SMichael Turquette [CLKID_SPI] = &gxbb_spi.hw, 1498738f66d3SMichael Turquette [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 1499738f66d3SMichael Turquette [CLKID_ETH] = &gxbb_eth.hw, 1500738f66d3SMichael Turquette [CLKID_DEMUX] = &gxbb_demux.hw, 1501738f66d3SMichael Turquette [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 1502738f66d3SMichael Turquette [CLKID_IEC958] = &gxbb_iec958.hw, 1503738f66d3SMichael Turquette [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 1504738f66d3SMichael Turquette [CLKID_AMCLK] = &gxbb_amclk.hw, 1505738f66d3SMichael Turquette [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 1506738f66d3SMichael Turquette [CLKID_MIXER] = &gxbb_mixer.hw, 1507738f66d3SMichael Turquette [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 1508738f66d3SMichael Turquette [CLKID_ADC] = &gxbb_adc.hw, 1509738f66d3SMichael Turquette [CLKID_BLKMV] = &gxbb_blkmv.hw, 1510738f66d3SMichael Turquette [CLKID_AIU] = &gxbb_aiu.hw, 1511738f66d3SMichael Turquette [CLKID_UART1] = &gxbb_uart1.hw, 1512738f66d3SMichael Turquette [CLKID_G2D] = &gxbb_g2d.hw, 1513738f66d3SMichael Turquette [CLKID_USB0] = &gxbb_usb0.hw, 1514738f66d3SMichael Turquette [CLKID_USB1] = &gxbb_usb1.hw, 1515738f66d3SMichael Turquette [CLKID_RESET] = &gxbb_reset.hw, 1516738f66d3SMichael Turquette [CLKID_NAND] = &gxbb_nand.hw, 1517738f66d3SMichael Turquette [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 1518738f66d3SMichael Turquette [CLKID_USB] = &gxbb_usb.hw, 1519738f66d3SMichael Turquette [CLKID_VDIN1] = &gxbb_vdin1.hw, 1520738f66d3SMichael Turquette [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 1521738f66d3SMichael Turquette [CLKID_EFUSE] = &gxbb_efuse.hw, 1522738f66d3SMichael Turquette [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 1523738f66d3SMichael Turquette [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 1524738f66d3SMichael Turquette [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 1525738f66d3SMichael Turquette [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 1526738f66d3SMichael Turquette [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 1527738f66d3SMichael Turquette [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 1528738f66d3SMichael Turquette [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 1529738f66d3SMichael Turquette [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 1530738f66d3SMichael Turquette [CLKID_DVIN] = &gxbb_dvin.hw, 1531738f66d3SMichael Turquette [CLKID_UART2] = &gxbb_uart2.hw, 1532738f66d3SMichael Turquette [CLKID_SANA] = &gxbb_sana.hw, 1533738f66d3SMichael Turquette [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 1534738f66d3SMichael Turquette [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 1535738f66d3SMichael Turquette [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 1536738f66d3SMichael Turquette [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 1537738f66d3SMichael Turquette [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 1538738f66d3SMichael Turquette [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 1539738f66d3SMichael Turquette [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 1540738f66d3SMichael Turquette [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 1541738f66d3SMichael Turquette [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 1542738f66d3SMichael Turquette [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 1543738f66d3SMichael Turquette [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 1544738f66d3SMichael Turquette [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 1545738f66d3SMichael Turquette [CLKID_ENC480P] = &gxbb_enc480p.hw, 1546738f66d3SMichael Turquette [CLKID_RNG1] = &gxbb_rng1.hw, 1547738f66d3SMichael Turquette [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 1548738f66d3SMichael Turquette [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 1549738f66d3SMichael Turquette [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 1550738f66d3SMichael Turquette [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 1551738f66d3SMichael Turquette [CLKID_EDP] = &gxbb_edp.hw, 1552738f66d3SMichael Turquette [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 1553738f66d3SMichael Turquette [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 1554738f66d3SMichael Turquette [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 1555738f66d3SMichael Turquette [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 1556738f66d3SMichael Turquette [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 155733608dcdSKevin Hilman [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 155833608dcdSKevin Hilman [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 155933608dcdSKevin Hilman [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 156033d0fcdfSMartin Blumenstingl [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 156133d0fcdfSMartin Blumenstingl [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 156233d0fcdfSMartin Blumenstingl [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 1563fac9a55bSNeil Armstrong [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 1564fac9a55bSNeil Armstrong [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 1565fac9a55bSNeil Armstrong [CLKID_MALI_0] = &gxbb_mali_0.hw, 1566fac9a55bSNeil Armstrong [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 1567fac9a55bSNeil Armstrong [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 1568fac9a55bSNeil Armstrong [CLKID_MALI_1] = &gxbb_mali_1.hw, 1569fac9a55bSNeil Armstrong [CLKID_MALI] = &gxbb_mali.hw, 15704087bd4bSJerome Brunet [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 15714087bd4bSJerome Brunet [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 15724087bd4bSJerome Brunet [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 15733c277c24SJerome Brunet [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 15743c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 15753c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 15767eaa44f6SJerome Brunet [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 157714c735c8SNeil Armstrong [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 157814c735c8SNeil Armstrong [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 157914c735c8SNeil Armstrong [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 1580914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 1581914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 1582914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 1583914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 1584914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 1585914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 1586914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 1587914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 1588914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 1589762a1f20SNeil Armstrong [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 1590762a1f20SNeil Armstrong [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 1591762a1f20SNeil Armstrong [CLKID_VPU_0] = &gxbb_vpu_0.hw, 1592762a1f20SNeil Armstrong [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 1593762a1f20SNeil Armstrong [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 1594762a1f20SNeil Armstrong [CLKID_VPU_1] = &gxbb_vpu_1.hw, 1595762a1f20SNeil Armstrong [CLKID_VPU] = &gxbb_vpu.hw, 1596762a1f20SNeil Armstrong [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 1597762a1f20SNeil Armstrong [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 1598762a1f20SNeil Armstrong [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 1599762a1f20SNeil Armstrong [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 1600762a1f20SNeil Armstrong [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 1601762a1f20SNeil Armstrong [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 1602762a1f20SNeil Armstrong [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 1603762a1f20SNeil Armstrong [CLKID_VAPB] = &gxbb_vapb.hw, 16041f6f1dcbSJerome Brunet [NR_CLKS] = NULL, 1605738f66d3SMichael Turquette }, 1606738f66d3SMichael Turquette .num = NR_CLKS, 1607738f66d3SMichael Turquette }; 1608738f66d3SMichael Turquette 16090d48fc55SNeil Armstrong static struct clk_hw_onecell_data gxl_hw_onecell_data = { 16100d48fc55SNeil Armstrong .hws = { 16110d48fc55SNeil Armstrong [CLKID_SYS_PLL] = &gxbb_sys_pll.hw, 16120d48fc55SNeil Armstrong [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw, 16130d48fc55SNeil Armstrong [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw, 16140d48fc55SNeil Armstrong [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw, 16150d48fc55SNeil Armstrong [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw, 16160d48fc55SNeil Armstrong [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw, 16170d48fc55SNeil Armstrong [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw, 16180d48fc55SNeil Armstrong [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw, 16190d48fc55SNeil Armstrong [CLKID_GP0_PLL] = &gxl_gp0_pll.hw, 16200d48fc55SNeil Armstrong [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw, 16210d48fc55SNeil Armstrong [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw, 16220d48fc55SNeil Armstrong [CLKID_CLK81] = &gxbb_clk81.hw, 16230d48fc55SNeil Armstrong [CLKID_MPLL0] = &gxbb_mpll0.hw, 16240d48fc55SNeil Armstrong [CLKID_MPLL1] = &gxbb_mpll1.hw, 16250d48fc55SNeil Armstrong [CLKID_MPLL2] = &gxbb_mpll2.hw, 16260d48fc55SNeil Armstrong [CLKID_DDR] = &gxbb_ddr.hw, 16270d48fc55SNeil Armstrong [CLKID_DOS] = &gxbb_dos.hw, 16280d48fc55SNeil Armstrong [CLKID_ISA] = &gxbb_isa.hw, 16290d48fc55SNeil Armstrong [CLKID_PL301] = &gxbb_pl301.hw, 16300d48fc55SNeil Armstrong [CLKID_PERIPHS] = &gxbb_periphs.hw, 16310d48fc55SNeil Armstrong [CLKID_SPICC] = &gxbb_spicc.hw, 16320d48fc55SNeil Armstrong [CLKID_I2C] = &gxbb_i2c.hw, 16330d48fc55SNeil Armstrong [CLKID_SAR_ADC] = &gxbb_sar_adc.hw, 16340d48fc55SNeil Armstrong [CLKID_SMART_CARD] = &gxbb_smart_card.hw, 16350d48fc55SNeil Armstrong [CLKID_RNG0] = &gxbb_rng0.hw, 16360d48fc55SNeil Armstrong [CLKID_UART0] = &gxbb_uart0.hw, 16370d48fc55SNeil Armstrong [CLKID_SDHC] = &gxbb_sdhc.hw, 16380d48fc55SNeil Armstrong [CLKID_STREAM] = &gxbb_stream.hw, 16390d48fc55SNeil Armstrong [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw, 16400d48fc55SNeil Armstrong [CLKID_SDIO] = &gxbb_sdio.hw, 16410d48fc55SNeil Armstrong [CLKID_ABUF] = &gxbb_abuf.hw, 16420d48fc55SNeil Armstrong [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw, 16430d48fc55SNeil Armstrong [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw, 16440d48fc55SNeil Armstrong [CLKID_SPI] = &gxbb_spi.hw, 16450d48fc55SNeil Armstrong [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw, 16460d48fc55SNeil Armstrong [CLKID_ETH] = &gxbb_eth.hw, 16470d48fc55SNeil Armstrong [CLKID_DEMUX] = &gxbb_demux.hw, 16480d48fc55SNeil Armstrong [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw, 16490d48fc55SNeil Armstrong [CLKID_IEC958] = &gxbb_iec958.hw, 16500d48fc55SNeil Armstrong [CLKID_I2S_OUT] = &gxbb_i2s_out.hw, 16510d48fc55SNeil Armstrong [CLKID_AMCLK] = &gxbb_amclk.hw, 16520d48fc55SNeil Armstrong [CLKID_AIFIFO2] = &gxbb_aififo2.hw, 16530d48fc55SNeil Armstrong [CLKID_MIXER] = &gxbb_mixer.hw, 16540d48fc55SNeil Armstrong [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw, 16550d48fc55SNeil Armstrong [CLKID_ADC] = &gxbb_adc.hw, 16560d48fc55SNeil Armstrong [CLKID_BLKMV] = &gxbb_blkmv.hw, 16570d48fc55SNeil Armstrong [CLKID_AIU] = &gxbb_aiu.hw, 16580d48fc55SNeil Armstrong [CLKID_UART1] = &gxbb_uart1.hw, 16590d48fc55SNeil Armstrong [CLKID_G2D] = &gxbb_g2d.hw, 16600d48fc55SNeil Armstrong [CLKID_USB0] = &gxbb_usb0.hw, 16610d48fc55SNeil Armstrong [CLKID_USB1] = &gxbb_usb1.hw, 16620d48fc55SNeil Armstrong [CLKID_RESET] = &gxbb_reset.hw, 16630d48fc55SNeil Armstrong [CLKID_NAND] = &gxbb_nand.hw, 16640d48fc55SNeil Armstrong [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw, 16650d48fc55SNeil Armstrong [CLKID_USB] = &gxbb_usb.hw, 16660d48fc55SNeil Armstrong [CLKID_VDIN1] = &gxbb_vdin1.hw, 16670d48fc55SNeil Armstrong [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw, 16680d48fc55SNeil Armstrong [CLKID_EFUSE] = &gxbb_efuse.hw, 16690d48fc55SNeil Armstrong [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw, 16700d48fc55SNeil Armstrong [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw, 16710d48fc55SNeil Armstrong [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw, 16720d48fc55SNeil Armstrong [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw, 16730d48fc55SNeil Armstrong [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw, 16740d48fc55SNeil Armstrong [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw, 16750d48fc55SNeil Armstrong [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw, 16760d48fc55SNeil Armstrong [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw, 16770d48fc55SNeil Armstrong [CLKID_DVIN] = &gxbb_dvin.hw, 16780d48fc55SNeil Armstrong [CLKID_UART2] = &gxbb_uart2.hw, 16790d48fc55SNeil Armstrong [CLKID_SANA] = &gxbb_sana.hw, 16800d48fc55SNeil Armstrong [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw, 16810d48fc55SNeil Armstrong [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw, 16820d48fc55SNeil Armstrong [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw, 16830d48fc55SNeil Armstrong [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw, 16840d48fc55SNeil Armstrong [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw, 16850d48fc55SNeil Armstrong [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw, 16860d48fc55SNeil Armstrong [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw, 16870d48fc55SNeil Armstrong [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw, 16880d48fc55SNeil Armstrong [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw, 16890d48fc55SNeil Armstrong [CLKID_DAC_CLK] = &gxbb_dac_clk.hw, 16900d48fc55SNeil Armstrong [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw, 16910d48fc55SNeil Armstrong [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw, 16920d48fc55SNeil Armstrong [CLKID_ENC480P] = &gxbb_enc480p.hw, 16930d48fc55SNeil Armstrong [CLKID_RNG1] = &gxbb_rng1.hw, 16940d48fc55SNeil Armstrong [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw, 16950d48fc55SNeil Armstrong [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw, 16960d48fc55SNeil Armstrong [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw, 16970d48fc55SNeil Armstrong [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw, 16980d48fc55SNeil Armstrong [CLKID_EDP] = &gxbb_edp.hw, 16990d48fc55SNeil Armstrong [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw, 17000d48fc55SNeil Armstrong [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw, 17010d48fc55SNeil Armstrong [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw, 17020d48fc55SNeil Armstrong [CLKID_AO_IFACE] = &gxbb_ao_iface.hw, 17030d48fc55SNeil Armstrong [CLKID_AO_I2C] = &gxbb_ao_i2c.hw, 17040d48fc55SNeil Armstrong [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw, 17050d48fc55SNeil Armstrong [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw, 17060d48fc55SNeil Armstrong [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw, 17070d48fc55SNeil Armstrong [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 17080d48fc55SNeil Armstrong [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 17090d48fc55SNeil Armstrong [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 17100d48fc55SNeil Armstrong [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw, 17110d48fc55SNeil Armstrong [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw, 17120d48fc55SNeil Armstrong [CLKID_MALI_0] = &gxbb_mali_0.hw, 17130d48fc55SNeil Armstrong [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw, 17140d48fc55SNeil Armstrong [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw, 17150d48fc55SNeil Armstrong [CLKID_MALI_1] = &gxbb_mali_1.hw, 17160d48fc55SNeil Armstrong [CLKID_MALI] = &gxbb_mali.hw, 17174087bd4bSJerome Brunet [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw, 17184087bd4bSJerome Brunet [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw, 17194087bd4bSJerome Brunet [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw, 17203c277c24SJerome Brunet [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw, 17213c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw, 17223c277c24SJerome Brunet [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw, 17237eaa44f6SJerome Brunet [CLKID_CTS_I958] = &gxbb_cts_i958.hw, 172414c735c8SNeil Armstrong [CLKID_32K_CLK] = &gxbb_32k_clk.hw, 172514c735c8SNeil Armstrong [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw, 172614c735c8SNeil Armstrong [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw, 1727914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw, 1728914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw, 1729914e6e80SJerome Brunet [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw, 1730914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw, 1731914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw, 1732914e6e80SJerome Brunet [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw, 1733914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 1734914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 1735914e6e80SJerome Brunet [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 1736762a1f20SNeil Armstrong [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw, 1737762a1f20SNeil Armstrong [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw, 1738762a1f20SNeil Armstrong [CLKID_VPU_0] = &gxbb_vpu_0.hw, 1739762a1f20SNeil Armstrong [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw, 1740762a1f20SNeil Armstrong [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw, 1741762a1f20SNeil Armstrong [CLKID_VPU_1] = &gxbb_vpu_1.hw, 1742762a1f20SNeil Armstrong [CLKID_VPU] = &gxbb_vpu.hw, 1743762a1f20SNeil Armstrong [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw, 1744762a1f20SNeil Armstrong [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw, 1745762a1f20SNeil Armstrong [CLKID_VAPB_0] = &gxbb_vapb_0.hw, 1746762a1f20SNeil Armstrong [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw, 1747762a1f20SNeil Armstrong [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw, 1748762a1f20SNeil Armstrong [CLKID_VAPB_1] = &gxbb_vapb_1.hw, 1749762a1f20SNeil Armstrong [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, 1750762a1f20SNeil Armstrong [CLKID_VAPB] = &gxbb_vapb.hw, 17511f6f1dcbSJerome Brunet [NR_CLKS] = NULL, 17520d48fc55SNeil Armstrong }, 17530d48fc55SNeil Armstrong .num = NR_CLKS, 17540d48fc55SNeil Armstrong }; 17550d48fc55SNeil Armstrong 1756738f66d3SMichael Turquette /* Convenience tables to populate base addresses in .probe */ 1757738f66d3SMichael Turquette 1758738f66d3SMichael Turquette static struct meson_clk_pll *const gxbb_clk_plls[] = { 1759738f66d3SMichael Turquette &gxbb_fixed_pll, 1760738f66d3SMichael Turquette &gxbb_hdmi_pll, 1761738f66d3SMichael Turquette &gxbb_sys_pll, 1762738f66d3SMichael Turquette &gxbb_gp0_pll, 1763738f66d3SMichael Turquette }; 1764738f66d3SMichael Turquette 17650d48fc55SNeil Armstrong static struct meson_clk_pll *const gxl_clk_plls[] = { 17660d48fc55SNeil Armstrong &gxbb_fixed_pll, 17670d48fc55SNeil Armstrong &gxbb_hdmi_pll, 17680d48fc55SNeil Armstrong &gxbb_sys_pll, 17690d48fc55SNeil Armstrong &gxl_gp0_pll, 17700d48fc55SNeil Armstrong }; 17710d48fc55SNeil Armstrong 1772738f66d3SMichael Turquette static struct meson_clk_mpll *const gxbb_clk_mplls[] = { 1773738f66d3SMichael Turquette &gxbb_mpll0, 1774738f66d3SMichael Turquette &gxbb_mpll1, 1775738f66d3SMichael Turquette &gxbb_mpll2, 1776738f66d3SMichael Turquette }; 1777738f66d3SMichael Turquette 1778f7e3a826SJerome Brunet static struct clk_gate *const gxbb_clk_gates[] = { 1779738f66d3SMichael Turquette &gxbb_clk81, 1780738f66d3SMichael Turquette &gxbb_ddr, 1781738f66d3SMichael Turquette &gxbb_dos, 1782738f66d3SMichael Turquette &gxbb_isa, 1783738f66d3SMichael Turquette &gxbb_pl301, 1784738f66d3SMichael Turquette &gxbb_periphs, 1785738f66d3SMichael Turquette &gxbb_spicc, 1786738f66d3SMichael Turquette &gxbb_i2c, 1787738f66d3SMichael Turquette &gxbb_sar_adc, 1788738f66d3SMichael Turquette &gxbb_smart_card, 1789738f66d3SMichael Turquette &gxbb_rng0, 1790738f66d3SMichael Turquette &gxbb_uart0, 1791738f66d3SMichael Turquette &gxbb_sdhc, 1792738f66d3SMichael Turquette &gxbb_stream, 1793738f66d3SMichael Turquette &gxbb_async_fifo, 1794738f66d3SMichael Turquette &gxbb_sdio, 1795738f66d3SMichael Turquette &gxbb_abuf, 1796738f66d3SMichael Turquette &gxbb_hiu_iface, 1797738f66d3SMichael Turquette &gxbb_assist_misc, 1798738f66d3SMichael Turquette &gxbb_spi, 1799738f66d3SMichael Turquette &gxbb_i2s_spdif, 1800738f66d3SMichael Turquette &gxbb_eth, 1801738f66d3SMichael Turquette &gxbb_demux, 1802738f66d3SMichael Turquette &gxbb_aiu_glue, 1803738f66d3SMichael Turquette &gxbb_iec958, 1804738f66d3SMichael Turquette &gxbb_i2s_out, 1805738f66d3SMichael Turquette &gxbb_amclk, 1806738f66d3SMichael Turquette &gxbb_aififo2, 1807738f66d3SMichael Turquette &gxbb_mixer, 1808738f66d3SMichael Turquette &gxbb_mixer_iface, 1809738f66d3SMichael Turquette &gxbb_adc, 1810738f66d3SMichael Turquette &gxbb_blkmv, 1811738f66d3SMichael Turquette &gxbb_aiu, 1812738f66d3SMichael Turquette &gxbb_uart1, 1813738f66d3SMichael Turquette &gxbb_g2d, 1814738f66d3SMichael Turquette &gxbb_usb0, 1815738f66d3SMichael Turquette &gxbb_usb1, 1816738f66d3SMichael Turquette &gxbb_reset, 1817738f66d3SMichael Turquette &gxbb_nand, 1818738f66d3SMichael Turquette &gxbb_dos_parser, 1819738f66d3SMichael Turquette &gxbb_usb, 1820738f66d3SMichael Turquette &gxbb_vdin1, 1821738f66d3SMichael Turquette &gxbb_ahb_arb0, 1822738f66d3SMichael Turquette &gxbb_efuse, 1823738f66d3SMichael Turquette &gxbb_boot_rom, 1824738f66d3SMichael Turquette &gxbb_ahb_data_bus, 1825738f66d3SMichael Turquette &gxbb_ahb_ctrl_bus, 1826738f66d3SMichael Turquette &gxbb_hdmi_intr_sync, 1827738f66d3SMichael Turquette &gxbb_hdmi_pclk, 1828738f66d3SMichael Turquette &gxbb_usb1_ddr_bridge, 1829738f66d3SMichael Turquette &gxbb_usb0_ddr_bridge, 1830738f66d3SMichael Turquette &gxbb_mmc_pclk, 1831738f66d3SMichael Turquette &gxbb_dvin, 1832738f66d3SMichael Turquette &gxbb_uart2, 1833738f66d3SMichael Turquette &gxbb_sana, 1834738f66d3SMichael Turquette &gxbb_vpu_intr, 1835738f66d3SMichael Turquette &gxbb_sec_ahb_ahb3_bridge, 1836738f66d3SMichael Turquette &gxbb_clk81_a53, 1837738f66d3SMichael Turquette &gxbb_vclk2_venci0, 1838738f66d3SMichael Turquette &gxbb_vclk2_venci1, 1839738f66d3SMichael Turquette &gxbb_vclk2_vencp0, 1840738f66d3SMichael Turquette &gxbb_vclk2_vencp1, 1841738f66d3SMichael Turquette &gxbb_gclk_venci_int0, 1842738f66d3SMichael Turquette &gxbb_gclk_vencp_int, 1843738f66d3SMichael Turquette &gxbb_dac_clk, 1844738f66d3SMichael Turquette &gxbb_aoclk_gate, 1845738f66d3SMichael Turquette &gxbb_iec958_gate, 1846738f66d3SMichael Turquette &gxbb_enc480p, 1847738f66d3SMichael Turquette &gxbb_rng1, 1848738f66d3SMichael Turquette &gxbb_gclk_venci_int1, 1849738f66d3SMichael Turquette &gxbb_vclk2_venclmcc, 1850738f66d3SMichael Turquette &gxbb_vclk2_vencl, 1851738f66d3SMichael Turquette &gxbb_vclk_other, 1852738f66d3SMichael Turquette &gxbb_edp, 1853738f66d3SMichael Turquette &gxbb_ao_media_cpu, 1854738f66d3SMichael Turquette &gxbb_ao_ahb_sram, 1855738f66d3SMichael Turquette &gxbb_ao_ahb_bus, 1856738f66d3SMichael Turquette &gxbb_ao_iface, 1857738f66d3SMichael Turquette &gxbb_ao_i2c, 185833608dcdSKevin Hilman &gxbb_emmc_a, 185933608dcdSKevin Hilman &gxbb_emmc_b, 186033608dcdSKevin Hilman &gxbb_emmc_c, 186133d0fcdfSMartin Blumenstingl &gxbb_sar_adc_clk, 1862fac9a55bSNeil Armstrong &gxbb_mali_0, 1863fac9a55bSNeil Armstrong &gxbb_mali_1, 18644087bd4bSJerome Brunet &gxbb_cts_amclk, 18653c277c24SJerome Brunet &gxbb_cts_mclk_i958, 186614c735c8SNeil Armstrong &gxbb_32k_clk, 1867914e6e80SJerome Brunet &gxbb_sd_emmc_a_clk0, 1868914e6e80SJerome Brunet &gxbb_sd_emmc_b_clk0, 1869914e6e80SJerome Brunet &gxbb_sd_emmc_c_clk0, 1870762a1f20SNeil Armstrong &gxbb_vpu_0, 1871762a1f20SNeil Armstrong &gxbb_vpu_1, 1872762a1f20SNeil Armstrong &gxbb_vapb_0, 1873762a1f20SNeil Armstrong &gxbb_vapb_1, 1874762a1f20SNeil Armstrong &gxbb_vapb, 1875738f66d3SMichael Turquette }; 1876738f66d3SMichael Turquette 1877b92332eeSJerome Brunet static struct clk_mux *const gxbb_clk_muxes[] = { 1878b92332eeSJerome Brunet &gxbb_mpeg_clk_sel, 1879b92332eeSJerome Brunet &gxbb_sar_adc_clk_sel, 1880fac9a55bSNeil Armstrong &gxbb_mali_0_sel, 1881fac9a55bSNeil Armstrong &gxbb_mali_1_sel, 1882fac9a55bSNeil Armstrong &gxbb_mali, 18834087bd4bSJerome Brunet &gxbb_cts_amclk_sel, 18843c277c24SJerome Brunet &gxbb_cts_mclk_i958_sel, 18857eaa44f6SJerome Brunet &gxbb_cts_i958, 188614c735c8SNeil Armstrong &gxbb_32k_clk_sel, 1887914e6e80SJerome Brunet &gxbb_sd_emmc_a_clk0_sel, 1888914e6e80SJerome Brunet &gxbb_sd_emmc_b_clk0_sel, 1889914e6e80SJerome Brunet &gxbb_sd_emmc_c_clk0_sel, 1890762a1f20SNeil Armstrong &gxbb_vpu_0_sel, 1891762a1f20SNeil Armstrong &gxbb_vpu_1_sel, 1892762a1f20SNeil Armstrong &gxbb_vpu, 1893762a1f20SNeil Armstrong &gxbb_vapb_0_sel, 1894762a1f20SNeil Armstrong &gxbb_vapb_1_sel, 1895762a1f20SNeil Armstrong &gxbb_vapb_sel, 1896b92332eeSJerome Brunet }; 1897b92332eeSJerome Brunet 1898b92332eeSJerome Brunet static struct clk_divider *const gxbb_clk_dividers[] = { 1899b92332eeSJerome Brunet &gxbb_mpeg_clk_div, 1900b92332eeSJerome Brunet &gxbb_sar_adc_clk_div, 1901fac9a55bSNeil Armstrong &gxbb_mali_0_div, 1902fac9a55bSNeil Armstrong &gxbb_mali_1_div, 19033c277c24SJerome Brunet &gxbb_cts_mclk_i958_div, 190414c735c8SNeil Armstrong &gxbb_32k_clk_div, 1905914e6e80SJerome Brunet &gxbb_sd_emmc_a_clk0_div, 1906914e6e80SJerome Brunet &gxbb_sd_emmc_b_clk0_div, 1907914e6e80SJerome Brunet &gxbb_sd_emmc_c_clk0_div, 1908762a1f20SNeil Armstrong &gxbb_vpu_0_div, 1909762a1f20SNeil Armstrong &gxbb_vpu_1_div, 1910762a1f20SNeil Armstrong &gxbb_vapb_0_div, 1911762a1f20SNeil Armstrong &gxbb_vapb_1_div, 1912b92332eeSJerome Brunet }; 1913b92332eeSJerome Brunet 19144087bd4bSJerome Brunet static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = { 19154087bd4bSJerome Brunet &gxbb_cts_amclk_div, 19164087bd4bSJerome Brunet }; 19174087bd4bSJerome Brunet 19180d48fc55SNeil Armstrong struct clkc_data { 19190d48fc55SNeil Armstrong struct clk_gate *const *clk_gates; 19200d48fc55SNeil Armstrong unsigned int clk_gates_count; 19210d48fc55SNeil Armstrong struct meson_clk_mpll *const *clk_mplls; 19220d48fc55SNeil Armstrong unsigned int clk_mplls_count; 19230d48fc55SNeil Armstrong struct meson_clk_pll *const *clk_plls; 19240d48fc55SNeil Armstrong unsigned int clk_plls_count; 19250d48fc55SNeil Armstrong struct clk_mux *const *clk_muxes; 19260d48fc55SNeil Armstrong unsigned int clk_muxes_count; 19270d48fc55SNeil Armstrong struct clk_divider *const *clk_dividers; 19280d48fc55SNeil Armstrong unsigned int clk_dividers_count; 19294087bd4bSJerome Brunet struct meson_clk_audio_divider *const *clk_audio_dividers; 19304087bd4bSJerome Brunet unsigned int clk_audio_dividers_count; 19310d48fc55SNeil Armstrong struct clk_hw_onecell_data *hw_onecell_data; 19320d48fc55SNeil Armstrong }; 19330d48fc55SNeil Armstrong 19340d48fc55SNeil Armstrong static const struct clkc_data gxbb_clkc_data = { 19350d48fc55SNeil Armstrong .clk_gates = gxbb_clk_gates, 19360d48fc55SNeil Armstrong .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates), 19370d48fc55SNeil Armstrong .clk_mplls = gxbb_clk_mplls, 19380d48fc55SNeil Armstrong .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls), 19390d48fc55SNeil Armstrong .clk_plls = gxbb_clk_plls, 19400d48fc55SNeil Armstrong .clk_plls_count = ARRAY_SIZE(gxbb_clk_plls), 19410d48fc55SNeil Armstrong .clk_muxes = gxbb_clk_muxes, 19420d48fc55SNeil Armstrong .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes), 19430d48fc55SNeil Armstrong .clk_dividers = gxbb_clk_dividers, 19440d48fc55SNeil Armstrong .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), 19454087bd4bSJerome Brunet .clk_audio_dividers = gxbb_audio_dividers, 19464087bd4bSJerome Brunet .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), 19470d48fc55SNeil Armstrong .hw_onecell_data = &gxbb_hw_onecell_data, 19480d48fc55SNeil Armstrong }; 19490d48fc55SNeil Armstrong 19500d48fc55SNeil Armstrong static const struct clkc_data gxl_clkc_data = { 19510d48fc55SNeil Armstrong .clk_gates = gxbb_clk_gates, 19520d48fc55SNeil Armstrong .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates), 19530d48fc55SNeil Armstrong .clk_mplls = gxbb_clk_mplls, 19540d48fc55SNeil Armstrong .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls), 19550d48fc55SNeil Armstrong .clk_plls = gxl_clk_plls, 19560d48fc55SNeil Armstrong .clk_plls_count = ARRAY_SIZE(gxl_clk_plls), 19570d48fc55SNeil Armstrong .clk_muxes = gxbb_clk_muxes, 19580d48fc55SNeil Armstrong .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes), 19590d48fc55SNeil Armstrong .clk_dividers = gxbb_clk_dividers, 19600d48fc55SNeil Armstrong .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), 19614087bd4bSJerome Brunet .clk_audio_dividers = gxbb_audio_dividers, 19624087bd4bSJerome Brunet .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), 19630d48fc55SNeil Armstrong .hw_onecell_data = &gxl_hw_onecell_data, 19640d48fc55SNeil Armstrong }; 19650d48fc55SNeil Armstrong 19660d48fc55SNeil Armstrong static const struct of_device_id clkc_match_table[] = { 19670d48fc55SNeil Armstrong { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data }, 19680d48fc55SNeil Armstrong { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data }, 19690d48fc55SNeil Armstrong {}, 19700d48fc55SNeil Armstrong }; 19710d48fc55SNeil Armstrong 1972738f66d3SMichael Turquette static int gxbb_clkc_probe(struct platform_device *pdev) 1973738f66d3SMichael Turquette { 19740d48fc55SNeil Armstrong const struct clkc_data *clkc_data; 1975738f66d3SMichael Turquette void __iomem *clk_base; 1976738f66d3SMichael Turquette int ret, clkid, i; 1977738f66d3SMichael Turquette struct device *dev = &pdev->dev; 1978738f66d3SMichael Turquette 19790d48fc55SNeil Armstrong clkc_data = of_device_get_match_data(&pdev->dev); 19800d48fc55SNeil Armstrong if (!clkc_data) 19810d48fc55SNeil Armstrong return -EINVAL; 19820d48fc55SNeil Armstrong 1983738f66d3SMichael Turquette /* Generic clocks and PLLs */ 1984738f66d3SMichael Turquette clk_base = of_iomap(dev->of_node, 0); 1985738f66d3SMichael Turquette if (!clk_base) { 1986738f66d3SMichael Turquette pr_err("%s: Unable to map clk base\n", __func__); 1987738f66d3SMichael Turquette return -ENXIO; 1988738f66d3SMichael Turquette } 1989738f66d3SMichael Turquette 1990738f66d3SMichael Turquette /* Populate base address for PLLs */ 19910d48fc55SNeil Armstrong for (i = 0; i < clkc_data->clk_plls_count; i++) 19920d48fc55SNeil Armstrong clkc_data->clk_plls[i]->base = clk_base; 1993738f66d3SMichael Turquette 1994738f66d3SMichael Turquette /* Populate base address for MPLLs */ 19950d48fc55SNeil Armstrong for (i = 0; i < clkc_data->clk_mplls_count; i++) 19960d48fc55SNeil Armstrong clkc_data->clk_mplls[i]->base = clk_base; 1997738f66d3SMichael Turquette 1998738f66d3SMichael Turquette /* Populate base address for gates */ 19990d48fc55SNeil Armstrong for (i = 0; i < clkc_data->clk_gates_count; i++) 20000d48fc55SNeil Armstrong clkc_data->clk_gates[i]->reg = clk_base + 20010d48fc55SNeil Armstrong (u64)clkc_data->clk_gates[i]->reg; 2002738f66d3SMichael Turquette 2003b92332eeSJerome Brunet /* Populate base address for muxes */ 20040d48fc55SNeil Armstrong for (i = 0; i < clkc_data->clk_muxes_count; i++) 20050d48fc55SNeil Armstrong clkc_data->clk_muxes[i]->reg = clk_base + 20060d48fc55SNeil Armstrong (u64)clkc_data->clk_muxes[i]->reg; 2007b92332eeSJerome Brunet 2008b92332eeSJerome Brunet /* Populate base address for dividers */ 20090d48fc55SNeil Armstrong for (i = 0; i < clkc_data->clk_dividers_count; i++) 20100d48fc55SNeil Armstrong clkc_data->clk_dividers[i]->reg = clk_base + 20110d48fc55SNeil Armstrong (u64)clkc_data->clk_dividers[i]->reg; 2012b92332eeSJerome Brunet 20134087bd4bSJerome Brunet /* Populate base address for the audio dividers */ 20144087bd4bSJerome Brunet for (i = 0; i < clkc_data->clk_audio_dividers_count; i++) 20154087bd4bSJerome Brunet clkc_data->clk_audio_dividers[i]->base = clk_base; 20164087bd4bSJerome Brunet 2017738f66d3SMichael Turquette /* 2018738f66d3SMichael Turquette * register all clks 2019738f66d3SMichael Turquette */ 20200d48fc55SNeil Armstrong for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) { 2021a70c6e06SJerome Brunet /* array might be sparse */ 2022a70c6e06SJerome Brunet if (!clkc_data->hw_onecell_data->hws[clkid]) 2023a70c6e06SJerome Brunet continue; 2024a70c6e06SJerome Brunet 20250d48fc55SNeil Armstrong ret = devm_clk_hw_register(dev, 20260d48fc55SNeil Armstrong clkc_data->hw_onecell_data->hws[clkid]); 2027738f66d3SMichael Turquette if (ret) 2028738f66d3SMichael Turquette goto iounmap; 2029738f66d3SMichael Turquette } 2030738f66d3SMichael Turquette 2031738f66d3SMichael Turquette return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, 20320d48fc55SNeil Armstrong clkc_data->hw_onecell_data); 2033738f66d3SMichael Turquette 2034738f66d3SMichael Turquette iounmap: 2035738f66d3SMichael Turquette iounmap(clk_base); 2036738f66d3SMichael Turquette return ret; 2037738f66d3SMichael Turquette } 2038738f66d3SMichael Turquette 2039738f66d3SMichael Turquette static struct platform_driver gxbb_driver = { 2040738f66d3SMichael Turquette .probe = gxbb_clkc_probe, 2041738f66d3SMichael Turquette .driver = { 2042738f66d3SMichael Turquette .name = "gxbb-clkc", 20430d48fc55SNeil Armstrong .of_match_table = clkc_match_table, 2044738f66d3SMichael Turquette }, 2045738f66d3SMichael Turquette }; 2046738f66d3SMichael Turquette 204700746f10SWei Yongjun builtin_platform_driver(gxbb_driver); 2048