1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2016 Amlogic, Inc. 4 * Author: Michael Turquette <mturquette@baylibre.com> 5 * 6 * Copyright (c) 2018 Amlogic, inc. 7 * Author: Qiufang Dai <qiufang.dai@amlogic.com> 8 * Author: Jian Hu <jian.hu@amlogic.com> 9 * 10 */ 11 #ifndef __G12A_H 12 #define __G12A_H 13 14 /* 15 * Clock controller register offsets 16 * 17 * Register offsets from the data sheet must be multiplied by 4 before 18 * adding them to the base address to get the right value. 19 */ 20 #define HHI_MIPI_CNTL0 0x000 21 #define HHI_MIPI_CNTL1 0x004 22 #define HHI_MIPI_CNTL2 0x008 23 #define HHI_MIPI_STS 0x00C 24 #define HHI_GP0_PLL_CNTL0 0x040 25 #define HHI_GP0_PLL_CNTL1 0x044 26 #define HHI_GP0_PLL_CNTL2 0x048 27 #define HHI_GP0_PLL_CNTL3 0x04C 28 #define HHI_GP0_PLL_CNTL4 0x050 29 #define HHI_GP0_PLL_CNTL5 0x054 30 #define HHI_GP0_PLL_CNTL6 0x058 31 #define HHI_GP0_PLL_STS 0x05C 32 #define HHI_GP1_PLL_CNTL0 0x060 33 #define HHI_GP1_PLL_CNTL1 0x064 34 #define HHI_GP1_PLL_CNTL2 0x068 35 #define HHI_GP1_PLL_CNTL3 0x06C 36 #define HHI_GP1_PLL_CNTL4 0x070 37 #define HHI_GP1_PLL_CNTL5 0x074 38 #define HHI_GP1_PLL_CNTL6 0x078 39 #define HHI_GP1_PLL_STS 0x07C 40 #define HHI_PCIE_PLL_CNTL0 0x098 41 #define HHI_PCIE_PLL_CNTL1 0x09C 42 #define HHI_PCIE_PLL_CNTL2 0x0A0 43 #define HHI_PCIE_PLL_CNTL3 0x0A4 44 #define HHI_PCIE_PLL_CNTL4 0x0A8 45 #define HHI_PCIE_PLL_CNTL5 0x0AC 46 #define HHI_PCIE_PLL_STS 0x0B8 47 #define HHI_HIFI_PLL_CNTL0 0x0D8 48 #define HHI_HIFI_PLL_CNTL1 0x0DC 49 #define HHI_HIFI_PLL_CNTL2 0x0E0 50 #define HHI_HIFI_PLL_CNTL3 0x0E4 51 #define HHI_HIFI_PLL_CNTL4 0x0E8 52 #define HHI_HIFI_PLL_CNTL5 0x0EC 53 #define HHI_HIFI_PLL_CNTL6 0x0F0 54 #define HHI_VIID_CLK_DIV 0x128 55 #define HHI_VIID_CLK_CNTL 0x12C 56 #define HHI_GCLK_MPEG0 0x140 57 #define HHI_GCLK_MPEG1 0x144 58 #define HHI_GCLK_MPEG2 0x148 59 #define HHI_GCLK_OTHER 0x150 60 #define HHI_GCLK_OTHER2 0x154 61 #define HHI_SYS_CPU_CLK_CNTL1 0x15c 62 #define HHI_VID_CLK_DIV 0x164 63 #define HHI_MPEG_CLK_CNTL 0x174 64 #define HHI_AUD_CLK_CNTL 0x178 65 #define HHI_VID_CLK_CNTL 0x17c 66 #define HHI_TS_CLK_CNTL 0x190 67 #define HHI_VID_CLK_CNTL2 0x194 68 #define HHI_SYS_CPU_CLK_CNTL0 0x19c 69 #define HHI_VID_PLL_CLK_DIV 0x1A0 70 #define HHI_MALI_CLK_CNTL 0x1b0 71 #define HHI_VPU_CLKC_CNTL 0x1b4 72 #define HHI_VPU_CLK_CNTL 0x1bC 73 #define HHI_NNA_CLK_CNTL 0x1C8 74 #define HHI_HDMI_CLK_CNTL 0x1CC 75 #define HHI_VDEC_CLK_CNTL 0x1E0 76 #define HHI_VDEC2_CLK_CNTL 0x1E4 77 #define HHI_VDEC3_CLK_CNTL 0x1E8 78 #define HHI_VDEC4_CLK_CNTL 0x1EC 79 #define HHI_HDCP22_CLK_CNTL 0x1F0 80 #define HHI_VAPBCLK_CNTL 0x1F4 81 #define HHI_SYS_CPUB_CLK_CNTL1 0x200 82 #define HHI_SYS_CPUB_CLK_CNTL 0x208 83 #define HHI_VPU_CLKB_CNTL 0x20C 84 #define HHI_SYS_CPU_CLK_CNTL2 0x210 85 #define HHI_SYS_CPU_CLK_CNTL3 0x214 86 #define HHI_SYS_CPU_CLK_CNTL4 0x218 87 #define HHI_SYS_CPU_CLK_CNTL5 0x21c 88 #define HHI_SYS_CPU_CLK_CNTL6 0x220 89 #define HHI_GEN_CLK_CNTL 0x228 90 #define HHI_VDIN_MEAS_CLK_CNTL 0x250 91 #define HHI_MIPIDSI_PHY_CLK_CNTL 0x254 92 #define HHI_NAND_CLK_CNTL 0x25C 93 #define HHI_SD_EMMC_CLK_CNTL 0x264 94 #define HHI_MPLL_CNTL0 0x278 95 #define HHI_MPLL_CNTL1 0x27C 96 #define HHI_MPLL_CNTL2 0x280 97 #define HHI_MPLL_CNTL3 0x284 98 #define HHI_MPLL_CNTL4 0x288 99 #define HHI_MPLL_CNTL5 0x28c 100 #define HHI_MPLL_CNTL6 0x290 101 #define HHI_MPLL_CNTL7 0x294 102 #define HHI_MPLL_CNTL8 0x298 103 #define HHI_FIX_PLL_CNTL0 0x2A0 104 #define HHI_FIX_PLL_CNTL1 0x2A4 105 #define HHI_FIX_PLL_CNTL3 0x2AC 106 #define HHI_SYS_PLL_CNTL0 0x2f4 107 #define HHI_SYS_PLL_CNTL1 0x2f8 108 #define HHI_SYS_PLL_CNTL2 0x2fc 109 #define HHI_SYS_PLL_CNTL3 0x300 110 #define HHI_SYS_PLL_CNTL4 0x304 111 #define HHI_SYS_PLL_CNTL5 0x308 112 #define HHI_SYS_PLL_CNTL6 0x30c 113 #define HHI_HDMI_PLL_CNTL0 0x320 114 #define HHI_HDMI_PLL_CNTL1 0x324 115 #define HHI_HDMI_PLL_CNTL2 0x328 116 #define HHI_HDMI_PLL_CNTL3 0x32c 117 #define HHI_HDMI_PLL_CNTL4 0x330 118 #define HHI_HDMI_PLL_CNTL5 0x334 119 #define HHI_HDMI_PLL_CNTL6 0x338 120 #define HHI_SPICC_CLK_CNTL 0x3dc 121 #define HHI_SYS1_PLL_CNTL0 0x380 122 #define HHI_SYS1_PLL_CNTL1 0x384 123 #define HHI_SYS1_PLL_CNTL2 0x388 124 #define HHI_SYS1_PLL_CNTL3 0x38c 125 #define HHI_SYS1_PLL_CNTL4 0x390 126 #define HHI_SYS1_PLL_CNTL5 0x394 127 #define HHI_SYS1_PLL_CNTL6 0x398 128 129 /* 130 * CLKID index values 131 * 132 * These indices are entirely contrived and do not map onto the hardware. 133 * It has now been decided to expose everything by default in the DT header: 134 * include/dt-bindings/clock/g12a-clkc.h. Only the clocks ids we don't want 135 * to expose, such as the internal muxes and dividers of composite clocks, 136 * will remain defined here. 137 */ 138 #define CLKID_MPEG_SEL 8 139 #define CLKID_MPEG_DIV 9 140 #define CLKID_SD_EMMC_A_CLK0_SEL 63 141 #define CLKID_SD_EMMC_A_CLK0_DIV 64 142 #define CLKID_SD_EMMC_B_CLK0_SEL 65 143 #define CLKID_SD_EMMC_B_CLK0_DIV 66 144 #define CLKID_SD_EMMC_C_CLK0_SEL 67 145 #define CLKID_SD_EMMC_C_CLK0_DIV 68 146 #define CLKID_MPLL0_DIV 69 147 #define CLKID_MPLL1_DIV 70 148 #define CLKID_MPLL2_DIV 71 149 #define CLKID_MPLL3_DIV 72 150 #define CLKID_MPLL_PREDIV 73 151 #define CLKID_FCLK_DIV2_DIV 75 152 #define CLKID_FCLK_DIV3_DIV 76 153 #define CLKID_FCLK_DIV4_DIV 77 154 #define CLKID_FCLK_DIV5_DIV 78 155 #define CLKID_FCLK_DIV7_DIV 79 156 #define CLKID_FCLK_DIV2P5_DIV 100 157 #define CLKID_FIXED_PLL_DCO 101 158 #define CLKID_SYS_PLL_DCO 102 159 #define CLKID_GP0_PLL_DCO 103 160 #define CLKID_HIFI_PLL_DCO 104 161 #define CLKID_VPU_0_DIV 111 162 #define CLKID_VPU_1_DIV 114 163 #define CLKID_VAPB_0_DIV 118 164 #define CLKID_VAPB_1_DIV 121 165 #define CLKID_HDMI_PLL_DCO 125 166 #define CLKID_HDMI_PLL_OD 126 167 #define CLKID_HDMI_PLL_OD2 127 168 #define CLKID_VID_PLL_SEL 130 169 #define CLKID_VID_PLL_DIV 131 170 #define CLKID_VCLK_SEL 132 171 #define CLKID_VCLK2_SEL 133 172 #define CLKID_VCLK_INPUT 134 173 #define CLKID_VCLK2_INPUT 135 174 #define CLKID_VCLK_DIV 136 175 #define CLKID_VCLK2_DIV 137 176 #define CLKID_VCLK_DIV2_EN 140 177 #define CLKID_VCLK_DIV4_EN 141 178 #define CLKID_VCLK_DIV6_EN 142 179 #define CLKID_VCLK_DIV12_EN 143 180 #define CLKID_VCLK2_DIV2_EN 144 181 #define CLKID_VCLK2_DIV4_EN 145 182 #define CLKID_VCLK2_DIV6_EN 146 183 #define CLKID_VCLK2_DIV12_EN 147 184 #define CLKID_CTS_ENCI_SEL 158 185 #define CLKID_CTS_ENCP_SEL 159 186 #define CLKID_CTS_VDAC_SEL 160 187 #define CLKID_HDMI_TX_SEL 161 188 #define CLKID_HDMI_SEL 166 189 #define CLKID_HDMI_DIV 167 190 #define CLKID_MALI_0_DIV 170 191 #define CLKID_MALI_1_DIV 173 192 #define CLKID_MPLL_50M_DIV 176 193 #define CLKID_SYS_PLL_DIV16_EN 178 194 #define CLKID_SYS_PLL_DIV16 179 195 #define CLKID_CPU_CLK_DYN0_SEL 180 196 #define CLKID_CPU_CLK_DYN0_DIV 181 197 #define CLKID_CPU_CLK_DYN0 182 198 #define CLKID_CPU_CLK_DYN1_SEL 183 199 #define CLKID_CPU_CLK_DYN1_DIV 184 200 #define CLKID_CPU_CLK_DYN1 185 201 #define CLKID_CPU_CLK_DYN 186 202 #define CLKID_CPU_CLK_DIV16_EN 188 203 #define CLKID_CPU_CLK_DIV16 189 204 #define CLKID_CPU_CLK_APB_DIV 190 205 #define CLKID_CPU_CLK_APB 191 206 #define CLKID_CPU_CLK_ATB_DIV 192 207 #define CLKID_CPU_CLK_ATB 193 208 #define CLKID_CPU_CLK_AXI_DIV 194 209 #define CLKID_CPU_CLK_AXI 195 210 #define CLKID_CPU_CLK_TRACE_DIV 196 211 #define CLKID_CPU_CLK_TRACE 197 212 #define CLKID_PCIE_PLL_DCO 198 213 #define CLKID_PCIE_PLL_DCO_DIV2 199 214 #define CLKID_PCIE_PLL_OD 200 215 #define CLKID_VDEC_1_SEL 202 216 #define CLKID_VDEC_1_DIV 203 217 #define CLKID_VDEC_HEVC_SEL 205 218 #define CLKID_VDEC_HEVC_DIV 206 219 #define CLKID_VDEC_HEVCF_SEL 208 220 #define CLKID_VDEC_HEVCF_DIV 209 221 #define CLKID_TS_DIV 211 222 #define CLKID_SYS1_PLL_DCO 213 223 #define CLKID_SYS1_PLL 214 224 #define CLKID_SYS1_PLL_DIV16_EN 215 225 #define CLKID_SYS1_PLL_DIV16 216 226 #define CLKID_CPUB_CLK_DYN0_SEL 217 227 #define CLKID_CPUB_CLK_DYN0_DIV 218 228 #define CLKID_CPUB_CLK_DYN0 219 229 #define CLKID_CPUB_CLK_DYN1_SEL 220 230 #define CLKID_CPUB_CLK_DYN1_DIV 221 231 #define CLKID_CPUB_CLK_DYN1 222 232 #define CLKID_CPUB_CLK_DYN 223 233 #define CLKID_CPUB_CLK_DIV16_EN 225 234 #define CLKID_CPUB_CLK_DIV16 226 235 #define CLKID_CPUB_CLK_DIV2 227 236 #define CLKID_CPUB_CLK_DIV3 228 237 #define CLKID_CPUB_CLK_DIV4 229 238 #define CLKID_CPUB_CLK_DIV5 230 239 #define CLKID_CPUB_CLK_DIV6 231 240 #define CLKID_CPUB_CLK_DIV7 232 241 #define CLKID_CPUB_CLK_DIV8 233 242 #define CLKID_CPUB_CLK_APB_SEL 234 243 #define CLKID_CPUB_CLK_APB 235 244 #define CLKID_CPUB_CLK_ATB_SEL 236 245 #define CLKID_CPUB_CLK_ATB 237 246 #define CLKID_CPUB_CLK_AXI_SEL 238 247 #define CLKID_CPUB_CLK_AXI 239 248 #define CLKID_CPUB_CLK_TRACE_SEL 240 249 #define CLKID_CPUB_CLK_TRACE 241 250 #define CLKID_GP1_PLL_DCO 242 251 #define CLKID_DSU_CLK_DYN0_SEL 244 252 #define CLKID_DSU_CLK_DYN0_DIV 245 253 #define CLKID_DSU_CLK_DYN0 246 254 #define CLKID_DSU_CLK_DYN1_SEL 247 255 #define CLKID_DSU_CLK_DYN1_DIV 248 256 #define CLKID_DSU_CLK_DYN1 249 257 #define CLKID_DSU_CLK_DYN 250 258 #define CLKID_DSU_CLK_FINAL 251 259 #define CLKID_SPICC0_SCLK_SEL 256 260 #define CLKID_SPICC0_SCLK_DIV 257 261 #define CLKID_SPICC1_SCLK_SEL 259 262 #define CLKID_SPICC1_SCLK_DIV 260 263 #define CLKID_NNA_AXI_CLK_SEL 262 264 #define CLKID_NNA_AXI_CLK_DIV 263 265 #define CLKID_NNA_CORE_CLK_SEL 265 266 #define CLKID_NNA_CORE_CLK_DIV 266 267 268 #define NR_CLKS 268 269 270 /* include the CLKIDs that have been made part of the DT binding */ 271 #include <dt-bindings/clock/g12a-clkc.h> 272 273 #endif /* __G12A_H */ 274