1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Amlogic Meson-G12A Clock Controller Driver 4 * 5 * Copyright (c) 2016 Baylibre SAS. 6 * Author: Michael Turquette <mturquette@baylibre.com> 7 * 8 * Copyright (c) 2018 Amlogic, inc. 9 * Author: Qiufang Dai <qiufang.dai@amlogic.com> 10 * Author: Jian Hu <jian.hu@amlogic.com> 11 */ 12 13 #include <linux/clk-provider.h> 14 #include <linux/init.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 18 #include "clk-input.h" 19 #include "clk-mpll.h" 20 #include "clk-pll.h" 21 #include "clk-regmap.h" 22 #include "vid-pll-div.h" 23 #include "meson-eeclk.h" 24 #include "g12a.h" 25 26 static DEFINE_SPINLOCK(meson_clk_lock); 27 28 static struct clk_regmap g12a_fixed_pll_dco = { 29 .data = &(struct meson_clk_pll_data){ 30 .en = { 31 .reg_off = HHI_FIX_PLL_CNTL0, 32 .shift = 28, 33 .width = 1, 34 }, 35 .m = { 36 .reg_off = HHI_FIX_PLL_CNTL0, 37 .shift = 0, 38 .width = 8, 39 }, 40 .n = { 41 .reg_off = HHI_FIX_PLL_CNTL0, 42 .shift = 10, 43 .width = 5, 44 }, 45 .frac = { 46 .reg_off = HHI_FIX_PLL_CNTL1, 47 .shift = 0, 48 .width = 17, 49 }, 50 .l = { 51 .reg_off = HHI_FIX_PLL_CNTL0, 52 .shift = 31, 53 .width = 1, 54 }, 55 .rst = { 56 .reg_off = HHI_FIX_PLL_CNTL0, 57 .shift = 29, 58 .width = 1, 59 }, 60 }, 61 .hw.init = &(struct clk_init_data){ 62 .name = "fixed_pll_dco", 63 .ops = &meson_clk_pll_ro_ops, 64 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 65 .num_parents = 1, 66 }, 67 }; 68 69 static struct clk_regmap g12a_fixed_pll = { 70 .data = &(struct clk_regmap_div_data){ 71 .offset = HHI_FIX_PLL_CNTL0, 72 .shift = 16, 73 .width = 2, 74 .flags = CLK_DIVIDER_POWER_OF_TWO, 75 }, 76 .hw.init = &(struct clk_init_data){ 77 .name = "fixed_pll", 78 .ops = &clk_regmap_divider_ro_ops, 79 .parent_names = (const char *[]){ "fixed_pll_dco" }, 80 .num_parents = 1, 81 /* 82 * This clock won't ever change at runtime so 83 * CLK_SET_RATE_PARENT is not required 84 */ 85 }, 86 }; 87 88 /* 89 * Internal sys pll emulation configuration parameters 90 */ 91 static const struct reg_sequence g12a_sys_init_regs[] = { 92 { .reg = HHI_SYS_PLL_CNTL1, .def = 0x00000000 }, 93 { .reg = HHI_SYS_PLL_CNTL2, .def = 0x00000000 }, 94 { .reg = HHI_SYS_PLL_CNTL3, .def = 0x48681c00 }, 95 { .reg = HHI_SYS_PLL_CNTL4, .def = 0x88770290 }, 96 { .reg = HHI_SYS_PLL_CNTL5, .def = 0x39272000 }, 97 { .reg = HHI_SYS_PLL_CNTL6, .def = 0x56540000 }, 98 }; 99 100 static struct clk_regmap g12a_sys_pll_dco = { 101 .data = &(struct meson_clk_pll_data){ 102 .en = { 103 .reg_off = HHI_SYS_PLL_CNTL0, 104 .shift = 28, 105 .width = 1, 106 }, 107 .m = { 108 .reg_off = HHI_SYS_PLL_CNTL0, 109 .shift = 0, 110 .width = 8, 111 }, 112 .n = { 113 .reg_off = HHI_SYS_PLL_CNTL0, 114 .shift = 10, 115 .width = 5, 116 }, 117 .l = { 118 .reg_off = HHI_SYS_PLL_CNTL0, 119 .shift = 31, 120 .width = 1, 121 }, 122 .rst = { 123 .reg_off = HHI_SYS_PLL_CNTL0, 124 .shift = 29, 125 .width = 1, 126 }, 127 .init_regs = g12a_sys_init_regs, 128 .init_count = ARRAY_SIZE(g12a_sys_init_regs), 129 }, 130 .hw.init = &(struct clk_init_data){ 131 .name = "sys_pll_dco", 132 .ops = &meson_clk_pll_ro_ops, 133 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 134 .num_parents = 1, 135 }, 136 }; 137 138 static struct clk_regmap g12a_sys_pll = { 139 .data = &(struct clk_regmap_div_data){ 140 .offset = HHI_SYS_PLL_CNTL0, 141 .shift = 16, 142 .width = 3, 143 .flags = CLK_DIVIDER_POWER_OF_TWO, 144 }, 145 .hw.init = &(struct clk_init_data){ 146 .name = "sys_pll", 147 .ops = &clk_regmap_divider_ro_ops, 148 .parent_names = (const char *[]){ "sys_pll_dco" }, 149 .num_parents = 1, 150 }, 151 }; 152 153 static const struct pll_mult_range g12a_gp0_pll_mult_range = { 154 .min = 55, 155 .max = 255, 156 }; 157 158 /* 159 * Internal gp0 pll emulation configuration parameters 160 */ 161 static const struct reg_sequence g12a_gp0_init_regs[] = { 162 { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 }, 163 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 }, 164 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 }, 165 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 }, 166 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 }, 167 { .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 }, 168 }; 169 170 static struct clk_regmap g12a_gp0_pll_dco = { 171 .data = &(struct meson_clk_pll_data){ 172 .en = { 173 .reg_off = HHI_GP0_PLL_CNTL0, 174 .shift = 28, 175 .width = 1, 176 }, 177 .m = { 178 .reg_off = HHI_GP0_PLL_CNTL0, 179 .shift = 0, 180 .width = 8, 181 }, 182 .n = { 183 .reg_off = HHI_GP0_PLL_CNTL0, 184 .shift = 10, 185 .width = 5, 186 }, 187 .frac = { 188 .reg_off = HHI_GP0_PLL_CNTL1, 189 .shift = 0, 190 .width = 17, 191 }, 192 .l = { 193 .reg_off = HHI_GP0_PLL_CNTL0, 194 .shift = 31, 195 .width = 1, 196 }, 197 .rst = { 198 .reg_off = HHI_GP0_PLL_CNTL0, 199 .shift = 29, 200 .width = 1, 201 }, 202 .range = &g12a_gp0_pll_mult_range, 203 .init_regs = g12a_gp0_init_regs, 204 .init_count = ARRAY_SIZE(g12a_gp0_init_regs), 205 }, 206 .hw.init = &(struct clk_init_data){ 207 .name = "gp0_pll_dco", 208 .ops = &meson_clk_pll_ops, 209 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 210 .num_parents = 1, 211 }, 212 }; 213 214 static struct clk_regmap g12a_gp0_pll = { 215 .data = &(struct clk_regmap_div_data){ 216 .offset = HHI_GP0_PLL_CNTL0, 217 .shift = 16, 218 .width = 3, 219 .flags = (CLK_DIVIDER_POWER_OF_TWO | 220 CLK_DIVIDER_ROUND_CLOSEST), 221 }, 222 .hw.init = &(struct clk_init_data){ 223 .name = "gp0_pll", 224 .ops = &clk_regmap_divider_ops, 225 .parent_names = (const char *[]){ "gp0_pll_dco" }, 226 .num_parents = 1, 227 .flags = CLK_SET_RATE_PARENT, 228 }, 229 }; 230 231 /* 232 * Internal hifi pll emulation configuration parameters 233 */ 234 static const struct reg_sequence g12a_hifi_init_regs[] = { 235 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 }, 236 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 }, 237 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 }, 238 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 }, 239 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 }, 240 { .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 }, 241 }; 242 243 static struct clk_regmap g12a_hifi_pll_dco = { 244 .data = &(struct meson_clk_pll_data){ 245 .en = { 246 .reg_off = HHI_HIFI_PLL_CNTL0, 247 .shift = 28, 248 .width = 1, 249 }, 250 .m = { 251 .reg_off = HHI_HIFI_PLL_CNTL0, 252 .shift = 0, 253 .width = 8, 254 }, 255 .n = { 256 .reg_off = HHI_HIFI_PLL_CNTL0, 257 .shift = 10, 258 .width = 5, 259 }, 260 .frac = { 261 .reg_off = HHI_HIFI_PLL_CNTL1, 262 .shift = 0, 263 .width = 17, 264 }, 265 .l = { 266 .reg_off = HHI_HIFI_PLL_CNTL0, 267 .shift = 31, 268 .width = 1, 269 }, 270 .rst = { 271 .reg_off = HHI_HIFI_PLL_CNTL0, 272 .shift = 29, 273 .width = 1, 274 }, 275 .range = &g12a_gp0_pll_mult_range, 276 .init_regs = g12a_hifi_init_regs, 277 .init_count = ARRAY_SIZE(g12a_hifi_init_regs), 278 .flags = CLK_MESON_PLL_ROUND_CLOSEST, 279 }, 280 .hw.init = &(struct clk_init_data){ 281 .name = "hifi_pll_dco", 282 .ops = &meson_clk_pll_ops, 283 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 284 .num_parents = 1, 285 }, 286 }; 287 288 static struct clk_regmap g12a_hifi_pll = { 289 .data = &(struct clk_regmap_div_data){ 290 .offset = HHI_HIFI_PLL_CNTL0, 291 .shift = 16, 292 .width = 2, 293 .flags = (CLK_DIVIDER_POWER_OF_TWO | 294 CLK_DIVIDER_ROUND_CLOSEST), 295 }, 296 .hw.init = &(struct clk_init_data){ 297 .name = "hifi_pll", 298 .ops = &clk_regmap_divider_ops, 299 .parent_names = (const char *[]){ "hifi_pll_dco" }, 300 .num_parents = 1, 301 .flags = CLK_SET_RATE_PARENT, 302 }, 303 }; 304 305 static struct clk_regmap g12a_hdmi_pll_dco = { 306 .data = &(struct meson_clk_pll_data){ 307 .en = { 308 .reg_off = HHI_HDMI_PLL_CNTL0, 309 .shift = 28, 310 .width = 1, 311 }, 312 .m = { 313 .reg_off = HHI_HDMI_PLL_CNTL0, 314 .shift = 0, 315 .width = 8, 316 }, 317 .n = { 318 .reg_off = HHI_HDMI_PLL_CNTL0, 319 .shift = 10, 320 .width = 5, 321 }, 322 .frac = { 323 .reg_off = HHI_HDMI_PLL_CNTL1, 324 .shift = 0, 325 .width = 16, 326 }, 327 .l = { 328 .reg_off = HHI_HDMI_PLL_CNTL0, 329 .shift = 30, 330 .width = 1, 331 }, 332 .rst = { 333 .reg_off = HHI_HDMI_PLL_CNTL0, 334 .shift = 29, 335 .width = 1, 336 }, 337 }, 338 .hw.init = &(struct clk_init_data){ 339 .name = "hdmi_pll_dco", 340 .ops = &meson_clk_pll_ro_ops, 341 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 342 .num_parents = 1, 343 /* 344 * Display directly handle hdmi pll registers ATM, we need 345 * NOCACHE to keep our view of the clock as accurate as possible 346 */ 347 .flags = CLK_GET_RATE_NOCACHE, 348 }, 349 }; 350 351 static struct clk_regmap g12a_hdmi_pll_od = { 352 .data = &(struct clk_regmap_div_data){ 353 .offset = HHI_HDMI_PLL_CNTL0, 354 .shift = 16, 355 .width = 2, 356 .flags = CLK_DIVIDER_POWER_OF_TWO, 357 }, 358 .hw.init = &(struct clk_init_data){ 359 .name = "hdmi_pll_od", 360 .ops = &clk_regmap_divider_ro_ops, 361 .parent_names = (const char *[]){ "hdmi_pll_dco" }, 362 .num_parents = 1, 363 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 364 }, 365 }; 366 367 static struct clk_regmap g12a_hdmi_pll_od2 = { 368 .data = &(struct clk_regmap_div_data){ 369 .offset = HHI_HDMI_PLL_CNTL0, 370 .shift = 18, 371 .width = 2, 372 .flags = CLK_DIVIDER_POWER_OF_TWO, 373 }, 374 .hw.init = &(struct clk_init_data){ 375 .name = "hdmi_pll_od2", 376 .ops = &clk_regmap_divider_ro_ops, 377 .parent_names = (const char *[]){ "hdmi_pll_od" }, 378 .num_parents = 1, 379 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 380 }, 381 }; 382 383 static struct clk_regmap g12a_hdmi_pll = { 384 .data = &(struct clk_regmap_div_data){ 385 .offset = HHI_HDMI_PLL_CNTL0, 386 .shift = 20, 387 .width = 2, 388 .flags = CLK_DIVIDER_POWER_OF_TWO, 389 }, 390 .hw.init = &(struct clk_init_data){ 391 .name = "hdmi_pll", 392 .ops = &clk_regmap_divider_ro_ops, 393 .parent_names = (const char *[]){ "hdmi_pll_od2" }, 394 .num_parents = 1, 395 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 396 }, 397 }; 398 399 static struct clk_fixed_factor g12a_fclk_div2_div = { 400 .mult = 1, 401 .div = 2, 402 .hw.init = &(struct clk_init_data){ 403 .name = "fclk_div2_div", 404 .ops = &clk_fixed_factor_ops, 405 .parent_names = (const char *[]){ "fixed_pll" }, 406 .num_parents = 1, 407 }, 408 }; 409 410 static struct clk_regmap g12a_fclk_div2 = { 411 .data = &(struct clk_regmap_gate_data){ 412 .offset = HHI_FIX_PLL_CNTL1, 413 .bit_idx = 24, 414 }, 415 .hw.init = &(struct clk_init_data){ 416 .name = "fclk_div2", 417 .ops = &clk_regmap_gate_ops, 418 .parent_names = (const char *[]){ "fclk_div2_div" }, 419 .num_parents = 1, 420 }, 421 }; 422 423 static struct clk_fixed_factor g12a_fclk_div3_div = { 424 .mult = 1, 425 .div = 3, 426 .hw.init = &(struct clk_init_data){ 427 .name = "fclk_div3_div", 428 .ops = &clk_fixed_factor_ops, 429 .parent_names = (const char *[]){ "fixed_pll" }, 430 .num_parents = 1, 431 }, 432 }; 433 434 static struct clk_regmap g12a_fclk_div3 = { 435 .data = &(struct clk_regmap_gate_data){ 436 .offset = HHI_FIX_PLL_CNTL1, 437 .bit_idx = 20, 438 }, 439 .hw.init = &(struct clk_init_data){ 440 .name = "fclk_div3", 441 .ops = &clk_regmap_gate_ops, 442 .parent_names = (const char *[]){ "fclk_div3_div" }, 443 .num_parents = 1, 444 }, 445 }; 446 447 static struct clk_fixed_factor g12a_fclk_div4_div = { 448 .mult = 1, 449 .div = 4, 450 .hw.init = &(struct clk_init_data){ 451 .name = "fclk_div4_div", 452 .ops = &clk_fixed_factor_ops, 453 .parent_names = (const char *[]){ "fixed_pll" }, 454 .num_parents = 1, 455 }, 456 }; 457 458 static struct clk_regmap g12a_fclk_div4 = { 459 .data = &(struct clk_regmap_gate_data){ 460 .offset = HHI_FIX_PLL_CNTL1, 461 .bit_idx = 21, 462 }, 463 .hw.init = &(struct clk_init_data){ 464 .name = "fclk_div4", 465 .ops = &clk_regmap_gate_ops, 466 .parent_names = (const char *[]){ "fclk_div4_div" }, 467 .num_parents = 1, 468 }, 469 }; 470 471 static struct clk_fixed_factor g12a_fclk_div5_div = { 472 .mult = 1, 473 .div = 5, 474 .hw.init = &(struct clk_init_data){ 475 .name = "fclk_div5_div", 476 .ops = &clk_fixed_factor_ops, 477 .parent_names = (const char *[]){ "fixed_pll" }, 478 .num_parents = 1, 479 }, 480 }; 481 482 static struct clk_regmap g12a_fclk_div5 = { 483 .data = &(struct clk_regmap_gate_data){ 484 .offset = HHI_FIX_PLL_CNTL1, 485 .bit_idx = 22, 486 }, 487 .hw.init = &(struct clk_init_data){ 488 .name = "fclk_div5", 489 .ops = &clk_regmap_gate_ops, 490 .parent_names = (const char *[]){ "fclk_div5_div" }, 491 .num_parents = 1, 492 }, 493 }; 494 495 static struct clk_fixed_factor g12a_fclk_div7_div = { 496 .mult = 1, 497 .div = 7, 498 .hw.init = &(struct clk_init_data){ 499 .name = "fclk_div7_div", 500 .ops = &clk_fixed_factor_ops, 501 .parent_names = (const char *[]){ "fixed_pll" }, 502 .num_parents = 1, 503 }, 504 }; 505 506 static struct clk_regmap g12a_fclk_div7 = { 507 .data = &(struct clk_regmap_gate_data){ 508 .offset = HHI_FIX_PLL_CNTL1, 509 .bit_idx = 23, 510 }, 511 .hw.init = &(struct clk_init_data){ 512 .name = "fclk_div7", 513 .ops = &clk_regmap_gate_ops, 514 .parent_names = (const char *[]){ "fclk_div7_div" }, 515 .num_parents = 1, 516 }, 517 }; 518 519 static struct clk_fixed_factor g12a_fclk_div2p5_div = { 520 .mult = 1, 521 .div = 5, 522 .hw.init = &(struct clk_init_data){ 523 .name = "fclk_div2p5_div", 524 .ops = &clk_fixed_factor_ops, 525 .parent_names = (const char *[]){ "fixed_pll_dco" }, 526 .num_parents = 1, 527 }, 528 }; 529 530 static struct clk_regmap g12a_fclk_div2p5 = { 531 .data = &(struct clk_regmap_gate_data){ 532 .offset = HHI_FIX_PLL_CNTL1, 533 .bit_idx = 25, 534 }, 535 .hw.init = &(struct clk_init_data){ 536 .name = "fclk_div2p5", 537 .ops = &clk_regmap_gate_ops, 538 .parent_names = (const char *[]){ "fclk_div2p5_div" }, 539 .num_parents = 1, 540 }, 541 }; 542 543 static struct clk_fixed_factor g12a_mpll_50m_div = { 544 .mult = 1, 545 .div = 80, 546 .hw.init = &(struct clk_init_data){ 547 .name = "mpll_50m_div", 548 .ops = &clk_fixed_factor_ops, 549 .parent_names = (const char *[]){ "fixed_pll_dco" }, 550 .num_parents = 1, 551 }, 552 }; 553 554 static struct clk_regmap g12a_mpll_50m = { 555 .data = &(struct clk_regmap_mux_data){ 556 .offset = HHI_FIX_PLL_CNTL3, 557 .mask = 0x1, 558 .shift = 5, 559 }, 560 .hw.init = &(struct clk_init_data){ 561 .name = "mpll_50m", 562 .ops = &clk_regmap_mux_ro_ops, 563 .parent_names = (const char *[]){ IN_PREFIX "xtal", 564 "mpll_50m_div" }, 565 .num_parents = 2, 566 }, 567 }; 568 569 static struct clk_fixed_factor g12a_mpll_prediv = { 570 .mult = 1, 571 .div = 2, 572 .hw.init = &(struct clk_init_data){ 573 .name = "mpll_prediv", 574 .ops = &clk_fixed_factor_ops, 575 .parent_names = (const char *[]){ "fixed_pll_dco" }, 576 .num_parents = 1, 577 }, 578 }; 579 580 static struct clk_regmap g12a_mpll0_div = { 581 .data = &(struct meson_clk_mpll_data){ 582 .sdm = { 583 .reg_off = HHI_MPLL_CNTL1, 584 .shift = 0, 585 .width = 14, 586 }, 587 .sdm_en = { 588 .reg_off = HHI_MPLL_CNTL1, 589 .shift = 30, 590 .width = 1, 591 }, 592 .n2 = { 593 .reg_off = HHI_MPLL_CNTL1, 594 .shift = 20, 595 .width = 9, 596 }, 597 .ssen = { 598 .reg_off = HHI_MPLL_CNTL1, 599 .shift = 29, 600 .width = 1, 601 }, 602 .lock = &meson_clk_lock, 603 }, 604 .hw.init = &(struct clk_init_data){ 605 .name = "mpll0_div", 606 .ops = &meson_clk_mpll_ops, 607 .parent_names = (const char *[]){ "mpll_prediv" }, 608 .num_parents = 1, 609 }, 610 }; 611 612 static struct clk_regmap g12a_mpll0 = { 613 .data = &(struct clk_regmap_gate_data){ 614 .offset = HHI_MPLL_CNTL1, 615 .bit_idx = 31, 616 }, 617 .hw.init = &(struct clk_init_data){ 618 .name = "mpll0", 619 .ops = &clk_regmap_gate_ops, 620 .parent_names = (const char *[]){ "mpll0_div" }, 621 .num_parents = 1, 622 .flags = CLK_SET_RATE_PARENT, 623 }, 624 }; 625 626 static struct clk_regmap g12a_mpll1_div = { 627 .data = &(struct meson_clk_mpll_data){ 628 .sdm = { 629 .reg_off = HHI_MPLL_CNTL3, 630 .shift = 0, 631 .width = 14, 632 }, 633 .sdm_en = { 634 .reg_off = HHI_MPLL_CNTL3, 635 .shift = 30, 636 .width = 1, 637 }, 638 .n2 = { 639 .reg_off = HHI_MPLL_CNTL3, 640 .shift = 20, 641 .width = 9, 642 }, 643 .ssen = { 644 .reg_off = HHI_MPLL_CNTL3, 645 .shift = 29, 646 .width = 1, 647 }, 648 .lock = &meson_clk_lock, 649 }, 650 .hw.init = &(struct clk_init_data){ 651 .name = "mpll1_div", 652 .ops = &meson_clk_mpll_ops, 653 .parent_names = (const char *[]){ "mpll_prediv" }, 654 .num_parents = 1, 655 }, 656 }; 657 658 static struct clk_regmap g12a_mpll1 = { 659 .data = &(struct clk_regmap_gate_data){ 660 .offset = HHI_MPLL_CNTL3, 661 .bit_idx = 31, 662 }, 663 .hw.init = &(struct clk_init_data){ 664 .name = "mpll1", 665 .ops = &clk_regmap_gate_ops, 666 .parent_names = (const char *[]){ "mpll1_div" }, 667 .num_parents = 1, 668 .flags = CLK_SET_RATE_PARENT, 669 }, 670 }; 671 672 static struct clk_regmap g12a_mpll2_div = { 673 .data = &(struct meson_clk_mpll_data){ 674 .sdm = { 675 .reg_off = HHI_MPLL_CNTL5, 676 .shift = 0, 677 .width = 14, 678 }, 679 .sdm_en = { 680 .reg_off = HHI_MPLL_CNTL5, 681 .shift = 30, 682 .width = 1, 683 }, 684 .n2 = { 685 .reg_off = HHI_MPLL_CNTL5, 686 .shift = 20, 687 .width = 9, 688 }, 689 .ssen = { 690 .reg_off = HHI_MPLL_CNTL5, 691 .shift = 29, 692 .width = 1, 693 }, 694 .lock = &meson_clk_lock, 695 }, 696 .hw.init = &(struct clk_init_data){ 697 .name = "mpll2_div", 698 .ops = &meson_clk_mpll_ops, 699 .parent_names = (const char *[]){ "mpll_prediv" }, 700 .num_parents = 1, 701 }, 702 }; 703 704 static struct clk_regmap g12a_mpll2 = { 705 .data = &(struct clk_regmap_gate_data){ 706 .offset = HHI_MPLL_CNTL5, 707 .bit_idx = 31, 708 }, 709 .hw.init = &(struct clk_init_data){ 710 .name = "mpll2", 711 .ops = &clk_regmap_gate_ops, 712 .parent_names = (const char *[]){ "mpll2_div" }, 713 .num_parents = 1, 714 .flags = CLK_SET_RATE_PARENT, 715 }, 716 }; 717 718 static struct clk_regmap g12a_mpll3_div = { 719 .data = &(struct meson_clk_mpll_data){ 720 .sdm = { 721 .reg_off = HHI_MPLL_CNTL7, 722 .shift = 0, 723 .width = 14, 724 }, 725 .sdm_en = { 726 .reg_off = HHI_MPLL_CNTL7, 727 .shift = 30, 728 .width = 1, 729 }, 730 .n2 = { 731 .reg_off = HHI_MPLL_CNTL7, 732 .shift = 20, 733 .width = 9, 734 }, 735 .ssen = { 736 .reg_off = HHI_MPLL_CNTL7, 737 .shift = 29, 738 .width = 1, 739 }, 740 .lock = &meson_clk_lock, 741 }, 742 .hw.init = &(struct clk_init_data){ 743 .name = "mpll3_div", 744 .ops = &meson_clk_mpll_ops, 745 .parent_names = (const char *[]){ "mpll_prediv" }, 746 .num_parents = 1, 747 }, 748 }; 749 750 static struct clk_regmap g12a_mpll3 = { 751 .data = &(struct clk_regmap_gate_data){ 752 .offset = HHI_MPLL_CNTL7, 753 .bit_idx = 31, 754 }, 755 .hw.init = &(struct clk_init_data){ 756 .name = "mpll3", 757 .ops = &clk_regmap_gate_ops, 758 .parent_names = (const char *[]){ "mpll3_div" }, 759 .num_parents = 1, 760 .flags = CLK_SET_RATE_PARENT, 761 }, 762 }; 763 764 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 765 static const char * const clk81_parent_names[] = { 766 IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", 767 "fclk_div3", "fclk_div5" 768 }; 769 770 static struct clk_regmap g12a_mpeg_clk_sel = { 771 .data = &(struct clk_regmap_mux_data){ 772 .offset = HHI_MPEG_CLK_CNTL, 773 .mask = 0x7, 774 .shift = 12, 775 .table = mux_table_clk81, 776 }, 777 .hw.init = &(struct clk_init_data){ 778 .name = "mpeg_clk_sel", 779 .ops = &clk_regmap_mux_ro_ops, 780 .parent_names = clk81_parent_names, 781 .num_parents = ARRAY_SIZE(clk81_parent_names), 782 }, 783 }; 784 785 static struct clk_regmap g12a_mpeg_clk_div = { 786 .data = &(struct clk_regmap_div_data){ 787 .offset = HHI_MPEG_CLK_CNTL, 788 .shift = 0, 789 .width = 7, 790 }, 791 .hw.init = &(struct clk_init_data){ 792 .name = "mpeg_clk_div", 793 .ops = &clk_regmap_divider_ops, 794 .parent_names = (const char *[]){ "mpeg_clk_sel" }, 795 .num_parents = 1, 796 .flags = CLK_SET_RATE_PARENT, 797 }, 798 }; 799 800 static struct clk_regmap g12a_clk81 = { 801 .data = &(struct clk_regmap_gate_data){ 802 .offset = HHI_MPEG_CLK_CNTL, 803 .bit_idx = 7, 804 }, 805 .hw.init = &(struct clk_init_data){ 806 .name = "clk81", 807 .ops = &clk_regmap_gate_ops, 808 .parent_names = (const char *[]){ "mpeg_clk_div" }, 809 .num_parents = 1, 810 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 811 }, 812 }; 813 814 static const char * const g12a_sd_emmc_clk0_parent_names[] = { 815 IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", 816 817 /* 818 * Following these parent clocks, we should also have had mpll2, mpll3 819 * and gp0_pll but these clocks are too precious to be used here. All 820 * the necessary rates for MMC and NAND operation can be acheived using 821 * g12a_ee_core or fclk_div clocks 822 */ 823 }; 824 825 /* SDIO clock */ 826 static struct clk_regmap g12a_sd_emmc_a_clk0_sel = { 827 .data = &(struct clk_regmap_mux_data){ 828 .offset = HHI_SD_EMMC_CLK_CNTL, 829 .mask = 0x7, 830 .shift = 9, 831 }, 832 .hw.init = &(struct clk_init_data) { 833 .name = "sd_emmc_a_clk0_sel", 834 .ops = &clk_regmap_mux_ops, 835 .parent_names = g12a_sd_emmc_clk0_parent_names, 836 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names), 837 .flags = CLK_SET_RATE_PARENT, 838 }, 839 }; 840 841 static struct clk_regmap g12a_sd_emmc_a_clk0_div = { 842 .data = &(struct clk_regmap_div_data){ 843 .offset = HHI_SD_EMMC_CLK_CNTL, 844 .shift = 0, 845 .width = 7, 846 }, 847 .hw.init = &(struct clk_init_data) { 848 .name = "sd_emmc_a_clk0_div", 849 .ops = &clk_regmap_divider_ops, 850 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" }, 851 .num_parents = 1, 852 .flags = CLK_SET_RATE_PARENT, 853 }, 854 }; 855 856 static struct clk_regmap g12a_sd_emmc_a_clk0 = { 857 .data = &(struct clk_regmap_gate_data){ 858 .offset = HHI_SD_EMMC_CLK_CNTL, 859 .bit_idx = 7, 860 }, 861 .hw.init = &(struct clk_init_data){ 862 .name = "sd_emmc_a_clk0", 863 .ops = &clk_regmap_gate_ops, 864 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" }, 865 .num_parents = 1, 866 .flags = CLK_SET_RATE_PARENT, 867 }, 868 }; 869 870 /* SDcard clock */ 871 static struct clk_regmap g12a_sd_emmc_b_clk0_sel = { 872 .data = &(struct clk_regmap_mux_data){ 873 .offset = HHI_SD_EMMC_CLK_CNTL, 874 .mask = 0x7, 875 .shift = 25, 876 }, 877 .hw.init = &(struct clk_init_data) { 878 .name = "sd_emmc_b_clk0_sel", 879 .ops = &clk_regmap_mux_ops, 880 .parent_names = g12a_sd_emmc_clk0_parent_names, 881 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names), 882 .flags = CLK_SET_RATE_PARENT, 883 }, 884 }; 885 886 static struct clk_regmap g12a_sd_emmc_b_clk0_div = { 887 .data = &(struct clk_regmap_div_data){ 888 .offset = HHI_SD_EMMC_CLK_CNTL, 889 .shift = 16, 890 .width = 7, 891 }, 892 .hw.init = &(struct clk_init_data) { 893 .name = "sd_emmc_b_clk0_div", 894 .ops = &clk_regmap_divider_ops, 895 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, 896 .num_parents = 1, 897 .flags = CLK_SET_RATE_PARENT, 898 }, 899 }; 900 901 static struct clk_regmap g12a_sd_emmc_b_clk0 = { 902 .data = &(struct clk_regmap_gate_data){ 903 .offset = HHI_SD_EMMC_CLK_CNTL, 904 .bit_idx = 23, 905 }, 906 .hw.init = &(struct clk_init_data){ 907 .name = "sd_emmc_b_clk0", 908 .ops = &clk_regmap_gate_ops, 909 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, 910 .num_parents = 1, 911 .flags = CLK_SET_RATE_PARENT, 912 }, 913 }; 914 915 /* EMMC/NAND clock */ 916 static struct clk_regmap g12a_sd_emmc_c_clk0_sel = { 917 .data = &(struct clk_regmap_mux_data){ 918 .offset = HHI_NAND_CLK_CNTL, 919 .mask = 0x7, 920 .shift = 9, 921 }, 922 .hw.init = &(struct clk_init_data) { 923 .name = "sd_emmc_c_clk0_sel", 924 .ops = &clk_regmap_mux_ops, 925 .parent_names = g12a_sd_emmc_clk0_parent_names, 926 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names), 927 .flags = CLK_SET_RATE_PARENT, 928 }, 929 }; 930 931 static struct clk_regmap g12a_sd_emmc_c_clk0_div = { 932 .data = &(struct clk_regmap_div_data){ 933 .offset = HHI_NAND_CLK_CNTL, 934 .shift = 0, 935 .width = 7, 936 }, 937 .hw.init = &(struct clk_init_data) { 938 .name = "sd_emmc_c_clk0_div", 939 .ops = &clk_regmap_divider_ops, 940 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, 941 .num_parents = 1, 942 .flags = CLK_SET_RATE_PARENT, 943 }, 944 }; 945 946 static struct clk_regmap g12a_sd_emmc_c_clk0 = { 947 .data = &(struct clk_regmap_gate_data){ 948 .offset = HHI_NAND_CLK_CNTL, 949 .bit_idx = 7, 950 }, 951 .hw.init = &(struct clk_init_data){ 952 .name = "sd_emmc_c_clk0", 953 .ops = &clk_regmap_gate_ops, 954 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, 955 .num_parents = 1, 956 .flags = CLK_SET_RATE_PARENT, 957 }, 958 }; 959 960 /* VPU Clock */ 961 962 static const char * const g12a_vpu_parent_names[] = { 963 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", 964 "mpll1", "vid_pll", "hifi_pll", "gp0_pll", 965 }; 966 967 static struct clk_regmap g12a_vpu_0_sel = { 968 .data = &(struct clk_regmap_mux_data){ 969 .offset = HHI_VPU_CLK_CNTL, 970 .mask = 0x3, 971 .shift = 9, 972 }, 973 .hw.init = &(struct clk_init_data){ 974 .name = "vpu_0_sel", 975 .ops = &clk_regmap_mux_ops, 976 .parent_names = g12a_vpu_parent_names, 977 .num_parents = ARRAY_SIZE(g12a_vpu_parent_names), 978 .flags = CLK_SET_RATE_NO_REPARENT, 979 }, 980 }; 981 982 static struct clk_regmap g12a_vpu_0_div = { 983 .data = &(struct clk_regmap_div_data){ 984 .offset = HHI_VPU_CLK_CNTL, 985 .shift = 0, 986 .width = 7, 987 }, 988 .hw.init = &(struct clk_init_data){ 989 .name = "vpu_0_div", 990 .ops = &clk_regmap_divider_ops, 991 .parent_names = (const char *[]){ "vpu_0_sel" }, 992 .num_parents = 1, 993 .flags = CLK_SET_RATE_PARENT, 994 }, 995 }; 996 997 static struct clk_regmap g12a_vpu_0 = { 998 .data = &(struct clk_regmap_gate_data){ 999 .offset = HHI_VPU_CLK_CNTL, 1000 .bit_idx = 8, 1001 }, 1002 .hw.init = &(struct clk_init_data) { 1003 .name = "vpu_0", 1004 .ops = &clk_regmap_gate_ops, 1005 .parent_names = (const char *[]){ "vpu_0_div" }, 1006 .num_parents = 1, 1007 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1008 }, 1009 }; 1010 1011 static struct clk_regmap g12a_vpu_1_sel = { 1012 .data = &(struct clk_regmap_mux_data){ 1013 .offset = HHI_VPU_CLK_CNTL, 1014 .mask = 0x3, 1015 .shift = 25, 1016 }, 1017 .hw.init = &(struct clk_init_data){ 1018 .name = "vpu_1_sel", 1019 .ops = &clk_regmap_mux_ops, 1020 .parent_names = g12a_vpu_parent_names, 1021 .num_parents = ARRAY_SIZE(g12a_vpu_parent_names), 1022 .flags = CLK_SET_RATE_NO_REPARENT, 1023 }, 1024 }; 1025 1026 static struct clk_regmap g12a_vpu_1_div = { 1027 .data = &(struct clk_regmap_div_data){ 1028 .offset = HHI_VPU_CLK_CNTL, 1029 .shift = 16, 1030 .width = 7, 1031 }, 1032 .hw.init = &(struct clk_init_data){ 1033 .name = "vpu_1_div", 1034 .ops = &clk_regmap_divider_ops, 1035 .parent_names = (const char *[]){ "vpu_1_sel" }, 1036 .num_parents = 1, 1037 .flags = CLK_SET_RATE_PARENT, 1038 }, 1039 }; 1040 1041 static struct clk_regmap g12a_vpu_1 = { 1042 .data = &(struct clk_regmap_gate_data){ 1043 .offset = HHI_VPU_CLK_CNTL, 1044 .bit_idx = 24, 1045 }, 1046 .hw.init = &(struct clk_init_data) { 1047 .name = "vpu_1", 1048 .ops = &clk_regmap_gate_ops, 1049 .parent_names = (const char *[]){ "vpu_1_div" }, 1050 .num_parents = 1, 1051 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1052 }, 1053 }; 1054 1055 static struct clk_regmap g12a_vpu = { 1056 .data = &(struct clk_regmap_mux_data){ 1057 .offset = HHI_VPU_CLK_CNTL, 1058 .mask = 1, 1059 .shift = 31, 1060 }, 1061 .hw.init = &(struct clk_init_data){ 1062 .name = "vpu", 1063 .ops = &clk_regmap_mux_ops, 1064 /* 1065 * bit 31 selects from 2 possible parents: 1066 * vpu_0 or vpu_1 1067 */ 1068 .parent_names = (const char *[]){ "vpu_0", "vpu_1" }, 1069 .num_parents = 2, 1070 .flags = CLK_SET_RATE_NO_REPARENT, 1071 }, 1072 }; 1073 1074 /* VAPB Clock */ 1075 1076 static const char * const g12a_vapb_parent_names[] = { 1077 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", 1078 "mpll1", "vid_pll", "mpll2", "fclk_div2p5", 1079 }; 1080 1081 static struct clk_regmap g12a_vapb_0_sel = { 1082 .data = &(struct clk_regmap_mux_data){ 1083 .offset = HHI_VAPBCLK_CNTL, 1084 .mask = 0x3, 1085 .shift = 9, 1086 }, 1087 .hw.init = &(struct clk_init_data){ 1088 .name = "vapb_0_sel", 1089 .ops = &clk_regmap_mux_ops, 1090 .parent_names = g12a_vapb_parent_names, 1091 .num_parents = ARRAY_SIZE(g12a_vapb_parent_names), 1092 .flags = CLK_SET_RATE_NO_REPARENT, 1093 }, 1094 }; 1095 1096 static struct clk_regmap g12a_vapb_0_div = { 1097 .data = &(struct clk_regmap_div_data){ 1098 .offset = HHI_VAPBCLK_CNTL, 1099 .shift = 0, 1100 .width = 7, 1101 }, 1102 .hw.init = &(struct clk_init_data){ 1103 .name = "vapb_0_div", 1104 .ops = &clk_regmap_divider_ops, 1105 .parent_names = (const char *[]){ "vapb_0_sel" }, 1106 .num_parents = 1, 1107 .flags = CLK_SET_RATE_PARENT, 1108 }, 1109 }; 1110 1111 static struct clk_regmap g12a_vapb_0 = { 1112 .data = &(struct clk_regmap_gate_data){ 1113 .offset = HHI_VAPBCLK_CNTL, 1114 .bit_idx = 8, 1115 }, 1116 .hw.init = &(struct clk_init_data) { 1117 .name = "vapb_0", 1118 .ops = &clk_regmap_gate_ops, 1119 .parent_names = (const char *[]){ "vapb_0_div" }, 1120 .num_parents = 1, 1121 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1122 }, 1123 }; 1124 1125 static struct clk_regmap g12a_vapb_1_sel = { 1126 .data = &(struct clk_regmap_mux_data){ 1127 .offset = HHI_VAPBCLK_CNTL, 1128 .mask = 0x3, 1129 .shift = 25, 1130 }, 1131 .hw.init = &(struct clk_init_data){ 1132 .name = "vapb_1_sel", 1133 .ops = &clk_regmap_mux_ops, 1134 .parent_names = g12a_vapb_parent_names, 1135 .num_parents = ARRAY_SIZE(g12a_vapb_parent_names), 1136 .flags = CLK_SET_RATE_NO_REPARENT, 1137 }, 1138 }; 1139 1140 static struct clk_regmap g12a_vapb_1_div = { 1141 .data = &(struct clk_regmap_div_data){ 1142 .offset = HHI_VAPBCLK_CNTL, 1143 .shift = 16, 1144 .width = 7, 1145 }, 1146 .hw.init = &(struct clk_init_data){ 1147 .name = "vapb_1_div", 1148 .ops = &clk_regmap_divider_ops, 1149 .parent_names = (const char *[]){ "vapb_1_sel" }, 1150 .num_parents = 1, 1151 .flags = CLK_SET_RATE_PARENT, 1152 }, 1153 }; 1154 1155 static struct clk_regmap g12a_vapb_1 = { 1156 .data = &(struct clk_regmap_gate_data){ 1157 .offset = HHI_VAPBCLK_CNTL, 1158 .bit_idx = 24, 1159 }, 1160 .hw.init = &(struct clk_init_data) { 1161 .name = "vapb_1", 1162 .ops = &clk_regmap_gate_ops, 1163 .parent_names = (const char *[]){ "vapb_1_div" }, 1164 .num_parents = 1, 1165 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1166 }, 1167 }; 1168 1169 static struct clk_regmap g12a_vapb_sel = { 1170 .data = &(struct clk_regmap_mux_data){ 1171 .offset = HHI_VAPBCLK_CNTL, 1172 .mask = 1, 1173 .shift = 31, 1174 }, 1175 .hw.init = &(struct clk_init_data){ 1176 .name = "vapb_sel", 1177 .ops = &clk_regmap_mux_ops, 1178 /* 1179 * bit 31 selects from 2 possible parents: 1180 * vapb_0 or vapb_1 1181 */ 1182 .parent_names = (const char *[]){ "vapb_0", "vapb_1" }, 1183 .num_parents = 2, 1184 .flags = CLK_SET_RATE_NO_REPARENT, 1185 }, 1186 }; 1187 1188 static struct clk_regmap g12a_vapb = { 1189 .data = &(struct clk_regmap_gate_data){ 1190 .offset = HHI_VAPBCLK_CNTL, 1191 .bit_idx = 30, 1192 }, 1193 .hw.init = &(struct clk_init_data) { 1194 .name = "vapb", 1195 .ops = &clk_regmap_gate_ops, 1196 .parent_names = (const char *[]){ "vapb_sel" }, 1197 .num_parents = 1, 1198 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1199 }, 1200 }; 1201 1202 /* Video Clocks */ 1203 1204 static struct clk_regmap g12a_vid_pll_div = { 1205 .data = &(struct meson_vid_pll_div_data){ 1206 .val = { 1207 .reg_off = HHI_VID_PLL_CLK_DIV, 1208 .shift = 0, 1209 .width = 15, 1210 }, 1211 .sel = { 1212 .reg_off = HHI_VID_PLL_CLK_DIV, 1213 .shift = 16, 1214 .width = 2, 1215 }, 1216 }, 1217 .hw.init = &(struct clk_init_data) { 1218 .name = "vid_pll_div", 1219 .ops = &meson_vid_pll_div_ro_ops, 1220 .parent_names = (const char *[]){ "hdmi_pll" }, 1221 .num_parents = 1, 1222 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 1223 }, 1224 }; 1225 1226 static const char * const g12a_vid_pll_parent_names[] = { "vid_pll_div", 1227 "hdmi_pll" }; 1228 1229 static struct clk_regmap g12a_vid_pll_sel = { 1230 .data = &(struct clk_regmap_mux_data){ 1231 .offset = HHI_VID_PLL_CLK_DIV, 1232 .mask = 0x1, 1233 .shift = 18, 1234 }, 1235 .hw.init = &(struct clk_init_data){ 1236 .name = "vid_pll_sel", 1237 .ops = &clk_regmap_mux_ops, 1238 /* 1239 * bit 18 selects from 2 possible parents: 1240 * vid_pll_div or hdmi_pll 1241 */ 1242 .parent_names = g12a_vid_pll_parent_names, 1243 .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_names), 1244 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1245 }, 1246 }; 1247 1248 static struct clk_regmap g12a_vid_pll = { 1249 .data = &(struct clk_regmap_gate_data){ 1250 .offset = HHI_VID_PLL_CLK_DIV, 1251 .bit_idx = 19, 1252 }, 1253 .hw.init = &(struct clk_init_data) { 1254 .name = "vid_pll", 1255 .ops = &clk_regmap_gate_ops, 1256 .parent_names = (const char *[]){ "vid_pll_sel" }, 1257 .num_parents = 1, 1258 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1259 }, 1260 }; 1261 1262 static const char * const g12a_vclk_parent_names[] = { 1263 "vid_pll", "gp0_pll", "hifi_pll", "mpll1", "fclk_div3", "fclk_div4", 1264 "fclk_div5", "fclk_div7" 1265 }; 1266 1267 static struct clk_regmap g12a_vclk_sel = { 1268 .data = &(struct clk_regmap_mux_data){ 1269 .offset = HHI_VID_CLK_CNTL, 1270 .mask = 0x7, 1271 .shift = 16, 1272 }, 1273 .hw.init = &(struct clk_init_data){ 1274 .name = "vclk_sel", 1275 .ops = &clk_regmap_mux_ops, 1276 .parent_names = g12a_vclk_parent_names, 1277 .num_parents = ARRAY_SIZE(g12a_vclk_parent_names), 1278 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1279 }, 1280 }; 1281 1282 static struct clk_regmap g12a_vclk2_sel = { 1283 .data = &(struct clk_regmap_mux_data){ 1284 .offset = HHI_VIID_CLK_CNTL, 1285 .mask = 0x7, 1286 .shift = 16, 1287 }, 1288 .hw.init = &(struct clk_init_data){ 1289 .name = "vclk2_sel", 1290 .ops = &clk_regmap_mux_ops, 1291 .parent_names = g12a_vclk_parent_names, 1292 .num_parents = ARRAY_SIZE(g12a_vclk_parent_names), 1293 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1294 }, 1295 }; 1296 1297 static struct clk_regmap g12a_vclk_input = { 1298 .data = &(struct clk_regmap_gate_data){ 1299 .offset = HHI_VID_CLK_DIV, 1300 .bit_idx = 16, 1301 }, 1302 .hw.init = &(struct clk_init_data) { 1303 .name = "vclk_input", 1304 .ops = &clk_regmap_gate_ops, 1305 .parent_names = (const char *[]){ "vclk_sel" }, 1306 .num_parents = 1, 1307 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1308 }, 1309 }; 1310 1311 static struct clk_regmap g12a_vclk2_input = { 1312 .data = &(struct clk_regmap_gate_data){ 1313 .offset = HHI_VIID_CLK_DIV, 1314 .bit_idx = 16, 1315 }, 1316 .hw.init = &(struct clk_init_data) { 1317 .name = "vclk2_input", 1318 .ops = &clk_regmap_gate_ops, 1319 .parent_names = (const char *[]){ "vclk2_sel" }, 1320 .num_parents = 1, 1321 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1322 }, 1323 }; 1324 1325 static struct clk_regmap g12a_vclk_div = { 1326 .data = &(struct clk_regmap_div_data){ 1327 .offset = HHI_VID_CLK_DIV, 1328 .shift = 0, 1329 .width = 8, 1330 }, 1331 .hw.init = &(struct clk_init_data){ 1332 .name = "vclk_div", 1333 .ops = &clk_regmap_divider_ops, 1334 .parent_names = (const char *[]){ "vclk_input" }, 1335 .num_parents = 1, 1336 .flags = CLK_GET_RATE_NOCACHE, 1337 }, 1338 }; 1339 1340 static struct clk_regmap g12a_vclk2_div = { 1341 .data = &(struct clk_regmap_div_data){ 1342 .offset = HHI_VIID_CLK_DIV, 1343 .shift = 0, 1344 .width = 8, 1345 }, 1346 .hw.init = &(struct clk_init_data){ 1347 .name = "vclk2_div", 1348 .ops = &clk_regmap_divider_ops, 1349 .parent_names = (const char *[]){ "vclk2_input" }, 1350 .num_parents = 1, 1351 .flags = CLK_GET_RATE_NOCACHE, 1352 }, 1353 }; 1354 1355 static struct clk_regmap g12a_vclk = { 1356 .data = &(struct clk_regmap_gate_data){ 1357 .offset = HHI_VID_CLK_CNTL, 1358 .bit_idx = 19, 1359 }, 1360 .hw.init = &(struct clk_init_data) { 1361 .name = "vclk", 1362 .ops = &clk_regmap_gate_ops, 1363 .parent_names = (const char *[]){ "vclk_div" }, 1364 .num_parents = 1, 1365 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1366 }, 1367 }; 1368 1369 static struct clk_regmap g12a_vclk2 = { 1370 .data = &(struct clk_regmap_gate_data){ 1371 .offset = HHI_VIID_CLK_CNTL, 1372 .bit_idx = 19, 1373 }, 1374 .hw.init = &(struct clk_init_data) { 1375 .name = "vclk2", 1376 .ops = &clk_regmap_gate_ops, 1377 .parent_names = (const char *[]){ "vclk2_div" }, 1378 .num_parents = 1, 1379 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1380 }, 1381 }; 1382 1383 static struct clk_regmap g12a_vclk_div1 = { 1384 .data = &(struct clk_regmap_gate_data){ 1385 .offset = HHI_VID_CLK_CNTL, 1386 .bit_idx = 0, 1387 }, 1388 .hw.init = &(struct clk_init_data) { 1389 .name = "vclk_div1", 1390 .ops = &clk_regmap_gate_ops, 1391 .parent_names = (const char *[]){ "vclk" }, 1392 .num_parents = 1, 1393 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1394 }, 1395 }; 1396 1397 static struct clk_regmap g12a_vclk_div2_en = { 1398 .data = &(struct clk_regmap_gate_data){ 1399 .offset = HHI_VID_CLK_CNTL, 1400 .bit_idx = 1, 1401 }, 1402 .hw.init = &(struct clk_init_data) { 1403 .name = "vclk_div2_en", 1404 .ops = &clk_regmap_gate_ops, 1405 .parent_names = (const char *[]){ "vclk" }, 1406 .num_parents = 1, 1407 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1408 }, 1409 }; 1410 1411 static struct clk_regmap g12a_vclk_div4_en = { 1412 .data = &(struct clk_regmap_gate_data){ 1413 .offset = HHI_VID_CLK_CNTL, 1414 .bit_idx = 2, 1415 }, 1416 .hw.init = &(struct clk_init_data) { 1417 .name = "vclk_div4_en", 1418 .ops = &clk_regmap_gate_ops, 1419 .parent_names = (const char *[]){ "vclk" }, 1420 .num_parents = 1, 1421 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1422 }, 1423 }; 1424 1425 static struct clk_regmap g12a_vclk_div6_en = { 1426 .data = &(struct clk_regmap_gate_data){ 1427 .offset = HHI_VID_CLK_CNTL, 1428 .bit_idx = 3, 1429 }, 1430 .hw.init = &(struct clk_init_data) { 1431 .name = "vclk_div6_en", 1432 .ops = &clk_regmap_gate_ops, 1433 .parent_names = (const char *[]){ "vclk" }, 1434 .num_parents = 1, 1435 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1436 }, 1437 }; 1438 1439 static struct clk_regmap g12a_vclk_div12_en = { 1440 .data = &(struct clk_regmap_gate_data){ 1441 .offset = HHI_VID_CLK_CNTL, 1442 .bit_idx = 4, 1443 }, 1444 .hw.init = &(struct clk_init_data) { 1445 .name = "vclk_div12_en", 1446 .ops = &clk_regmap_gate_ops, 1447 .parent_names = (const char *[]){ "vclk" }, 1448 .num_parents = 1, 1449 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1450 }, 1451 }; 1452 1453 static struct clk_regmap g12a_vclk2_div1 = { 1454 .data = &(struct clk_regmap_gate_data){ 1455 .offset = HHI_VIID_CLK_CNTL, 1456 .bit_idx = 0, 1457 }, 1458 .hw.init = &(struct clk_init_data) { 1459 .name = "vclk2_div1", 1460 .ops = &clk_regmap_gate_ops, 1461 .parent_names = (const char *[]){ "vclk2" }, 1462 .num_parents = 1, 1463 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1464 }, 1465 }; 1466 1467 static struct clk_regmap g12a_vclk2_div2_en = { 1468 .data = &(struct clk_regmap_gate_data){ 1469 .offset = HHI_VIID_CLK_CNTL, 1470 .bit_idx = 1, 1471 }, 1472 .hw.init = &(struct clk_init_data) { 1473 .name = "vclk2_div2_en", 1474 .ops = &clk_regmap_gate_ops, 1475 .parent_names = (const char *[]){ "vclk2" }, 1476 .num_parents = 1, 1477 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1478 }, 1479 }; 1480 1481 static struct clk_regmap g12a_vclk2_div4_en = { 1482 .data = &(struct clk_regmap_gate_data){ 1483 .offset = HHI_VIID_CLK_CNTL, 1484 .bit_idx = 2, 1485 }, 1486 .hw.init = &(struct clk_init_data) { 1487 .name = "vclk2_div4_en", 1488 .ops = &clk_regmap_gate_ops, 1489 .parent_names = (const char *[]){ "vclk2" }, 1490 .num_parents = 1, 1491 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1492 }, 1493 }; 1494 1495 static struct clk_regmap g12a_vclk2_div6_en = { 1496 .data = &(struct clk_regmap_gate_data){ 1497 .offset = HHI_VIID_CLK_CNTL, 1498 .bit_idx = 3, 1499 }, 1500 .hw.init = &(struct clk_init_data) { 1501 .name = "vclk2_div6_en", 1502 .ops = &clk_regmap_gate_ops, 1503 .parent_names = (const char *[]){ "vclk2" }, 1504 .num_parents = 1, 1505 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1506 }, 1507 }; 1508 1509 static struct clk_regmap g12a_vclk2_div12_en = { 1510 .data = &(struct clk_regmap_gate_data){ 1511 .offset = HHI_VIID_CLK_CNTL, 1512 .bit_idx = 4, 1513 }, 1514 .hw.init = &(struct clk_init_data) { 1515 .name = "vclk2_div12_en", 1516 .ops = &clk_regmap_gate_ops, 1517 .parent_names = (const char *[]){ "vclk2" }, 1518 .num_parents = 1, 1519 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1520 }, 1521 }; 1522 1523 static struct clk_fixed_factor g12a_vclk_div2 = { 1524 .mult = 1, 1525 .div = 2, 1526 .hw.init = &(struct clk_init_data){ 1527 .name = "vclk_div2", 1528 .ops = &clk_fixed_factor_ops, 1529 .parent_names = (const char *[]){ "vclk_div2_en" }, 1530 .num_parents = 1, 1531 }, 1532 }; 1533 1534 static struct clk_fixed_factor g12a_vclk_div4 = { 1535 .mult = 1, 1536 .div = 4, 1537 .hw.init = &(struct clk_init_data){ 1538 .name = "vclk_div4", 1539 .ops = &clk_fixed_factor_ops, 1540 .parent_names = (const char *[]){ "vclk_div4_en" }, 1541 .num_parents = 1, 1542 }, 1543 }; 1544 1545 static struct clk_fixed_factor g12a_vclk_div6 = { 1546 .mult = 1, 1547 .div = 6, 1548 .hw.init = &(struct clk_init_data){ 1549 .name = "vclk_div6", 1550 .ops = &clk_fixed_factor_ops, 1551 .parent_names = (const char *[]){ "vclk_div6_en" }, 1552 .num_parents = 1, 1553 }, 1554 }; 1555 1556 static struct clk_fixed_factor g12a_vclk_div12 = { 1557 .mult = 1, 1558 .div = 12, 1559 .hw.init = &(struct clk_init_data){ 1560 .name = "vclk_div12", 1561 .ops = &clk_fixed_factor_ops, 1562 .parent_names = (const char *[]){ "vclk_div12_en" }, 1563 .num_parents = 1, 1564 }, 1565 }; 1566 1567 static struct clk_fixed_factor g12a_vclk2_div2 = { 1568 .mult = 1, 1569 .div = 2, 1570 .hw.init = &(struct clk_init_data){ 1571 .name = "vclk2_div2", 1572 .ops = &clk_fixed_factor_ops, 1573 .parent_names = (const char *[]){ "vclk2_div2_en" }, 1574 .num_parents = 1, 1575 }, 1576 }; 1577 1578 static struct clk_fixed_factor g12a_vclk2_div4 = { 1579 .mult = 1, 1580 .div = 4, 1581 .hw.init = &(struct clk_init_data){ 1582 .name = "vclk2_div4", 1583 .ops = &clk_fixed_factor_ops, 1584 .parent_names = (const char *[]){ "vclk2_div4_en" }, 1585 .num_parents = 1, 1586 }, 1587 }; 1588 1589 static struct clk_fixed_factor g12a_vclk2_div6 = { 1590 .mult = 1, 1591 .div = 6, 1592 .hw.init = &(struct clk_init_data){ 1593 .name = "vclk2_div6", 1594 .ops = &clk_fixed_factor_ops, 1595 .parent_names = (const char *[]){ "vclk2_div6_en" }, 1596 .num_parents = 1, 1597 }, 1598 }; 1599 1600 static struct clk_fixed_factor g12a_vclk2_div12 = { 1601 .mult = 1, 1602 .div = 12, 1603 .hw.init = &(struct clk_init_data){ 1604 .name = "vclk2_div12", 1605 .ops = &clk_fixed_factor_ops, 1606 .parent_names = (const char *[]){ "vclk2_div12_en" }, 1607 .num_parents = 1, 1608 }, 1609 }; 1610 1611 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 1612 static const char * const g12a_cts_parent_names[] = { 1613 "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6", 1614 "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4", 1615 "vclk2_div6", "vclk2_div12" 1616 }; 1617 1618 static struct clk_regmap g12a_cts_enci_sel = { 1619 .data = &(struct clk_regmap_mux_data){ 1620 .offset = HHI_VID_CLK_DIV, 1621 .mask = 0xf, 1622 .shift = 28, 1623 .table = mux_table_cts_sel, 1624 }, 1625 .hw.init = &(struct clk_init_data){ 1626 .name = "cts_enci_sel", 1627 .ops = &clk_regmap_mux_ops, 1628 .parent_names = g12a_cts_parent_names, 1629 .num_parents = ARRAY_SIZE(g12a_cts_parent_names), 1630 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1631 }, 1632 }; 1633 1634 static struct clk_regmap g12a_cts_encp_sel = { 1635 .data = &(struct clk_regmap_mux_data){ 1636 .offset = HHI_VID_CLK_DIV, 1637 .mask = 0xf, 1638 .shift = 20, 1639 .table = mux_table_cts_sel, 1640 }, 1641 .hw.init = &(struct clk_init_data){ 1642 .name = "cts_encp_sel", 1643 .ops = &clk_regmap_mux_ops, 1644 .parent_names = g12a_cts_parent_names, 1645 .num_parents = ARRAY_SIZE(g12a_cts_parent_names), 1646 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1647 }, 1648 }; 1649 1650 static struct clk_regmap g12a_cts_vdac_sel = { 1651 .data = &(struct clk_regmap_mux_data){ 1652 .offset = HHI_VIID_CLK_DIV, 1653 .mask = 0xf, 1654 .shift = 28, 1655 .table = mux_table_cts_sel, 1656 }, 1657 .hw.init = &(struct clk_init_data){ 1658 .name = "cts_vdac_sel", 1659 .ops = &clk_regmap_mux_ops, 1660 .parent_names = g12a_cts_parent_names, 1661 .num_parents = ARRAY_SIZE(g12a_cts_parent_names), 1662 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1663 }, 1664 }; 1665 1666 /* TOFIX: add support for cts_tcon */ 1667 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 1668 static const char * const g12a_cts_hdmi_tx_parent_names[] = { 1669 "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6", 1670 "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4", 1671 "vclk2_div6", "vclk2_div12" 1672 }; 1673 1674 static struct clk_regmap g12a_hdmi_tx_sel = { 1675 .data = &(struct clk_regmap_mux_data){ 1676 .offset = HHI_HDMI_CLK_CNTL, 1677 .mask = 0xf, 1678 .shift = 16, 1679 .table = mux_table_hdmi_tx_sel, 1680 }, 1681 .hw.init = &(struct clk_init_data){ 1682 .name = "hdmi_tx_sel", 1683 .ops = &clk_regmap_mux_ops, 1684 .parent_names = g12a_cts_hdmi_tx_parent_names, 1685 .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_names), 1686 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1687 }, 1688 }; 1689 1690 static struct clk_regmap g12a_cts_enci = { 1691 .data = &(struct clk_regmap_gate_data){ 1692 .offset = HHI_VID_CLK_CNTL2, 1693 .bit_idx = 0, 1694 }, 1695 .hw.init = &(struct clk_init_data) { 1696 .name = "cts_enci", 1697 .ops = &clk_regmap_gate_ops, 1698 .parent_names = (const char *[]){ "cts_enci_sel" }, 1699 .num_parents = 1, 1700 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1701 }, 1702 }; 1703 1704 static struct clk_regmap g12a_cts_encp = { 1705 .data = &(struct clk_regmap_gate_data){ 1706 .offset = HHI_VID_CLK_CNTL2, 1707 .bit_idx = 2, 1708 }, 1709 .hw.init = &(struct clk_init_data) { 1710 .name = "cts_encp", 1711 .ops = &clk_regmap_gate_ops, 1712 .parent_names = (const char *[]){ "cts_encp_sel" }, 1713 .num_parents = 1, 1714 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1715 }, 1716 }; 1717 1718 static struct clk_regmap g12a_cts_vdac = { 1719 .data = &(struct clk_regmap_gate_data){ 1720 .offset = HHI_VID_CLK_CNTL2, 1721 .bit_idx = 4, 1722 }, 1723 .hw.init = &(struct clk_init_data) { 1724 .name = "cts_vdac", 1725 .ops = &clk_regmap_gate_ops, 1726 .parent_names = (const char *[]){ "cts_vdac_sel" }, 1727 .num_parents = 1, 1728 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1729 }, 1730 }; 1731 1732 static struct clk_regmap g12a_hdmi_tx = { 1733 .data = &(struct clk_regmap_gate_data){ 1734 .offset = HHI_VID_CLK_CNTL2, 1735 .bit_idx = 5, 1736 }, 1737 .hw.init = &(struct clk_init_data) { 1738 .name = "hdmi_tx", 1739 .ops = &clk_regmap_gate_ops, 1740 .parent_names = (const char *[]){ "hdmi_tx_sel" }, 1741 .num_parents = 1, 1742 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1743 }, 1744 }; 1745 1746 /* HDMI Clocks */ 1747 1748 static const char * const g12a_hdmi_parent_names[] = { 1749 IN_PREFIX "xtal", "fclk_div4", "fclk_div3", "fclk_div5" 1750 }; 1751 1752 static struct clk_regmap g12a_hdmi_sel = { 1753 .data = &(struct clk_regmap_mux_data){ 1754 .offset = HHI_HDMI_CLK_CNTL, 1755 .mask = 0x3, 1756 .shift = 9, 1757 .flags = CLK_MUX_ROUND_CLOSEST, 1758 }, 1759 .hw.init = &(struct clk_init_data){ 1760 .name = "hdmi_sel", 1761 .ops = &clk_regmap_mux_ops, 1762 .parent_names = g12a_hdmi_parent_names, 1763 .num_parents = ARRAY_SIZE(g12a_hdmi_parent_names), 1764 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1765 }, 1766 }; 1767 1768 static struct clk_regmap g12a_hdmi_div = { 1769 .data = &(struct clk_regmap_div_data){ 1770 .offset = HHI_HDMI_CLK_CNTL, 1771 .shift = 0, 1772 .width = 7, 1773 }, 1774 .hw.init = &(struct clk_init_data){ 1775 .name = "hdmi_div", 1776 .ops = &clk_regmap_divider_ops, 1777 .parent_names = (const char *[]){ "hdmi_sel" }, 1778 .num_parents = 1, 1779 .flags = CLK_GET_RATE_NOCACHE, 1780 }, 1781 }; 1782 1783 static struct clk_regmap g12a_hdmi = { 1784 .data = &(struct clk_regmap_gate_data){ 1785 .offset = HHI_HDMI_CLK_CNTL, 1786 .bit_idx = 8, 1787 }, 1788 .hw.init = &(struct clk_init_data) { 1789 .name = "hdmi", 1790 .ops = &clk_regmap_gate_ops, 1791 .parent_names = (const char *[]){ "hdmi_div" }, 1792 .num_parents = 1, 1793 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1794 }, 1795 }; 1796 1797 /* 1798 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 1799 * muxed by a glitch-free switch. 1800 */ 1801 1802 static const char * const g12a_mali_0_1_parent_names[] = { 1803 IN_PREFIX "xtal", "gp0_pll", "hihi_pll", "fclk_div2p5", 1804 "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7" 1805 }; 1806 1807 static struct clk_regmap g12a_mali_0_sel = { 1808 .data = &(struct clk_regmap_mux_data){ 1809 .offset = HHI_MALI_CLK_CNTL, 1810 .mask = 0x7, 1811 .shift = 9, 1812 }, 1813 .hw.init = &(struct clk_init_data){ 1814 .name = "mali_0_sel", 1815 .ops = &clk_regmap_mux_ops, 1816 .parent_names = g12a_mali_0_1_parent_names, 1817 .num_parents = 8, 1818 .flags = CLK_SET_RATE_NO_REPARENT, 1819 }, 1820 }; 1821 1822 static struct clk_regmap g12a_mali_0_div = { 1823 .data = &(struct clk_regmap_div_data){ 1824 .offset = HHI_MALI_CLK_CNTL, 1825 .shift = 0, 1826 .width = 7, 1827 }, 1828 .hw.init = &(struct clk_init_data){ 1829 .name = "mali_0_div", 1830 .ops = &clk_regmap_divider_ops, 1831 .parent_names = (const char *[]){ "mali_0_sel" }, 1832 .num_parents = 1, 1833 .flags = CLK_SET_RATE_NO_REPARENT, 1834 }, 1835 }; 1836 1837 static struct clk_regmap g12a_mali_0 = { 1838 .data = &(struct clk_regmap_gate_data){ 1839 .offset = HHI_MALI_CLK_CNTL, 1840 .bit_idx = 8, 1841 }, 1842 .hw.init = &(struct clk_init_data){ 1843 .name = "mali_0", 1844 .ops = &clk_regmap_gate_ops, 1845 .parent_names = (const char *[]){ "mali_0_div" }, 1846 .num_parents = 1, 1847 .flags = CLK_SET_RATE_PARENT, 1848 }, 1849 }; 1850 1851 static struct clk_regmap g12a_mali_1_sel = { 1852 .data = &(struct clk_regmap_mux_data){ 1853 .offset = HHI_MALI_CLK_CNTL, 1854 .mask = 0x7, 1855 .shift = 25, 1856 }, 1857 .hw.init = &(struct clk_init_data){ 1858 .name = "mali_1_sel", 1859 .ops = &clk_regmap_mux_ops, 1860 .parent_names = g12a_mali_0_1_parent_names, 1861 .num_parents = 8, 1862 .flags = CLK_SET_RATE_NO_REPARENT, 1863 }, 1864 }; 1865 1866 static struct clk_regmap g12a_mali_1_div = { 1867 .data = &(struct clk_regmap_div_data){ 1868 .offset = HHI_MALI_CLK_CNTL, 1869 .shift = 16, 1870 .width = 7, 1871 }, 1872 .hw.init = &(struct clk_init_data){ 1873 .name = "mali_1_div", 1874 .ops = &clk_regmap_divider_ops, 1875 .parent_names = (const char *[]){ "mali_1_sel" }, 1876 .num_parents = 1, 1877 .flags = CLK_SET_RATE_NO_REPARENT, 1878 }, 1879 }; 1880 1881 static struct clk_regmap g12a_mali_1 = { 1882 .data = &(struct clk_regmap_gate_data){ 1883 .offset = HHI_MALI_CLK_CNTL, 1884 .bit_idx = 24, 1885 }, 1886 .hw.init = &(struct clk_init_data){ 1887 .name = "mali_1", 1888 .ops = &clk_regmap_gate_ops, 1889 .parent_names = (const char *[]){ "mali_1_div" }, 1890 .num_parents = 1, 1891 .flags = CLK_SET_RATE_PARENT, 1892 }, 1893 }; 1894 1895 static const char * const g12a_mali_parent_names[] = { 1896 "mali_0", "mali_1" 1897 }; 1898 1899 static struct clk_regmap g12a_mali = { 1900 .data = &(struct clk_regmap_mux_data){ 1901 .offset = HHI_MALI_CLK_CNTL, 1902 .mask = 1, 1903 .shift = 31, 1904 }, 1905 .hw.init = &(struct clk_init_data){ 1906 .name = "mali", 1907 .ops = &clk_regmap_mux_ops, 1908 .parent_names = g12a_mali_parent_names, 1909 .num_parents = 2, 1910 .flags = CLK_SET_RATE_NO_REPARENT, 1911 }, 1912 }; 1913 1914 /* Everything Else (EE) domain gates */ 1915 static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0); 1916 static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1); 1917 static MESON_GATE(g12a_audio_locker, HHI_GCLK_MPEG0, 2); 1918 static MESON_GATE(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3); 1919 static MESON_GATE(g12a_eth_phy, HHI_GCLK_MPEG0, 4); 1920 static MESON_GATE(g12a_isa, HHI_GCLK_MPEG0, 5); 1921 static MESON_GATE(g12a_pl301, HHI_GCLK_MPEG0, 6); 1922 static MESON_GATE(g12a_periphs, HHI_GCLK_MPEG0, 7); 1923 static MESON_GATE(g12a_spicc_0, HHI_GCLK_MPEG0, 8); 1924 static MESON_GATE(g12a_i2c, HHI_GCLK_MPEG0, 9); 1925 static MESON_GATE(g12a_sana, HHI_GCLK_MPEG0, 10); 1926 static MESON_GATE(g12a_sd, HHI_GCLK_MPEG0, 11); 1927 static MESON_GATE(g12a_rng0, HHI_GCLK_MPEG0, 12); 1928 static MESON_GATE(g12a_uart0, HHI_GCLK_MPEG0, 13); 1929 static MESON_GATE(g12a_spicc_1, HHI_GCLK_MPEG0, 14); 1930 static MESON_GATE(g12a_hiu_reg, HHI_GCLK_MPEG0, 19); 1931 static MESON_GATE(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20); 1932 static MESON_GATE(g12a_assist_misc, HHI_GCLK_MPEG0, 23); 1933 static MESON_GATE(g12a_emmc_a, HHI_GCLK_MPEG0, 4); 1934 static MESON_GATE(g12a_emmc_b, HHI_GCLK_MPEG0, 25); 1935 static MESON_GATE(g12a_emmc_c, HHI_GCLK_MPEG0, 26); 1936 static MESON_GATE(g12a_audio_codec, HHI_GCLK_MPEG0, 28); 1937 1938 static MESON_GATE(g12a_audio, HHI_GCLK_MPEG1, 0); 1939 static MESON_GATE(g12a_eth_core, HHI_GCLK_MPEG1, 3); 1940 static MESON_GATE(g12a_demux, HHI_GCLK_MPEG1, 4); 1941 static MESON_GATE(g12a_audio_ififo, HHI_GCLK_MPEG1, 11); 1942 static MESON_GATE(g12a_adc, HHI_GCLK_MPEG1, 13); 1943 static MESON_GATE(g12a_uart1, HHI_GCLK_MPEG1, 16); 1944 static MESON_GATE(g12a_g2d, HHI_GCLK_MPEG1, 20); 1945 static MESON_GATE(g12a_reset, HHI_GCLK_MPEG1, 23); 1946 static MESON_GATE(g12a_pcie_comb, HHI_GCLK_MPEG1, 24); 1947 static MESON_GATE(g12a_parser, HHI_GCLK_MPEG1, 25); 1948 static MESON_GATE(g12a_usb_general, HHI_GCLK_MPEG1, 26); 1949 static MESON_GATE(g12a_pcie_phy, HHI_GCLK_MPEG1, 27); 1950 static MESON_GATE(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29); 1951 1952 static MESON_GATE(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1); 1953 static MESON_GATE(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 1954 static MESON_GATE(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3); 1955 static MESON_GATE(g12a_htx_pclk, HHI_GCLK_MPEG2, 4); 1956 static MESON_GATE(g12a_bt656, HHI_GCLK_MPEG2, 6); 1957 static MESON_GATE(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8); 1958 static MESON_GATE(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11); 1959 static MESON_GATE(g12a_uart2, HHI_GCLK_MPEG2, 15); 1960 static MESON_GATE(g12a_vpu_intr, HHI_GCLK_MPEG2, 25); 1961 static MESON_GATE(g12a_gic, HHI_GCLK_MPEG2, 30); 1962 1963 static MESON_GATE(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1); 1964 static MESON_GATE(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2); 1965 static MESON_GATE(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3); 1966 static MESON_GATE(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4); 1967 static MESON_GATE(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5); 1968 static MESON_GATE(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6); 1969 static MESON_GATE(g12a_vclk2_other, HHI_GCLK_OTHER, 7); 1970 static MESON_GATE(g12a_vclk2_enci, HHI_GCLK_OTHER, 8); 1971 static MESON_GATE(g12a_vclk2_encp, HHI_GCLK_OTHER, 9); 1972 static MESON_GATE(g12a_dac_clk, HHI_GCLK_OTHER, 10); 1973 static MESON_GATE(g12a_aoclk_gate, HHI_GCLK_OTHER, 14); 1974 static MESON_GATE(g12a_iec958_gate, HHI_GCLK_OTHER, 16); 1975 static MESON_GATE(g12a_enc480p, HHI_GCLK_OTHER, 20); 1976 static MESON_GATE(g12a_rng1, HHI_GCLK_OTHER, 21); 1977 static MESON_GATE(g12a_vclk2_enct, HHI_GCLK_OTHER, 22); 1978 static MESON_GATE(g12a_vclk2_encl, HHI_GCLK_OTHER, 23); 1979 static MESON_GATE(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24); 1980 static MESON_GATE(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25); 1981 static MESON_GATE(g12a_vclk2_other1, HHI_GCLK_OTHER, 26); 1982 1983 static MESON_GATE_RO(g12a_dma, HHI_GCLK_OTHER2, 0); 1984 static MESON_GATE_RO(g12a_efuse, HHI_GCLK_OTHER2, 1); 1985 static MESON_GATE_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2); 1986 static MESON_GATE_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3); 1987 static MESON_GATE_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4); 1988 1989 /* Array of all clocks provided by this provider */ 1990 static struct clk_hw_onecell_data g12a_hw_onecell_data = { 1991 .hws = { 1992 [CLKID_SYS_PLL] = &g12a_sys_pll.hw, 1993 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw, 1994 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw, 1995 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw, 1996 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw, 1997 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw, 1998 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw, 1999 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw, 2000 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw, 2001 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw, 2002 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw, 2003 [CLKID_CLK81] = &g12a_clk81.hw, 2004 [CLKID_MPLL0] = &g12a_mpll0.hw, 2005 [CLKID_MPLL1] = &g12a_mpll1.hw, 2006 [CLKID_MPLL2] = &g12a_mpll2.hw, 2007 [CLKID_MPLL3] = &g12a_mpll3.hw, 2008 [CLKID_DDR] = &g12a_ddr.hw, 2009 [CLKID_DOS] = &g12a_dos.hw, 2010 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw, 2011 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw, 2012 [CLKID_ETH_PHY] = &g12a_eth_phy.hw, 2013 [CLKID_ISA] = &g12a_isa.hw, 2014 [CLKID_PL301] = &g12a_pl301.hw, 2015 [CLKID_PERIPHS] = &g12a_periphs.hw, 2016 [CLKID_SPICC0] = &g12a_spicc_0.hw, 2017 [CLKID_I2C] = &g12a_i2c.hw, 2018 [CLKID_SANA] = &g12a_sana.hw, 2019 [CLKID_SD] = &g12a_sd.hw, 2020 [CLKID_RNG0] = &g12a_rng0.hw, 2021 [CLKID_UART0] = &g12a_uart0.hw, 2022 [CLKID_SPICC1] = &g12a_spicc_1.hw, 2023 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw, 2024 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw, 2025 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw, 2026 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw, 2027 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw, 2028 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw, 2029 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw, 2030 [CLKID_AUDIO] = &g12a_audio.hw, 2031 [CLKID_ETH] = &g12a_eth_core.hw, 2032 [CLKID_DEMUX] = &g12a_demux.hw, 2033 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw, 2034 [CLKID_ADC] = &g12a_adc.hw, 2035 [CLKID_UART1] = &g12a_uart1.hw, 2036 [CLKID_G2D] = &g12a_g2d.hw, 2037 [CLKID_RESET] = &g12a_reset.hw, 2038 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw, 2039 [CLKID_PARSER] = &g12a_parser.hw, 2040 [CLKID_USB] = &g12a_usb_general.hw, 2041 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw, 2042 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw, 2043 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw, 2044 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw, 2045 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw, 2046 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw, 2047 [CLKID_BT656] = &g12a_bt656.hw, 2048 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw, 2049 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw, 2050 [CLKID_UART2] = &g12a_uart2.hw, 2051 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw, 2052 [CLKID_GIC] = &g12a_gic.hw, 2053 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw, 2054 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw, 2055 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw, 2056 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw, 2057 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw, 2058 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw, 2059 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw, 2060 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw, 2061 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw, 2062 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw, 2063 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw, 2064 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw, 2065 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw, 2066 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw, 2067 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw, 2068 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw, 2069 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw, 2070 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw, 2071 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw, 2072 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw, 2073 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw, 2074 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw, 2075 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw, 2076 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw, 2077 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw, 2078 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw, 2079 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw, 2080 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw, 2081 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw, 2082 [CLKID_DAC_CLK] = &g12a_dac_clk.hw, 2083 [CLKID_AOCLK] = &g12a_aoclk_gate.hw, 2084 [CLKID_IEC958] = &g12a_iec958_gate.hw, 2085 [CLKID_ENC480P] = &g12a_enc480p.hw, 2086 [CLKID_RNG1] = &g12a_rng1.hw, 2087 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw, 2088 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw, 2089 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw, 2090 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw, 2091 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw, 2092 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw, 2093 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw, 2094 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw, 2095 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw, 2096 [CLKID_DMA] = &g12a_dma.hw, 2097 [CLKID_EFUSE] = &g12a_efuse.hw, 2098 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw, 2099 [CLKID_RESET_SEC] = &g12a_reset_sec.hw, 2100 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw, 2101 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw, 2102 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw, 2103 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw, 2104 [CLKID_VPU_0] = &g12a_vpu_0.hw, 2105 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw, 2106 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw, 2107 [CLKID_VPU_1] = &g12a_vpu_1.hw, 2108 [CLKID_VPU] = &g12a_vpu.hw, 2109 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw, 2110 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw, 2111 [CLKID_VAPB_0] = &g12a_vapb_0.hw, 2112 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw, 2113 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw, 2114 [CLKID_VAPB_1] = &g12a_vapb_1.hw, 2115 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw, 2116 [CLKID_VAPB] = &g12a_vapb.hw, 2117 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw, 2118 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw, 2119 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw, 2120 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw, 2121 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw, 2122 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, 2123 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw, 2124 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw, 2125 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw, 2126 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw, 2127 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw, 2128 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw, 2129 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw, 2130 [CLKID_VCLK] = &g12a_vclk.hw, 2131 [CLKID_VCLK2] = &g12a_vclk2.hw, 2132 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw, 2133 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw, 2134 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw, 2135 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw, 2136 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw, 2137 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw, 2138 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw, 2139 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw, 2140 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw, 2141 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw, 2142 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw, 2143 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw, 2144 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw, 2145 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw, 2146 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw, 2147 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw, 2148 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw, 2149 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, 2150 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, 2151 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, 2152 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, 2153 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, 2154 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, 2155 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, 2156 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, 2157 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, 2158 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw, 2159 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw, 2160 [CLKID_HDMI] = &g12a_hdmi.hw, 2161 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw, 2162 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw, 2163 [CLKID_MALI_0] = &g12a_mali_0.hw, 2164 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw, 2165 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw, 2166 [CLKID_MALI_1] = &g12a_mali_1.hw, 2167 [CLKID_MALI] = &g12a_mali.hw, 2168 [CLKID_MPLL_5OM_DIV] = &g12a_mpll_50m_div.hw, 2169 [CLKID_MPLL_5OM] = &g12a_mpll_50m.hw, 2170 [NR_CLKS] = NULL, 2171 }, 2172 .num = NR_CLKS, 2173 }; 2174 2175 /* Convenience table to populate regmap in .probe */ 2176 static struct clk_regmap *const g12a_clk_regmaps[] = { 2177 &g12a_clk81, 2178 &g12a_dos, 2179 &g12a_ddr, 2180 &g12a_audio_locker, 2181 &g12a_mipi_dsi_host, 2182 &g12a_eth_phy, 2183 &g12a_isa, 2184 &g12a_pl301, 2185 &g12a_periphs, 2186 &g12a_spicc_0, 2187 &g12a_i2c, 2188 &g12a_sana, 2189 &g12a_sd, 2190 &g12a_rng0, 2191 &g12a_uart0, 2192 &g12a_spicc_1, 2193 &g12a_hiu_reg, 2194 &g12a_mipi_dsi_phy, 2195 &g12a_assist_misc, 2196 &g12a_emmc_a, 2197 &g12a_emmc_b, 2198 &g12a_emmc_c, 2199 &g12a_audio_codec, 2200 &g12a_audio, 2201 &g12a_eth_core, 2202 &g12a_demux, 2203 &g12a_audio_ififo, 2204 &g12a_adc, 2205 &g12a_uart1, 2206 &g12a_g2d, 2207 &g12a_reset, 2208 &g12a_pcie_comb, 2209 &g12a_parser, 2210 &g12a_usb_general, 2211 &g12a_pcie_phy, 2212 &g12a_ahb_arb0, 2213 &g12a_ahb_data_bus, 2214 &g12a_ahb_ctrl_bus, 2215 &g12a_htx_hdcp22, 2216 &g12a_htx_pclk, 2217 &g12a_bt656, 2218 &g12a_usb1_to_ddr, 2219 &g12a_mmc_pclk, 2220 &g12a_vpu_intr, 2221 &g12a_gic, 2222 &g12a_sd_emmc_a_clk0, 2223 &g12a_sd_emmc_b_clk0, 2224 &g12a_sd_emmc_c_clk0, 2225 &g12a_mpeg_clk_div, 2226 &g12a_sd_emmc_a_clk0_div, 2227 &g12a_sd_emmc_b_clk0_div, 2228 &g12a_sd_emmc_c_clk0_div, 2229 &g12a_mpeg_clk_sel, 2230 &g12a_sd_emmc_a_clk0_sel, 2231 &g12a_sd_emmc_b_clk0_sel, 2232 &g12a_sd_emmc_c_clk0_sel, 2233 &g12a_mpll0, 2234 &g12a_mpll1, 2235 &g12a_mpll2, 2236 &g12a_mpll3, 2237 &g12a_mpll0_div, 2238 &g12a_mpll1_div, 2239 &g12a_mpll2_div, 2240 &g12a_mpll3_div, 2241 &g12a_fixed_pll, 2242 &g12a_sys_pll, 2243 &g12a_gp0_pll, 2244 &g12a_hifi_pll, 2245 &g12a_vclk2_venci0, 2246 &g12a_vclk2_venci1, 2247 &g12a_vclk2_vencp0, 2248 &g12a_vclk2_vencp1, 2249 &g12a_vclk2_venct0, 2250 &g12a_vclk2_venct1, 2251 &g12a_vclk2_other, 2252 &g12a_vclk2_enci, 2253 &g12a_vclk2_encp, 2254 &g12a_dac_clk, 2255 &g12a_aoclk_gate, 2256 &g12a_iec958_gate, 2257 &g12a_enc480p, 2258 &g12a_rng1, 2259 &g12a_vclk2_enct, 2260 &g12a_vclk2_encl, 2261 &g12a_vclk2_venclmmc, 2262 &g12a_vclk2_vencl, 2263 &g12a_vclk2_other1, 2264 &g12a_fixed_pll_dco, 2265 &g12a_sys_pll_dco, 2266 &g12a_gp0_pll_dco, 2267 &g12a_hifi_pll_dco, 2268 &g12a_fclk_div2, 2269 &g12a_fclk_div3, 2270 &g12a_fclk_div4, 2271 &g12a_fclk_div5, 2272 &g12a_fclk_div7, 2273 &g12a_fclk_div2p5, 2274 &g12a_dma, 2275 &g12a_efuse, 2276 &g12a_rom_boot, 2277 &g12a_reset_sec, 2278 &g12a_sec_ahb_apb3, 2279 &g12a_vpu_0_sel, 2280 &g12a_vpu_0_div, 2281 &g12a_vpu_0, 2282 &g12a_vpu_1_sel, 2283 &g12a_vpu_1_div, 2284 &g12a_vpu_1, 2285 &g12a_vpu, 2286 &g12a_vapb_0_sel, 2287 &g12a_vapb_0_div, 2288 &g12a_vapb_0, 2289 &g12a_vapb_1_sel, 2290 &g12a_vapb_1_div, 2291 &g12a_vapb_1, 2292 &g12a_vapb_sel, 2293 &g12a_vapb, 2294 &g12a_hdmi_pll_dco, 2295 &g12a_hdmi_pll_od, 2296 &g12a_hdmi_pll_od2, 2297 &g12a_hdmi_pll, 2298 &g12a_vid_pll_div, 2299 &g12a_vid_pll_sel, 2300 &g12a_vid_pll, 2301 &g12a_vclk_sel, 2302 &g12a_vclk2_sel, 2303 &g12a_vclk_input, 2304 &g12a_vclk2_input, 2305 &g12a_vclk_div, 2306 &g12a_vclk2_div, 2307 &g12a_vclk, 2308 &g12a_vclk2, 2309 &g12a_vclk_div1, 2310 &g12a_vclk_div2_en, 2311 &g12a_vclk_div4_en, 2312 &g12a_vclk_div6_en, 2313 &g12a_vclk_div12_en, 2314 &g12a_vclk2_div1, 2315 &g12a_vclk2_div2_en, 2316 &g12a_vclk2_div4_en, 2317 &g12a_vclk2_div6_en, 2318 &g12a_vclk2_div12_en, 2319 &g12a_cts_enci_sel, 2320 &g12a_cts_encp_sel, 2321 &g12a_cts_vdac_sel, 2322 &g12a_hdmi_tx_sel, 2323 &g12a_cts_enci, 2324 &g12a_cts_encp, 2325 &g12a_cts_vdac, 2326 &g12a_hdmi_tx, 2327 &g12a_hdmi_sel, 2328 &g12a_hdmi_div, 2329 &g12a_hdmi, 2330 &g12a_mali_0_sel, 2331 &g12a_mali_0_div, 2332 &g12a_mali_0, 2333 &g12a_mali_1_sel, 2334 &g12a_mali_1_div, 2335 &g12a_mali_1, 2336 &g12a_mali, 2337 &g12a_mpll_50m, 2338 }; 2339 2340 static const struct meson_eeclkc_data g12a_clkc_data = { 2341 .regmap_clks = g12a_clk_regmaps, 2342 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), 2343 .hw_onecell_data = &g12a_hw_onecell_data 2344 }; 2345 2346 static const struct of_device_id clkc_match_table[] = { 2347 { .compatible = "amlogic,g12a-clkc", .data = &g12a_clkc_data }, 2348 {} 2349 }; 2350 2351 static struct platform_driver g12a_driver = { 2352 .probe = meson_eeclkc_probe, 2353 .driver = { 2354 .name = "g12a-clkc", 2355 .of_match_table = clkc_match_table, 2356 }, 2357 }; 2358 2359 builtin_platform_driver(g12a_driver); 2360