1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2018 BayLibre, SAS. 3 // Author: Jerome Brunet <jbrunet@baylibre.com> 4 5 #ifndef __CLK_REGMAP_H 6 #define __CLK_REGMAP_H 7 8 #include <linux/clk-provider.h> 9 #include <linux/regmap.h> 10 11 /** 12 * struct clk_regmap - regmap backed clock 13 * 14 * @hw: handle between common and hardware-specific interfaces 15 * @map: pointer to the regmap structure controlling the clock 16 * @data: data specific to the clock type 17 * 18 * Clock which is controlled by regmap backed registers. The actual type of 19 * of the clock is controlled by the clock_ops and data. 20 */ 21 struct clk_regmap { 22 struct clk_hw hw; 23 struct regmap *map; 24 void *data; 25 }; 26 27 #define to_clk_regmap(_hw) container_of(_hw, struct clk_regmap, hw) 28 29 /** 30 * struct clk_regmap_gate_data - regmap backed gate specific data 31 * 32 * @offset: offset of the register controlling gate 33 * @bit_idx: single bit controlling gate 34 * @flags: hardware-specific flags 35 * 36 * Flags: 37 * Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored 38 */ 39 struct clk_regmap_gate_data { 40 unsigned int offset; 41 u8 bit_idx; 42 u8 flags; 43 }; 44 45 static inline struct clk_regmap_gate_data * 46 clk_get_regmap_gate_data(struct clk_regmap *clk) 47 { 48 return (struct clk_regmap_gate_data *)clk->data; 49 } 50 51 extern const struct clk_ops clk_regmap_gate_ops; 52 53 /** 54 * struct clk_regmap_div_data - regmap backed adjustable divider specific data 55 * 56 * @offset: offset of the register controlling the divider 57 * @shift: shift to the divider bit field 58 * @width: width of the divider bit field 59 * @table: array of value/divider pairs, last entry should have div = 0 60 * 61 * Flags: 62 * Same as clk_divider except CLK_DIVIDER_HIWORD_MASK which is ignored 63 */ 64 struct clk_regmap_div_data { 65 unsigned int offset; 66 u8 shift; 67 u8 width; 68 u8 flags; 69 const struct clk_div_table *table; 70 }; 71 72 static inline struct clk_regmap_div_data * 73 clk_get_regmap_div_data(struct clk_regmap *clk) 74 { 75 return (struct clk_regmap_div_data *)clk->data; 76 } 77 78 extern const struct clk_ops clk_regmap_divider_ops; 79 extern const struct clk_ops clk_regmap_divider_ro_ops; 80 81 /** 82 * struct clk_regmap_mux_data - regmap backed multiplexer clock specific data 83 * 84 * @hw: handle between common and hardware-specific interfaces 85 * @offset: offset of theregister controlling multiplexer 86 * @table: array of parent indexed register values 87 * @shift: shift to multiplexer bit field 88 * @mask: mask of mutliplexer bit field 89 * @flags: hardware-specific flags 90 * 91 * Flags: 92 * Same as clk_divider except CLK_MUX_HIWORD_MASK which is ignored 93 */ 94 struct clk_regmap_mux_data { 95 unsigned int offset; 96 u32 *table; 97 u32 mask; 98 u8 shift; 99 u8 flags; 100 }; 101 102 static inline struct clk_regmap_mux_data * 103 clk_get_regmap_mux_data(struct clk_regmap *clk) 104 { 105 return (struct clk_regmap_mux_data *)clk->data; 106 } 107 108 extern const struct clk_ops clk_regmap_mux_ops; 109 extern const struct clk_ops clk_regmap_mux_ro_ops; 110 111 #endif /* __CLK_REGMAP_H */ 112