1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 BayLibre, SAS. 4 * Author: Jerome Brunet <jbrunet@baylibre.com> 5 */ 6 7 #include "clk-regmap.h" 8 9 static int clk_regmap_gate_endisable(struct clk_hw *hw, int enable) 10 { 11 struct clk_regmap *clk = to_clk_regmap(hw); 12 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); 13 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; 14 15 set ^= enable; 16 17 return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), 18 set ? BIT(gate->bit_idx) : 0); 19 } 20 21 static int clk_regmap_gate_enable(struct clk_hw *hw) 22 { 23 return clk_regmap_gate_endisable(hw, 1); 24 } 25 26 static void clk_regmap_gate_disable(struct clk_hw *hw) 27 { 28 clk_regmap_gate_endisable(hw, 0); 29 } 30 31 static int clk_regmap_gate_is_enabled(struct clk_hw *hw) 32 { 33 struct clk_regmap *clk = to_clk_regmap(hw); 34 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); 35 unsigned int val; 36 37 regmap_read(clk->map, gate->offset, &val); 38 if (gate->flags & CLK_GATE_SET_TO_DISABLE) 39 val ^= BIT(gate->bit_idx); 40 41 val &= BIT(gate->bit_idx); 42 43 return val ? 1 : 0; 44 } 45 46 const struct clk_ops clk_regmap_gate_ops = { 47 .enable = clk_regmap_gate_enable, 48 .disable = clk_regmap_gate_disable, 49 .is_enabled = clk_regmap_gate_is_enabled, 50 }; 51 EXPORT_SYMBOL_GPL(clk_regmap_gate_ops); 52 53 static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw, 54 unsigned long prate) 55 { 56 struct clk_regmap *clk = to_clk_regmap(hw); 57 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); 58 unsigned int val; 59 int ret; 60 61 ret = regmap_read(clk->map, div->offset, &val); 62 if (ret) 63 /* Gives a hint that something is wrong */ 64 return 0; 65 66 val >>= div->shift; 67 val &= clk_div_mask(div->width); 68 return divider_recalc_rate(hw, prate, val, div->table, div->flags, 69 div->width); 70 } 71 72 static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate, 73 unsigned long *prate) 74 { 75 struct clk_regmap *clk = to_clk_regmap(hw); 76 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); 77 unsigned int val; 78 int ret; 79 80 /* if read only, just return current value */ 81 if (div->flags & CLK_DIVIDER_READ_ONLY) { 82 ret = regmap_read(clk->map, div->offset, &val); 83 if (ret) 84 /* Gives a hint that something is wrong */ 85 return 0; 86 87 val >>= div->shift; 88 val &= clk_div_mask(div->width); 89 90 return divider_ro_round_rate(hw, rate, prate, div->table, 91 div->width, div->flags, val); 92 } 93 94 return divider_round_rate(hw, rate, prate, div->table, div->width, 95 div->flags); 96 } 97 98 static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate, 99 unsigned long parent_rate) 100 { 101 struct clk_regmap *clk = to_clk_regmap(hw); 102 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); 103 unsigned int val; 104 int ret; 105 106 ret = divider_get_val(rate, parent_rate, div->table, div->width, 107 div->flags); 108 if (ret < 0) 109 return ret; 110 111 val = (unsigned int)ret << div->shift; 112 return regmap_update_bits(clk->map, div->offset, 113 clk_div_mask(div->width) << div->shift, val); 114 }; 115 116 /* Would prefer clk_regmap_div_ro_ops but clashes with qcom */ 117 118 const struct clk_ops clk_regmap_divider_ops = { 119 .recalc_rate = clk_regmap_div_recalc_rate, 120 .round_rate = clk_regmap_div_round_rate, 121 .set_rate = clk_regmap_div_set_rate, 122 }; 123 EXPORT_SYMBOL_GPL(clk_regmap_divider_ops); 124 125 const struct clk_ops clk_regmap_divider_ro_ops = { 126 .recalc_rate = clk_regmap_div_recalc_rate, 127 .round_rate = clk_regmap_div_round_rate, 128 }; 129 EXPORT_SYMBOL_GPL(clk_regmap_divider_ro_ops); 130 131 static u8 clk_regmap_mux_get_parent(struct clk_hw *hw) 132 { 133 struct clk_regmap *clk = to_clk_regmap(hw); 134 struct clk_regmap_mux_data *mux = clk_get_regmap_mux_data(clk); 135 unsigned int val; 136 int ret; 137 138 ret = regmap_read(clk->map, mux->offset, &val); 139 if (ret) 140 return ret; 141 142 val >>= mux->shift; 143 val &= mux->mask; 144 return clk_mux_val_to_index(hw, mux->table, mux->flags, val); 145 } 146 147 static int clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index) 148 { 149 struct clk_regmap *clk = to_clk_regmap(hw); 150 struct clk_regmap_mux_data *mux = clk_get_regmap_mux_data(clk); 151 unsigned int val = clk_mux_index_to_val(mux->table, mux->flags, index); 152 153 return regmap_update_bits(clk->map, mux->offset, 154 mux->mask << mux->shift, 155 val << mux->shift); 156 } 157 158 static int clk_regmap_mux_determine_rate(struct clk_hw *hw, 159 struct clk_rate_request *req) 160 { 161 struct clk_regmap *clk = to_clk_regmap(hw); 162 struct clk_regmap_mux_data *mux = clk_get_regmap_mux_data(clk); 163 164 return clk_mux_determine_rate_flags(hw, req, mux->flags); 165 } 166 167 const struct clk_ops clk_regmap_mux_ops = { 168 .get_parent = clk_regmap_mux_get_parent, 169 .set_parent = clk_regmap_mux_set_parent, 170 .determine_rate = clk_regmap_mux_determine_rate, 171 }; 172 EXPORT_SYMBOL_GPL(clk_regmap_mux_ops); 173 174 const struct clk_ops clk_regmap_mux_ro_ops = { 175 .get_parent = clk_regmap_mux_get_parent, 176 }; 177 EXPORT_SYMBOL_GPL(clk_regmap_mux_ro_ops); 178