1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 BayLibre, SAS. 4 * Author: Jerome Brunet <jbrunet@baylibre.com> 5 */ 6 7 #include "clk-regmap.h" 8 9 static int clk_regmap_gate_endisable(struct clk_hw *hw, int enable) 10 { 11 struct clk_regmap *clk = to_clk_regmap(hw); 12 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); 13 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; 14 15 set ^= enable; 16 17 return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), 18 set ? BIT(gate->bit_idx) : 0); 19 } 20 21 static int clk_regmap_gate_enable(struct clk_hw *hw) 22 { 23 return clk_regmap_gate_endisable(hw, 1); 24 } 25 26 static void clk_regmap_gate_disable(struct clk_hw *hw) 27 { 28 clk_regmap_gate_endisable(hw, 0); 29 } 30 31 static int clk_regmap_gate_is_enabled(struct clk_hw *hw) 32 { 33 struct clk_regmap *clk = to_clk_regmap(hw); 34 struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); 35 unsigned int val; 36 37 regmap_read(clk->map, gate->offset, &val); 38 if (gate->flags & CLK_GATE_SET_TO_DISABLE) 39 val ^= BIT(gate->bit_idx); 40 41 val &= BIT(gate->bit_idx); 42 43 return val ? 1 : 0; 44 } 45 46 const struct clk_ops clk_regmap_gate_ops = { 47 .enable = clk_regmap_gate_enable, 48 .disable = clk_regmap_gate_disable, 49 .is_enabled = clk_regmap_gate_is_enabled, 50 }; 51 EXPORT_SYMBOL_GPL(clk_regmap_gate_ops); 52 53 const struct clk_ops clk_regmap_gate_ro_ops = { 54 .is_enabled = clk_regmap_gate_is_enabled, 55 }; 56 EXPORT_SYMBOL_GPL(clk_regmap_gate_ro_ops); 57 58 static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw, 59 unsigned long prate) 60 { 61 struct clk_regmap *clk = to_clk_regmap(hw); 62 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); 63 unsigned int val; 64 int ret; 65 66 ret = regmap_read(clk->map, div->offset, &val); 67 if (ret) 68 /* Gives a hint that something is wrong */ 69 return 0; 70 71 val >>= div->shift; 72 val &= clk_div_mask(div->width); 73 return divider_recalc_rate(hw, prate, val, div->table, div->flags, 74 div->width); 75 } 76 77 static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate, 78 unsigned long *prate) 79 { 80 struct clk_regmap *clk = to_clk_regmap(hw); 81 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); 82 unsigned int val; 83 int ret; 84 85 /* if read only, just return current value */ 86 if (div->flags & CLK_DIVIDER_READ_ONLY) { 87 ret = regmap_read(clk->map, div->offset, &val); 88 if (ret) 89 /* Gives a hint that something is wrong */ 90 return 0; 91 92 val >>= div->shift; 93 val &= clk_div_mask(div->width); 94 95 return divider_ro_round_rate(hw, rate, prate, div->table, 96 div->width, div->flags, val); 97 } 98 99 return divider_round_rate(hw, rate, prate, div->table, div->width, 100 div->flags); 101 } 102 103 static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate, 104 unsigned long parent_rate) 105 { 106 struct clk_regmap *clk = to_clk_regmap(hw); 107 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); 108 unsigned int val; 109 int ret; 110 111 ret = divider_get_val(rate, parent_rate, div->table, div->width, 112 div->flags); 113 if (ret < 0) 114 return ret; 115 116 val = (unsigned int)ret << div->shift; 117 return regmap_update_bits(clk->map, div->offset, 118 clk_div_mask(div->width) << div->shift, val); 119 }; 120 121 /* Would prefer clk_regmap_div_ro_ops but clashes with qcom */ 122 123 const struct clk_ops clk_regmap_divider_ops = { 124 .recalc_rate = clk_regmap_div_recalc_rate, 125 .round_rate = clk_regmap_div_round_rate, 126 .set_rate = clk_regmap_div_set_rate, 127 }; 128 EXPORT_SYMBOL_GPL(clk_regmap_divider_ops); 129 130 const struct clk_ops clk_regmap_divider_ro_ops = { 131 .recalc_rate = clk_regmap_div_recalc_rate, 132 .round_rate = clk_regmap_div_round_rate, 133 }; 134 EXPORT_SYMBOL_GPL(clk_regmap_divider_ro_ops); 135 136 static u8 clk_regmap_mux_get_parent(struct clk_hw *hw) 137 { 138 struct clk_regmap *clk = to_clk_regmap(hw); 139 struct clk_regmap_mux_data *mux = clk_get_regmap_mux_data(clk); 140 unsigned int val; 141 int ret; 142 143 ret = regmap_read(clk->map, mux->offset, &val); 144 if (ret) 145 return ret; 146 147 val >>= mux->shift; 148 val &= mux->mask; 149 return clk_mux_val_to_index(hw, mux->table, mux->flags, val); 150 } 151 152 static int clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index) 153 { 154 struct clk_regmap *clk = to_clk_regmap(hw); 155 struct clk_regmap_mux_data *mux = clk_get_regmap_mux_data(clk); 156 unsigned int val = clk_mux_index_to_val(mux->table, mux->flags, index); 157 158 return regmap_update_bits(clk->map, mux->offset, 159 mux->mask << mux->shift, 160 val << mux->shift); 161 } 162 163 static int clk_regmap_mux_determine_rate(struct clk_hw *hw, 164 struct clk_rate_request *req) 165 { 166 struct clk_regmap *clk = to_clk_regmap(hw); 167 struct clk_regmap_mux_data *mux = clk_get_regmap_mux_data(clk); 168 169 return clk_mux_determine_rate_flags(hw, req, mux->flags); 170 } 171 172 const struct clk_ops clk_regmap_mux_ops = { 173 .get_parent = clk_regmap_mux_get_parent, 174 .set_parent = clk_regmap_mux_set_parent, 175 .determine_rate = clk_regmap_mux_determine_rate, 176 }; 177 EXPORT_SYMBOL_GPL(clk_regmap_mux_ops); 178 179 const struct clk_ops clk_regmap_mux_ro_ops = { 180 .get_parent = clk_regmap_mux_get_parent, 181 }; 182 EXPORT_SYMBOL_GPL(clk_regmap_mux_ro_ops); 183