1 /* 2 * Copyright (c) 2015 Endless Mobile, Inc. 3 * Author: Carlo Caione <carlo@endlessm.com> 4 * 5 * Copyright (c) 2018 Baylibre, SAS. 6 * Author: Jerome Brunet <jbrunet@baylibre.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 /* 22 * In the most basic form, a Meson PLL is composed as follows: 23 * 24 * PLL 25 * +------------------------------+ 26 * | | 27 * in -----[ /N ]---[ *M ]---[ >>OD ]----->> out 28 * | ^ ^ | 29 * +------------------------------+ 30 * | | 31 * FREF VCO 32 * 33 * out = in * (m + frac / frac_max) / (n << sum(ods)) 34 */ 35 36 #include <linux/clk-provider.h> 37 #include <linux/delay.h> 38 #include <linux/err.h> 39 #include <linux/io.h> 40 #include <linux/math64.h> 41 #include <linux/module.h> 42 #include <linux/of_address.h> 43 #include <linux/slab.h> 44 #include <linux/string.h> 45 46 #include "clkc.h" 47 48 static inline struct meson_clk_pll_data * 49 meson_clk_pll_data(struct clk_regmap *clk) 50 { 51 return (struct meson_clk_pll_data *)clk->data; 52 } 53 54 static unsigned long __pll_params_to_rate(unsigned long parent_rate, 55 const struct pll_rate_table *pllt, 56 u16 frac, 57 struct meson_clk_pll_data *pll) 58 { 59 u64 rate = (u64)parent_rate * pllt->m; 60 unsigned int od = pllt->od + pllt->od2 + pllt->od3; 61 62 if (frac && MESON_PARM_APPLICABLE(&pll->frac)) { 63 u64 frac_rate = (u64)parent_rate * frac; 64 65 rate += DIV_ROUND_UP_ULL(frac_rate, 66 (1 << pll->frac.width)); 67 } 68 69 return DIV_ROUND_UP_ULL(rate, pllt->n << od); 70 } 71 72 static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, 73 unsigned long parent_rate) 74 { 75 struct clk_regmap *clk = to_clk_regmap(hw); 76 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); 77 struct pll_rate_table pllt; 78 u16 frac; 79 80 pllt.n = meson_parm_read(clk->map, &pll->n); 81 pllt.m = meson_parm_read(clk->map, &pll->m); 82 pllt.od = meson_parm_read(clk->map, &pll->od); 83 84 pllt.od2 = MESON_PARM_APPLICABLE(&pll->od2) ? 85 meson_parm_read(clk->map, &pll->od2) : 86 0; 87 88 pllt.od3 = MESON_PARM_APPLICABLE(&pll->od3) ? 89 meson_parm_read(clk->map, &pll->od3) : 90 0; 91 92 frac = MESON_PARM_APPLICABLE(&pll->frac) ? 93 meson_parm_read(clk->map, &pll->frac) : 94 0; 95 96 return __pll_params_to_rate(parent_rate, &pllt, frac, pll); 97 } 98 99 static u16 __pll_params_with_frac(unsigned long rate, 100 unsigned long parent_rate, 101 const struct pll_rate_table *pllt, 102 struct meson_clk_pll_data *pll) 103 { 104 u16 frac_max = (1 << pll->frac.width); 105 u64 val = (u64)rate * pllt->n; 106 107 val <<= pllt->od + pllt->od2 + pllt->od3; 108 109 if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) 110 val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate); 111 else 112 val = div_u64(val * frac_max, parent_rate); 113 114 val -= pllt->m * frac_max; 115 116 return min((u16)val, (u16)(frac_max - 1)); 117 } 118 119 static const struct pll_rate_table * 120 meson_clk_get_pll_settings(unsigned long rate, 121 struct meson_clk_pll_data *pll) 122 { 123 const struct pll_rate_table *table = pll->table; 124 unsigned int i = 0; 125 126 if (!table) 127 return NULL; 128 129 /* Find the first table element exceeding rate */ 130 while (table[i].rate && table[i].rate <= rate) 131 i++; 132 133 if (i != 0) { 134 if (MESON_PARM_APPLICABLE(&pll->frac) || 135 !(pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) || 136 (abs(rate - table[i - 1].rate) < 137 abs(rate - table[i].rate))) 138 i--; 139 } 140 141 return (struct pll_rate_table *)&table[i]; 142 } 143 144 static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 145 unsigned long *parent_rate) 146 { 147 struct clk_regmap *clk = to_clk_regmap(hw); 148 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); 149 const struct pll_rate_table *pllt = 150 meson_clk_get_pll_settings(rate, pll); 151 u16 frac; 152 153 if (!pllt) 154 return meson_clk_pll_recalc_rate(hw, *parent_rate); 155 156 if (!MESON_PARM_APPLICABLE(&pll->frac) 157 || rate == pllt->rate) 158 return pllt->rate; 159 160 /* 161 * The rate provided by the setting is not an exact match, let's 162 * try to improve the result using the fractional parameter 163 */ 164 frac = __pll_params_with_frac(rate, *parent_rate, pllt, pll); 165 166 return __pll_params_to_rate(*parent_rate, pllt, frac, pll); 167 } 168 169 static int meson_clk_pll_wait_lock(struct clk_hw *hw) 170 { 171 struct clk_regmap *clk = to_clk_regmap(hw); 172 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); 173 int delay = 24000000; 174 175 do { 176 /* Is the clock locked now ? */ 177 if (meson_parm_read(clk->map, &pll->l)) 178 return 0; 179 180 delay--; 181 } while (delay > 0); 182 183 return -ETIMEDOUT; 184 } 185 186 static void meson_clk_pll_init(struct clk_hw *hw) 187 { 188 struct clk_regmap *clk = to_clk_regmap(hw); 189 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); 190 191 if (pll->init_count) { 192 meson_parm_write(clk->map, &pll->rst, 1); 193 regmap_multi_reg_write(clk->map, pll->init_regs, 194 pll->init_count); 195 meson_parm_write(clk->map, &pll->rst, 0); 196 } 197 } 198 199 static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 200 unsigned long parent_rate) 201 { 202 struct clk_regmap *clk = to_clk_regmap(hw); 203 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); 204 const struct pll_rate_table *pllt; 205 unsigned long old_rate; 206 u16 frac = 0; 207 208 if (parent_rate == 0 || rate == 0) 209 return -EINVAL; 210 211 old_rate = rate; 212 213 pllt = meson_clk_get_pll_settings(rate, pll); 214 if (!pllt) 215 return -EINVAL; 216 217 /* Put the pll in reset to write the params */ 218 meson_parm_write(clk->map, &pll->rst, 1); 219 220 meson_parm_write(clk->map, &pll->n, pllt->n); 221 meson_parm_write(clk->map, &pll->m, pllt->m); 222 meson_parm_write(clk->map, &pll->od, pllt->od); 223 224 if (MESON_PARM_APPLICABLE(&pll->od2)) 225 meson_parm_write(clk->map, &pll->od2, pllt->od2); 226 227 if (MESON_PARM_APPLICABLE(&pll->od3)) 228 meson_parm_write(clk->map, &pll->od3, pllt->od3); 229 230 if (MESON_PARM_APPLICABLE(&pll->frac)) { 231 frac = __pll_params_with_frac(rate, parent_rate, pllt, pll); 232 meson_parm_write(clk->map, &pll->frac, frac); 233 } 234 235 /* make sure the reset is cleared at this point */ 236 meson_parm_write(clk->map, &pll->rst, 0); 237 238 if (meson_clk_pll_wait_lock(hw)) { 239 pr_warn("%s: pll did not lock, trying to restore old rate %lu\n", 240 __func__, old_rate); 241 /* 242 * FIXME: Do we really need/want this HACK ? 243 * It looks unsafe. what happens if the clock gets into a 244 * broken state and we can't lock back on the old_rate ? Looks 245 * like an infinite recursion is possible 246 */ 247 meson_clk_pll_set_rate(hw, old_rate, parent_rate); 248 } 249 250 return 0; 251 } 252 253 const struct clk_ops meson_clk_pll_ops = { 254 .init = meson_clk_pll_init, 255 .recalc_rate = meson_clk_pll_recalc_rate, 256 .round_rate = meson_clk_pll_round_rate, 257 .set_rate = meson_clk_pll_set_rate, 258 }; 259 260 const struct clk_ops meson_clk_pll_ro_ops = { 261 .recalc_rate = meson_clk_pll_recalc_rate, 262 }; 263