1 /* 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright (c) 2016 AmLogic, Inc. 8 * Author: Michael Turquette <mturquette@baylibre.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING 24 * 25 * BSD LICENSE 26 * 27 * Copyright (c) 2016 AmLogic, Inc. 28 * Author: Michael Turquette <mturquette@baylibre.com> 29 * 30 * Redistribution and use in source and binary forms, with or without 31 * modification, are permitted provided that the following conditions 32 * are met: 33 * 34 * * Redistributions of source code must retain the above copyright 35 * notice, this list of conditions and the following disclaimer. 36 * * Redistributions in binary form must reproduce the above copyright 37 * notice, this list of conditions and the following disclaimer in 38 * the documentation and/or other materials provided with the 39 * distribution. 40 * * Neither the name of Intel Corporation nor the names of its 41 * contributors may be used to endorse or promote products derived 42 * from this software without specific prior written permission. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 45 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 46 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 47 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 48 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 49 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 54 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 55 */ 56 57 /* 58 * MultiPhase Locked Loops are outputs from a PLL with additional frequency 59 * scaling capabilities. MPLL rates are calculated as: 60 * 61 * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384) 62 */ 63 64 #include <linux/clk-provider.h> 65 #include "clkc.h" 66 67 #define SDM_DEN 16384 68 #define N2_MIN 4 69 #define N2_MAX 511 70 71 static inline struct meson_clk_mpll_data * 72 meson_clk_mpll_data(struct clk_regmap *clk) 73 { 74 return (struct meson_clk_mpll_data *)clk->data; 75 } 76 77 static long rate_from_params(unsigned long parent_rate, 78 unsigned int sdm, 79 unsigned int n2) 80 { 81 unsigned long divisor = (SDM_DEN * n2) + sdm; 82 83 if (n2 < N2_MIN) 84 return -EINVAL; 85 86 return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor); 87 } 88 89 static void params_from_rate(unsigned long requested_rate, 90 unsigned long parent_rate, 91 unsigned int *sdm, 92 unsigned int *n2) 93 { 94 uint64_t div = parent_rate; 95 unsigned long rem = do_div(div, requested_rate); 96 97 if (div < N2_MIN) { 98 *n2 = N2_MIN; 99 *sdm = 0; 100 } else if (div > N2_MAX) { 101 *n2 = N2_MAX; 102 *sdm = SDM_DEN - 1; 103 } else { 104 *n2 = div; 105 *sdm = DIV_ROUND_UP_ULL((u64)rem * SDM_DEN, requested_rate); 106 } 107 } 108 109 static unsigned long mpll_recalc_rate(struct clk_hw *hw, 110 unsigned long parent_rate) 111 { 112 struct clk_regmap *clk = to_clk_regmap(hw); 113 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); 114 unsigned int sdm, n2; 115 long rate; 116 117 sdm = meson_parm_read(clk->map, &mpll->sdm); 118 n2 = meson_parm_read(clk->map, &mpll->n2); 119 120 rate = rate_from_params(parent_rate, sdm, n2); 121 return rate < 0 ? 0 : rate; 122 } 123 124 static long mpll_round_rate(struct clk_hw *hw, 125 unsigned long rate, 126 unsigned long *parent_rate) 127 { 128 unsigned int sdm, n2; 129 130 params_from_rate(rate, *parent_rate, &sdm, &n2); 131 return rate_from_params(*parent_rate, sdm, n2); 132 } 133 134 static int mpll_set_rate(struct clk_hw *hw, 135 unsigned long rate, 136 unsigned long parent_rate) 137 { 138 struct clk_regmap *clk = to_clk_regmap(hw); 139 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); 140 unsigned int sdm, n2; 141 unsigned long flags = 0; 142 143 params_from_rate(rate, parent_rate, &sdm, &n2); 144 145 if (mpll->lock) 146 spin_lock_irqsave(mpll->lock, flags); 147 else 148 __acquire(mpll->lock); 149 150 /* Enable and set the fractional part */ 151 meson_parm_write(clk->map, &mpll->sdm, sdm); 152 meson_parm_write(clk->map, &mpll->sdm_en, 1); 153 154 /* Set additional fractional part enable if required */ 155 if (MESON_PARM_APPLICABLE(&mpll->ssen)) 156 meson_parm_write(clk->map, &mpll->ssen, 1); 157 158 /* Set the integer divider part */ 159 meson_parm_write(clk->map, &mpll->n2, n2); 160 161 /* Set the magic misc bit if required */ 162 if (MESON_PARM_APPLICABLE(&mpll->misc)) 163 meson_parm_write(clk->map, &mpll->misc, 1); 164 165 if (mpll->lock) 166 spin_unlock_irqrestore(mpll->lock, flags); 167 else 168 __release(mpll->lock); 169 170 return 0; 171 } 172 173 const struct clk_ops meson_clk_mpll_ro_ops = { 174 .recalc_rate = mpll_recalc_rate, 175 .round_rate = mpll_round_rate, 176 }; 177 178 const struct clk_ops meson_clk_mpll_ops = { 179 .recalc_rate = mpll_recalc_rate, 180 .round_rate = mpll_round_rate, 181 .set_rate = mpll_set_rate, 182 }; 183