1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AmLogic Meson-AXG Clock Controller Driver 4 * 5 * Copyright (c) 2016 Baylibre SAS. 6 * Author: Michael Turquette <mturquette@baylibre.com> 7 * 8 * Copyright (c) 2017 Amlogic, inc. 9 * Author: Qiufang Dai <qiufang.dai@amlogic.com> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/clk-provider.h> 14 #include <linux/of_address.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/init.h> 18 19 #include "clkc.h" 20 #include "axg.h" 21 22 static DEFINE_SPINLOCK(meson_clk_lock); 23 24 static const struct pll_rate_table sys_pll_rate_table[] = { 25 PLL_RATE(24000000, 56, 1, 2), 26 PLL_RATE(48000000, 64, 1, 2), 27 PLL_RATE(72000000, 72, 1, 2), 28 PLL_RATE(96000000, 64, 1, 2), 29 PLL_RATE(120000000, 80, 1, 2), 30 PLL_RATE(144000000, 96, 1, 2), 31 PLL_RATE(168000000, 56, 1, 1), 32 PLL_RATE(192000000, 64, 1, 1), 33 PLL_RATE(216000000, 72, 1, 1), 34 PLL_RATE(240000000, 80, 1, 1), 35 PLL_RATE(264000000, 88, 1, 1), 36 PLL_RATE(288000000, 96, 1, 1), 37 PLL_RATE(312000000, 52, 1, 2), 38 PLL_RATE(336000000, 56, 1, 2), 39 PLL_RATE(360000000, 60, 1, 2), 40 PLL_RATE(384000000, 64, 1, 2), 41 PLL_RATE(408000000, 68, 1, 2), 42 PLL_RATE(432000000, 72, 1, 2), 43 PLL_RATE(456000000, 76, 1, 2), 44 PLL_RATE(480000000, 80, 1, 2), 45 PLL_RATE(504000000, 84, 1, 2), 46 PLL_RATE(528000000, 88, 1, 2), 47 PLL_RATE(552000000, 92, 1, 2), 48 PLL_RATE(576000000, 96, 1, 2), 49 PLL_RATE(600000000, 50, 1, 1), 50 PLL_RATE(624000000, 52, 1, 1), 51 PLL_RATE(648000000, 54, 1, 1), 52 PLL_RATE(672000000, 56, 1, 1), 53 PLL_RATE(696000000, 58, 1, 1), 54 PLL_RATE(720000000, 60, 1, 1), 55 PLL_RATE(744000000, 62, 1, 1), 56 PLL_RATE(768000000, 64, 1, 1), 57 PLL_RATE(792000000, 66, 1, 1), 58 PLL_RATE(816000000, 68, 1, 1), 59 PLL_RATE(840000000, 70, 1, 1), 60 PLL_RATE(864000000, 72, 1, 1), 61 PLL_RATE(888000000, 74, 1, 1), 62 PLL_RATE(912000000, 76, 1, 1), 63 PLL_RATE(936000000, 78, 1, 1), 64 PLL_RATE(960000000, 80, 1, 1), 65 PLL_RATE(984000000, 82, 1, 1), 66 PLL_RATE(1008000000, 84, 1, 1), 67 PLL_RATE(1032000000, 86, 1, 1), 68 PLL_RATE(1056000000, 88, 1, 1), 69 PLL_RATE(1080000000, 90, 1, 1), 70 PLL_RATE(1104000000, 92, 1, 1), 71 PLL_RATE(1128000000, 94, 1, 1), 72 PLL_RATE(1152000000, 96, 1, 1), 73 PLL_RATE(1176000000, 98, 1, 1), 74 PLL_RATE(1200000000, 50, 1, 0), 75 PLL_RATE(1224000000, 51, 1, 0), 76 PLL_RATE(1248000000, 52, 1, 0), 77 PLL_RATE(1272000000, 53, 1, 0), 78 PLL_RATE(1296000000, 54, 1, 0), 79 PLL_RATE(1320000000, 55, 1, 0), 80 PLL_RATE(1344000000, 56, 1, 0), 81 PLL_RATE(1368000000, 57, 1, 0), 82 PLL_RATE(1392000000, 58, 1, 0), 83 PLL_RATE(1416000000, 59, 1, 0), 84 PLL_RATE(1440000000, 60, 1, 0), 85 PLL_RATE(1464000000, 61, 1, 0), 86 PLL_RATE(1488000000, 62, 1, 0), 87 PLL_RATE(1512000000, 63, 1, 0), 88 PLL_RATE(1536000000, 64, 1, 0), 89 PLL_RATE(1560000000, 65, 1, 0), 90 PLL_RATE(1584000000, 66, 1, 0), 91 PLL_RATE(1608000000, 67, 1, 0), 92 PLL_RATE(1632000000, 68, 1, 0), 93 PLL_RATE(1656000000, 68, 1, 0), 94 PLL_RATE(1680000000, 68, 1, 0), 95 PLL_RATE(1704000000, 68, 1, 0), 96 PLL_RATE(1728000000, 69, 1, 0), 97 PLL_RATE(1752000000, 69, 1, 0), 98 PLL_RATE(1776000000, 69, 1, 0), 99 PLL_RATE(1800000000, 69, 1, 0), 100 PLL_RATE(1824000000, 70, 1, 0), 101 PLL_RATE(1848000000, 70, 1, 0), 102 PLL_RATE(1872000000, 70, 1, 0), 103 PLL_RATE(1896000000, 70, 1, 0), 104 PLL_RATE(1920000000, 71, 1, 0), 105 PLL_RATE(1944000000, 71, 1, 0), 106 PLL_RATE(1968000000, 71, 1, 0), 107 PLL_RATE(1992000000, 71, 1, 0), 108 PLL_RATE(2016000000, 72, 1, 0), 109 PLL_RATE(2040000000, 72, 1, 0), 110 PLL_RATE(2064000000, 72, 1, 0), 111 PLL_RATE(2088000000, 72, 1, 0), 112 PLL_RATE(2112000000, 73, 1, 0), 113 { /* sentinel */ }, 114 }; 115 116 static struct meson_clk_pll axg_fixed_pll = { 117 .m = { 118 .reg_off = HHI_MPLL_CNTL, 119 .shift = 0, 120 .width = 9, 121 }, 122 .n = { 123 .reg_off = HHI_MPLL_CNTL, 124 .shift = 9, 125 .width = 5, 126 }, 127 .od = { 128 .reg_off = HHI_MPLL_CNTL, 129 .shift = 16, 130 .width = 2, 131 }, 132 .lock = &meson_clk_lock, 133 .hw.init = &(struct clk_init_data){ 134 .name = "fixed_pll", 135 .ops = &meson_clk_pll_ro_ops, 136 .parent_names = (const char *[]){ "xtal" }, 137 .num_parents = 1, 138 }, 139 }; 140 141 static struct meson_clk_pll axg_sys_pll = { 142 .m = { 143 .reg_off = HHI_SYS_PLL_CNTL, 144 .shift = 0, 145 .width = 9, 146 }, 147 .n = { 148 .reg_off = HHI_SYS_PLL_CNTL, 149 .shift = 9, 150 .width = 5, 151 }, 152 .od = { 153 .reg_off = HHI_SYS_PLL_CNTL, 154 .shift = 10, 155 .width = 2, 156 }, 157 .rate_table = sys_pll_rate_table, 158 .rate_count = ARRAY_SIZE(sys_pll_rate_table), 159 .lock = &meson_clk_lock, 160 .hw.init = &(struct clk_init_data){ 161 .name = "sys_pll", 162 .ops = &meson_clk_pll_ro_ops, 163 .parent_names = (const char *[]){ "xtal" }, 164 .num_parents = 1, 165 .flags = CLK_GET_RATE_NOCACHE, 166 }, 167 }; 168 169 static const struct pll_rate_table axg_gp0_pll_rate_table[] = { 170 PLL_RATE(240000000, 40, 1, 2), 171 PLL_RATE(246000000, 41, 1, 2), 172 PLL_RATE(252000000, 42, 1, 2), 173 PLL_RATE(258000000, 43, 1, 2), 174 PLL_RATE(264000000, 44, 1, 2), 175 PLL_RATE(270000000, 45, 1, 2), 176 PLL_RATE(276000000, 46, 1, 2), 177 PLL_RATE(282000000, 47, 1, 2), 178 PLL_RATE(288000000, 48, 1, 2), 179 PLL_RATE(294000000, 49, 1, 2), 180 PLL_RATE(300000000, 50, 1, 2), 181 PLL_RATE(306000000, 51, 1, 2), 182 PLL_RATE(312000000, 52, 1, 2), 183 PLL_RATE(318000000, 53, 1, 2), 184 PLL_RATE(324000000, 54, 1, 2), 185 PLL_RATE(330000000, 55, 1, 2), 186 PLL_RATE(336000000, 56, 1, 2), 187 PLL_RATE(342000000, 57, 1, 2), 188 PLL_RATE(348000000, 58, 1, 2), 189 PLL_RATE(354000000, 59, 1, 2), 190 PLL_RATE(360000000, 60, 1, 2), 191 PLL_RATE(366000000, 61, 1, 2), 192 PLL_RATE(372000000, 62, 1, 2), 193 PLL_RATE(378000000, 63, 1, 2), 194 PLL_RATE(384000000, 64, 1, 2), 195 PLL_RATE(390000000, 65, 1, 3), 196 PLL_RATE(396000000, 66, 1, 3), 197 PLL_RATE(402000000, 67, 1, 3), 198 PLL_RATE(408000000, 68, 1, 3), 199 PLL_RATE(480000000, 40, 1, 1), 200 PLL_RATE(492000000, 41, 1, 1), 201 PLL_RATE(504000000, 42, 1, 1), 202 PLL_RATE(516000000, 43, 1, 1), 203 PLL_RATE(528000000, 44, 1, 1), 204 PLL_RATE(540000000, 45, 1, 1), 205 PLL_RATE(552000000, 46, 1, 1), 206 PLL_RATE(564000000, 47, 1, 1), 207 PLL_RATE(576000000, 48, 1, 1), 208 PLL_RATE(588000000, 49, 1, 1), 209 PLL_RATE(600000000, 50, 1, 1), 210 PLL_RATE(612000000, 51, 1, 1), 211 PLL_RATE(624000000, 52, 1, 1), 212 PLL_RATE(636000000, 53, 1, 1), 213 PLL_RATE(648000000, 54, 1, 1), 214 PLL_RATE(660000000, 55, 1, 1), 215 PLL_RATE(672000000, 56, 1, 1), 216 PLL_RATE(684000000, 57, 1, 1), 217 PLL_RATE(696000000, 58, 1, 1), 218 PLL_RATE(708000000, 59, 1, 1), 219 PLL_RATE(720000000, 60, 1, 1), 220 PLL_RATE(732000000, 61, 1, 1), 221 PLL_RATE(744000000, 62, 1, 1), 222 PLL_RATE(756000000, 63, 1, 1), 223 PLL_RATE(768000000, 64, 1, 1), 224 PLL_RATE(780000000, 65, 1, 1), 225 PLL_RATE(792000000, 66, 1, 1), 226 PLL_RATE(804000000, 67, 1, 1), 227 PLL_RATE(816000000, 68, 1, 1), 228 PLL_RATE(960000000, 40, 1, 0), 229 PLL_RATE(984000000, 41, 1, 0), 230 PLL_RATE(1008000000, 42, 1, 0), 231 PLL_RATE(1032000000, 43, 1, 0), 232 PLL_RATE(1056000000, 44, 1, 0), 233 PLL_RATE(1080000000, 45, 1, 0), 234 PLL_RATE(1104000000, 46, 1, 0), 235 PLL_RATE(1128000000, 47, 1, 0), 236 PLL_RATE(1152000000, 48, 1, 0), 237 PLL_RATE(1176000000, 49, 1, 0), 238 PLL_RATE(1200000000, 50, 1, 0), 239 PLL_RATE(1224000000, 51, 1, 0), 240 PLL_RATE(1248000000, 52, 1, 0), 241 PLL_RATE(1272000000, 53, 1, 0), 242 PLL_RATE(1296000000, 54, 1, 0), 243 PLL_RATE(1320000000, 55, 1, 0), 244 PLL_RATE(1344000000, 56, 1, 0), 245 PLL_RATE(1368000000, 57, 1, 0), 246 PLL_RATE(1392000000, 58, 1, 0), 247 PLL_RATE(1416000000, 59, 1, 0), 248 PLL_RATE(1440000000, 60, 1, 0), 249 PLL_RATE(1464000000, 61, 1, 0), 250 PLL_RATE(1488000000, 62, 1, 0), 251 PLL_RATE(1512000000, 63, 1, 0), 252 PLL_RATE(1536000000, 64, 1, 0), 253 PLL_RATE(1560000000, 65, 1, 0), 254 PLL_RATE(1584000000, 66, 1, 0), 255 PLL_RATE(1608000000, 67, 1, 0), 256 PLL_RATE(1632000000, 68, 1, 0), 257 { /* sentinel */ }, 258 }; 259 260 static struct pll_params_table axg_gp0_params_table[] = { 261 PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250), 262 PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000), 263 PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be), 264 PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288), 265 PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d), 266 PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000), 267 }; 268 269 static struct meson_clk_pll axg_gp0_pll = { 270 .m = { 271 .reg_off = HHI_GP0_PLL_CNTL, 272 .shift = 0, 273 .width = 9, 274 }, 275 .n = { 276 .reg_off = HHI_GP0_PLL_CNTL, 277 .shift = 9, 278 .width = 5, 279 }, 280 .od = { 281 .reg_off = HHI_GP0_PLL_CNTL, 282 .shift = 16, 283 .width = 2, 284 }, 285 .params = { 286 .params_table = axg_gp0_params_table, 287 .params_count = ARRAY_SIZE(axg_gp0_params_table), 288 .no_init_reset = true, 289 .reset_lock_loop = true, 290 }, 291 .rate_table = axg_gp0_pll_rate_table, 292 .rate_count = ARRAY_SIZE(axg_gp0_pll_rate_table), 293 .lock = &meson_clk_lock, 294 .hw.init = &(struct clk_init_data){ 295 .name = "gp0_pll", 296 .ops = &meson_clk_pll_ops, 297 .parent_names = (const char *[]){ "xtal" }, 298 .num_parents = 1, 299 }, 300 }; 301 302 303 static struct clk_fixed_factor axg_fclk_div2 = { 304 .mult = 1, 305 .div = 2, 306 .hw.init = &(struct clk_init_data){ 307 .name = "fclk_div2", 308 .ops = &clk_fixed_factor_ops, 309 .parent_names = (const char *[]){ "fixed_pll" }, 310 .num_parents = 1, 311 }, 312 }; 313 314 static struct clk_fixed_factor axg_fclk_div3 = { 315 .mult = 1, 316 .div = 3, 317 .hw.init = &(struct clk_init_data){ 318 .name = "fclk_div3", 319 .ops = &clk_fixed_factor_ops, 320 .parent_names = (const char *[]){ "fixed_pll" }, 321 .num_parents = 1, 322 }, 323 }; 324 325 static struct clk_fixed_factor axg_fclk_div4 = { 326 .mult = 1, 327 .div = 4, 328 .hw.init = &(struct clk_init_data){ 329 .name = "fclk_div4", 330 .ops = &clk_fixed_factor_ops, 331 .parent_names = (const char *[]){ "fixed_pll" }, 332 .num_parents = 1, 333 }, 334 }; 335 336 static struct clk_fixed_factor axg_fclk_div5 = { 337 .mult = 1, 338 .div = 5, 339 .hw.init = &(struct clk_init_data){ 340 .name = "fclk_div5", 341 .ops = &clk_fixed_factor_ops, 342 .parent_names = (const char *[]){ "fixed_pll" }, 343 .num_parents = 1, 344 }, 345 }; 346 347 static struct clk_fixed_factor axg_fclk_div7 = { 348 .mult = 1, 349 .div = 7, 350 .hw.init = &(struct clk_init_data){ 351 .name = "fclk_div7", 352 .ops = &clk_fixed_factor_ops, 353 .parent_names = (const char *[]){ "fixed_pll" }, 354 .num_parents = 1, 355 }, 356 }; 357 358 static struct meson_clk_mpll axg_mpll0 = { 359 .sdm = { 360 .reg_off = HHI_MPLL_CNTL7, 361 .shift = 0, 362 .width = 14, 363 }, 364 .sdm_en = { 365 .reg_off = HHI_MPLL_CNTL7, 366 .shift = 15, 367 .width = 1, 368 }, 369 .n2 = { 370 .reg_off = HHI_MPLL_CNTL7, 371 .shift = 16, 372 .width = 9, 373 }, 374 .en = { 375 .reg_off = HHI_MPLL_CNTL7, 376 .shift = 14, 377 .width = 1, 378 }, 379 .ssen = { 380 .reg_off = HHI_MPLL_CNTL, 381 .shift = 25, 382 .width = 1, 383 }, 384 .lock = &meson_clk_lock, 385 .hw.init = &(struct clk_init_data){ 386 .name = "mpll0", 387 .ops = &meson_clk_mpll_ops, 388 .parent_names = (const char *[]){ "fixed_pll" }, 389 .num_parents = 1, 390 }, 391 }; 392 393 static struct meson_clk_mpll axg_mpll1 = { 394 .sdm = { 395 .reg_off = HHI_MPLL_CNTL8, 396 .shift = 0, 397 .width = 14, 398 }, 399 .sdm_en = { 400 .reg_off = HHI_MPLL_CNTL8, 401 .shift = 15, 402 .width = 1, 403 }, 404 .n2 = { 405 .reg_off = HHI_MPLL_CNTL8, 406 .shift = 16, 407 .width = 9, 408 }, 409 .en = { 410 .reg_off = HHI_MPLL_CNTL8, 411 .shift = 14, 412 .width = 1, 413 }, 414 .lock = &meson_clk_lock, 415 .hw.init = &(struct clk_init_data){ 416 .name = "mpll1", 417 .ops = &meson_clk_mpll_ops, 418 .parent_names = (const char *[]){ "fixed_pll" }, 419 .num_parents = 1, 420 }, 421 }; 422 423 static struct meson_clk_mpll axg_mpll2 = { 424 .sdm = { 425 .reg_off = HHI_MPLL_CNTL9, 426 .shift = 0, 427 .width = 14, 428 }, 429 .sdm_en = { 430 .reg_off = HHI_MPLL_CNTL9, 431 .shift = 15, 432 .width = 1, 433 }, 434 .n2 = { 435 .reg_off = HHI_MPLL_CNTL9, 436 .shift = 16, 437 .width = 9, 438 }, 439 .en = { 440 .reg_off = HHI_MPLL_CNTL9, 441 .shift = 14, 442 .width = 1, 443 }, 444 .lock = &meson_clk_lock, 445 .hw.init = &(struct clk_init_data){ 446 .name = "mpll2", 447 .ops = &meson_clk_mpll_ops, 448 .parent_names = (const char *[]){ "fixed_pll" }, 449 .num_parents = 1, 450 }, 451 }; 452 453 static struct meson_clk_mpll axg_mpll3 = { 454 .sdm = { 455 .reg_off = HHI_MPLL3_CNTL0, 456 .shift = 12, 457 .width = 14, 458 }, 459 .sdm_en = { 460 .reg_off = HHI_MPLL3_CNTL0, 461 .shift = 11, 462 .width = 1, 463 }, 464 .n2 = { 465 .reg_off = HHI_MPLL3_CNTL0, 466 .shift = 2, 467 .width = 9, 468 }, 469 .en = { 470 .reg_off = HHI_MPLL3_CNTL0, 471 .shift = 0, 472 .width = 1, 473 }, 474 .lock = &meson_clk_lock, 475 .hw.init = &(struct clk_init_data){ 476 .name = "mpll3", 477 .ops = &meson_clk_mpll_ops, 478 .parent_names = (const char *[]){ "fixed_pll" }, 479 .num_parents = 1, 480 }, 481 }; 482 483 /* 484 * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers 485 * and should be modeled with their respective PLLs via the forthcoming 486 * coordinated clock rates feature 487 */ 488 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 489 static const char * const clk81_parent_names[] = { 490 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", 491 "fclk_div3", "fclk_div5" 492 }; 493 494 static struct clk_mux axg_mpeg_clk_sel = { 495 .reg = (void *)HHI_MPEG_CLK_CNTL, 496 .mask = 0x7, 497 .shift = 12, 498 .flags = CLK_MUX_READ_ONLY, 499 .table = mux_table_clk81, 500 .lock = &meson_clk_lock, 501 .hw.init = &(struct clk_init_data){ 502 .name = "mpeg_clk_sel", 503 .ops = &clk_mux_ro_ops, 504 .parent_names = clk81_parent_names, 505 .num_parents = ARRAY_SIZE(clk81_parent_names), 506 }, 507 }; 508 509 static struct clk_divider axg_mpeg_clk_div = { 510 .reg = (void *)HHI_MPEG_CLK_CNTL, 511 .shift = 0, 512 .width = 7, 513 .lock = &meson_clk_lock, 514 .hw.init = &(struct clk_init_data){ 515 .name = "mpeg_clk_div", 516 .ops = &clk_divider_ops, 517 .parent_names = (const char *[]){ "mpeg_clk_sel" }, 518 .num_parents = 1, 519 .flags = CLK_SET_RATE_PARENT, 520 }, 521 }; 522 523 static struct clk_gate axg_clk81 = { 524 .reg = (void *)HHI_MPEG_CLK_CNTL, 525 .bit_idx = 7, 526 .lock = &meson_clk_lock, 527 .hw.init = &(struct clk_init_data){ 528 .name = "clk81", 529 .ops = &clk_gate_ops, 530 .parent_names = (const char *[]){ "mpeg_clk_div" }, 531 .num_parents = 1, 532 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 533 }, 534 }; 535 536 static const char * const axg_sd_emmc_clk0_parent_names[] = { 537 "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", 538 539 /* 540 * Following these parent clocks, we should also have had mpll2, mpll3 541 * and gp0_pll but these clocks are too precious to be used here. All 542 * the necessary rates for MMC and NAND operation can be acheived using 543 * xtal or fclk_div clocks 544 */ 545 }; 546 547 /* SDcard clock */ 548 static struct clk_mux axg_sd_emmc_b_clk0_sel = { 549 .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 550 .mask = 0x7, 551 .shift = 25, 552 .lock = &meson_clk_lock, 553 .hw.init = &(struct clk_init_data) { 554 .name = "sd_emmc_b_clk0_sel", 555 .ops = &clk_mux_ops, 556 .parent_names = axg_sd_emmc_clk0_parent_names, 557 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names), 558 .flags = CLK_SET_RATE_PARENT, 559 }, 560 }; 561 562 static struct clk_divider axg_sd_emmc_b_clk0_div = { 563 .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 564 .shift = 16, 565 .width = 7, 566 .lock = &meson_clk_lock, 567 .flags = CLK_DIVIDER_ROUND_CLOSEST, 568 .hw.init = &(struct clk_init_data) { 569 .name = "sd_emmc_b_clk0_div", 570 .ops = &clk_divider_ops, 571 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, 572 .num_parents = 1, 573 .flags = CLK_SET_RATE_PARENT, 574 }, 575 }; 576 577 static struct clk_gate axg_sd_emmc_b_clk0 = { 578 .reg = (void *)HHI_SD_EMMC_CLK_CNTL, 579 .bit_idx = 23, 580 .lock = &meson_clk_lock, 581 .hw.init = &(struct clk_init_data){ 582 .name = "sd_emmc_b_clk0", 583 .ops = &clk_gate_ops, 584 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, 585 .num_parents = 1, 586 .flags = CLK_SET_RATE_PARENT, 587 }, 588 }; 589 590 /* EMMC/NAND clock */ 591 static struct clk_mux axg_sd_emmc_c_clk0_sel = { 592 .reg = (void *)HHI_NAND_CLK_CNTL, 593 .mask = 0x7, 594 .shift = 9, 595 .lock = &meson_clk_lock, 596 .hw.init = &(struct clk_init_data) { 597 .name = "sd_emmc_c_clk0_sel", 598 .ops = &clk_mux_ops, 599 .parent_names = axg_sd_emmc_clk0_parent_names, 600 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names), 601 .flags = CLK_SET_RATE_PARENT, 602 }, 603 }; 604 605 static struct clk_divider axg_sd_emmc_c_clk0_div = { 606 .reg = (void *)HHI_NAND_CLK_CNTL, 607 .shift = 0, 608 .width = 7, 609 .lock = &meson_clk_lock, 610 .flags = CLK_DIVIDER_ROUND_CLOSEST, 611 .hw.init = &(struct clk_init_data) { 612 .name = "sd_emmc_c_clk0_div", 613 .ops = &clk_divider_ops, 614 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, 615 .num_parents = 1, 616 .flags = CLK_SET_RATE_PARENT, 617 }, 618 }; 619 620 static struct clk_gate axg_sd_emmc_c_clk0 = { 621 .reg = (void *)HHI_NAND_CLK_CNTL, 622 .bit_idx = 7, 623 .lock = &meson_clk_lock, 624 .hw.init = &(struct clk_init_data){ 625 .name = "sd_emmc_c_clk0", 626 .ops = &clk_gate_ops, 627 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, 628 .num_parents = 1, 629 .flags = CLK_SET_RATE_PARENT, 630 }, 631 }; 632 633 /* Everything Else (EE) domain gates */ 634 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0); 635 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2); 636 static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3); 637 static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5); 638 static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6); 639 static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7); 640 static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8); 641 static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9); 642 static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12); 643 static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13); 644 static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14); 645 static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15); 646 static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16); 647 static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17); 648 static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19); 649 static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23); 650 static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25); 651 static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26); 652 static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27); 653 static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30); 654 655 static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0); 656 static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3); 657 static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16); 658 static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20); 659 static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21); 660 static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22); 661 static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23); 662 static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26); 663 static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29); 664 static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30); 665 static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31); 666 667 static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1); 668 static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); 669 static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8); 670 static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9); 671 static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11); 672 static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25); 673 static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); 674 static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30); 675 676 /* Always On (AO) domain gates */ 677 678 static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0); 679 static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1); 680 static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2); 681 static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3); 682 static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4); 683 684 /* Array of all clocks provided by this provider */ 685 686 static struct clk_hw_onecell_data axg_hw_onecell_data = { 687 .hws = { 688 [CLKID_SYS_PLL] = &axg_sys_pll.hw, 689 [CLKID_FIXED_PLL] = &axg_fixed_pll.hw, 690 [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw, 691 [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw, 692 [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw, 693 [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw, 694 [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw, 695 [CLKID_GP0_PLL] = &axg_gp0_pll.hw, 696 [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw, 697 [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw, 698 [CLKID_CLK81] = &axg_clk81.hw, 699 [CLKID_MPLL0] = &axg_mpll0.hw, 700 [CLKID_MPLL1] = &axg_mpll1.hw, 701 [CLKID_MPLL2] = &axg_mpll2.hw, 702 [CLKID_MPLL3] = &axg_mpll3.hw, 703 [CLKID_DDR] = &axg_ddr.hw, 704 [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw, 705 [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw, 706 [CLKID_ISA] = &axg_isa.hw, 707 [CLKID_PL301] = &axg_pl301.hw, 708 [CLKID_PERIPHS] = &axg_periphs.hw, 709 [CLKID_SPICC0] = &axg_spicc_0.hw, 710 [CLKID_I2C] = &axg_i2c.hw, 711 [CLKID_RNG0] = &axg_rng0.hw, 712 [CLKID_UART0] = &axg_uart0.hw, 713 [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw, 714 [CLKID_SPICC1] = &axg_spicc_1.hw, 715 [CLKID_PCIE_A] = &axg_pcie_a.hw, 716 [CLKID_PCIE_B] = &axg_pcie_b.hw, 717 [CLKID_HIU_IFACE] = &axg_hiu_reg.hw, 718 [CLKID_ASSIST_MISC] = &axg_assist_misc.hw, 719 [CLKID_SD_EMMC_B] = &axg_emmc_b.hw, 720 [CLKID_SD_EMMC_C] = &axg_emmc_c.hw, 721 [CLKID_DMA] = &axg_dma.hw, 722 [CLKID_SPI] = &axg_spi.hw, 723 [CLKID_AUDIO] = &axg_audio.hw, 724 [CLKID_ETH] = &axg_eth_core.hw, 725 [CLKID_UART1] = &axg_uart1.hw, 726 [CLKID_G2D] = &axg_g2d.hw, 727 [CLKID_USB0] = &axg_usb0.hw, 728 [CLKID_USB1] = &axg_usb1.hw, 729 [CLKID_RESET] = &axg_reset.hw, 730 [CLKID_USB] = &axg_usb_general.hw, 731 [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw, 732 [CLKID_EFUSE] = &axg_efuse.hw, 733 [CLKID_BOOT_ROM] = &axg_boot_rom.hw, 734 [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw, 735 [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw, 736 [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw, 737 [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw, 738 [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw, 739 [CLKID_VPU_INTR] = &axg_vpu_intr.hw, 740 [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw, 741 [CLKID_GIC] = &axg_gic.hw, 742 [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw, 743 [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw, 744 [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw, 745 [CLKID_AO_IFACE] = &axg_ao_iface.hw, 746 [CLKID_AO_I2C] = &axg_ao_i2c.hw, 747 [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw, 748 [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw, 749 [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw, 750 [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw, 751 [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw, 752 [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw, 753 [NR_CLKS] = NULL, 754 }, 755 .num = NR_CLKS, 756 }; 757 758 /* Convenience tables to populate base addresses in .probe */ 759 760 static struct meson_clk_pll *const axg_clk_plls[] = { 761 &axg_fixed_pll, 762 &axg_sys_pll, 763 &axg_gp0_pll, 764 }; 765 766 static struct meson_clk_mpll *const axg_clk_mplls[] = { 767 &axg_mpll0, 768 &axg_mpll1, 769 &axg_mpll2, 770 &axg_mpll3, 771 }; 772 773 static struct clk_gate *const axg_clk_gates[] = { 774 &axg_clk81, 775 &axg_ddr, 776 &axg_audio_locker, 777 &axg_mipi_dsi_host, 778 &axg_isa, 779 &axg_pl301, 780 &axg_periphs, 781 &axg_spicc_0, 782 &axg_i2c, 783 &axg_rng0, 784 &axg_uart0, 785 &axg_mipi_dsi_phy, 786 &axg_spicc_1, 787 &axg_pcie_a, 788 &axg_pcie_b, 789 &axg_hiu_reg, 790 &axg_assist_misc, 791 &axg_emmc_b, 792 &axg_emmc_c, 793 &axg_dma, 794 &axg_spi, 795 &axg_audio, 796 &axg_eth_core, 797 &axg_uart1, 798 &axg_g2d, 799 &axg_usb0, 800 &axg_usb1, 801 &axg_reset, 802 &axg_usb_general, 803 &axg_ahb_arb0, 804 &axg_efuse, 805 &axg_boot_rom, 806 &axg_ahb_data_bus, 807 &axg_ahb_ctrl_bus, 808 &axg_usb1_to_ddr, 809 &axg_usb0_to_ddr, 810 &axg_mmc_pclk, 811 &axg_vpu_intr, 812 &axg_sec_ahb_ahb3_bridge, 813 &axg_gic, 814 &axg_ao_media_cpu, 815 &axg_ao_ahb_sram, 816 &axg_ao_ahb_bus, 817 &axg_ao_iface, 818 &axg_ao_i2c, 819 &axg_sd_emmc_b_clk0, 820 &axg_sd_emmc_c_clk0, 821 }; 822 823 static struct clk_mux *const axg_clk_muxes[] = { 824 &axg_mpeg_clk_sel, 825 &axg_sd_emmc_b_clk0_sel, 826 &axg_sd_emmc_c_clk0_sel, 827 }; 828 829 static struct clk_divider *const axg_clk_dividers[] = { 830 &axg_mpeg_clk_div, 831 &axg_sd_emmc_b_clk0_div, 832 &axg_sd_emmc_c_clk0_div, 833 }; 834 835 struct clkc_data { 836 struct clk_gate *const *clk_gates; 837 unsigned int clk_gates_count; 838 struct meson_clk_mpll *const *clk_mplls; 839 unsigned int clk_mplls_count; 840 struct meson_clk_pll *const *clk_plls; 841 unsigned int clk_plls_count; 842 struct clk_mux *const *clk_muxes; 843 unsigned int clk_muxes_count; 844 struct clk_divider *const *clk_dividers; 845 unsigned int clk_dividers_count; 846 struct clk_hw_onecell_data *hw_onecell_data; 847 }; 848 849 static const struct clkc_data axg_clkc_data = { 850 .clk_gates = axg_clk_gates, 851 .clk_gates_count = ARRAY_SIZE(axg_clk_gates), 852 .clk_mplls = axg_clk_mplls, 853 .clk_mplls_count = ARRAY_SIZE(axg_clk_mplls), 854 .clk_plls = axg_clk_plls, 855 .clk_plls_count = ARRAY_SIZE(axg_clk_plls), 856 .clk_muxes = axg_clk_muxes, 857 .clk_muxes_count = ARRAY_SIZE(axg_clk_muxes), 858 .clk_dividers = axg_clk_dividers, 859 .clk_dividers_count = ARRAY_SIZE(axg_clk_dividers), 860 .hw_onecell_data = &axg_hw_onecell_data, 861 }; 862 863 static const struct of_device_id clkc_match_table[] = { 864 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data }, 865 {} 866 }; 867 868 static int axg_clkc_probe(struct platform_device *pdev) 869 { 870 struct device *dev = &pdev->dev; 871 const struct clkc_data *clkc_data; 872 struct resource *res; 873 void __iomem *clk_base; 874 int ret, clkid, i; 875 876 clkc_data = of_device_get_match_data(&pdev->dev); 877 if (!clkc_data) 878 return -EINVAL; 879 880 /* Generic clocks and PLLs */ 881 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 882 if (!res) 883 return -EINVAL; 884 clk_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 885 if (!clk_base) { 886 dev_err(&pdev->dev, "Unable to map clk base\n"); 887 return -ENXIO; 888 } 889 890 /* Populate base address for PLLs */ 891 for (i = 0; i < clkc_data->clk_plls_count; i++) 892 clkc_data->clk_plls[i]->base = clk_base; 893 894 /* Populate base address for MPLLs */ 895 for (i = 0; i < clkc_data->clk_mplls_count; i++) 896 clkc_data->clk_mplls[i]->base = clk_base; 897 898 /* Populate base address for gates */ 899 for (i = 0; i < clkc_data->clk_gates_count; i++) 900 clkc_data->clk_gates[i]->reg = clk_base + 901 (u64)clkc_data->clk_gates[i]->reg; 902 903 /* Populate base address for muxes */ 904 for (i = 0; i < clkc_data->clk_muxes_count; i++) 905 clkc_data->clk_muxes[i]->reg = clk_base + 906 (u64)clkc_data->clk_muxes[i]->reg; 907 908 /* Populate base address for dividers */ 909 for (i = 0; i < clkc_data->clk_dividers_count; i++) 910 clkc_data->clk_dividers[i]->reg = clk_base + 911 (u64)clkc_data->clk_dividers[i]->reg; 912 913 for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) { 914 /* array might be sparse */ 915 if (!clkc_data->hw_onecell_data->hws[clkid]) 916 continue; 917 918 ret = devm_clk_hw_register(dev, 919 clkc_data->hw_onecell_data->hws[clkid]); 920 if (ret) { 921 dev_err(&pdev->dev, "Clock registration failed\n"); 922 return ret; 923 } 924 } 925 926 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, 927 clkc_data->hw_onecell_data); 928 } 929 930 static struct platform_driver axg_driver = { 931 .probe = axg_clkc_probe, 932 .driver = { 933 .name = "axg-clkc", 934 .of_match_table = clkc_match_table, 935 }, 936 }; 937 938 builtin_platform_driver(axg_driver); 939