1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* 3 * Copyright (c) 2018 BayLibre, SAS. 4 * Author: Jerome Brunet <jbrunet@baylibre.com> 5 */ 6 7 #ifndef __AXG_AUDIO_CLKC_H 8 #define __AXG_AUDIO_CLKC_H 9 10 /* 11 * Audio Clock register offsets 12 * 13 * Register offsets from the datasheet must be multiplied by 4 before 14 * to get the right offset 15 */ 16 #define AUDIO_CLK_GATE_EN 0x000 17 #define AUDIO_MCLK_A_CTRL 0x004 18 #define AUDIO_MCLK_B_CTRL 0x008 19 #define AUDIO_MCLK_C_CTRL 0x00C 20 #define AUDIO_MCLK_D_CTRL 0x010 21 #define AUDIO_MCLK_E_CTRL 0x014 22 #define AUDIO_MCLK_F_CTRL 0x018 23 #define AUDIO_MST_PAD_CTRL0 0x01c 24 #define AUDIO_MST_PAD_CTRL1 0x020 25 #define AUDIO_SW_RESET 0x024 26 #define AUDIO_MST_A_SCLK_CTRL0 0x040 27 #define AUDIO_MST_A_SCLK_CTRL1 0x044 28 #define AUDIO_MST_B_SCLK_CTRL0 0x048 29 #define AUDIO_MST_B_SCLK_CTRL1 0x04C 30 #define AUDIO_MST_C_SCLK_CTRL0 0x050 31 #define AUDIO_MST_C_SCLK_CTRL1 0x054 32 #define AUDIO_MST_D_SCLK_CTRL0 0x058 33 #define AUDIO_MST_D_SCLK_CTRL1 0x05C 34 #define AUDIO_MST_E_SCLK_CTRL0 0x060 35 #define AUDIO_MST_E_SCLK_CTRL1 0x064 36 #define AUDIO_MST_F_SCLK_CTRL0 0x068 37 #define AUDIO_MST_F_SCLK_CTRL1 0x06C 38 #define AUDIO_CLK_TDMIN_A_CTRL 0x080 39 #define AUDIO_CLK_TDMIN_B_CTRL 0x084 40 #define AUDIO_CLK_TDMIN_C_CTRL 0x088 41 #define AUDIO_CLK_TDMIN_LB_CTRL 0x08C 42 #define AUDIO_CLK_TDMOUT_A_CTRL 0x090 43 #define AUDIO_CLK_TDMOUT_B_CTRL 0x094 44 #define AUDIO_CLK_TDMOUT_C_CTRL 0x098 45 #define AUDIO_CLK_SPDIFIN_CTRL 0x09C 46 #define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0 47 #define AUDIO_CLK_RESAMPLE_CTRL 0x0A4 48 #define AUDIO_CLK_LOCKER_CTRL 0x0A8 49 #define AUDIO_CLK_PDMIN_CTRL0 0x0AC 50 #define AUDIO_CLK_PDMIN_CTRL1 0x0B0 51 #define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4 52 53 /* SM1 introduce new register and some shifts :( */ 54 #define AUDIO_CLK_GATE_EN1 0x004 55 #define AUDIO_SM1_MCLK_A_CTRL 0x008 56 #define AUDIO_SM1_MCLK_B_CTRL 0x00C 57 #define AUDIO_SM1_MCLK_C_CTRL 0x010 58 #define AUDIO_SM1_MCLK_D_CTRL 0x014 59 #define AUDIO_SM1_MCLK_E_CTRL 0x018 60 #define AUDIO_SM1_MCLK_F_CTRL 0x01C 61 #define AUDIO_SM1_MST_PAD_CTRL0 0x020 62 #define AUDIO_SM1_MST_PAD_CTRL1 0x024 63 #define AUDIO_SM1_SW_RESET0 0x028 64 #define AUDIO_SM1_SW_RESET1 0x02C 65 #define AUDIO_CLK81_CTRL 0x030 66 #define AUDIO_CLK81_EN 0x034 67 /* 68 * CLKID index values 69 * These indices are entirely contrived and do not map onto the hardware. 70 */ 71 72 #define AUD_CLKID_MST_A_MCLK_SEL 59 73 #define AUD_CLKID_MST_B_MCLK_SEL 60 74 #define AUD_CLKID_MST_C_MCLK_SEL 61 75 #define AUD_CLKID_MST_D_MCLK_SEL 62 76 #define AUD_CLKID_MST_E_MCLK_SEL 63 77 #define AUD_CLKID_MST_F_MCLK_SEL 64 78 #define AUD_CLKID_MST_A_MCLK_DIV 65 79 #define AUD_CLKID_MST_B_MCLK_DIV 66 80 #define AUD_CLKID_MST_C_MCLK_DIV 67 81 #define AUD_CLKID_MST_D_MCLK_DIV 68 82 #define AUD_CLKID_MST_E_MCLK_DIV 69 83 #define AUD_CLKID_MST_F_MCLK_DIV 70 84 #define AUD_CLKID_SPDIFOUT_CLK_SEL 71 85 #define AUD_CLKID_SPDIFOUT_CLK_DIV 72 86 #define AUD_CLKID_SPDIFIN_CLK_SEL 73 87 #define AUD_CLKID_SPDIFIN_CLK_DIV 74 88 #define AUD_CLKID_PDM_DCLK_SEL 75 89 #define AUD_CLKID_PDM_DCLK_DIV 76 90 #define AUD_CLKID_PDM_SYSCLK_SEL 77 91 #define AUD_CLKID_PDM_SYSCLK_DIV 78 92 #define AUD_CLKID_MST_A_SCLK_PRE_EN 92 93 #define AUD_CLKID_MST_B_SCLK_PRE_EN 93 94 #define AUD_CLKID_MST_C_SCLK_PRE_EN 94 95 #define AUD_CLKID_MST_D_SCLK_PRE_EN 95 96 #define AUD_CLKID_MST_E_SCLK_PRE_EN 96 97 #define AUD_CLKID_MST_F_SCLK_PRE_EN 97 98 #define AUD_CLKID_MST_A_SCLK_DIV 98 99 #define AUD_CLKID_MST_B_SCLK_DIV 99 100 #define AUD_CLKID_MST_C_SCLK_DIV 100 101 #define AUD_CLKID_MST_D_SCLK_DIV 101 102 #define AUD_CLKID_MST_E_SCLK_DIV 102 103 #define AUD_CLKID_MST_F_SCLK_DIV 103 104 #define AUD_CLKID_MST_A_SCLK_POST_EN 104 105 #define AUD_CLKID_MST_B_SCLK_POST_EN 105 106 #define AUD_CLKID_MST_C_SCLK_POST_EN 106 107 #define AUD_CLKID_MST_D_SCLK_POST_EN 107 108 #define AUD_CLKID_MST_E_SCLK_POST_EN 108 109 #define AUD_CLKID_MST_F_SCLK_POST_EN 109 110 #define AUD_CLKID_MST_A_LRCLK_DIV 110 111 #define AUD_CLKID_MST_B_LRCLK_DIV 111 112 #define AUD_CLKID_MST_C_LRCLK_DIV 112 113 #define AUD_CLKID_MST_D_LRCLK_DIV 113 114 #define AUD_CLKID_MST_E_LRCLK_DIV 114 115 #define AUD_CLKID_MST_F_LRCLK_DIV 115 116 #define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 137 117 #define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 138 118 #define AUD_CLKID_TDMIN_C_SCLK_PRE_EN 139 119 #define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 140 120 #define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 141 121 #define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 142 122 #define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN 143 123 #define AUD_CLKID_TDMIN_A_SCLK_POST_EN 144 124 #define AUD_CLKID_TDMIN_B_SCLK_POST_EN 145 125 #define AUD_CLKID_TDMIN_C_SCLK_POST_EN 146 126 #define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 147 127 #define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148 128 #define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149 129 #define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150 130 #define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153 131 #define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154 132 #define AUD_CLKID_CLK81_EN 173 133 #define AUD_CLKID_SYSCLK_A_DIV 174 134 #define AUD_CLKID_SYSCLK_B_DIV 175 135 #define AUD_CLKID_SYSCLK_A_EN 176 136 #define AUD_CLKID_SYSCLK_B_EN 177 137 138 /* include the CLKIDs which are part of the DT bindings */ 139 #include <dt-bindings/clock/axg-audio-clkc.h> 140 141 #define NR_CLKS 178 142 143 #endif /*__AXG_AUDIO_CLKC_H */ 144