11cd50181SJerome Brunet /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 21cd50181SJerome Brunet /* 31cd50181SJerome Brunet * Copyright (c) 2018 BayLibre, SAS. 41cd50181SJerome Brunet * Author: Jerome Brunet <jbrunet@baylibre.com> 51cd50181SJerome Brunet */ 61cd50181SJerome Brunet 71cd50181SJerome Brunet #ifndef __AXG_AUDIO_CLKC_H 81cd50181SJerome Brunet #define __AXG_AUDIO_CLKC_H 91cd50181SJerome Brunet 101cd50181SJerome Brunet /* 111cd50181SJerome Brunet * Audio Clock register offsets 121cd50181SJerome Brunet * 131cd50181SJerome Brunet * Register offsets from the datasheet must be multiplied by 4 before 141cd50181SJerome Brunet * to get the right offset 151cd50181SJerome Brunet */ 161cd50181SJerome Brunet #define AUDIO_CLK_GATE_EN 0x000 171cd50181SJerome Brunet #define AUDIO_MCLK_A_CTRL 0x004 181cd50181SJerome Brunet #define AUDIO_MCLK_B_CTRL 0x008 191cd50181SJerome Brunet #define AUDIO_MCLK_C_CTRL 0x00C 201cd50181SJerome Brunet #define AUDIO_MCLK_D_CTRL 0x010 211cd50181SJerome Brunet #define AUDIO_MCLK_E_CTRL 0x014 221cd50181SJerome Brunet #define AUDIO_MCLK_F_CTRL 0x018 2307500138SMaxime Jourdan #define AUDIO_MST_PAD_CTRL0 0x01c 2407500138SMaxime Jourdan #define AUDIO_MST_PAD_CTRL1 0x020 257cfefab6SJerome Brunet #define AUDIO_SW_RESET 0x024 261cd50181SJerome Brunet #define AUDIO_MST_A_SCLK_CTRL0 0x040 271cd50181SJerome Brunet #define AUDIO_MST_A_SCLK_CTRL1 0x044 281cd50181SJerome Brunet #define AUDIO_MST_B_SCLK_CTRL0 0x048 291cd50181SJerome Brunet #define AUDIO_MST_B_SCLK_CTRL1 0x04C 301cd50181SJerome Brunet #define AUDIO_MST_C_SCLK_CTRL0 0x050 311cd50181SJerome Brunet #define AUDIO_MST_C_SCLK_CTRL1 0x054 321cd50181SJerome Brunet #define AUDIO_MST_D_SCLK_CTRL0 0x058 331cd50181SJerome Brunet #define AUDIO_MST_D_SCLK_CTRL1 0x05C 341cd50181SJerome Brunet #define AUDIO_MST_E_SCLK_CTRL0 0x060 351cd50181SJerome Brunet #define AUDIO_MST_E_SCLK_CTRL1 0x064 361cd50181SJerome Brunet #define AUDIO_MST_F_SCLK_CTRL0 0x068 371cd50181SJerome Brunet #define AUDIO_MST_F_SCLK_CTRL1 0x06C 381cd50181SJerome Brunet #define AUDIO_CLK_TDMIN_A_CTRL 0x080 391cd50181SJerome Brunet #define AUDIO_CLK_TDMIN_B_CTRL 0x084 401cd50181SJerome Brunet #define AUDIO_CLK_TDMIN_C_CTRL 0x088 411cd50181SJerome Brunet #define AUDIO_CLK_TDMIN_LB_CTRL 0x08C 421cd50181SJerome Brunet #define AUDIO_CLK_TDMOUT_A_CTRL 0x090 431cd50181SJerome Brunet #define AUDIO_CLK_TDMOUT_B_CTRL 0x094 441cd50181SJerome Brunet #define AUDIO_CLK_TDMOUT_C_CTRL 0x098 451cd50181SJerome Brunet #define AUDIO_CLK_SPDIFIN_CTRL 0x09C 461cd50181SJerome Brunet #define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0 471cd50181SJerome Brunet #define AUDIO_CLK_RESAMPLE_CTRL 0x0A4 481cd50181SJerome Brunet #define AUDIO_CLK_LOCKER_CTRL 0x0A8 491cd50181SJerome Brunet #define AUDIO_CLK_PDMIN_CTRL0 0x0AC 501cd50181SJerome Brunet #define AUDIO_CLK_PDMIN_CTRL1 0x0B0 5107500138SMaxime Jourdan #define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4 521cd50181SJerome Brunet 53be4fe445SJerome Brunet /* SM1 introduce new register and some shifts :( */ 54be4fe445SJerome Brunet #define AUDIO_CLK_GATE_EN1 0x004 55be4fe445SJerome Brunet #define AUDIO_SM1_MCLK_A_CTRL 0x008 56be4fe445SJerome Brunet #define AUDIO_SM1_MCLK_B_CTRL 0x00C 57be4fe445SJerome Brunet #define AUDIO_SM1_MCLK_C_CTRL 0x010 58be4fe445SJerome Brunet #define AUDIO_SM1_MCLK_D_CTRL 0x014 59be4fe445SJerome Brunet #define AUDIO_SM1_MCLK_E_CTRL 0x018 60be4fe445SJerome Brunet #define AUDIO_SM1_MCLK_F_CTRL 0x01C 61be4fe445SJerome Brunet #define AUDIO_SM1_MST_PAD_CTRL0 0x020 62be4fe445SJerome Brunet #define AUDIO_SM1_MST_PAD_CTRL1 0x024 63be4fe445SJerome Brunet #define AUDIO_SM1_SW_RESET0 0x028 64be4fe445SJerome Brunet #define AUDIO_SM1_SW_RESET1 0x02C 65be4fe445SJerome Brunet #define AUDIO_CLK81_CTRL 0x030 66be4fe445SJerome Brunet #define AUDIO_CLK81_EN 0x034 671cd50181SJerome Brunet /* 681cd50181SJerome Brunet * CLKID index values 691cd50181SJerome Brunet * These indices are entirely contrived and do not map onto the hardware. 701cd50181SJerome Brunet */ 711cd50181SJerome Brunet 721cd50181SJerome Brunet #define AUD_CLKID_MST_A_MCLK_SEL 59 731cd50181SJerome Brunet #define AUD_CLKID_MST_B_MCLK_SEL 60 741cd50181SJerome Brunet #define AUD_CLKID_MST_C_MCLK_SEL 61 751cd50181SJerome Brunet #define AUD_CLKID_MST_D_MCLK_SEL 62 761cd50181SJerome Brunet #define AUD_CLKID_MST_E_MCLK_SEL 63 771cd50181SJerome Brunet #define AUD_CLKID_MST_F_MCLK_SEL 64 781cd50181SJerome Brunet #define AUD_CLKID_MST_A_MCLK_DIV 65 791cd50181SJerome Brunet #define AUD_CLKID_MST_B_MCLK_DIV 66 801cd50181SJerome Brunet #define AUD_CLKID_MST_C_MCLK_DIV 67 811cd50181SJerome Brunet #define AUD_CLKID_MST_D_MCLK_DIV 68 821cd50181SJerome Brunet #define AUD_CLKID_MST_E_MCLK_DIV 69 831cd50181SJerome Brunet #define AUD_CLKID_MST_F_MCLK_DIV 70 841cd50181SJerome Brunet #define AUD_CLKID_SPDIFOUT_CLK_SEL 71 851cd50181SJerome Brunet #define AUD_CLKID_SPDIFOUT_CLK_DIV 72 861cd50181SJerome Brunet #define AUD_CLKID_SPDIFIN_CLK_SEL 73 871cd50181SJerome Brunet #define AUD_CLKID_SPDIFIN_CLK_DIV 74 881cd50181SJerome Brunet #define AUD_CLKID_PDM_DCLK_SEL 75 891cd50181SJerome Brunet #define AUD_CLKID_PDM_DCLK_DIV 76 901cd50181SJerome Brunet #define AUD_CLKID_PDM_SYSCLK_SEL 77 911cd50181SJerome Brunet #define AUD_CLKID_PDM_SYSCLK_DIV 78 921cd50181SJerome Brunet #define AUD_CLKID_MST_A_SCLK_PRE_EN 92 931cd50181SJerome Brunet #define AUD_CLKID_MST_B_SCLK_PRE_EN 93 941cd50181SJerome Brunet #define AUD_CLKID_MST_C_SCLK_PRE_EN 94 951cd50181SJerome Brunet #define AUD_CLKID_MST_D_SCLK_PRE_EN 95 961cd50181SJerome Brunet #define AUD_CLKID_MST_E_SCLK_PRE_EN 96 971cd50181SJerome Brunet #define AUD_CLKID_MST_F_SCLK_PRE_EN 97 981cd50181SJerome Brunet #define AUD_CLKID_MST_A_SCLK_DIV 98 991cd50181SJerome Brunet #define AUD_CLKID_MST_B_SCLK_DIV 99 1001cd50181SJerome Brunet #define AUD_CLKID_MST_C_SCLK_DIV 100 1011cd50181SJerome Brunet #define AUD_CLKID_MST_D_SCLK_DIV 101 1021cd50181SJerome Brunet #define AUD_CLKID_MST_E_SCLK_DIV 102 1031cd50181SJerome Brunet #define AUD_CLKID_MST_F_SCLK_DIV 103 1041cd50181SJerome Brunet #define AUD_CLKID_MST_A_SCLK_POST_EN 104 1051cd50181SJerome Brunet #define AUD_CLKID_MST_B_SCLK_POST_EN 105 1061cd50181SJerome Brunet #define AUD_CLKID_MST_C_SCLK_POST_EN 106 1071cd50181SJerome Brunet #define AUD_CLKID_MST_D_SCLK_POST_EN 107 1081cd50181SJerome Brunet #define AUD_CLKID_MST_E_SCLK_POST_EN 108 1091cd50181SJerome Brunet #define AUD_CLKID_MST_F_SCLK_POST_EN 109 1101cd50181SJerome Brunet #define AUD_CLKID_MST_A_LRCLK_DIV 110 1111cd50181SJerome Brunet #define AUD_CLKID_MST_B_LRCLK_DIV 111 1121cd50181SJerome Brunet #define AUD_CLKID_MST_C_LRCLK_DIV 112 1131cd50181SJerome Brunet #define AUD_CLKID_MST_D_LRCLK_DIV 113 1141cd50181SJerome Brunet #define AUD_CLKID_MST_E_LRCLK_DIV 114 1151cd50181SJerome Brunet #define AUD_CLKID_MST_F_LRCLK_DIV 115 1161cd50181SJerome Brunet #define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 137 1171cd50181SJerome Brunet #define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 138 1181cd50181SJerome Brunet #define AUD_CLKID_TDMIN_C_SCLK_PRE_EN 139 1191cd50181SJerome Brunet #define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 140 1201cd50181SJerome Brunet #define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 141 1211cd50181SJerome Brunet #define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 142 1221cd50181SJerome Brunet #define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN 143 1231cd50181SJerome Brunet #define AUD_CLKID_TDMIN_A_SCLK_POST_EN 144 1241cd50181SJerome Brunet #define AUD_CLKID_TDMIN_B_SCLK_POST_EN 145 1251cd50181SJerome Brunet #define AUD_CLKID_TDMIN_C_SCLK_POST_EN 146 1261cd50181SJerome Brunet #define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 147 1271cd50181SJerome Brunet #define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148 1281cd50181SJerome Brunet #define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149 1291cd50181SJerome Brunet #define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150 13007500138SMaxime Jourdan #define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153 13107500138SMaxime Jourdan #define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154 132be4fe445SJerome Brunet #define AUD_CLKID_CLK81_EN 173 133be4fe445SJerome Brunet #define AUD_CLKID_SYSCLK_A_DIV 174 134be4fe445SJerome Brunet #define AUD_CLKID_SYSCLK_B_DIV 175 135be4fe445SJerome Brunet #define AUD_CLKID_SYSCLK_A_EN 176 136be4fe445SJerome Brunet #define AUD_CLKID_SYSCLK_B_EN 177 137cf52db45SJerome Brunet 1381cd50181SJerome Brunet /* include the CLKIDs which are part of the DT bindings */ 1391cd50181SJerome Brunet #include <dt-bindings/clock/axg-audio-clkc.h> 1401cd50181SJerome Brunet 141be4fe445SJerome Brunet #define NR_CLKS 178 1421cd50181SJerome Brunet 1431cd50181SJerome Brunet #endif /*__AXG_AUDIO_CLKC_H */ 144