1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Copyright (c) 2018 BayLibre, SAS. 4 * Author: Jerome Brunet <jbrunet@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/init.h> 10 #include <linux/of_device.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/reset.h> 15 #include <linux/slab.h> 16 17 #include "axg-audio.h" 18 #include "clk-input.h" 19 #include "clk-regmap.h" 20 #include "clk-phase.h" 21 #include "sclk-div.h" 22 23 #define AUD_MST_IN_COUNT 8 24 #define AUD_SLV_SCLK_COUNT 10 25 #define AUD_SLV_LRCLK_COUNT 10 26 27 #define AUD_GATE(_name, _reg, _bit, _pname, _iflags) \ 28 struct clk_regmap aud_##_name = { \ 29 .data = &(struct clk_regmap_gate_data){ \ 30 .offset = (_reg), \ 31 .bit_idx = (_bit), \ 32 }, \ 33 .hw.init = &(struct clk_init_data) { \ 34 .name = "aud_"#_name, \ 35 .ops = &clk_regmap_gate_ops, \ 36 .parent_names = (const char *[]){ _pname }, \ 37 .num_parents = 1, \ 38 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ 39 }, \ 40 } 41 42 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags) \ 43 struct clk_regmap aud_##_name = { \ 44 .data = &(struct clk_regmap_mux_data){ \ 45 .offset = (_reg), \ 46 .mask = (_mask), \ 47 .shift = (_shift), \ 48 .flags = (_dflags), \ 49 }, \ 50 .hw.init = &(struct clk_init_data){ \ 51 .name = "aud_"#_name, \ 52 .ops = &clk_regmap_mux_ops, \ 53 .parent_names = (_pnames), \ 54 .num_parents = ARRAY_SIZE(_pnames), \ 55 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ 56 }, \ 57 } 58 59 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) \ 60 struct clk_regmap aud_##_name = { \ 61 .data = &(struct clk_regmap_div_data){ \ 62 .offset = (_reg), \ 63 .shift = (_shift), \ 64 .width = (_width), \ 65 .flags = (_dflags), \ 66 }, \ 67 .hw.init = &(struct clk_init_data){ \ 68 .name = "aud_"#_name, \ 69 .ops = &clk_regmap_divider_ops, \ 70 .parent_names = (const char *[]) { _pname }, \ 71 .num_parents = 1, \ 72 .flags = (_iflags), \ 73 }, \ 74 } 75 76 #define AUD_PCLK_GATE(_name, _bit) \ 77 AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "audio_pclk", 0) 78 79 /* Audio peripheral clocks */ 80 static AUD_PCLK_GATE(ddr_arb, 0); 81 static AUD_PCLK_GATE(pdm, 1); 82 static AUD_PCLK_GATE(tdmin_a, 2); 83 static AUD_PCLK_GATE(tdmin_b, 3); 84 static AUD_PCLK_GATE(tdmin_c, 4); 85 static AUD_PCLK_GATE(tdmin_lb, 5); 86 static AUD_PCLK_GATE(tdmout_a, 6); 87 static AUD_PCLK_GATE(tdmout_b, 7); 88 static AUD_PCLK_GATE(tdmout_c, 8); 89 static AUD_PCLK_GATE(frddr_a, 9); 90 static AUD_PCLK_GATE(frddr_b, 10); 91 static AUD_PCLK_GATE(frddr_c, 11); 92 static AUD_PCLK_GATE(toddr_a, 12); 93 static AUD_PCLK_GATE(toddr_b, 13); 94 static AUD_PCLK_GATE(toddr_c, 14); 95 static AUD_PCLK_GATE(loopback, 15); 96 static AUD_PCLK_GATE(spdifin, 16); 97 static AUD_PCLK_GATE(spdifout, 17); 98 static AUD_PCLK_GATE(resample, 18); 99 static AUD_PCLK_GATE(power_detect, 19); 100 static AUD_PCLK_GATE(spdifout_b, 21); 101 102 /* Audio Master Clocks */ 103 static const char * const mst_mux_parent_names[] = { 104 "aud_mst_in0", "aud_mst_in1", "aud_mst_in2", "aud_mst_in3", 105 "aud_mst_in4", "aud_mst_in5", "aud_mst_in6", "aud_mst_in7", 106 }; 107 108 #define AUD_MST_MUX(_name, _reg, _flag) \ 109 AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \ 110 mst_mux_parent_names, CLK_SET_RATE_PARENT) 111 112 #define AUD_MST_MCLK_MUX(_name, _reg) \ 113 AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST) 114 115 #define AUD_MST_SYS_MUX(_name, _reg) \ 116 AUD_MST_MUX(_name, _reg, 0) 117 118 static AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL); 119 static AUD_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL); 120 static AUD_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL); 121 static AUD_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL); 122 static AUD_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL); 123 static AUD_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL); 124 static AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); 125 static AUD_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0); 126 static AUD_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); 127 static AUD_MST_SYS_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 128 static AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL); 129 130 #define AUD_MST_DIV(_name, _reg, _flag) \ 131 AUD_DIV(_name##_div, _reg, 0, 16, _flag, \ 132 "aud_"#_name"_sel", CLK_SET_RATE_PARENT) \ 133 134 #define AUD_MST_MCLK_DIV(_name, _reg) \ 135 AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST) 136 137 #define AUD_MST_SYS_DIV(_name, _reg) \ 138 AUD_MST_DIV(_name, _reg, 0) 139 140 static AUD_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL); 141 static AUD_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL); 142 static AUD_MST_MCLK_DIV(mst_c_mclk, AUDIO_MCLK_C_CTRL); 143 static AUD_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL); 144 static AUD_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL); 145 static AUD_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL); 146 static AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); 147 static AUD_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0); 148 static AUD_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); 149 static AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 150 static AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL); 151 152 #define AUD_MST_MCLK_GATE(_name, _reg) \ 153 AUD_GATE(_name, _reg, 31, "aud_"#_name"_div", \ 154 CLK_SET_RATE_PARENT) 155 156 static AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL); 157 static AUD_MST_MCLK_GATE(mst_b_mclk, AUDIO_MCLK_B_CTRL); 158 static AUD_MST_MCLK_GATE(mst_c_mclk, AUDIO_MCLK_C_CTRL); 159 static AUD_MST_MCLK_GATE(mst_d_mclk, AUDIO_MCLK_D_CTRL); 160 static AUD_MST_MCLK_GATE(mst_e_mclk, AUDIO_MCLK_E_CTRL); 161 static AUD_MST_MCLK_GATE(mst_f_mclk, AUDIO_MCLK_F_CTRL); 162 static AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL); 163 static AUD_MST_MCLK_GATE(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL); 164 static AUD_MST_MCLK_GATE(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0); 165 static AUD_MST_MCLK_GATE(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 166 static AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL); 167 168 /* Sample Clocks */ 169 #define AUD_MST_SCLK_PRE_EN(_name, _reg) \ 170 AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \ 171 "aud_mst_"#_name"_mclk", 0) 172 173 static AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0); 174 static AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0); 175 static AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0); 176 static AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0); 177 static AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0); 178 static AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0); 179 180 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ 181 _hi_shift, _hi_width, _pname, _iflags) \ 182 struct clk_regmap aud_##_name = { \ 183 .data = &(struct meson_sclk_div_data) { \ 184 .div = { \ 185 .reg_off = (_reg), \ 186 .shift = (_div_shift), \ 187 .width = (_div_width), \ 188 }, \ 189 .hi = { \ 190 .reg_off = (_reg), \ 191 .shift = (_hi_shift), \ 192 .width = (_hi_width), \ 193 }, \ 194 }, \ 195 .hw.init = &(struct clk_init_data) { \ 196 .name = "aud_"#_name, \ 197 .ops = &meson_sclk_div_ops, \ 198 .parent_names = (const char *[]) { _pname }, \ 199 .num_parents = 1, \ 200 .flags = (_iflags), \ 201 }, \ 202 } 203 204 #define AUD_MST_SCLK_DIV(_name, _reg) \ 205 AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \ 206 "aud_mst_"#_name"_sclk_pre_en", \ 207 CLK_SET_RATE_PARENT) 208 209 static AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0); 210 static AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0); 211 static AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0); 212 static AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0); 213 static AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0); 214 static AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0); 215 216 #define AUD_MST_SCLK_POST_EN(_name, _reg) \ 217 AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \ 218 "aud_mst_"#_name"_sclk_div", CLK_SET_RATE_PARENT) 219 220 static AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0); 221 static AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0); 222 static AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0); 223 static AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0); 224 static AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0); 225 static AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0); 226 227 #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ 228 _pname, _iflags) \ 229 struct clk_regmap aud_##_name = { \ 230 .data = &(struct meson_clk_triphase_data) { \ 231 .ph0 = { \ 232 .reg_off = (_reg), \ 233 .shift = (_shift0), \ 234 .width = (_width), \ 235 }, \ 236 .ph1 = { \ 237 .reg_off = (_reg), \ 238 .shift = (_shift1), \ 239 .width = (_width), \ 240 }, \ 241 .ph2 = { \ 242 .reg_off = (_reg), \ 243 .shift = (_shift2), \ 244 .width = (_width), \ 245 }, \ 246 }, \ 247 .hw.init = &(struct clk_init_data) { \ 248 .name = "aud_"#_name, \ 249 .ops = &meson_clk_triphase_ops, \ 250 .parent_names = (const char *[]) { _pname }, \ 251 .num_parents = 1, \ 252 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ 253 }, \ 254 } 255 256 #define AUD_MST_SCLK(_name, _reg) \ 257 AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \ 258 "aud_mst_"#_name"_sclk_post_en", CLK_SET_RATE_PARENT) 259 260 static AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1); 261 static AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1); 262 static AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1); 263 static AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1); 264 static AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1); 265 static AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1); 266 267 #define AUD_MST_LRCLK_DIV(_name, _reg) \ 268 AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \ 269 "aud_mst_"#_name"_sclk_post_en", 0) \ 270 271 static AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0); 272 static AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0); 273 static AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0); 274 static AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0); 275 static AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0); 276 static AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0); 277 278 #define AUD_MST_LRCLK(_name, _reg) \ 279 AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \ 280 "aud_mst_"#_name"_lrclk_div", CLK_SET_RATE_PARENT) 281 282 static AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1); 283 static AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1); 284 static AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1); 285 static AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1); 286 static AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1); 287 static AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1); 288 289 static const char * const tdm_sclk_parent_names[] = { 290 "aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk", 291 "aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk", 292 "aud_slv_sclk0", "aud_slv_sclk1", "aud_slv_sclk2", 293 "aud_slv_sclk3", "aud_slv_sclk4", "aud_slv_sclk5", 294 "aud_slv_sclk6", "aud_slv_sclk7", "aud_slv_sclk8", 295 "aud_slv_sclk9" 296 }; 297 298 #define AUD_TDM_SCLK_MUX(_name, _reg) \ 299 AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \ 300 CLK_MUX_ROUND_CLOSEST, \ 301 tdm_sclk_parent_names, 0) 302 303 static AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL); 304 static AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL); 305 static AUD_TDM_SCLK_MUX(in_c, AUDIO_CLK_TDMIN_C_CTRL); 306 static AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 307 static AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 308 static AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 309 static AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 310 311 #define AUD_TDM_SCLK_PRE_EN(_name, _reg) \ 312 AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \ 313 "aud_tdm"#_name"_sclk_sel", CLK_SET_RATE_PARENT) 314 315 static AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL); 316 static AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL); 317 static AUD_TDM_SCLK_PRE_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL); 318 static AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 319 static AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 320 static AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 321 static AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 322 323 #define AUD_TDM_SCLK_POST_EN(_name, _reg) \ 324 AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \ 325 "aud_tdm"#_name"_sclk_pre_en", CLK_SET_RATE_PARENT) 326 327 static AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL); 328 static AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL); 329 static AUD_TDM_SCLK_POST_EN(in_c, AUDIO_CLK_TDMIN_C_CTRL); 330 static AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 331 static AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 332 static AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 333 static AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 334 335 #define AUD_TDM_SCLK(_name, _reg) \ 336 struct clk_regmap aud_tdm##_name##_sclk = { \ 337 .data = &(struct meson_clk_phase_data) { \ 338 .ph = { \ 339 .reg_off = (_reg), \ 340 .shift = 29, \ 341 .width = 1, \ 342 }, \ 343 }, \ 344 .hw.init = &(struct clk_init_data) { \ 345 .name = "aud_tdm"#_name"_sclk", \ 346 .ops = &meson_clk_phase_ops, \ 347 .parent_names = (const char *[]) \ 348 { "aud_tdm"#_name"_sclk_post_en" }, \ 349 .num_parents = 1, \ 350 .flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT, \ 351 }, \ 352 } 353 354 static AUD_TDM_SCLK(in_a, AUDIO_CLK_TDMIN_A_CTRL); 355 static AUD_TDM_SCLK(in_b, AUDIO_CLK_TDMIN_B_CTRL); 356 static AUD_TDM_SCLK(in_c, AUDIO_CLK_TDMIN_C_CTRL); 357 static AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 358 static AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 359 static AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 360 static AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 361 362 static const char * const tdm_lrclk_parent_names[] = { 363 "aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk", 364 "aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk", 365 "aud_slv_lrclk0", "aud_slv_lrclk1", "aud_slv_lrclk2", 366 "aud_slv_lrclk3", "aud_slv_lrclk4", "aud_slv_lrclk5", 367 "aud_slv_lrclk6", "aud_slv_lrclk7", "aud_slv_lrclk8", 368 "aud_slv_lrclk9" 369 }; 370 371 #define AUD_TDM_LRLCK(_name, _reg) \ 372 AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \ 373 CLK_MUX_ROUND_CLOSEST, \ 374 tdm_lrclk_parent_names, 0) 375 376 static AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL); 377 static AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL); 378 static AUD_TDM_LRLCK(in_c, AUDIO_CLK_TDMIN_C_CTRL); 379 static AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL); 380 static AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 381 static AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 382 static AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 383 384 /* G12a Pad control */ 385 #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents) \ 386 AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents, \ 387 CLK_SET_RATE_NO_REPARENT) 388 389 static const char * const mclk_pad_ctrl_parent_names[] = { 390 "aud_mst_a_mclk", "aud_mst_b_mclk", "aud_mst_c_mclk", 391 "aud_mst_d_mclk", "aud_mst_e_mclk", "aud_mst_f_mclk", 392 }; 393 394 static AUD_TDM_PAD_CTRL(mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0, 395 mclk_pad_ctrl_parent_names); 396 static AUD_TDM_PAD_CTRL(mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4, 397 mclk_pad_ctrl_parent_names); 398 399 static const char * const lrclk_pad_ctrl_parent_names[] = { 400 "aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk", 401 "aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk", 402 }; 403 404 static AUD_TDM_PAD_CTRL(lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16, 405 lrclk_pad_ctrl_parent_names); 406 static AUD_TDM_PAD_CTRL(lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20, 407 lrclk_pad_ctrl_parent_names); 408 static AUD_TDM_PAD_CTRL(lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24, 409 lrclk_pad_ctrl_parent_names); 410 411 static const char * const sclk_pad_ctrl_parent_names[] = { 412 "aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk", 413 "aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk", 414 }; 415 416 static AUD_TDM_PAD_CTRL(sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0, 417 sclk_pad_ctrl_parent_names); 418 static AUD_TDM_PAD_CTRL(sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4, 419 sclk_pad_ctrl_parent_names); 420 static AUD_TDM_PAD_CTRL(sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8, 421 sclk_pad_ctrl_parent_names); 422 423 /* 424 * Array of all clocks provided by this provider 425 * The input clocks of the controller will be populated at runtime 426 */ 427 static struct clk_hw_onecell_data axg_audio_hw_onecell_data = { 428 .hws = { 429 [AUD_CLKID_DDR_ARB] = &aud_ddr_arb.hw, 430 [AUD_CLKID_PDM] = &aud_pdm.hw, 431 [AUD_CLKID_TDMIN_A] = &aud_tdmin_a.hw, 432 [AUD_CLKID_TDMIN_B] = &aud_tdmin_b.hw, 433 [AUD_CLKID_TDMIN_C] = &aud_tdmin_c.hw, 434 [AUD_CLKID_TDMIN_LB] = &aud_tdmin_lb.hw, 435 [AUD_CLKID_TDMOUT_A] = &aud_tdmout_a.hw, 436 [AUD_CLKID_TDMOUT_B] = &aud_tdmout_b.hw, 437 [AUD_CLKID_TDMOUT_C] = &aud_tdmout_c.hw, 438 [AUD_CLKID_FRDDR_A] = &aud_frddr_a.hw, 439 [AUD_CLKID_FRDDR_B] = &aud_frddr_b.hw, 440 [AUD_CLKID_FRDDR_C] = &aud_frddr_c.hw, 441 [AUD_CLKID_TODDR_A] = &aud_toddr_a.hw, 442 [AUD_CLKID_TODDR_B] = &aud_toddr_b.hw, 443 [AUD_CLKID_TODDR_C] = &aud_toddr_c.hw, 444 [AUD_CLKID_LOOPBACK] = &aud_loopback.hw, 445 [AUD_CLKID_SPDIFIN] = &aud_spdifin.hw, 446 [AUD_CLKID_SPDIFOUT] = &aud_spdifout.hw, 447 [AUD_CLKID_RESAMPLE] = &aud_resample.hw, 448 [AUD_CLKID_POWER_DETECT] = &aud_power_detect.hw, 449 [AUD_CLKID_MST_A_MCLK_SEL] = &aud_mst_a_mclk_sel.hw, 450 [AUD_CLKID_MST_B_MCLK_SEL] = &aud_mst_b_mclk_sel.hw, 451 [AUD_CLKID_MST_C_MCLK_SEL] = &aud_mst_c_mclk_sel.hw, 452 [AUD_CLKID_MST_D_MCLK_SEL] = &aud_mst_d_mclk_sel.hw, 453 [AUD_CLKID_MST_E_MCLK_SEL] = &aud_mst_e_mclk_sel.hw, 454 [AUD_CLKID_MST_F_MCLK_SEL] = &aud_mst_f_mclk_sel.hw, 455 [AUD_CLKID_MST_A_MCLK_DIV] = &aud_mst_a_mclk_div.hw, 456 [AUD_CLKID_MST_B_MCLK_DIV] = &aud_mst_b_mclk_div.hw, 457 [AUD_CLKID_MST_C_MCLK_DIV] = &aud_mst_c_mclk_div.hw, 458 [AUD_CLKID_MST_D_MCLK_DIV] = &aud_mst_d_mclk_div.hw, 459 [AUD_CLKID_MST_E_MCLK_DIV] = &aud_mst_e_mclk_div.hw, 460 [AUD_CLKID_MST_F_MCLK_DIV] = &aud_mst_f_mclk_div.hw, 461 [AUD_CLKID_MST_A_MCLK] = &aud_mst_a_mclk.hw, 462 [AUD_CLKID_MST_B_MCLK] = &aud_mst_b_mclk.hw, 463 [AUD_CLKID_MST_C_MCLK] = &aud_mst_c_mclk.hw, 464 [AUD_CLKID_MST_D_MCLK] = &aud_mst_d_mclk.hw, 465 [AUD_CLKID_MST_E_MCLK] = &aud_mst_e_mclk.hw, 466 [AUD_CLKID_MST_F_MCLK] = &aud_mst_f_mclk.hw, 467 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &aud_spdifout_clk_sel.hw, 468 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &aud_spdifout_clk_div.hw, 469 [AUD_CLKID_SPDIFOUT_CLK] = &aud_spdifout_clk.hw, 470 [AUD_CLKID_SPDIFIN_CLK_SEL] = &aud_spdifin_clk_sel.hw, 471 [AUD_CLKID_SPDIFIN_CLK_DIV] = &aud_spdifin_clk_div.hw, 472 [AUD_CLKID_SPDIFIN_CLK] = &aud_spdifin_clk.hw, 473 [AUD_CLKID_PDM_DCLK_SEL] = &aud_pdm_dclk_sel.hw, 474 [AUD_CLKID_PDM_DCLK_DIV] = &aud_pdm_dclk_div.hw, 475 [AUD_CLKID_PDM_DCLK] = &aud_pdm_dclk.hw, 476 [AUD_CLKID_PDM_SYSCLK_SEL] = &aud_pdm_sysclk_sel.hw, 477 [AUD_CLKID_PDM_SYSCLK_DIV] = &aud_pdm_sysclk_div.hw, 478 [AUD_CLKID_PDM_SYSCLK] = &aud_pdm_sysclk.hw, 479 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &aud_mst_a_sclk_pre_en.hw, 480 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &aud_mst_b_sclk_pre_en.hw, 481 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &aud_mst_c_sclk_pre_en.hw, 482 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &aud_mst_d_sclk_pre_en.hw, 483 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &aud_mst_e_sclk_pre_en.hw, 484 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &aud_mst_f_sclk_pre_en.hw, 485 [AUD_CLKID_MST_A_SCLK_DIV] = &aud_mst_a_sclk_div.hw, 486 [AUD_CLKID_MST_B_SCLK_DIV] = &aud_mst_b_sclk_div.hw, 487 [AUD_CLKID_MST_C_SCLK_DIV] = &aud_mst_c_sclk_div.hw, 488 [AUD_CLKID_MST_D_SCLK_DIV] = &aud_mst_d_sclk_div.hw, 489 [AUD_CLKID_MST_E_SCLK_DIV] = &aud_mst_e_sclk_div.hw, 490 [AUD_CLKID_MST_F_SCLK_DIV] = &aud_mst_f_sclk_div.hw, 491 [AUD_CLKID_MST_A_SCLK_POST_EN] = &aud_mst_a_sclk_post_en.hw, 492 [AUD_CLKID_MST_B_SCLK_POST_EN] = &aud_mst_b_sclk_post_en.hw, 493 [AUD_CLKID_MST_C_SCLK_POST_EN] = &aud_mst_c_sclk_post_en.hw, 494 [AUD_CLKID_MST_D_SCLK_POST_EN] = &aud_mst_d_sclk_post_en.hw, 495 [AUD_CLKID_MST_E_SCLK_POST_EN] = &aud_mst_e_sclk_post_en.hw, 496 [AUD_CLKID_MST_F_SCLK_POST_EN] = &aud_mst_f_sclk_post_en.hw, 497 [AUD_CLKID_MST_A_SCLK] = &aud_mst_a_sclk.hw, 498 [AUD_CLKID_MST_B_SCLK] = &aud_mst_b_sclk.hw, 499 [AUD_CLKID_MST_C_SCLK] = &aud_mst_c_sclk.hw, 500 [AUD_CLKID_MST_D_SCLK] = &aud_mst_d_sclk.hw, 501 [AUD_CLKID_MST_E_SCLK] = &aud_mst_e_sclk.hw, 502 [AUD_CLKID_MST_F_SCLK] = &aud_mst_f_sclk.hw, 503 [AUD_CLKID_MST_A_LRCLK_DIV] = &aud_mst_a_lrclk_div.hw, 504 [AUD_CLKID_MST_B_LRCLK_DIV] = &aud_mst_b_lrclk_div.hw, 505 [AUD_CLKID_MST_C_LRCLK_DIV] = &aud_mst_c_lrclk_div.hw, 506 [AUD_CLKID_MST_D_LRCLK_DIV] = &aud_mst_d_lrclk_div.hw, 507 [AUD_CLKID_MST_E_LRCLK_DIV] = &aud_mst_e_lrclk_div.hw, 508 [AUD_CLKID_MST_F_LRCLK_DIV] = &aud_mst_f_lrclk_div.hw, 509 [AUD_CLKID_MST_A_LRCLK] = &aud_mst_a_lrclk.hw, 510 [AUD_CLKID_MST_B_LRCLK] = &aud_mst_b_lrclk.hw, 511 [AUD_CLKID_MST_C_LRCLK] = &aud_mst_c_lrclk.hw, 512 [AUD_CLKID_MST_D_LRCLK] = &aud_mst_d_lrclk.hw, 513 [AUD_CLKID_MST_E_LRCLK] = &aud_mst_e_lrclk.hw, 514 [AUD_CLKID_MST_F_LRCLK] = &aud_mst_f_lrclk.hw, 515 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &aud_tdmin_a_sclk_sel.hw, 516 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &aud_tdmin_b_sclk_sel.hw, 517 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &aud_tdmin_c_sclk_sel.hw, 518 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &aud_tdmin_lb_sclk_sel.hw, 519 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &aud_tdmout_a_sclk_sel.hw, 520 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &aud_tdmout_b_sclk_sel.hw, 521 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &aud_tdmout_c_sclk_sel.hw, 522 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &aud_tdmin_a_sclk_pre_en.hw, 523 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &aud_tdmin_b_sclk_pre_en.hw, 524 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &aud_tdmin_c_sclk_pre_en.hw, 525 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &aud_tdmin_lb_sclk_pre_en.hw, 526 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &aud_tdmout_a_sclk_pre_en.hw, 527 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &aud_tdmout_b_sclk_pre_en.hw, 528 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &aud_tdmout_c_sclk_pre_en.hw, 529 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &aud_tdmin_a_sclk_post_en.hw, 530 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &aud_tdmin_b_sclk_post_en.hw, 531 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &aud_tdmin_c_sclk_post_en.hw, 532 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &aud_tdmin_lb_sclk_post_en.hw, 533 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &aud_tdmout_a_sclk_post_en.hw, 534 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &aud_tdmout_b_sclk_post_en.hw, 535 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &aud_tdmout_c_sclk_post_en.hw, 536 [AUD_CLKID_TDMIN_A_SCLK] = &aud_tdmin_a_sclk.hw, 537 [AUD_CLKID_TDMIN_B_SCLK] = &aud_tdmin_b_sclk.hw, 538 [AUD_CLKID_TDMIN_C_SCLK] = &aud_tdmin_c_sclk.hw, 539 [AUD_CLKID_TDMIN_LB_SCLK] = &aud_tdmin_lb_sclk.hw, 540 [AUD_CLKID_TDMOUT_A_SCLK] = &aud_tdmout_a_sclk.hw, 541 [AUD_CLKID_TDMOUT_B_SCLK] = &aud_tdmout_b_sclk.hw, 542 [AUD_CLKID_TDMOUT_C_SCLK] = &aud_tdmout_c_sclk.hw, 543 [AUD_CLKID_TDMIN_A_LRCLK] = &aud_tdmin_a_lrclk.hw, 544 [AUD_CLKID_TDMIN_B_LRCLK] = &aud_tdmin_b_lrclk.hw, 545 [AUD_CLKID_TDMIN_C_LRCLK] = &aud_tdmin_c_lrclk.hw, 546 [AUD_CLKID_TDMIN_LB_LRCLK] = &aud_tdmin_lb_lrclk.hw, 547 [AUD_CLKID_TDMOUT_A_LRCLK] = &aud_tdmout_a_lrclk.hw, 548 [AUD_CLKID_TDMOUT_B_LRCLK] = &aud_tdmout_b_lrclk.hw, 549 [AUD_CLKID_TDMOUT_C_LRCLK] = &aud_tdmout_c_lrclk.hw, 550 [NR_CLKS] = NULL, 551 }, 552 .num = NR_CLKS, 553 }; 554 555 /* 556 * Array of all G12A clocks provided by this provider 557 * The input clocks of the controller will be populated at runtime 558 */ 559 static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = { 560 .hws = { 561 [AUD_CLKID_DDR_ARB] = &aud_ddr_arb.hw, 562 [AUD_CLKID_PDM] = &aud_pdm.hw, 563 [AUD_CLKID_TDMIN_A] = &aud_tdmin_a.hw, 564 [AUD_CLKID_TDMIN_B] = &aud_tdmin_b.hw, 565 [AUD_CLKID_TDMIN_C] = &aud_tdmin_c.hw, 566 [AUD_CLKID_TDMIN_LB] = &aud_tdmin_lb.hw, 567 [AUD_CLKID_TDMOUT_A] = &aud_tdmout_a.hw, 568 [AUD_CLKID_TDMOUT_B] = &aud_tdmout_b.hw, 569 [AUD_CLKID_TDMOUT_C] = &aud_tdmout_c.hw, 570 [AUD_CLKID_FRDDR_A] = &aud_frddr_a.hw, 571 [AUD_CLKID_FRDDR_B] = &aud_frddr_b.hw, 572 [AUD_CLKID_FRDDR_C] = &aud_frddr_c.hw, 573 [AUD_CLKID_TODDR_A] = &aud_toddr_a.hw, 574 [AUD_CLKID_TODDR_B] = &aud_toddr_b.hw, 575 [AUD_CLKID_TODDR_C] = &aud_toddr_c.hw, 576 [AUD_CLKID_LOOPBACK] = &aud_loopback.hw, 577 [AUD_CLKID_SPDIFIN] = &aud_spdifin.hw, 578 [AUD_CLKID_SPDIFOUT] = &aud_spdifout.hw, 579 [AUD_CLKID_RESAMPLE] = &aud_resample.hw, 580 [AUD_CLKID_POWER_DETECT] = &aud_power_detect.hw, 581 [AUD_CLKID_SPDIFOUT_B] = &aud_spdifout_b.hw, 582 [AUD_CLKID_MST_A_MCLK_SEL] = &aud_mst_a_mclk_sel.hw, 583 [AUD_CLKID_MST_B_MCLK_SEL] = &aud_mst_b_mclk_sel.hw, 584 [AUD_CLKID_MST_C_MCLK_SEL] = &aud_mst_c_mclk_sel.hw, 585 [AUD_CLKID_MST_D_MCLK_SEL] = &aud_mst_d_mclk_sel.hw, 586 [AUD_CLKID_MST_E_MCLK_SEL] = &aud_mst_e_mclk_sel.hw, 587 [AUD_CLKID_MST_F_MCLK_SEL] = &aud_mst_f_mclk_sel.hw, 588 [AUD_CLKID_MST_A_MCLK_DIV] = &aud_mst_a_mclk_div.hw, 589 [AUD_CLKID_MST_B_MCLK_DIV] = &aud_mst_b_mclk_div.hw, 590 [AUD_CLKID_MST_C_MCLK_DIV] = &aud_mst_c_mclk_div.hw, 591 [AUD_CLKID_MST_D_MCLK_DIV] = &aud_mst_d_mclk_div.hw, 592 [AUD_CLKID_MST_E_MCLK_DIV] = &aud_mst_e_mclk_div.hw, 593 [AUD_CLKID_MST_F_MCLK_DIV] = &aud_mst_f_mclk_div.hw, 594 [AUD_CLKID_MST_A_MCLK] = &aud_mst_a_mclk.hw, 595 [AUD_CLKID_MST_B_MCLK] = &aud_mst_b_mclk.hw, 596 [AUD_CLKID_MST_C_MCLK] = &aud_mst_c_mclk.hw, 597 [AUD_CLKID_MST_D_MCLK] = &aud_mst_d_mclk.hw, 598 [AUD_CLKID_MST_E_MCLK] = &aud_mst_e_mclk.hw, 599 [AUD_CLKID_MST_F_MCLK] = &aud_mst_f_mclk.hw, 600 [AUD_CLKID_SPDIFOUT_CLK_SEL] = &aud_spdifout_clk_sel.hw, 601 [AUD_CLKID_SPDIFOUT_CLK_DIV] = &aud_spdifout_clk_div.hw, 602 [AUD_CLKID_SPDIFOUT_CLK] = &aud_spdifout_clk.hw, 603 [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &aud_spdifout_b_clk_sel.hw, 604 [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &aud_spdifout_b_clk_div.hw, 605 [AUD_CLKID_SPDIFOUT_B_CLK] = &aud_spdifout_b_clk.hw, 606 [AUD_CLKID_SPDIFIN_CLK_SEL] = &aud_spdifin_clk_sel.hw, 607 [AUD_CLKID_SPDIFIN_CLK_DIV] = &aud_spdifin_clk_div.hw, 608 [AUD_CLKID_SPDIFIN_CLK] = &aud_spdifin_clk.hw, 609 [AUD_CLKID_PDM_DCLK_SEL] = &aud_pdm_dclk_sel.hw, 610 [AUD_CLKID_PDM_DCLK_DIV] = &aud_pdm_dclk_div.hw, 611 [AUD_CLKID_PDM_DCLK] = &aud_pdm_dclk.hw, 612 [AUD_CLKID_PDM_SYSCLK_SEL] = &aud_pdm_sysclk_sel.hw, 613 [AUD_CLKID_PDM_SYSCLK_DIV] = &aud_pdm_sysclk_div.hw, 614 [AUD_CLKID_PDM_SYSCLK] = &aud_pdm_sysclk.hw, 615 [AUD_CLKID_MST_A_SCLK_PRE_EN] = &aud_mst_a_sclk_pre_en.hw, 616 [AUD_CLKID_MST_B_SCLK_PRE_EN] = &aud_mst_b_sclk_pre_en.hw, 617 [AUD_CLKID_MST_C_SCLK_PRE_EN] = &aud_mst_c_sclk_pre_en.hw, 618 [AUD_CLKID_MST_D_SCLK_PRE_EN] = &aud_mst_d_sclk_pre_en.hw, 619 [AUD_CLKID_MST_E_SCLK_PRE_EN] = &aud_mst_e_sclk_pre_en.hw, 620 [AUD_CLKID_MST_F_SCLK_PRE_EN] = &aud_mst_f_sclk_pre_en.hw, 621 [AUD_CLKID_MST_A_SCLK_DIV] = &aud_mst_a_sclk_div.hw, 622 [AUD_CLKID_MST_B_SCLK_DIV] = &aud_mst_b_sclk_div.hw, 623 [AUD_CLKID_MST_C_SCLK_DIV] = &aud_mst_c_sclk_div.hw, 624 [AUD_CLKID_MST_D_SCLK_DIV] = &aud_mst_d_sclk_div.hw, 625 [AUD_CLKID_MST_E_SCLK_DIV] = &aud_mst_e_sclk_div.hw, 626 [AUD_CLKID_MST_F_SCLK_DIV] = &aud_mst_f_sclk_div.hw, 627 [AUD_CLKID_MST_A_SCLK_POST_EN] = &aud_mst_a_sclk_post_en.hw, 628 [AUD_CLKID_MST_B_SCLK_POST_EN] = &aud_mst_b_sclk_post_en.hw, 629 [AUD_CLKID_MST_C_SCLK_POST_EN] = &aud_mst_c_sclk_post_en.hw, 630 [AUD_CLKID_MST_D_SCLK_POST_EN] = &aud_mst_d_sclk_post_en.hw, 631 [AUD_CLKID_MST_E_SCLK_POST_EN] = &aud_mst_e_sclk_post_en.hw, 632 [AUD_CLKID_MST_F_SCLK_POST_EN] = &aud_mst_f_sclk_post_en.hw, 633 [AUD_CLKID_MST_A_SCLK] = &aud_mst_a_sclk.hw, 634 [AUD_CLKID_MST_B_SCLK] = &aud_mst_b_sclk.hw, 635 [AUD_CLKID_MST_C_SCLK] = &aud_mst_c_sclk.hw, 636 [AUD_CLKID_MST_D_SCLK] = &aud_mst_d_sclk.hw, 637 [AUD_CLKID_MST_E_SCLK] = &aud_mst_e_sclk.hw, 638 [AUD_CLKID_MST_F_SCLK] = &aud_mst_f_sclk.hw, 639 [AUD_CLKID_MST_A_LRCLK_DIV] = &aud_mst_a_lrclk_div.hw, 640 [AUD_CLKID_MST_B_LRCLK_DIV] = &aud_mst_b_lrclk_div.hw, 641 [AUD_CLKID_MST_C_LRCLK_DIV] = &aud_mst_c_lrclk_div.hw, 642 [AUD_CLKID_MST_D_LRCLK_DIV] = &aud_mst_d_lrclk_div.hw, 643 [AUD_CLKID_MST_E_LRCLK_DIV] = &aud_mst_e_lrclk_div.hw, 644 [AUD_CLKID_MST_F_LRCLK_DIV] = &aud_mst_f_lrclk_div.hw, 645 [AUD_CLKID_MST_A_LRCLK] = &aud_mst_a_lrclk.hw, 646 [AUD_CLKID_MST_B_LRCLK] = &aud_mst_b_lrclk.hw, 647 [AUD_CLKID_MST_C_LRCLK] = &aud_mst_c_lrclk.hw, 648 [AUD_CLKID_MST_D_LRCLK] = &aud_mst_d_lrclk.hw, 649 [AUD_CLKID_MST_E_LRCLK] = &aud_mst_e_lrclk.hw, 650 [AUD_CLKID_MST_F_LRCLK] = &aud_mst_f_lrclk.hw, 651 [AUD_CLKID_TDMIN_A_SCLK_SEL] = &aud_tdmin_a_sclk_sel.hw, 652 [AUD_CLKID_TDMIN_B_SCLK_SEL] = &aud_tdmin_b_sclk_sel.hw, 653 [AUD_CLKID_TDMIN_C_SCLK_SEL] = &aud_tdmin_c_sclk_sel.hw, 654 [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &aud_tdmin_lb_sclk_sel.hw, 655 [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &aud_tdmout_a_sclk_sel.hw, 656 [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &aud_tdmout_b_sclk_sel.hw, 657 [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &aud_tdmout_c_sclk_sel.hw, 658 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &aud_tdmin_a_sclk_pre_en.hw, 659 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &aud_tdmin_b_sclk_pre_en.hw, 660 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &aud_tdmin_c_sclk_pre_en.hw, 661 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &aud_tdmin_lb_sclk_pre_en.hw, 662 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &aud_tdmout_a_sclk_pre_en.hw, 663 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &aud_tdmout_b_sclk_pre_en.hw, 664 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &aud_tdmout_c_sclk_pre_en.hw, 665 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &aud_tdmin_a_sclk_post_en.hw, 666 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &aud_tdmin_b_sclk_post_en.hw, 667 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &aud_tdmin_c_sclk_post_en.hw, 668 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &aud_tdmin_lb_sclk_post_en.hw, 669 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &aud_tdmout_a_sclk_post_en.hw, 670 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &aud_tdmout_b_sclk_post_en.hw, 671 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &aud_tdmout_c_sclk_post_en.hw, 672 [AUD_CLKID_TDMIN_A_SCLK] = &aud_tdmin_a_sclk.hw, 673 [AUD_CLKID_TDMIN_B_SCLK] = &aud_tdmin_b_sclk.hw, 674 [AUD_CLKID_TDMIN_C_SCLK] = &aud_tdmin_c_sclk.hw, 675 [AUD_CLKID_TDMIN_LB_SCLK] = &aud_tdmin_lb_sclk.hw, 676 [AUD_CLKID_TDMOUT_A_SCLK] = &aud_tdmout_a_sclk.hw, 677 [AUD_CLKID_TDMOUT_B_SCLK] = &aud_tdmout_b_sclk.hw, 678 [AUD_CLKID_TDMOUT_C_SCLK] = &aud_tdmout_c_sclk.hw, 679 [AUD_CLKID_TDMIN_A_LRCLK] = &aud_tdmin_a_lrclk.hw, 680 [AUD_CLKID_TDMIN_B_LRCLK] = &aud_tdmin_b_lrclk.hw, 681 [AUD_CLKID_TDMIN_C_LRCLK] = &aud_tdmin_c_lrclk.hw, 682 [AUD_CLKID_TDMIN_LB_LRCLK] = &aud_tdmin_lb_lrclk.hw, 683 [AUD_CLKID_TDMOUT_A_LRCLK] = &aud_tdmout_a_lrclk.hw, 684 [AUD_CLKID_TDMOUT_B_LRCLK] = &aud_tdmout_b_lrclk.hw, 685 [AUD_CLKID_TDMOUT_C_LRCLK] = &aud_tdmout_c_lrclk.hw, 686 [AUD_CLKID_TDM_MCLK_PAD0] = &aud_tdm_mclk_pad_0.hw, 687 [AUD_CLKID_TDM_MCLK_PAD1] = &aud_tdm_mclk_pad_1.hw, 688 [AUD_CLKID_TDM_LRCLK_PAD0] = &aud_tdm_lrclk_pad_0.hw, 689 [AUD_CLKID_TDM_LRCLK_PAD1] = &aud_tdm_lrclk_pad_1.hw, 690 [AUD_CLKID_TDM_LRCLK_PAD2] = &aud_tdm_lrclk_pad_2.hw, 691 [AUD_CLKID_TDM_SCLK_PAD0] = &aud_tdm_sclk_pad_0.hw, 692 [AUD_CLKID_TDM_SCLK_PAD1] = &aud_tdm_sclk_pad_1.hw, 693 [AUD_CLKID_TDM_SCLK_PAD2] = &aud_tdm_sclk_pad_2.hw, 694 [NR_CLKS] = NULL, 695 }, 696 .num = NR_CLKS, 697 }; 698 699 /* Convenience table to populate regmap in .probe() 700 * Note that this table is shared between both AXG and G12A, 701 * with spdifout_b clocks being exclusive to G12A. Since those 702 * clocks are not declared within the AXG onecell table, we do not 703 * feel the need to have separate AXG/G12A regmap tables. 704 */ 705 static struct clk_regmap *const aud_clk_regmaps[] = { 706 &aud_ddr_arb, 707 &aud_pdm, 708 &aud_tdmin_a, 709 &aud_tdmin_b, 710 &aud_tdmin_c, 711 &aud_tdmin_lb, 712 &aud_tdmout_a, 713 &aud_tdmout_b, 714 &aud_tdmout_c, 715 &aud_frddr_a, 716 &aud_frddr_b, 717 &aud_frddr_c, 718 &aud_toddr_a, 719 &aud_toddr_b, 720 &aud_toddr_c, 721 &aud_loopback, 722 &aud_spdifin, 723 &aud_spdifout, 724 &aud_resample, 725 &aud_power_detect, 726 &aud_spdifout_b, 727 &aud_mst_a_mclk_sel, 728 &aud_mst_b_mclk_sel, 729 &aud_mst_c_mclk_sel, 730 &aud_mst_d_mclk_sel, 731 &aud_mst_e_mclk_sel, 732 &aud_mst_f_mclk_sel, 733 &aud_mst_a_mclk_div, 734 &aud_mst_b_mclk_div, 735 &aud_mst_c_mclk_div, 736 &aud_mst_d_mclk_div, 737 &aud_mst_e_mclk_div, 738 &aud_mst_f_mclk_div, 739 &aud_mst_a_mclk, 740 &aud_mst_b_mclk, 741 &aud_mst_c_mclk, 742 &aud_mst_d_mclk, 743 &aud_mst_e_mclk, 744 &aud_mst_f_mclk, 745 &aud_spdifout_clk_sel, 746 &aud_spdifout_clk_div, 747 &aud_spdifout_clk, 748 &aud_spdifin_clk_sel, 749 &aud_spdifin_clk_div, 750 &aud_spdifin_clk, 751 &aud_pdm_dclk_sel, 752 &aud_pdm_dclk_div, 753 &aud_pdm_dclk, 754 &aud_pdm_sysclk_sel, 755 &aud_pdm_sysclk_div, 756 &aud_pdm_sysclk, 757 &aud_mst_a_sclk_pre_en, 758 &aud_mst_b_sclk_pre_en, 759 &aud_mst_c_sclk_pre_en, 760 &aud_mst_d_sclk_pre_en, 761 &aud_mst_e_sclk_pre_en, 762 &aud_mst_f_sclk_pre_en, 763 &aud_mst_a_sclk_div, 764 &aud_mst_b_sclk_div, 765 &aud_mst_c_sclk_div, 766 &aud_mst_d_sclk_div, 767 &aud_mst_e_sclk_div, 768 &aud_mst_f_sclk_div, 769 &aud_mst_a_sclk_post_en, 770 &aud_mst_b_sclk_post_en, 771 &aud_mst_c_sclk_post_en, 772 &aud_mst_d_sclk_post_en, 773 &aud_mst_e_sclk_post_en, 774 &aud_mst_f_sclk_post_en, 775 &aud_mst_a_sclk, 776 &aud_mst_b_sclk, 777 &aud_mst_c_sclk, 778 &aud_mst_d_sclk, 779 &aud_mst_e_sclk, 780 &aud_mst_f_sclk, 781 &aud_mst_a_lrclk_div, 782 &aud_mst_b_lrclk_div, 783 &aud_mst_c_lrclk_div, 784 &aud_mst_d_lrclk_div, 785 &aud_mst_e_lrclk_div, 786 &aud_mst_f_lrclk_div, 787 &aud_mst_a_lrclk, 788 &aud_mst_b_lrclk, 789 &aud_mst_c_lrclk, 790 &aud_mst_d_lrclk, 791 &aud_mst_e_lrclk, 792 &aud_mst_f_lrclk, 793 &aud_tdmin_a_sclk_sel, 794 &aud_tdmin_b_sclk_sel, 795 &aud_tdmin_c_sclk_sel, 796 &aud_tdmin_lb_sclk_sel, 797 &aud_tdmout_a_sclk_sel, 798 &aud_tdmout_b_sclk_sel, 799 &aud_tdmout_c_sclk_sel, 800 &aud_tdmin_a_sclk_pre_en, 801 &aud_tdmin_b_sclk_pre_en, 802 &aud_tdmin_c_sclk_pre_en, 803 &aud_tdmin_lb_sclk_pre_en, 804 &aud_tdmout_a_sclk_pre_en, 805 &aud_tdmout_b_sclk_pre_en, 806 &aud_tdmout_c_sclk_pre_en, 807 &aud_tdmin_a_sclk_post_en, 808 &aud_tdmin_b_sclk_post_en, 809 &aud_tdmin_c_sclk_post_en, 810 &aud_tdmin_lb_sclk_post_en, 811 &aud_tdmout_a_sclk_post_en, 812 &aud_tdmout_b_sclk_post_en, 813 &aud_tdmout_c_sclk_post_en, 814 &aud_tdmin_a_sclk, 815 &aud_tdmin_b_sclk, 816 &aud_tdmin_c_sclk, 817 &aud_tdmin_lb_sclk, 818 &aud_tdmout_a_sclk, 819 &aud_tdmout_b_sclk, 820 &aud_tdmout_c_sclk, 821 &aud_tdmin_a_lrclk, 822 &aud_tdmin_b_lrclk, 823 &aud_tdmin_c_lrclk, 824 &aud_tdmin_lb_lrclk, 825 &aud_tdmout_a_lrclk, 826 &aud_tdmout_b_lrclk, 827 &aud_tdmout_c_lrclk, 828 &aud_spdifout_b_clk_sel, 829 &aud_spdifout_b_clk_div, 830 &aud_spdifout_b_clk, 831 &aud_tdm_mclk_pad_0, 832 &aud_tdm_mclk_pad_1, 833 &aud_tdm_lrclk_pad_0, 834 &aud_tdm_lrclk_pad_1, 835 &aud_tdm_lrclk_pad_2, 836 &aud_tdm_sclk_pad_0, 837 &aud_tdm_sclk_pad_1, 838 &aud_tdm_sclk_pad_2, 839 }; 840 841 static int devm_clk_get_enable(struct device *dev, char *id) 842 { 843 struct clk *clk; 844 int ret; 845 846 clk = devm_clk_get(dev, id); 847 if (IS_ERR(clk)) { 848 ret = PTR_ERR(clk); 849 if (ret != -EPROBE_DEFER) 850 dev_err(dev, "failed to get %s", id); 851 return ret; 852 } 853 854 ret = clk_prepare_enable(clk); 855 if (ret) { 856 dev_err(dev, "failed to enable %s", id); 857 return ret; 858 } 859 860 ret = devm_add_action_or_reset(dev, 861 (void(*)(void *))clk_disable_unprepare, 862 clk); 863 if (ret) { 864 dev_err(dev, "failed to add reset action on %s", id); 865 return ret; 866 } 867 868 return 0; 869 } 870 871 static int axg_register_clk_hw_input(struct device *dev, 872 const char *name) 873 { 874 char *clk_name; 875 struct clk_hw *hw; 876 int err = 0; 877 878 clk_name = kasprintf(GFP_KERNEL, "aud_%s", name); 879 if (!clk_name) 880 return -ENOMEM; 881 882 hw = meson_clk_hw_register_input(dev, name, clk_name, 0); 883 if (IS_ERR(hw)) { 884 /* It is ok if an input clock is missing */ 885 if (PTR_ERR(hw) == -ENOENT) { 886 dev_dbg(dev, "%s not provided", name); 887 } else { 888 err = PTR_ERR(hw); 889 if (err != -EPROBE_DEFER) 890 dev_err(dev, "failed to get %s clock", name); 891 } 892 } 893 894 kfree(clk_name); 895 return err; 896 } 897 898 static int axg_register_clk_hw_inputs(struct device *dev, 899 const char *basename, 900 unsigned int count) 901 { 902 char *name; 903 int i, ret; 904 905 for (i = 0; i < count; i++) { 906 name = kasprintf(GFP_KERNEL, "%s%d", basename, i); 907 if (!name) 908 return -ENOMEM; 909 910 ret = axg_register_clk_hw_input(dev, name); 911 kfree(name); 912 if (ret) 913 return ret; 914 } 915 916 return 0; 917 } 918 919 static const struct regmap_config axg_audio_regmap_cfg = { 920 .reg_bits = 32, 921 .val_bits = 32, 922 .reg_stride = 4, 923 .max_register = AUDIO_CLK_PDMIN_CTRL1, 924 }; 925 926 struct audioclk_data { 927 struct clk_hw_onecell_data *hw_onecell_data; 928 }; 929 930 static int axg_audio_clkc_probe(struct platform_device *pdev) 931 { 932 struct device *dev = &pdev->dev; 933 const struct audioclk_data *data; 934 struct regmap *map; 935 struct resource *res; 936 void __iomem *regs; 937 struct clk_hw *hw; 938 int ret, i; 939 940 data = of_device_get_match_data(dev); 941 if (!data) 942 return -EINVAL; 943 944 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 945 regs = devm_ioremap_resource(dev, res); 946 if (IS_ERR(regs)) 947 return PTR_ERR(regs); 948 949 map = devm_regmap_init_mmio(dev, regs, &axg_audio_regmap_cfg); 950 if (IS_ERR(map)) { 951 dev_err(dev, "failed to init regmap: %ld\n", PTR_ERR(map)); 952 return PTR_ERR(map); 953 } 954 955 /* Get the mandatory peripheral clock */ 956 ret = devm_clk_get_enable(dev, "pclk"); 957 if (ret) 958 return ret; 959 960 ret = device_reset(dev); 961 if (ret) { 962 dev_err(dev, "failed to reset device\n"); 963 return ret; 964 } 965 966 /* Register the peripheral input clock */ 967 hw = meson_clk_hw_register_input(dev, "pclk", "audio_pclk", 0); 968 if (IS_ERR(hw)) 969 return PTR_ERR(hw); 970 971 /* Register optional input master clocks */ 972 ret = axg_register_clk_hw_inputs(dev, "mst_in", 973 AUD_MST_IN_COUNT); 974 if (ret) 975 return ret; 976 977 /* Register optional input slave sclks */ 978 ret = axg_register_clk_hw_inputs(dev, "slv_sclk", 979 AUD_SLV_SCLK_COUNT); 980 if (ret) 981 return ret; 982 983 /* Register optional input slave lrclks */ 984 ret = axg_register_clk_hw_inputs(dev, "slv_lrclk", 985 AUD_SLV_LRCLK_COUNT); 986 if (ret) 987 return ret; 988 989 /* Populate regmap for the regmap backed clocks */ 990 for (i = 0; i < ARRAY_SIZE(aud_clk_regmaps); i++) 991 aud_clk_regmaps[i]->map = map; 992 993 /* Take care to skip the registered input clocks */ 994 for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) { 995 hw = data->hw_onecell_data->hws[i]; 996 /* array might be sparse */ 997 if (!hw) 998 continue; 999 1000 ret = devm_clk_hw_register(dev, hw); 1001 if (ret) { 1002 dev_err(dev, "failed to register clock %s\n", 1003 hw->init->name); 1004 return ret; 1005 } 1006 } 1007 1008 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 1009 data->hw_onecell_data); 1010 } 1011 1012 static const struct audioclk_data axg_audioclk_data = { 1013 .hw_onecell_data = &axg_audio_hw_onecell_data, 1014 }; 1015 1016 static const struct audioclk_data g12a_audioclk_data = { 1017 .hw_onecell_data = &g12a_audio_hw_onecell_data, 1018 }; 1019 1020 static const struct of_device_id clkc_match_table[] = { 1021 { 1022 .compatible = "amlogic,axg-audio-clkc", 1023 .data = &axg_audioclk_data 1024 }, { 1025 .compatible = "amlogic,g12a-audio-clkc", 1026 .data = &g12a_audioclk_data 1027 }, {} 1028 }; 1029 MODULE_DEVICE_TABLE(of, clkc_match_table); 1030 1031 static struct platform_driver axg_audio_driver = { 1032 .probe = axg_audio_clkc_probe, 1033 .driver = { 1034 .name = "axg-audio-clkc", 1035 .of_match_table = clkc_match_table, 1036 }, 1037 }; 1038 module_platform_driver(axg_audio_driver); 1039 1040 MODULE_DESCRIPTION("Amlogic AXG/G12A Audio Clock driver"); 1041 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>"); 1042 MODULE_LICENSE("GPL v2"); 1043