1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Amlogic A1 Peripherals Clock Controller internals 4 * 5 * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 6 * Author: Jian Hu <jian.hu@amlogic.com> 7 * 8 * Copyright (c) 2023, SberDevices. All Rights Reserved. 9 * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> 10 */ 11 12 #ifndef __A1_PERIPHERALS_H 13 #define __A1_PERIPHERALS_H 14 15 /* peripherals clock controller register offset */ 16 #define SYS_OSCIN_CTRL 0x0 17 #define RTC_BY_OSCIN_CTRL0 0x4 18 #define RTC_BY_OSCIN_CTRL1 0x8 19 #define RTC_CTRL 0xc 20 #define SYS_CLK_CTRL0 0x10 21 #define SYS_CLK_EN0 0x1c 22 #define SYS_CLK_EN1 0x20 23 #define AXI_CLK_EN 0x24 24 #define DSPA_CLK_EN 0x28 25 #define DSPB_CLK_EN 0x2c 26 #define DSPA_CLK_CTRL0 0x30 27 #define DSPB_CLK_CTRL0 0x34 28 #define CLK12_24_CTRL 0x38 29 #define GEN_CLK_CTRL 0x3c 30 #define SAR_ADC_CLK_CTRL 0xc0 31 #define PWM_CLK_AB_CTRL 0xc4 32 #define PWM_CLK_CD_CTRL 0xc8 33 #define PWM_CLK_EF_CTRL 0xcc 34 #define SPICC_CLK_CTRL 0xd0 35 #define TS_CLK_CTRL 0xd4 36 #define SPIFC_CLK_CTRL 0xd8 37 #define USB_BUSCLK_CTRL 0xdc 38 #define SD_EMMC_CLK_CTRL 0xe0 39 #define CECA_CLK_CTRL0 0xe4 40 #define CECA_CLK_CTRL1 0xe8 41 #define CECB_CLK_CTRL0 0xec 42 #define CECB_CLK_CTRL1 0xf0 43 #define PSRAM_CLK_CTRL 0xf4 44 #define DMC_CLK_CTRL 0xf8 45 46 /* include the CLKIDs that have been made part of the DT binding */ 47 #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h> 48 49 /* 50 * CLKID index values for internal clocks 51 * 52 * These indices are entirely contrived and do not map onto the hardware. 53 * It has now been decided to expose everything by default in the DT header: 54 * include/dt-bindings/clock/a1-peripherals-clkc.h. 55 * Only the clocks ids we don't want to expose, such as the internal muxes and 56 * dividers of composite clocks, will remain defined here. 57 */ 58 #define CLKID_XTAL_IN 0 59 #define CLKID_DSPA_SEL 61 60 #define CLKID_DSPB_SEL 62 61 #define CLKID_SARADC_SEL 74 62 #define CLKID_SYS_A_SEL 89 63 #define CLKID_SYS_A_DIV 90 64 #define CLKID_SYS_A 91 65 #define CLKID_SYS_B_SEL 92 66 #define CLKID_SYS_B_DIV 93 67 #define CLKID_SYS_B 94 68 #define CLKID_DSPA_A_DIV 96 69 #define CLKID_DSPA_A 97 70 #define CLKID_DSPA_B_DIV 99 71 #define CLKID_DSPA_B 100 72 #define CLKID_DSPB_A_DIV 102 73 #define CLKID_DSPB_A 103 74 #define CLKID_DSPB_B_DIV 105 75 #define CLKID_DSPB_B 106 76 #define CLKID_RTC_32K_IN 107 77 #define CLKID_RTC_32K_DIV 108 78 #define CLKID_RTC_32K_XTAL 109 79 #define CLKID_RTC_32K_SEL 110 80 #define CLKID_CECB_32K_IN 111 81 #define CLKID_CECB_32K_DIV 112 82 #define CLKID_CECA_32K_IN 115 83 #define CLKID_CECA_32K_DIV 116 84 #define CLKID_DIV2_PRE 119 85 #define CLKID_24M_DIV2 120 86 #define CLKID_GEN_DIV 122 87 #define CLKID_SARADC_DIV 123 88 #define CLKID_PWM_A_DIV 125 89 #define CLKID_PWM_B_DIV 127 90 #define CLKID_PWM_C_DIV 129 91 #define CLKID_PWM_D_DIV 131 92 #define CLKID_PWM_E_DIV 133 93 #define CLKID_PWM_F_DIV 135 94 #define CLKID_SPICC_SEL 136 95 #define CLKID_SPICC_DIV 137 96 #define CLKID_SPICC_SEL2 138 97 #define CLKID_TS_DIV 139 98 #define CLKID_SPIFC_SEL 140 99 #define CLKID_SPIFC_DIV 141 100 #define CLKID_SPIFC_SEL2 142 101 #define CLKID_USB_BUS_SEL 143 102 #define CLKID_USB_BUS_DIV 144 103 #define CLKID_SD_EMMC_SEL 145 104 #define CLKID_SD_EMMC_DIV 146 105 #define CLKID_PSRAM_SEL 148 106 #define CLKID_PSRAM_DIV 149 107 #define CLKID_PSRAM_SEL2 150 108 #define CLKID_DMC_SEL 151 109 #define CLKID_DMC_DIV 152 110 #define CLKID_DMC_SEL2 153 111 112 #endif /* __A1_PERIPHERALS_H */ 113