1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 4 * Author: Jian Hu <jian.hu@amlogic.com> 5 * 6 * Copyright (c) 2023, SberDevices. All Rights Reserved. 7 * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> 8 */ 9 10 #include <linux/clk-provider.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include "a1-peripherals.h" 14 #include "clk-dualdiv.h" 15 #include "clk-regmap.h" 16 17 static struct clk_regmap xtal_in = { 18 .data = &(struct clk_regmap_gate_data){ 19 .offset = SYS_OSCIN_CTRL, 20 .bit_idx = 0, 21 }, 22 .hw.init = &(struct clk_init_data) { 23 .name = "xtal_in", 24 .ops = &clk_regmap_gate_ro_ops, 25 .parent_data = &(const struct clk_parent_data) { 26 .fw_name = "xtal", 27 }, 28 .num_parents = 1, 29 }, 30 }; 31 32 static struct clk_regmap fixpll_in = { 33 .data = &(struct clk_regmap_gate_data){ 34 .offset = SYS_OSCIN_CTRL, 35 .bit_idx = 1, 36 }, 37 .hw.init = &(struct clk_init_data) { 38 .name = "fixpll_in", 39 .ops = &clk_regmap_gate_ro_ops, 40 .parent_data = &(const struct clk_parent_data) { 41 .fw_name = "xtal", 42 }, 43 .num_parents = 1, 44 }, 45 }; 46 47 static struct clk_regmap usb_phy_in = { 48 .data = &(struct clk_regmap_gate_data){ 49 .offset = SYS_OSCIN_CTRL, 50 .bit_idx = 2, 51 }, 52 .hw.init = &(struct clk_init_data) { 53 .name = "usb_phy_in", 54 .ops = &clk_regmap_gate_ops, 55 .parent_data = &(const struct clk_parent_data) { 56 .fw_name = "xtal", 57 }, 58 .num_parents = 1, 59 }, 60 }; 61 62 static struct clk_regmap usb_ctrl_in = { 63 .data = &(struct clk_regmap_gate_data){ 64 .offset = SYS_OSCIN_CTRL, 65 .bit_idx = 3, 66 }, 67 .hw.init = &(struct clk_init_data) { 68 .name = "usb_ctrl_in", 69 .ops = &clk_regmap_gate_ops, 70 .parent_data = &(const struct clk_parent_data) { 71 .fw_name = "xtal", 72 }, 73 .num_parents = 1, 74 }, 75 }; 76 77 static struct clk_regmap hifipll_in = { 78 .data = &(struct clk_regmap_gate_data){ 79 .offset = SYS_OSCIN_CTRL, 80 .bit_idx = 4, 81 }, 82 .hw.init = &(struct clk_init_data) { 83 .name = "hifipll_in", 84 .ops = &clk_regmap_gate_ops, 85 .parent_data = &(const struct clk_parent_data) { 86 .fw_name = "xtal", 87 }, 88 .num_parents = 1, 89 }, 90 }; 91 92 static struct clk_regmap syspll_in = { 93 .data = &(struct clk_regmap_gate_data){ 94 .offset = SYS_OSCIN_CTRL, 95 .bit_idx = 5, 96 }, 97 .hw.init = &(struct clk_init_data) { 98 .name = "syspll_in", 99 .ops = &clk_regmap_gate_ops, 100 .parent_data = &(const struct clk_parent_data) { 101 .fw_name = "xtal", 102 }, 103 .num_parents = 1, 104 }, 105 }; 106 107 static struct clk_regmap dds_in = { 108 .data = &(struct clk_regmap_gate_data){ 109 .offset = SYS_OSCIN_CTRL, 110 .bit_idx = 6, 111 }, 112 .hw.init = &(struct clk_init_data) { 113 .name = "dds_in", 114 .ops = &clk_regmap_gate_ops, 115 .parent_data = &(const struct clk_parent_data) { 116 .fw_name = "xtal", 117 }, 118 .num_parents = 1, 119 }, 120 }; 121 122 static struct clk_regmap rtc_32k_in = { 123 .data = &(struct clk_regmap_gate_data){ 124 .offset = RTC_BY_OSCIN_CTRL0, 125 .bit_idx = 31, 126 }, 127 .hw.init = &(struct clk_init_data) { 128 .name = "rtc_32k_in", 129 .ops = &clk_regmap_gate_ops, 130 .parent_data = &(const struct clk_parent_data) { 131 .fw_name = "xtal", 132 }, 133 .num_parents = 1, 134 }, 135 }; 136 137 static const struct meson_clk_dualdiv_param clk_32k_div_table[] = { 138 { 139 .dual = 1, 140 .n1 = 733, 141 .m1 = 8, 142 .n2 = 732, 143 .m2 = 11, 144 }, 145 {} 146 }; 147 148 static struct clk_regmap rtc_32k_div = { 149 .data = &(struct meson_clk_dualdiv_data){ 150 .n1 = { 151 .reg_off = RTC_BY_OSCIN_CTRL0, 152 .shift = 0, 153 .width = 12, 154 }, 155 .n2 = { 156 .reg_off = RTC_BY_OSCIN_CTRL0, 157 .shift = 12, 158 .width = 12, 159 }, 160 .m1 = { 161 .reg_off = RTC_BY_OSCIN_CTRL1, 162 .shift = 0, 163 .width = 12, 164 }, 165 .m2 = { 166 .reg_off = RTC_BY_OSCIN_CTRL1, 167 .shift = 12, 168 .width = 12, 169 }, 170 .dual = { 171 .reg_off = RTC_BY_OSCIN_CTRL0, 172 .shift = 28, 173 .width = 1, 174 }, 175 .table = clk_32k_div_table, 176 }, 177 .hw.init = &(struct clk_init_data){ 178 .name = "rtc_32k_div", 179 .ops = &meson_clk_dualdiv_ops, 180 .parent_hws = (const struct clk_hw *[]) { 181 &rtc_32k_in.hw 182 }, 183 .num_parents = 1, 184 }, 185 }; 186 187 static struct clk_regmap rtc_32k_xtal = { 188 .data = &(struct clk_regmap_gate_data){ 189 .offset = RTC_BY_OSCIN_CTRL1, 190 .bit_idx = 24, 191 }, 192 .hw.init = &(struct clk_init_data) { 193 .name = "rtc_32k_xtal", 194 .ops = &clk_regmap_gate_ops, 195 .parent_hws = (const struct clk_hw *[]) { 196 &rtc_32k_in.hw 197 }, 198 .num_parents = 1, 199 }, 200 }; 201 202 static struct clk_regmap rtc_32k_sel = { 203 .data = &(struct clk_regmap_mux_data) { 204 .offset = RTC_CTRL, 205 .mask = 0x3, 206 .shift = 0, 207 .flags = CLK_MUX_ROUND_CLOSEST, 208 }, 209 .hw.init = &(struct clk_init_data){ 210 .name = "rtc_32k_sel", 211 .ops = &clk_regmap_mux_ops, 212 .parent_hws = (const struct clk_hw *[]) { 213 &rtc_32k_xtal.hw, 214 &rtc_32k_div.hw, 215 }, 216 .num_parents = 2, 217 .flags = CLK_SET_RATE_PARENT, 218 }, 219 }; 220 221 static struct clk_regmap rtc = { 222 .data = &(struct clk_regmap_gate_data){ 223 .offset = RTC_BY_OSCIN_CTRL0, 224 .bit_idx = 30, 225 }, 226 .hw.init = &(struct clk_init_data){ 227 .name = "rtc", 228 .ops = &clk_regmap_gate_ops, 229 .parent_hws = (const struct clk_hw *[]) { 230 &rtc_32k_sel.hw 231 }, 232 .num_parents = 1, 233 .flags = CLK_SET_RATE_PARENT, 234 }, 235 }; 236 237 static u32 mux_table_sys[] = { 0, 1, 2, 3, 7 }; 238 static const struct clk_parent_data sys_parents[] = { 239 { .fw_name = "xtal" }, 240 { .fw_name = "fclk_div2" }, 241 { .fw_name = "fclk_div3" }, 242 { .fw_name = "fclk_div5" }, 243 { .hw = &rtc.hw }, 244 }; 245 246 static struct clk_regmap sys_b_sel = { 247 .data = &(struct clk_regmap_mux_data){ 248 .offset = SYS_CLK_CTRL0, 249 .mask = 0x7, 250 .shift = 26, 251 .table = mux_table_sys, 252 }, 253 .hw.init = &(struct clk_init_data){ 254 .name = "sys_b_sel", 255 .ops = &clk_regmap_mux_ro_ops, 256 .parent_data = sys_parents, 257 .num_parents = ARRAY_SIZE(sys_parents), 258 }, 259 }; 260 261 static struct clk_regmap sys_b_div = { 262 .data = &(struct clk_regmap_div_data){ 263 .offset = SYS_CLK_CTRL0, 264 .shift = 16, 265 .width = 10, 266 }, 267 .hw.init = &(struct clk_init_data){ 268 .name = "sys_b_div", 269 .ops = &clk_regmap_divider_ro_ops, 270 .parent_hws = (const struct clk_hw *[]) { 271 &sys_b_sel.hw 272 }, 273 .num_parents = 1, 274 .flags = CLK_SET_RATE_PARENT, 275 }, 276 }; 277 278 static struct clk_regmap sys_b = { 279 .data = &(struct clk_regmap_gate_data){ 280 .offset = SYS_CLK_CTRL0, 281 .bit_idx = 29, 282 }, 283 .hw.init = &(struct clk_init_data) { 284 .name = "sys_b", 285 .ops = &clk_regmap_gate_ro_ops, 286 .parent_hws = (const struct clk_hw *[]) { 287 &sys_b_div.hw 288 }, 289 .num_parents = 1, 290 .flags = CLK_SET_RATE_PARENT, 291 }, 292 }; 293 294 static struct clk_regmap sys_a_sel = { 295 .data = &(struct clk_regmap_mux_data){ 296 .offset = SYS_CLK_CTRL0, 297 .mask = 0x7, 298 .shift = 10, 299 .table = mux_table_sys, 300 }, 301 .hw.init = &(struct clk_init_data){ 302 .name = "sys_a_sel", 303 .ops = &clk_regmap_mux_ro_ops, 304 .parent_data = sys_parents, 305 .num_parents = ARRAY_SIZE(sys_parents), 306 }, 307 }; 308 309 static struct clk_regmap sys_a_div = { 310 .data = &(struct clk_regmap_div_data){ 311 .offset = SYS_CLK_CTRL0, 312 .shift = 0, 313 .width = 10, 314 }, 315 .hw.init = &(struct clk_init_data){ 316 .name = "sys_a_div", 317 .ops = &clk_regmap_divider_ro_ops, 318 .parent_hws = (const struct clk_hw *[]) { 319 &sys_a_sel.hw 320 }, 321 .num_parents = 1, 322 .flags = CLK_SET_RATE_PARENT, 323 }, 324 }; 325 326 static struct clk_regmap sys_a = { 327 .data = &(struct clk_regmap_gate_data){ 328 .offset = SYS_CLK_CTRL0, 329 .bit_idx = 13, 330 }, 331 .hw.init = &(struct clk_init_data) { 332 .name = "sys_a", 333 .ops = &clk_regmap_gate_ro_ops, 334 .parent_hws = (const struct clk_hw *[]) { 335 &sys_a_div.hw 336 }, 337 .num_parents = 1, 338 .flags = CLK_SET_RATE_PARENT, 339 }, 340 }; 341 342 static struct clk_regmap sys = { 343 .data = &(struct clk_regmap_mux_data){ 344 .offset = SYS_CLK_CTRL0, 345 .mask = 0x1, 346 .shift = 31, 347 }, 348 .hw.init = &(struct clk_init_data){ 349 .name = "sys", 350 .ops = &clk_regmap_mux_ro_ops, 351 .parent_hws = (const struct clk_hw *[]) { 352 &sys_a.hw, 353 &sys_b.hw, 354 }, 355 .num_parents = 2, 356 /* 357 * This clock is used by APB bus which is set in boot ROM code 358 * and is required by the platform to operate correctly. 359 * Until the following condition are met, we need this clock to 360 * be marked as critical: 361 * a) Mark the clock used by a firmware resource, if possible 362 * b) CCF has a clock hand-off mechanism to make the sure the 363 * clock stays on until the proper driver comes along 364 */ 365 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 366 }, 367 }; 368 369 static u32 mux_table_dsp_ab[] = { 0, 1, 2, 3, 4, 7 }; 370 static const struct clk_parent_data dsp_ab_parent_data[] = { 371 { .fw_name = "xtal", }, 372 { .fw_name = "fclk_div2", }, 373 { .fw_name = "fclk_div3", }, 374 { .fw_name = "fclk_div5", }, 375 { .fw_name = "hifi_pll", }, 376 { .hw = &rtc.hw }, 377 }; 378 379 static struct clk_regmap dspa_a_sel = { 380 .data = &(struct clk_regmap_mux_data){ 381 .offset = DSPA_CLK_CTRL0, 382 .mask = 0x7, 383 .shift = 10, 384 .table = mux_table_dsp_ab, 385 }, 386 .hw.init = &(struct clk_init_data){ 387 .name = "dspa_a_sel", 388 .ops = &clk_regmap_mux_ops, 389 .parent_data = dsp_ab_parent_data, 390 .num_parents = ARRAY_SIZE(dsp_ab_parent_data), 391 }, 392 }; 393 394 static struct clk_regmap dspa_a_div = { 395 .data = &(struct clk_regmap_div_data){ 396 .offset = DSPA_CLK_CTRL0, 397 .shift = 0, 398 .width = 10, 399 }, 400 .hw.init = &(struct clk_init_data){ 401 .name = "dspa_a_div", 402 .ops = &clk_regmap_divider_ops, 403 .parent_hws = (const struct clk_hw *[]) { 404 &dspa_a_sel.hw 405 }, 406 .num_parents = 1, 407 .flags = CLK_SET_RATE_PARENT, 408 }, 409 }; 410 411 static struct clk_regmap dspa_a = { 412 .data = &(struct clk_regmap_gate_data){ 413 .offset = DSPA_CLK_CTRL0, 414 .bit_idx = 13, 415 }, 416 .hw.init = &(struct clk_init_data) { 417 .name = "dspa_a", 418 .ops = &clk_regmap_gate_ops, 419 .parent_hws = (const struct clk_hw *[]) { 420 &dspa_a_div.hw 421 }, 422 .num_parents = 1, 423 .flags = CLK_SET_RATE_PARENT, 424 }, 425 }; 426 427 static struct clk_regmap dspa_b_sel = { 428 .data = &(struct clk_regmap_mux_data){ 429 .offset = DSPA_CLK_CTRL0, 430 .mask = 0x7, 431 .shift = 26, 432 .table = mux_table_dsp_ab, 433 }, 434 .hw.init = &(struct clk_init_data){ 435 .name = "dspa_b_sel", 436 .ops = &clk_regmap_mux_ops, 437 .parent_data = dsp_ab_parent_data, 438 .num_parents = ARRAY_SIZE(dsp_ab_parent_data), 439 }, 440 }; 441 442 static struct clk_regmap dspa_b_div = { 443 .data = &(struct clk_regmap_div_data){ 444 .offset = DSPA_CLK_CTRL0, 445 .shift = 16, 446 .width = 10, 447 }, 448 .hw.init = &(struct clk_init_data){ 449 .name = "dspa_b_div", 450 .ops = &clk_regmap_divider_ops, 451 .parent_hws = (const struct clk_hw *[]) { 452 &dspa_b_sel.hw 453 }, 454 .num_parents = 1, 455 .flags = CLK_SET_RATE_PARENT, 456 }, 457 }; 458 459 static struct clk_regmap dspa_b = { 460 .data = &(struct clk_regmap_gate_data){ 461 .offset = DSPA_CLK_CTRL0, 462 .bit_idx = 29, 463 }, 464 .hw.init = &(struct clk_init_data) { 465 .name = "dspa_b", 466 .ops = &clk_regmap_gate_ops, 467 .parent_hws = (const struct clk_hw *[]) { 468 &dspa_b_div.hw 469 }, 470 .num_parents = 1, 471 .flags = CLK_SET_RATE_PARENT, 472 }, 473 }; 474 475 static struct clk_regmap dspa_sel = { 476 .data = &(struct clk_regmap_mux_data){ 477 .offset = DSPA_CLK_CTRL0, 478 .mask = 0x1, 479 .shift = 15, 480 }, 481 .hw.init = &(struct clk_init_data){ 482 .name = "dspa_sel", 483 .ops = &clk_regmap_mux_ops, 484 .parent_hws = (const struct clk_hw *[]) { 485 &dspa_a.hw, 486 &dspa_b.hw, 487 }, 488 .num_parents = 2, 489 .flags = CLK_SET_RATE_PARENT, 490 }, 491 }; 492 493 static struct clk_regmap dspa_en = { 494 .data = &(struct clk_regmap_gate_data){ 495 .offset = DSPA_CLK_EN, 496 .bit_idx = 1, 497 }, 498 .hw.init = &(struct clk_init_data) { 499 .name = "dspa_en", 500 .ops = &clk_regmap_gate_ops, 501 .parent_hws = (const struct clk_hw *[]) { 502 &dspa_sel.hw 503 }, 504 .num_parents = 1, 505 .flags = CLK_SET_RATE_PARENT, 506 }, 507 }; 508 509 static struct clk_regmap dspa_en_nic = { 510 .data = &(struct clk_regmap_gate_data){ 511 .offset = DSPA_CLK_EN, 512 .bit_idx = 0, 513 }, 514 .hw.init = &(struct clk_init_data) { 515 .name = "dspa_en_nic", 516 .ops = &clk_regmap_gate_ops, 517 .parent_hws = (const struct clk_hw *[]) { 518 &dspa_sel.hw 519 }, 520 .num_parents = 1, 521 .flags = CLK_SET_RATE_PARENT, 522 }, 523 }; 524 525 static struct clk_regmap dspb_a_sel = { 526 .data = &(struct clk_regmap_mux_data){ 527 .offset = DSPB_CLK_CTRL0, 528 .mask = 0x7, 529 .shift = 10, 530 .table = mux_table_dsp_ab, 531 }, 532 .hw.init = &(struct clk_init_data){ 533 .name = "dspb_a_sel", 534 .ops = &clk_regmap_mux_ops, 535 .parent_data = dsp_ab_parent_data, 536 .num_parents = ARRAY_SIZE(dsp_ab_parent_data), 537 }, 538 }; 539 540 static struct clk_regmap dspb_a_div = { 541 .data = &(struct clk_regmap_div_data){ 542 .offset = DSPB_CLK_CTRL0, 543 .shift = 0, 544 .width = 10, 545 }, 546 .hw.init = &(struct clk_init_data){ 547 .name = "dspb_a_div", 548 .ops = &clk_regmap_divider_ops, 549 .parent_hws = (const struct clk_hw *[]) { 550 &dspb_a_sel.hw 551 }, 552 .num_parents = 1, 553 .flags = CLK_SET_RATE_PARENT, 554 }, 555 }; 556 557 static struct clk_regmap dspb_a = { 558 .data = &(struct clk_regmap_gate_data){ 559 .offset = DSPB_CLK_CTRL0, 560 .bit_idx = 13, 561 }, 562 .hw.init = &(struct clk_init_data) { 563 .name = "dspb_a", 564 .ops = &clk_regmap_gate_ops, 565 .parent_hws = (const struct clk_hw *[]) { 566 &dspb_a_div.hw 567 }, 568 .num_parents = 1, 569 .flags = CLK_SET_RATE_PARENT, 570 }, 571 }; 572 573 static struct clk_regmap dspb_b_sel = { 574 .data = &(struct clk_regmap_mux_data){ 575 .offset = DSPB_CLK_CTRL0, 576 .mask = 0x7, 577 .shift = 26, 578 .table = mux_table_dsp_ab, 579 }, 580 .hw.init = &(struct clk_init_data){ 581 .name = "dspb_b_sel", 582 .ops = &clk_regmap_mux_ops, 583 .parent_data = dsp_ab_parent_data, 584 .num_parents = ARRAY_SIZE(dsp_ab_parent_data), 585 }, 586 }; 587 588 static struct clk_regmap dspb_b_div = { 589 .data = &(struct clk_regmap_div_data){ 590 .offset = DSPB_CLK_CTRL0, 591 .shift = 16, 592 .width = 10, 593 }, 594 .hw.init = &(struct clk_init_data){ 595 .name = "dspb_b_div", 596 .ops = &clk_regmap_divider_ops, 597 .parent_hws = (const struct clk_hw *[]) { 598 &dspb_b_sel.hw 599 }, 600 .num_parents = 1, 601 .flags = CLK_SET_RATE_PARENT, 602 }, 603 }; 604 605 static struct clk_regmap dspb_b = { 606 .data = &(struct clk_regmap_gate_data){ 607 .offset = DSPB_CLK_CTRL0, 608 .bit_idx = 29, 609 }, 610 .hw.init = &(struct clk_init_data) { 611 .name = "dspb_b", 612 .ops = &clk_regmap_gate_ops, 613 .parent_hws = (const struct clk_hw *[]) { 614 &dspb_b_div.hw 615 }, 616 .num_parents = 1, 617 .flags = CLK_SET_RATE_PARENT, 618 }, 619 }; 620 621 static struct clk_regmap dspb_sel = { 622 .data = &(struct clk_regmap_mux_data){ 623 .offset = DSPB_CLK_CTRL0, 624 .mask = 0x1, 625 .shift = 15, 626 }, 627 .hw.init = &(struct clk_init_data){ 628 .name = "dspb_sel", 629 .ops = &clk_regmap_mux_ops, 630 .parent_hws = (const struct clk_hw *[]) { 631 &dspb_a.hw, 632 &dspb_b.hw, 633 }, 634 .num_parents = 2, 635 .flags = CLK_SET_RATE_PARENT, 636 }, 637 }; 638 639 static struct clk_regmap dspb_en = { 640 .data = &(struct clk_regmap_gate_data){ 641 .offset = DSPB_CLK_EN, 642 .bit_idx = 1, 643 }, 644 .hw.init = &(struct clk_init_data) { 645 .name = "dspb_en", 646 .ops = &clk_regmap_gate_ops, 647 .parent_hws = (const struct clk_hw *[]) { 648 &dspb_sel.hw 649 }, 650 .num_parents = 1, 651 .flags = CLK_SET_RATE_PARENT, 652 }, 653 }; 654 655 static struct clk_regmap dspb_en_nic = { 656 .data = &(struct clk_regmap_gate_data){ 657 .offset = DSPB_CLK_EN, 658 .bit_idx = 0, 659 }, 660 .hw.init = &(struct clk_init_data) { 661 .name = "dspb_en_nic", 662 .ops = &clk_regmap_gate_ops, 663 .parent_hws = (const struct clk_hw *[]) { 664 &dspb_sel.hw 665 }, 666 .num_parents = 1, 667 .flags = CLK_SET_RATE_PARENT, 668 }, 669 }; 670 671 static struct clk_regmap clk_24m = { 672 .data = &(struct clk_regmap_gate_data){ 673 .offset = CLK12_24_CTRL, 674 .bit_idx = 11, 675 }, 676 .hw.init = &(struct clk_init_data) { 677 .name = "24m", 678 .ops = &clk_regmap_gate_ops, 679 .parent_data = &(const struct clk_parent_data) { 680 .fw_name = "xtal", 681 }, 682 .num_parents = 1, 683 }, 684 }; 685 686 static struct clk_fixed_factor clk_24m_div2 = { 687 .mult = 1, 688 .div = 2, 689 .hw.init = &(struct clk_init_data){ 690 .name = "24m_div2", 691 .ops = &clk_fixed_factor_ops, 692 .parent_hws = (const struct clk_hw *[]) { 693 &clk_24m.hw 694 }, 695 .num_parents = 1, 696 }, 697 }; 698 699 static struct clk_regmap clk_12m = { 700 .data = &(struct clk_regmap_gate_data){ 701 .offset = CLK12_24_CTRL, 702 .bit_idx = 10, 703 }, 704 .hw.init = &(struct clk_init_data) { 705 .name = "12m", 706 .ops = &clk_regmap_gate_ops, 707 .parent_hws = (const struct clk_hw *[]) { 708 &clk_24m_div2.hw 709 }, 710 .num_parents = 1, 711 }, 712 }; 713 714 static struct clk_regmap fclk_div2_divn_pre = { 715 .data = &(struct clk_regmap_div_data){ 716 .offset = CLK12_24_CTRL, 717 .shift = 0, 718 .width = 8, 719 }, 720 .hw.init = &(struct clk_init_data){ 721 .name = "fclk_div2_divn_pre", 722 .ops = &clk_regmap_divider_ops, 723 .parent_data = &(const struct clk_parent_data) { 724 .fw_name = "fclk_div2", 725 }, 726 .num_parents = 1, 727 }, 728 }; 729 730 static struct clk_regmap fclk_div2_divn = { 731 .data = &(struct clk_regmap_gate_data){ 732 .offset = CLK12_24_CTRL, 733 .bit_idx = 12, 734 }, 735 .hw.init = &(struct clk_init_data){ 736 .name = "fclk_div2_divn", 737 .ops = &clk_regmap_gate_ops, 738 .parent_hws = (const struct clk_hw *[]) { 739 &fclk_div2_divn_pre.hw 740 }, 741 .num_parents = 1, 742 .flags = CLK_SET_RATE_PARENT, 743 }, 744 }; 745 746 /* 747 * the index 2 is sys_pll_div16, it will be implemented in the CPU clock driver, 748 * the index 4 is the clock measurement source, it's not supported yet 749 */ 750 static u32 gen_table[] = { 0, 1, 3, 5, 6, 7, 8 }; 751 static const struct clk_parent_data gen_parent_data[] = { 752 { .fw_name = "xtal", }, 753 { .hw = &rtc.hw }, 754 { .fw_name = "hifi_pll", }, 755 { .fw_name = "fclk_div2", }, 756 { .fw_name = "fclk_div3", }, 757 { .fw_name = "fclk_div5", }, 758 { .fw_name = "fclk_div7", }, 759 }; 760 761 static struct clk_regmap gen_sel = { 762 .data = &(struct clk_regmap_mux_data){ 763 .offset = GEN_CLK_CTRL, 764 .mask = 0xf, 765 .shift = 12, 766 .table = gen_table, 767 }, 768 .hw.init = &(struct clk_init_data){ 769 .name = "gen_sel", 770 .ops = &clk_regmap_mux_ops, 771 .parent_data = gen_parent_data, 772 .num_parents = ARRAY_SIZE(gen_parent_data), 773 /* 774 * The GEN clock can be connected to an external pad, so it 775 * may be set up directly from the device tree. Additionally, 776 * the GEN clock can be inherited from a more accurate RTC 777 * clock, so in certain situations, it may be necessary 778 * to freeze its parent. 779 */ 780 .flags = CLK_SET_RATE_NO_REPARENT, 781 }, 782 }; 783 784 static struct clk_regmap gen_div = { 785 .data = &(struct clk_regmap_div_data){ 786 .offset = GEN_CLK_CTRL, 787 .shift = 0, 788 .width = 11, 789 }, 790 .hw.init = &(struct clk_init_data){ 791 .name = "gen_div", 792 .ops = &clk_regmap_divider_ops, 793 .parent_hws = (const struct clk_hw *[]) { 794 &gen_sel.hw 795 }, 796 .num_parents = 1, 797 .flags = CLK_SET_RATE_PARENT, 798 }, 799 }; 800 801 static struct clk_regmap gen = { 802 .data = &(struct clk_regmap_gate_data){ 803 .offset = GEN_CLK_CTRL, 804 .bit_idx = 11, 805 }, 806 .hw.init = &(struct clk_init_data) { 807 .name = "gen", 808 .ops = &clk_regmap_gate_ops, 809 .parent_hws = (const struct clk_hw *[]) { 810 &gen_div.hw 811 }, 812 .num_parents = 1, 813 .flags = CLK_SET_RATE_PARENT, 814 }, 815 }; 816 817 static struct clk_regmap saradc_sel = { 818 .data = &(struct clk_regmap_mux_data){ 819 .offset = SAR_ADC_CLK_CTRL, 820 .mask = 0x1, 821 .shift = 9, 822 }, 823 .hw.init = &(struct clk_init_data){ 824 .name = "saradc_sel", 825 .ops = &clk_regmap_mux_ops, 826 .parent_data = (const struct clk_parent_data []) { 827 { .fw_name = "xtal", }, 828 { .hw = &sys.hw, }, 829 }, 830 .num_parents = 2, 831 }, 832 }; 833 834 static struct clk_regmap saradc_div = { 835 .data = &(struct clk_regmap_div_data){ 836 .offset = SAR_ADC_CLK_CTRL, 837 .shift = 0, 838 .width = 8, 839 }, 840 .hw.init = &(struct clk_init_data){ 841 .name = "saradc_div", 842 .ops = &clk_regmap_divider_ops, 843 .parent_hws = (const struct clk_hw *[]) { 844 &saradc_sel.hw 845 }, 846 .num_parents = 1, 847 .flags = CLK_SET_RATE_PARENT, 848 }, 849 }; 850 851 static struct clk_regmap saradc = { 852 .data = &(struct clk_regmap_gate_data){ 853 .offset = SAR_ADC_CLK_CTRL, 854 .bit_idx = 8, 855 }, 856 .hw.init = &(struct clk_init_data) { 857 .name = "saradc", 858 .ops = &clk_regmap_gate_ops, 859 .parent_hws = (const struct clk_hw *[]) { 860 &saradc_div.hw 861 }, 862 .num_parents = 1, 863 .flags = CLK_SET_RATE_PARENT, 864 }, 865 }; 866 867 static const struct clk_parent_data pwm_abcd_parents[] = { 868 { .fw_name = "xtal", }, 869 { .hw = &sys.hw }, 870 { .hw = &rtc.hw }, 871 }; 872 873 static struct clk_regmap pwm_a_sel = { 874 .data = &(struct clk_regmap_mux_data){ 875 .offset = PWM_CLK_AB_CTRL, 876 .mask = 0x1, 877 .shift = 9, 878 }, 879 .hw.init = &(struct clk_init_data){ 880 .name = "pwm_a_sel", 881 .ops = &clk_regmap_mux_ops, 882 .parent_data = pwm_abcd_parents, 883 .num_parents = ARRAY_SIZE(pwm_abcd_parents), 884 }, 885 }; 886 887 static struct clk_regmap pwm_a_div = { 888 .data = &(struct clk_regmap_div_data){ 889 .offset = PWM_CLK_AB_CTRL, 890 .shift = 0, 891 .width = 8, 892 }, 893 .hw.init = &(struct clk_init_data){ 894 .name = "pwm_a_div", 895 .ops = &clk_regmap_divider_ops, 896 .parent_hws = (const struct clk_hw *[]) { 897 &pwm_a_sel.hw 898 }, 899 .num_parents = 1, 900 .flags = CLK_SET_RATE_PARENT, 901 }, 902 }; 903 904 static struct clk_regmap pwm_a = { 905 .data = &(struct clk_regmap_gate_data){ 906 .offset = PWM_CLK_AB_CTRL, 907 .bit_idx = 8, 908 }, 909 .hw.init = &(struct clk_init_data) { 910 .name = "pwm_a", 911 .ops = &clk_regmap_gate_ops, 912 .parent_hws = (const struct clk_hw *[]) { 913 &pwm_a_div.hw 914 }, 915 .num_parents = 1, 916 .flags = CLK_SET_RATE_PARENT, 917 }, 918 }; 919 920 static struct clk_regmap pwm_b_sel = { 921 .data = &(struct clk_regmap_mux_data){ 922 .offset = PWM_CLK_AB_CTRL, 923 .mask = 0x1, 924 .shift = 25, 925 }, 926 .hw.init = &(struct clk_init_data){ 927 .name = "pwm_b_sel", 928 .ops = &clk_regmap_mux_ops, 929 .parent_data = pwm_abcd_parents, 930 .num_parents = ARRAY_SIZE(pwm_abcd_parents), 931 }, 932 }; 933 934 static struct clk_regmap pwm_b_div = { 935 .data = &(struct clk_regmap_div_data){ 936 .offset = PWM_CLK_AB_CTRL, 937 .shift = 16, 938 .width = 8, 939 }, 940 .hw.init = &(struct clk_init_data){ 941 .name = "pwm_b_div", 942 .ops = &clk_regmap_divider_ops, 943 .parent_hws = (const struct clk_hw *[]) { 944 &pwm_b_sel.hw 945 }, 946 .num_parents = 1, 947 .flags = CLK_SET_RATE_PARENT, 948 }, 949 }; 950 951 static struct clk_regmap pwm_b = { 952 .data = &(struct clk_regmap_gate_data){ 953 .offset = PWM_CLK_AB_CTRL, 954 .bit_idx = 24, 955 }, 956 .hw.init = &(struct clk_init_data) { 957 .name = "pwm_b", 958 .ops = &clk_regmap_gate_ops, 959 .parent_hws = (const struct clk_hw *[]) { 960 &pwm_b_div.hw 961 }, 962 .num_parents = 1, 963 .flags = CLK_SET_RATE_PARENT, 964 }, 965 }; 966 967 static struct clk_regmap pwm_c_sel = { 968 .data = &(struct clk_regmap_mux_data){ 969 .offset = PWM_CLK_CD_CTRL, 970 .mask = 0x1, 971 .shift = 9, 972 }, 973 .hw.init = &(struct clk_init_data){ 974 .name = "pwm_c_sel", 975 .ops = &clk_regmap_mux_ops, 976 .parent_data = pwm_abcd_parents, 977 .num_parents = ARRAY_SIZE(pwm_abcd_parents), 978 }, 979 }; 980 981 static struct clk_regmap pwm_c_div = { 982 .data = &(struct clk_regmap_div_data){ 983 .offset = PWM_CLK_CD_CTRL, 984 .shift = 0, 985 .width = 8, 986 }, 987 .hw.init = &(struct clk_init_data){ 988 .name = "pwm_c_div", 989 .ops = &clk_regmap_divider_ops, 990 .parent_hws = (const struct clk_hw *[]) { 991 &pwm_c_sel.hw 992 }, 993 .num_parents = 1, 994 .flags = CLK_SET_RATE_PARENT, 995 }, 996 }; 997 998 static struct clk_regmap pwm_c = { 999 .data = &(struct clk_regmap_gate_data){ 1000 .offset = PWM_CLK_CD_CTRL, 1001 .bit_idx = 8, 1002 }, 1003 .hw.init = &(struct clk_init_data) { 1004 .name = "pwm_c", 1005 .ops = &clk_regmap_gate_ops, 1006 .parent_hws = (const struct clk_hw *[]) { 1007 &pwm_c_div.hw 1008 }, 1009 .num_parents = 1, 1010 .flags = CLK_SET_RATE_PARENT, 1011 }, 1012 }; 1013 1014 static struct clk_regmap pwm_d_sel = { 1015 .data = &(struct clk_regmap_mux_data){ 1016 .offset = PWM_CLK_CD_CTRL, 1017 .mask = 0x1, 1018 .shift = 25, 1019 }, 1020 .hw.init = &(struct clk_init_data){ 1021 .name = "pwm_d_sel", 1022 .ops = &clk_regmap_mux_ops, 1023 .parent_data = pwm_abcd_parents, 1024 .num_parents = ARRAY_SIZE(pwm_abcd_parents), 1025 }, 1026 }; 1027 1028 static struct clk_regmap pwm_d_div = { 1029 .data = &(struct clk_regmap_div_data){ 1030 .offset = PWM_CLK_CD_CTRL, 1031 .shift = 16, 1032 .width = 8, 1033 }, 1034 .hw.init = &(struct clk_init_data){ 1035 .name = "pwm_d_div", 1036 .ops = &clk_regmap_divider_ops, 1037 .parent_hws = (const struct clk_hw *[]) { 1038 &pwm_d_sel.hw 1039 }, 1040 .num_parents = 1, 1041 .flags = CLK_SET_RATE_PARENT, 1042 }, 1043 }; 1044 1045 static struct clk_regmap pwm_d = { 1046 .data = &(struct clk_regmap_gate_data){ 1047 .offset = PWM_CLK_CD_CTRL, 1048 .bit_idx = 24, 1049 }, 1050 .hw.init = &(struct clk_init_data) { 1051 .name = "pwm_d", 1052 .ops = &clk_regmap_gate_ops, 1053 .parent_hws = (const struct clk_hw *[]) { 1054 &pwm_d_div.hw 1055 }, 1056 .num_parents = 1, 1057 .flags = CLK_SET_RATE_PARENT, 1058 }, 1059 }; 1060 1061 static const struct clk_parent_data pwm_ef_parents[] = { 1062 { .fw_name = "xtal", }, 1063 { .hw = &sys.hw }, 1064 { .fw_name = "fclk_div5", }, 1065 { .hw = &rtc.hw }, 1066 }; 1067 1068 static struct clk_regmap pwm_e_sel = { 1069 .data = &(struct clk_regmap_mux_data){ 1070 .offset = PWM_CLK_EF_CTRL, 1071 .mask = 0x3, 1072 .shift = 9, 1073 }, 1074 .hw.init = &(struct clk_init_data){ 1075 .name = "pwm_e_sel", 1076 .ops = &clk_regmap_mux_ops, 1077 .parent_data = pwm_ef_parents, 1078 .num_parents = ARRAY_SIZE(pwm_ef_parents), 1079 }, 1080 }; 1081 1082 static struct clk_regmap pwm_e_div = { 1083 .data = &(struct clk_regmap_div_data){ 1084 .offset = PWM_CLK_EF_CTRL, 1085 .shift = 0, 1086 .width = 8, 1087 }, 1088 .hw.init = &(struct clk_init_data){ 1089 .name = "pwm_e_div", 1090 .ops = &clk_regmap_divider_ops, 1091 .parent_hws = (const struct clk_hw *[]) { 1092 &pwm_e_sel.hw 1093 }, 1094 .num_parents = 1, 1095 .flags = CLK_SET_RATE_PARENT, 1096 }, 1097 }; 1098 1099 static struct clk_regmap pwm_e = { 1100 .data = &(struct clk_regmap_gate_data){ 1101 .offset = PWM_CLK_EF_CTRL, 1102 .bit_idx = 8, 1103 }, 1104 .hw.init = &(struct clk_init_data) { 1105 .name = "pwm_e", 1106 .ops = &clk_regmap_gate_ops, 1107 .parent_hws = (const struct clk_hw *[]) { 1108 &pwm_e_div.hw 1109 }, 1110 .num_parents = 1, 1111 .flags = CLK_SET_RATE_PARENT, 1112 }, 1113 }; 1114 1115 static struct clk_regmap pwm_f_sel = { 1116 .data = &(struct clk_regmap_mux_data){ 1117 .offset = PWM_CLK_EF_CTRL, 1118 .mask = 0x3, 1119 .shift = 25, 1120 }, 1121 .hw.init = &(struct clk_init_data){ 1122 .name = "pwm_f_sel", 1123 .ops = &clk_regmap_mux_ops, 1124 .parent_data = pwm_ef_parents, 1125 .num_parents = ARRAY_SIZE(pwm_ef_parents), 1126 }, 1127 }; 1128 1129 static struct clk_regmap pwm_f_div = { 1130 .data = &(struct clk_regmap_div_data){ 1131 .offset = PWM_CLK_EF_CTRL, 1132 .shift = 16, 1133 .width = 8, 1134 }, 1135 .hw.init = &(struct clk_init_data){ 1136 .name = "pwm_f_div", 1137 .ops = &clk_regmap_divider_ops, 1138 .parent_hws = (const struct clk_hw *[]) { 1139 &pwm_f_sel.hw 1140 }, 1141 .num_parents = 1, 1142 .flags = CLK_SET_RATE_PARENT, 1143 }, 1144 }; 1145 1146 static struct clk_regmap pwm_f = { 1147 .data = &(struct clk_regmap_gate_data){ 1148 .offset = PWM_CLK_EF_CTRL, 1149 .bit_idx = 24, 1150 }, 1151 .hw.init = &(struct clk_init_data) { 1152 .name = "pwm_f", 1153 .ops = &clk_regmap_gate_ops, 1154 .parent_hws = (const struct clk_hw *[]) { 1155 &pwm_f_div.hw 1156 }, 1157 .num_parents = 1, 1158 .flags = CLK_SET_RATE_PARENT, 1159 }, 1160 }; 1161 1162 /* 1163 * spicc clk 1164 * fdiv2 |\ |\ _____ 1165 * ---------| |---DIV--| | | | spicc out 1166 * ---------| | | |-----|GATE |--------- 1167 * ..... |/ | / |_____| 1168 * --------------------|/ 1169 * 24M 1170 */ 1171 static const struct clk_parent_data spicc_spifc_parents[] = { 1172 { .fw_name = "fclk_div2"}, 1173 { .fw_name = "fclk_div3"}, 1174 { .fw_name = "fclk_div5"}, 1175 { .fw_name = "hifi_pll" }, 1176 }; 1177 1178 static struct clk_regmap spicc_sel = { 1179 .data = &(struct clk_regmap_mux_data){ 1180 .offset = SPICC_CLK_CTRL, 1181 .mask = 0x3, 1182 .shift = 9, 1183 }, 1184 .hw.init = &(struct clk_init_data){ 1185 .name = "spicc_sel", 1186 .ops = &clk_regmap_mux_ops, 1187 .parent_data = spicc_spifc_parents, 1188 .num_parents = ARRAY_SIZE(spicc_spifc_parents), 1189 }, 1190 }; 1191 1192 static struct clk_regmap spicc_div = { 1193 .data = &(struct clk_regmap_div_data){ 1194 .offset = SPICC_CLK_CTRL, 1195 .shift = 0, 1196 .width = 8, 1197 }, 1198 .hw.init = &(struct clk_init_data){ 1199 .name = "spicc_div", 1200 .ops = &clk_regmap_divider_ops, 1201 .parent_hws = (const struct clk_hw *[]) { 1202 &spicc_sel.hw 1203 }, 1204 .num_parents = 1, 1205 .flags = CLK_SET_RATE_PARENT, 1206 }, 1207 }; 1208 1209 static struct clk_regmap spicc_sel2 = { 1210 .data = &(struct clk_regmap_mux_data){ 1211 .offset = SPICC_CLK_CTRL, 1212 .mask = 0x1, 1213 .shift = 15, 1214 }, 1215 .hw.init = &(struct clk_init_data){ 1216 .name = "spicc_sel2", 1217 .ops = &clk_regmap_mux_ops, 1218 .parent_data = (const struct clk_parent_data []) { 1219 { .hw = &spicc_div.hw }, 1220 { .fw_name = "xtal", }, 1221 }, 1222 .num_parents = 2, 1223 .flags = CLK_SET_RATE_PARENT, 1224 }, 1225 }; 1226 1227 static struct clk_regmap spicc = { 1228 .data = &(struct clk_regmap_gate_data){ 1229 .offset = SPICC_CLK_CTRL, 1230 .bit_idx = 8, 1231 }, 1232 .hw.init = &(struct clk_init_data) { 1233 .name = "spicc", 1234 .ops = &clk_regmap_gate_ops, 1235 .parent_hws = (const struct clk_hw *[]) { 1236 &spicc_sel2.hw 1237 }, 1238 .num_parents = 1, 1239 .flags = CLK_SET_RATE_PARENT, 1240 }, 1241 }; 1242 1243 static struct clk_regmap ts_div = { 1244 .data = &(struct clk_regmap_div_data){ 1245 .offset = TS_CLK_CTRL, 1246 .shift = 0, 1247 .width = 8, 1248 }, 1249 .hw.init = &(struct clk_init_data){ 1250 .name = "ts_div", 1251 .ops = &clk_regmap_divider_ops, 1252 .parent_data = &(const struct clk_parent_data) { 1253 .fw_name = "xtal", 1254 }, 1255 .num_parents = 1, 1256 }, 1257 }; 1258 1259 static struct clk_regmap ts = { 1260 .data = &(struct clk_regmap_gate_data){ 1261 .offset = TS_CLK_CTRL, 1262 .bit_idx = 8, 1263 }, 1264 .hw.init = &(struct clk_init_data) { 1265 .name = "ts", 1266 .ops = &clk_regmap_gate_ops, 1267 .parent_hws = (const struct clk_hw *[]) { 1268 &ts_div.hw 1269 }, 1270 .num_parents = 1, 1271 .flags = CLK_SET_RATE_PARENT, 1272 }, 1273 }; 1274 1275 static struct clk_regmap spifc_sel = { 1276 .data = &(struct clk_regmap_mux_data){ 1277 .offset = SPIFC_CLK_CTRL, 1278 .mask = 0x3, 1279 .shift = 9, 1280 }, 1281 .hw.init = &(struct clk_init_data){ 1282 .name = "spifc_sel", 1283 .ops = &clk_regmap_mux_ops, 1284 .parent_data = spicc_spifc_parents, 1285 .num_parents = ARRAY_SIZE(spicc_spifc_parents), 1286 }, 1287 }; 1288 1289 static struct clk_regmap spifc_div = { 1290 .data = &(struct clk_regmap_div_data){ 1291 .offset = SPIFC_CLK_CTRL, 1292 .shift = 0, 1293 .width = 8, 1294 }, 1295 .hw.init = &(struct clk_init_data){ 1296 .name = "spifc_div", 1297 .ops = &clk_regmap_divider_ops, 1298 .parent_hws = (const struct clk_hw *[]) { 1299 &spifc_sel.hw 1300 }, 1301 .num_parents = 1, 1302 .flags = CLK_SET_RATE_PARENT, 1303 }, 1304 }; 1305 1306 static struct clk_regmap spifc_sel2 = { 1307 .data = &(struct clk_regmap_mux_data){ 1308 .offset = SPIFC_CLK_CTRL, 1309 .mask = 0x1, 1310 .shift = 15, 1311 }, 1312 .hw.init = &(struct clk_init_data){ 1313 .name = "spifc_sel2", 1314 .ops = &clk_regmap_mux_ops, 1315 .parent_data = (const struct clk_parent_data []) { 1316 { .hw = &spifc_div.hw }, 1317 { .fw_name = "xtal", }, 1318 }, 1319 .num_parents = 2, 1320 .flags = CLK_SET_RATE_PARENT, 1321 }, 1322 }; 1323 1324 static struct clk_regmap spifc = { 1325 .data = &(struct clk_regmap_gate_data){ 1326 .offset = SPIFC_CLK_CTRL, 1327 .bit_idx = 8, 1328 }, 1329 .hw.init = &(struct clk_init_data) { 1330 .name = "spifc", 1331 .ops = &clk_regmap_gate_ops, 1332 .parent_hws = (const struct clk_hw *[]) { 1333 &spifc_sel2.hw 1334 }, 1335 .num_parents = 1, 1336 .flags = CLK_SET_RATE_PARENT, 1337 }, 1338 }; 1339 1340 static const struct clk_parent_data usb_bus_parents[] = { 1341 { .fw_name = "xtal", }, 1342 { .hw = &sys.hw }, 1343 { .fw_name = "fclk_div3", }, 1344 { .fw_name = "fclk_div5", }, 1345 }; 1346 1347 static struct clk_regmap usb_bus_sel = { 1348 .data = &(struct clk_regmap_mux_data){ 1349 .offset = USB_BUSCLK_CTRL, 1350 .mask = 0x3, 1351 .shift = 9, 1352 }, 1353 .hw.init = &(struct clk_init_data){ 1354 .name = "usb_bus_sel", 1355 .ops = &clk_regmap_mux_ops, 1356 .parent_data = usb_bus_parents, 1357 .num_parents = ARRAY_SIZE(usb_bus_parents), 1358 .flags = CLK_SET_RATE_PARENT, 1359 }, 1360 }; 1361 1362 static struct clk_regmap usb_bus_div = { 1363 .data = &(struct clk_regmap_div_data){ 1364 .offset = USB_BUSCLK_CTRL, 1365 .shift = 0, 1366 .width = 8, 1367 }, 1368 .hw.init = &(struct clk_init_data){ 1369 .name = "usb_bus_div", 1370 .ops = &clk_regmap_divider_ops, 1371 .parent_hws = (const struct clk_hw *[]) { 1372 &usb_bus_sel.hw 1373 }, 1374 .num_parents = 1, 1375 .flags = CLK_SET_RATE_PARENT, 1376 }, 1377 }; 1378 1379 static struct clk_regmap usb_bus = { 1380 .data = &(struct clk_regmap_gate_data){ 1381 .offset = USB_BUSCLK_CTRL, 1382 .bit_idx = 8, 1383 }, 1384 .hw.init = &(struct clk_init_data) { 1385 .name = "usb_bus", 1386 .ops = &clk_regmap_gate_ops, 1387 .parent_hws = (const struct clk_hw *[]) { 1388 &usb_bus_div.hw 1389 }, 1390 .num_parents = 1, 1391 .flags = CLK_SET_RATE_PARENT, 1392 }, 1393 }; 1394 1395 static const struct clk_parent_data sd_emmc_psram_dmc_parents[] = { 1396 { .fw_name = "fclk_div2", }, 1397 { .fw_name = "fclk_div3", }, 1398 { .fw_name = "fclk_div5", }, 1399 { .fw_name = "hifi_pll", }, 1400 }; 1401 1402 static struct clk_regmap sd_emmc_sel = { 1403 .data = &(struct clk_regmap_mux_data){ 1404 .offset = SD_EMMC_CLK_CTRL, 1405 .mask = 0x3, 1406 .shift = 9, 1407 }, 1408 .hw.init = &(struct clk_init_data){ 1409 .name = "sd_emmc_sel", 1410 .ops = &clk_regmap_mux_ops, 1411 .parent_data = sd_emmc_psram_dmc_parents, 1412 .num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents), 1413 }, 1414 }; 1415 1416 static struct clk_regmap sd_emmc_div = { 1417 .data = &(struct clk_regmap_div_data){ 1418 .offset = SD_EMMC_CLK_CTRL, 1419 .shift = 0, 1420 .width = 8, 1421 }, 1422 .hw.init = &(struct clk_init_data){ 1423 .name = "sd_emmc_div", 1424 .ops = &clk_regmap_divider_ops, 1425 .parent_hws = (const struct clk_hw *[]) { 1426 &sd_emmc_sel.hw 1427 }, 1428 .num_parents = 1, 1429 .flags = CLK_SET_RATE_PARENT, 1430 }, 1431 }; 1432 1433 static struct clk_regmap sd_emmc_sel2 = { 1434 .data = &(struct clk_regmap_mux_data){ 1435 .offset = SD_EMMC_CLK_CTRL, 1436 .mask = 0x1, 1437 .shift = 15, 1438 }, 1439 .hw.init = &(struct clk_init_data){ 1440 .name = "sd_emmc_sel2", 1441 .ops = &clk_regmap_mux_ops, 1442 .parent_data = (const struct clk_parent_data []) { 1443 { .hw = &sd_emmc_div.hw }, 1444 { .fw_name = "xtal", }, 1445 }, 1446 .num_parents = 2, 1447 .flags = CLK_SET_RATE_PARENT, 1448 }, 1449 }; 1450 1451 static struct clk_regmap sd_emmc = { 1452 .data = &(struct clk_regmap_gate_data){ 1453 .offset = SD_EMMC_CLK_CTRL, 1454 .bit_idx = 8, 1455 }, 1456 .hw.init = &(struct clk_init_data) { 1457 .name = "sd_emmc", 1458 .ops = &clk_regmap_gate_ops, 1459 .parent_hws = (const struct clk_hw *[]) { 1460 &sd_emmc_sel2.hw 1461 }, 1462 .num_parents = 1, 1463 .flags = CLK_SET_RATE_PARENT, 1464 }, 1465 }; 1466 1467 static struct clk_regmap psram_sel = { 1468 .data = &(struct clk_regmap_mux_data){ 1469 .offset = PSRAM_CLK_CTRL, 1470 .mask = 0x3, 1471 .shift = 9, 1472 }, 1473 .hw.init = &(struct clk_init_data){ 1474 .name = "psram_sel", 1475 .ops = &clk_regmap_mux_ops, 1476 .parent_data = sd_emmc_psram_dmc_parents, 1477 .num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents), 1478 }, 1479 }; 1480 1481 static struct clk_regmap psram_div = { 1482 .data = &(struct clk_regmap_div_data){ 1483 .offset = PSRAM_CLK_CTRL, 1484 .shift = 0, 1485 .width = 8, 1486 }, 1487 .hw.init = &(struct clk_init_data){ 1488 .name = "psram_div", 1489 .ops = &clk_regmap_divider_ops, 1490 .parent_hws = (const struct clk_hw *[]) { 1491 &psram_sel.hw 1492 }, 1493 .num_parents = 1, 1494 .flags = CLK_SET_RATE_PARENT, 1495 }, 1496 }; 1497 1498 static struct clk_regmap psram_sel2 = { 1499 .data = &(struct clk_regmap_mux_data){ 1500 .offset = PSRAM_CLK_CTRL, 1501 .mask = 0x1, 1502 .shift = 15, 1503 }, 1504 .hw.init = &(struct clk_init_data){ 1505 .name = "psram_sel2", 1506 .ops = &clk_regmap_mux_ops, 1507 .parent_data = (const struct clk_parent_data []) { 1508 { .hw = &psram_div.hw }, 1509 { .fw_name = "xtal", }, 1510 }, 1511 .num_parents = 2, 1512 .flags = CLK_SET_RATE_PARENT, 1513 }, 1514 }; 1515 1516 static struct clk_regmap psram = { 1517 .data = &(struct clk_regmap_gate_data){ 1518 .offset = PSRAM_CLK_CTRL, 1519 .bit_idx = 8, 1520 }, 1521 .hw.init = &(struct clk_init_data) { 1522 .name = "psram", 1523 .ops = &clk_regmap_gate_ops, 1524 .parent_hws = (const struct clk_hw *[]) { 1525 &psram_sel2.hw 1526 }, 1527 .num_parents = 1, 1528 .flags = CLK_SET_RATE_PARENT, 1529 }, 1530 }; 1531 1532 static struct clk_regmap dmc_sel = { 1533 .data = &(struct clk_regmap_mux_data){ 1534 .offset = DMC_CLK_CTRL, 1535 .mask = 0x3, 1536 .shift = 9, 1537 }, 1538 .hw.init = &(struct clk_init_data){ 1539 .name = "dmc_sel", 1540 .ops = &clk_regmap_mux_ops, 1541 .parent_data = sd_emmc_psram_dmc_parents, 1542 .num_parents = ARRAY_SIZE(sd_emmc_psram_dmc_parents), 1543 }, 1544 }; 1545 1546 static struct clk_regmap dmc_div = { 1547 .data = &(struct clk_regmap_div_data){ 1548 .offset = DMC_CLK_CTRL, 1549 .shift = 0, 1550 .width = 8, 1551 }, 1552 .hw.init = &(struct clk_init_data){ 1553 .name = "dmc_div", 1554 .ops = &clk_regmap_divider_ops, 1555 .parent_hws = (const struct clk_hw *[]) { 1556 &dmc_sel.hw 1557 }, 1558 .num_parents = 1, 1559 .flags = CLK_SET_RATE_PARENT, 1560 }, 1561 }; 1562 1563 static struct clk_regmap dmc_sel2 = { 1564 .data = &(struct clk_regmap_mux_data){ 1565 .offset = DMC_CLK_CTRL, 1566 .mask = 0x1, 1567 .shift = 15, 1568 }, 1569 .hw.init = &(struct clk_init_data){ 1570 .name = "dmc_sel2", 1571 .ops = &clk_regmap_mux_ops, 1572 .parent_data = (const struct clk_parent_data []) { 1573 { .hw = &dmc_div.hw }, 1574 { .fw_name = "xtal", }, 1575 }, 1576 .num_parents = 2, 1577 .flags = CLK_SET_RATE_PARENT, 1578 }, 1579 }; 1580 1581 static struct clk_regmap dmc = { 1582 .data = &(struct clk_regmap_gate_data){ 1583 .offset = DMC_CLK_CTRL, 1584 .bit_idx = 8, 1585 }, 1586 .hw.init = &(struct clk_init_data) { 1587 .name = "dmc", 1588 .ops = &clk_regmap_gate_ro_ops, 1589 .parent_hws = (const struct clk_hw *[]) { 1590 &dmc_sel2.hw 1591 }, 1592 .num_parents = 1, 1593 .flags = CLK_SET_RATE_PARENT, 1594 }, 1595 }; 1596 1597 static struct clk_regmap ceca_32k_in = { 1598 .data = &(struct clk_regmap_gate_data){ 1599 .offset = CECA_CLK_CTRL0, 1600 .bit_idx = 31, 1601 }, 1602 .hw.init = &(struct clk_init_data) { 1603 .name = "ceca_32k_in", 1604 .ops = &clk_regmap_gate_ops, 1605 .parent_data = &(const struct clk_parent_data) { 1606 .fw_name = "xtal", 1607 }, 1608 .num_parents = 1, 1609 }, 1610 }; 1611 1612 static struct clk_regmap ceca_32k_div = { 1613 .data = &(struct meson_clk_dualdiv_data){ 1614 .n1 = { 1615 .reg_off = CECA_CLK_CTRL0, 1616 .shift = 0, 1617 .width = 12, 1618 }, 1619 .n2 = { 1620 .reg_off = CECA_CLK_CTRL0, 1621 .shift = 12, 1622 .width = 12, 1623 }, 1624 .m1 = { 1625 .reg_off = CECA_CLK_CTRL1, 1626 .shift = 0, 1627 .width = 12, 1628 }, 1629 .m2 = { 1630 .reg_off = CECA_CLK_CTRL1, 1631 .shift = 12, 1632 .width = 12, 1633 }, 1634 .dual = { 1635 .reg_off = CECA_CLK_CTRL0, 1636 .shift = 28, 1637 .width = 1, 1638 }, 1639 .table = clk_32k_div_table, 1640 }, 1641 .hw.init = &(struct clk_init_data){ 1642 .name = "ceca_32k_div", 1643 .ops = &meson_clk_dualdiv_ops, 1644 .parent_hws = (const struct clk_hw *[]) { 1645 &ceca_32k_in.hw 1646 }, 1647 .num_parents = 1, 1648 }, 1649 }; 1650 1651 static struct clk_regmap ceca_32k_sel_pre = { 1652 .data = &(struct clk_regmap_mux_data) { 1653 .offset = CECA_CLK_CTRL1, 1654 .mask = 0x1, 1655 .shift = 24, 1656 .flags = CLK_MUX_ROUND_CLOSEST, 1657 }, 1658 .hw.init = &(struct clk_init_data){ 1659 .name = "ceca_32k_sel_pre", 1660 .ops = &clk_regmap_mux_ops, 1661 .parent_hws = (const struct clk_hw *[]) { 1662 &ceca_32k_div.hw, 1663 &ceca_32k_in.hw, 1664 }, 1665 .num_parents = 2, 1666 .flags = CLK_SET_RATE_PARENT, 1667 }, 1668 }; 1669 1670 static struct clk_regmap ceca_32k_sel = { 1671 .data = &(struct clk_regmap_mux_data) { 1672 .offset = CECA_CLK_CTRL1, 1673 .mask = 0x1, 1674 .shift = 31, 1675 .flags = CLK_MUX_ROUND_CLOSEST, 1676 }, 1677 .hw.init = &(struct clk_init_data){ 1678 .name = "ceca_32k_sel", 1679 .ops = &clk_regmap_mux_ops, 1680 .parent_hws = (const struct clk_hw *[]) { 1681 &ceca_32k_sel_pre.hw, 1682 &rtc.hw, 1683 }, 1684 .num_parents = 2, 1685 }, 1686 }; 1687 1688 static struct clk_regmap ceca_32k_out = { 1689 .data = &(struct clk_regmap_gate_data){ 1690 .offset = CECA_CLK_CTRL0, 1691 .bit_idx = 30, 1692 }, 1693 .hw.init = &(struct clk_init_data){ 1694 .name = "ceca_32k_out", 1695 .ops = &clk_regmap_gate_ops, 1696 .parent_hws = (const struct clk_hw *[]) { 1697 &ceca_32k_sel.hw 1698 }, 1699 .num_parents = 1, 1700 .flags = CLK_SET_RATE_PARENT, 1701 }, 1702 }; 1703 1704 static struct clk_regmap cecb_32k_in = { 1705 .data = &(struct clk_regmap_gate_data){ 1706 .offset = CECB_CLK_CTRL0, 1707 .bit_idx = 31, 1708 }, 1709 .hw.init = &(struct clk_init_data) { 1710 .name = "cecb_32k_in", 1711 .ops = &clk_regmap_gate_ops, 1712 .parent_data = &(const struct clk_parent_data) { 1713 .fw_name = "xtal", 1714 }, 1715 .num_parents = 1, 1716 }, 1717 }; 1718 1719 static struct clk_regmap cecb_32k_div = { 1720 .data = &(struct meson_clk_dualdiv_data){ 1721 .n1 = { 1722 .reg_off = CECB_CLK_CTRL0, 1723 .shift = 0, 1724 .width = 12, 1725 }, 1726 .n2 = { 1727 .reg_off = CECB_CLK_CTRL0, 1728 .shift = 12, 1729 .width = 12, 1730 }, 1731 .m1 = { 1732 .reg_off = CECB_CLK_CTRL1, 1733 .shift = 0, 1734 .width = 12, 1735 }, 1736 .m2 = { 1737 .reg_off = CECB_CLK_CTRL1, 1738 .shift = 12, 1739 .width = 12, 1740 }, 1741 .dual = { 1742 .reg_off = CECB_CLK_CTRL0, 1743 .shift = 28, 1744 .width = 1, 1745 }, 1746 .table = clk_32k_div_table, 1747 }, 1748 .hw.init = &(struct clk_init_data){ 1749 .name = "cecb_32k_div", 1750 .ops = &meson_clk_dualdiv_ops, 1751 .parent_hws = (const struct clk_hw *[]) { 1752 &cecb_32k_in.hw 1753 }, 1754 .num_parents = 1, 1755 }, 1756 }; 1757 1758 static struct clk_regmap cecb_32k_sel_pre = { 1759 .data = &(struct clk_regmap_mux_data) { 1760 .offset = CECB_CLK_CTRL1, 1761 .mask = 0x1, 1762 .shift = 24, 1763 .flags = CLK_MUX_ROUND_CLOSEST, 1764 }, 1765 .hw.init = &(struct clk_init_data){ 1766 .name = "cecb_32k_sel_pre", 1767 .ops = &clk_regmap_mux_ops, 1768 .parent_hws = (const struct clk_hw *[]) { 1769 &cecb_32k_div.hw, 1770 &cecb_32k_in.hw, 1771 }, 1772 .num_parents = 2, 1773 .flags = CLK_SET_RATE_PARENT, 1774 }, 1775 }; 1776 1777 static struct clk_regmap cecb_32k_sel = { 1778 .data = &(struct clk_regmap_mux_data) { 1779 .offset = CECB_CLK_CTRL1, 1780 .mask = 0x1, 1781 .shift = 31, 1782 .flags = CLK_MUX_ROUND_CLOSEST, 1783 }, 1784 .hw.init = &(struct clk_init_data){ 1785 .name = "cecb_32k_sel", 1786 .ops = &clk_regmap_mux_ops, 1787 .parent_hws = (const struct clk_hw *[]) { 1788 &cecb_32k_sel_pre.hw, 1789 &rtc.hw, 1790 }, 1791 .num_parents = 2, 1792 }, 1793 }; 1794 1795 static struct clk_regmap cecb_32k_out = { 1796 .data = &(struct clk_regmap_gate_data){ 1797 .offset = CECB_CLK_CTRL0, 1798 .bit_idx = 30, 1799 }, 1800 .hw.init = &(struct clk_init_data){ 1801 .name = "cecb_32k_out", 1802 .ops = &clk_regmap_gate_ops, 1803 .parent_hws = (const struct clk_hw *[]) { 1804 &cecb_32k_sel.hw 1805 }, 1806 .num_parents = 1, 1807 .flags = CLK_SET_RATE_PARENT, 1808 }, 1809 }; 1810 1811 #define MESON_GATE(_name, _reg, _bit) \ 1812 MESON_PCLK(_name, _reg, _bit, &sys.hw) 1813 1814 static MESON_GATE(clktree, SYS_CLK_EN0, 0); 1815 static MESON_GATE(reset_ctrl, SYS_CLK_EN0, 1); 1816 static MESON_GATE(analog_ctrl, SYS_CLK_EN0, 2); 1817 static MESON_GATE(pwr_ctrl, SYS_CLK_EN0, 3); 1818 static MESON_GATE(pad_ctrl, SYS_CLK_EN0, 4); 1819 static MESON_GATE(sys_ctrl, SYS_CLK_EN0, 5); 1820 static MESON_GATE(temp_sensor, SYS_CLK_EN0, 6); 1821 static MESON_GATE(am2axi_dev, SYS_CLK_EN0, 7); 1822 static MESON_GATE(spicc_b, SYS_CLK_EN0, 8); 1823 static MESON_GATE(spicc_a, SYS_CLK_EN0, 9); 1824 static MESON_GATE(msr, SYS_CLK_EN0, 10); 1825 static MESON_GATE(audio, SYS_CLK_EN0, 11); 1826 static MESON_GATE(jtag_ctrl, SYS_CLK_EN0, 12); 1827 static MESON_GATE(saradc_en, SYS_CLK_EN0, 13); 1828 static MESON_GATE(pwm_ef, SYS_CLK_EN0, 14); 1829 static MESON_GATE(pwm_cd, SYS_CLK_EN0, 15); 1830 static MESON_GATE(pwm_ab, SYS_CLK_EN0, 16); 1831 static MESON_GATE(cec, SYS_CLK_EN0, 17); 1832 static MESON_GATE(i2c_s, SYS_CLK_EN0, 18); 1833 static MESON_GATE(ir_ctrl, SYS_CLK_EN0, 19); 1834 static MESON_GATE(i2c_m_d, SYS_CLK_EN0, 20); 1835 static MESON_GATE(i2c_m_c, SYS_CLK_EN0, 21); 1836 static MESON_GATE(i2c_m_b, SYS_CLK_EN0, 22); 1837 static MESON_GATE(i2c_m_a, SYS_CLK_EN0, 23); 1838 static MESON_GATE(acodec, SYS_CLK_EN0, 24); 1839 static MESON_GATE(otp, SYS_CLK_EN0, 25); 1840 static MESON_GATE(sd_emmc_a, SYS_CLK_EN0, 26); 1841 static MESON_GATE(usb_phy, SYS_CLK_EN0, 27); 1842 static MESON_GATE(usb_ctrl, SYS_CLK_EN0, 28); 1843 static MESON_GATE(sys_dspb, SYS_CLK_EN0, 29); 1844 static MESON_GATE(sys_dspa, SYS_CLK_EN0, 30); 1845 static MESON_GATE(dma, SYS_CLK_EN0, 31); 1846 static MESON_GATE(irq_ctrl, SYS_CLK_EN1, 0); 1847 static MESON_GATE(nic, SYS_CLK_EN1, 1); 1848 static MESON_GATE(gic, SYS_CLK_EN1, 2); 1849 static MESON_GATE(uart_c, SYS_CLK_EN1, 3); 1850 static MESON_GATE(uart_b, SYS_CLK_EN1, 4); 1851 static MESON_GATE(uart_a, SYS_CLK_EN1, 5); 1852 static MESON_GATE(sys_psram, SYS_CLK_EN1, 6); 1853 static MESON_GATE(rsa, SYS_CLK_EN1, 8); 1854 static MESON_GATE(coresight, SYS_CLK_EN1, 9); 1855 static MESON_GATE(am2axi_vad, AXI_CLK_EN, 0); 1856 static MESON_GATE(audio_vad, AXI_CLK_EN, 1); 1857 static MESON_GATE(axi_dmc, AXI_CLK_EN, 3); 1858 static MESON_GATE(axi_psram, AXI_CLK_EN, 4); 1859 static MESON_GATE(ramb, AXI_CLK_EN, 5); 1860 static MESON_GATE(rama, AXI_CLK_EN, 6); 1861 static MESON_GATE(axi_spifc, AXI_CLK_EN, 7); 1862 static MESON_GATE(axi_nic, AXI_CLK_EN, 8); 1863 static MESON_GATE(axi_dma, AXI_CLK_EN, 9); 1864 static MESON_GATE(cpu_ctrl, AXI_CLK_EN, 10); 1865 static MESON_GATE(rom, AXI_CLK_EN, 11); 1866 static MESON_GATE(prod_i2c, AXI_CLK_EN, 12); 1867 1868 /* Array of all clocks registered by this provider */ 1869 static struct clk_hw_onecell_data a1_periphs_clks = { 1870 .hws = { 1871 [CLKID_XTAL_IN] = &xtal_in.hw, 1872 [CLKID_FIXPLL_IN] = &fixpll_in.hw, 1873 [CLKID_USB_PHY_IN] = &usb_phy_in.hw, 1874 [CLKID_USB_CTRL_IN] = &usb_ctrl_in.hw, 1875 [CLKID_HIFIPLL_IN] = &hifipll_in.hw, 1876 [CLKID_SYSPLL_IN] = &syspll_in.hw, 1877 [CLKID_DDS_IN] = &dds_in.hw, 1878 [CLKID_SYS] = &sys.hw, 1879 [CLKID_CLKTREE] = &clktree.hw, 1880 [CLKID_RESET_CTRL] = &reset_ctrl.hw, 1881 [CLKID_ANALOG_CTRL] = &analog_ctrl.hw, 1882 [CLKID_PWR_CTRL] = &pwr_ctrl.hw, 1883 [CLKID_PAD_CTRL] = &pad_ctrl.hw, 1884 [CLKID_SYS_CTRL] = &sys_ctrl.hw, 1885 [CLKID_TEMP_SENSOR] = &temp_sensor.hw, 1886 [CLKID_AM2AXI_DIV] = &am2axi_dev.hw, 1887 [CLKID_SPICC_B] = &spicc_b.hw, 1888 [CLKID_SPICC_A] = &spicc_a.hw, 1889 [CLKID_MSR] = &msr.hw, 1890 [CLKID_AUDIO] = &audio.hw, 1891 [CLKID_JTAG_CTRL] = &jtag_ctrl.hw, 1892 [CLKID_SARADC_EN] = &saradc_en.hw, 1893 [CLKID_PWM_EF] = &pwm_ef.hw, 1894 [CLKID_PWM_CD] = &pwm_cd.hw, 1895 [CLKID_PWM_AB] = &pwm_ab.hw, 1896 [CLKID_CEC] = &cec.hw, 1897 [CLKID_I2C_S] = &i2c_s.hw, 1898 [CLKID_IR_CTRL] = &ir_ctrl.hw, 1899 [CLKID_I2C_M_D] = &i2c_m_d.hw, 1900 [CLKID_I2C_M_C] = &i2c_m_c.hw, 1901 [CLKID_I2C_M_B] = &i2c_m_b.hw, 1902 [CLKID_I2C_M_A] = &i2c_m_a.hw, 1903 [CLKID_ACODEC] = &acodec.hw, 1904 [CLKID_OTP] = &otp.hw, 1905 [CLKID_SD_EMMC_A] = &sd_emmc_a.hw, 1906 [CLKID_USB_PHY] = &usb_phy.hw, 1907 [CLKID_USB_CTRL] = &usb_ctrl.hw, 1908 [CLKID_SYS_DSPB] = &sys_dspb.hw, 1909 [CLKID_SYS_DSPA] = &sys_dspa.hw, 1910 [CLKID_DMA] = &dma.hw, 1911 [CLKID_IRQ_CTRL] = &irq_ctrl.hw, 1912 [CLKID_NIC] = &nic.hw, 1913 [CLKID_GIC] = &gic.hw, 1914 [CLKID_UART_C] = &uart_c.hw, 1915 [CLKID_UART_B] = &uart_b.hw, 1916 [CLKID_UART_A] = &uart_a.hw, 1917 [CLKID_SYS_PSRAM] = &sys_psram.hw, 1918 [CLKID_RSA] = &rsa.hw, 1919 [CLKID_CORESIGHT] = &coresight.hw, 1920 [CLKID_AM2AXI_VAD] = &am2axi_vad.hw, 1921 [CLKID_AUDIO_VAD] = &audio_vad.hw, 1922 [CLKID_AXI_DMC] = &axi_dmc.hw, 1923 [CLKID_AXI_PSRAM] = &axi_psram.hw, 1924 [CLKID_RAMB] = &ramb.hw, 1925 [CLKID_RAMA] = &rama.hw, 1926 [CLKID_AXI_SPIFC] = &axi_spifc.hw, 1927 [CLKID_AXI_NIC] = &axi_nic.hw, 1928 [CLKID_AXI_DMA] = &axi_dma.hw, 1929 [CLKID_CPU_CTRL] = &cpu_ctrl.hw, 1930 [CLKID_ROM] = &rom.hw, 1931 [CLKID_PROC_I2C] = &prod_i2c.hw, 1932 [CLKID_DSPA_SEL] = &dspa_sel.hw, 1933 [CLKID_DSPB_SEL] = &dspb_sel.hw, 1934 [CLKID_DSPA_EN] = &dspa_en.hw, 1935 [CLKID_DSPA_EN_NIC] = &dspa_en_nic.hw, 1936 [CLKID_DSPB_EN] = &dspb_en.hw, 1937 [CLKID_DSPB_EN_NIC] = &dspb_en_nic.hw, 1938 [CLKID_RTC] = &rtc.hw, 1939 [CLKID_CECA_32K] = &ceca_32k_out.hw, 1940 [CLKID_CECB_32K] = &cecb_32k_out.hw, 1941 [CLKID_24M] = &clk_24m.hw, 1942 [CLKID_12M] = &clk_12m.hw, 1943 [CLKID_FCLK_DIV2_DIVN] = &fclk_div2_divn.hw, 1944 [CLKID_GEN] = &gen.hw, 1945 [CLKID_SARADC_SEL] = &saradc_sel.hw, 1946 [CLKID_SARADC] = &saradc.hw, 1947 [CLKID_PWM_A] = &pwm_a.hw, 1948 [CLKID_PWM_B] = &pwm_b.hw, 1949 [CLKID_PWM_C] = &pwm_c.hw, 1950 [CLKID_PWM_D] = &pwm_d.hw, 1951 [CLKID_PWM_E] = &pwm_e.hw, 1952 [CLKID_PWM_F] = &pwm_f.hw, 1953 [CLKID_SPICC] = &spicc.hw, 1954 [CLKID_TS] = &ts.hw, 1955 [CLKID_SPIFC] = &spifc.hw, 1956 [CLKID_USB_BUS] = &usb_bus.hw, 1957 [CLKID_SD_EMMC] = &sd_emmc.hw, 1958 [CLKID_PSRAM] = &psram.hw, 1959 [CLKID_DMC] = &dmc.hw, 1960 [CLKID_SYS_A_SEL] = &sys_a_sel.hw, 1961 [CLKID_SYS_A_DIV] = &sys_a_div.hw, 1962 [CLKID_SYS_A] = &sys_a.hw, 1963 [CLKID_SYS_B_SEL] = &sys_b_sel.hw, 1964 [CLKID_SYS_B_DIV] = &sys_b_div.hw, 1965 [CLKID_SYS_B] = &sys_b.hw, 1966 [CLKID_DSPA_A_SEL] = &dspa_a_sel.hw, 1967 [CLKID_DSPA_A_DIV] = &dspa_a_div.hw, 1968 [CLKID_DSPA_A] = &dspa_a.hw, 1969 [CLKID_DSPA_B_SEL] = &dspa_b_sel.hw, 1970 [CLKID_DSPA_B_DIV] = &dspa_b_div.hw, 1971 [CLKID_DSPA_B] = &dspa_b.hw, 1972 [CLKID_DSPB_A_SEL] = &dspb_a_sel.hw, 1973 [CLKID_DSPB_A_DIV] = &dspb_a_div.hw, 1974 [CLKID_DSPB_A] = &dspb_a.hw, 1975 [CLKID_DSPB_B_SEL] = &dspb_b_sel.hw, 1976 [CLKID_DSPB_B_DIV] = &dspb_b_div.hw, 1977 [CLKID_DSPB_B] = &dspb_b.hw, 1978 [CLKID_RTC_32K_IN] = &rtc_32k_in.hw, 1979 [CLKID_RTC_32K_DIV] = &rtc_32k_div.hw, 1980 [CLKID_RTC_32K_XTAL] = &rtc_32k_xtal.hw, 1981 [CLKID_RTC_32K_SEL] = &rtc_32k_sel.hw, 1982 [CLKID_CECB_32K_IN] = &cecb_32k_in.hw, 1983 [CLKID_CECB_32K_DIV] = &cecb_32k_div.hw, 1984 [CLKID_CECB_32K_SEL_PRE] = &cecb_32k_sel_pre.hw, 1985 [CLKID_CECB_32K_SEL] = &cecb_32k_sel.hw, 1986 [CLKID_CECA_32K_IN] = &ceca_32k_in.hw, 1987 [CLKID_CECA_32K_DIV] = &ceca_32k_div.hw, 1988 [CLKID_CECA_32K_SEL_PRE] = &ceca_32k_sel_pre.hw, 1989 [CLKID_CECA_32K_SEL] = &ceca_32k_sel.hw, 1990 [CLKID_DIV2_PRE] = &fclk_div2_divn_pre.hw, 1991 [CLKID_24M_DIV2] = &clk_24m_div2.hw, 1992 [CLKID_GEN_SEL] = &gen_sel.hw, 1993 [CLKID_GEN_DIV] = &gen_div.hw, 1994 [CLKID_SARADC_DIV] = &saradc_div.hw, 1995 [CLKID_PWM_A_SEL] = &pwm_a_sel.hw, 1996 [CLKID_PWM_A_DIV] = &pwm_a_div.hw, 1997 [CLKID_PWM_B_SEL] = &pwm_b_sel.hw, 1998 [CLKID_PWM_B_DIV] = &pwm_b_div.hw, 1999 [CLKID_PWM_C_SEL] = &pwm_c_sel.hw, 2000 [CLKID_PWM_C_DIV] = &pwm_c_div.hw, 2001 [CLKID_PWM_D_SEL] = &pwm_d_sel.hw, 2002 [CLKID_PWM_D_DIV] = &pwm_d_div.hw, 2003 [CLKID_PWM_E_SEL] = &pwm_e_sel.hw, 2004 [CLKID_PWM_E_DIV] = &pwm_e_div.hw, 2005 [CLKID_PWM_F_SEL] = &pwm_f_sel.hw, 2006 [CLKID_PWM_F_DIV] = &pwm_f_div.hw, 2007 [CLKID_SPICC_SEL] = &spicc_sel.hw, 2008 [CLKID_SPICC_DIV] = &spicc_div.hw, 2009 [CLKID_SPICC_SEL2] = &spicc_sel2.hw, 2010 [CLKID_TS_DIV] = &ts_div.hw, 2011 [CLKID_SPIFC_SEL] = &spifc_sel.hw, 2012 [CLKID_SPIFC_DIV] = &spifc_div.hw, 2013 [CLKID_SPIFC_SEL2] = &spifc_sel2.hw, 2014 [CLKID_USB_BUS_SEL] = &usb_bus_sel.hw, 2015 [CLKID_USB_BUS_DIV] = &usb_bus_div.hw, 2016 [CLKID_SD_EMMC_SEL] = &sd_emmc_sel.hw, 2017 [CLKID_SD_EMMC_DIV] = &sd_emmc_div.hw, 2018 [CLKID_SD_EMMC_SEL2] = &sd_emmc_sel2.hw, 2019 [CLKID_PSRAM_SEL] = &psram_sel.hw, 2020 [CLKID_PSRAM_DIV] = &psram_div.hw, 2021 [CLKID_PSRAM_SEL2] = &psram_sel2.hw, 2022 [CLKID_DMC_SEL] = &dmc_sel.hw, 2023 [CLKID_DMC_DIV] = &dmc_div.hw, 2024 [CLKID_DMC_SEL2] = &dmc_sel2.hw, 2025 [NR_CLKS] = NULL, 2026 }, 2027 .num = NR_CLKS, 2028 }; 2029 2030 /* Convenience table to populate regmap in .probe */ 2031 static struct clk_regmap *const a1_periphs_regmaps[] = { 2032 &xtal_in, 2033 &fixpll_in, 2034 &usb_phy_in, 2035 &usb_ctrl_in, 2036 &hifipll_in, 2037 &syspll_in, 2038 &dds_in, 2039 &sys, 2040 &clktree, 2041 &reset_ctrl, 2042 &analog_ctrl, 2043 &pwr_ctrl, 2044 &pad_ctrl, 2045 &sys_ctrl, 2046 &temp_sensor, 2047 &am2axi_dev, 2048 &spicc_b, 2049 &spicc_a, 2050 &msr, 2051 &audio, 2052 &jtag_ctrl, 2053 &saradc_en, 2054 &pwm_ef, 2055 &pwm_cd, 2056 &pwm_ab, 2057 &cec, 2058 &i2c_s, 2059 &ir_ctrl, 2060 &i2c_m_d, 2061 &i2c_m_c, 2062 &i2c_m_b, 2063 &i2c_m_a, 2064 &acodec, 2065 &otp, 2066 &sd_emmc_a, 2067 &usb_phy, 2068 &usb_ctrl, 2069 &sys_dspb, 2070 &sys_dspa, 2071 &dma, 2072 &irq_ctrl, 2073 &nic, 2074 &gic, 2075 &uart_c, 2076 &uart_b, 2077 &uart_a, 2078 &sys_psram, 2079 &rsa, 2080 &coresight, 2081 &am2axi_vad, 2082 &audio_vad, 2083 &axi_dmc, 2084 &axi_psram, 2085 &ramb, 2086 &rama, 2087 &axi_spifc, 2088 &axi_nic, 2089 &axi_dma, 2090 &cpu_ctrl, 2091 &rom, 2092 &prod_i2c, 2093 &dspa_sel, 2094 &dspb_sel, 2095 &dspa_en, 2096 &dspa_en_nic, 2097 &dspb_en, 2098 &dspb_en_nic, 2099 &rtc, 2100 &ceca_32k_out, 2101 &cecb_32k_out, 2102 &clk_24m, 2103 &clk_12m, 2104 &fclk_div2_divn, 2105 &gen, 2106 &saradc_sel, 2107 &saradc, 2108 &pwm_a, 2109 &pwm_b, 2110 &pwm_c, 2111 &pwm_d, 2112 &pwm_e, 2113 &pwm_f, 2114 &spicc, 2115 &ts, 2116 &spifc, 2117 &usb_bus, 2118 &sd_emmc, 2119 &psram, 2120 &dmc, 2121 &sys_a_sel, 2122 &sys_a_div, 2123 &sys_a, 2124 &sys_b_sel, 2125 &sys_b_div, 2126 &sys_b, 2127 &dspa_a_sel, 2128 &dspa_a_div, 2129 &dspa_a, 2130 &dspa_b_sel, 2131 &dspa_b_div, 2132 &dspa_b, 2133 &dspb_a_sel, 2134 &dspb_a_div, 2135 &dspb_a, 2136 &dspb_b_sel, 2137 &dspb_b_div, 2138 &dspb_b, 2139 &rtc_32k_in, 2140 &rtc_32k_div, 2141 &rtc_32k_xtal, 2142 &rtc_32k_sel, 2143 &cecb_32k_in, 2144 &cecb_32k_div, 2145 &cecb_32k_sel_pre, 2146 &cecb_32k_sel, 2147 &ceca_32k_in, 2148 &ceca_32k_div, 2149 &ceca_32k_sel_pre, 2150 &ceca_32k_sel, 2151 &fclk_div2_divn_pre, 2152 &gen_sel, 2153 &gen_div, 2154 &saradc_div, 2155 &pwm_a_sel, 2156 &pwm_a_div, 2157 &pwm_b_sel, 2158 &pwm_b_div, 2159 &pwm_c_sel, 2160 &pwm_c_div, 2161 &pwm_d_sel, 2162 &pwm_d_div, 2163 &pwm_e_sel, 2164 &pwm_e_div, 2165 &pwm_f_sel, 2166 &pwm_f_div, 2167 &spicc_sel, 2168 &spicc_div, 2169 &spicc_sel2, 2170 &ts_div, 2171 &spifc_sel, 2172 &spifc_div, 2173 &spifc_sel2, 2174 &usb_bus_sel, 2175 &usb_bus_div, 2176 &sd_emmc_sel, 2177 &sd_emmc_div, 2178 &sd_emmc_sel2, 2179 &psram_sel, 2180 &psram_div, 2181 &psram_sel2, 2182 &dmc_sel, 2183 &dmc_div, 2184 &dmc_sel2, 2185 }; 2186 2187 static struct regmap_config a1_periphs_regmap_cfg = { 2188 .reg_bits = 32, 2189 .val_bits = 32, 2190 .reg_stride = 4, 2191 }; 2192 2193 static int meson_a1_periphs_probe(struct platform_device *pdev) 2194 { 2195 struct device *dev = &pdev->dev; 2196 void __iomem *base; 2197 struct regmap *map; 2198 int clkid, i, err; 2199 2200 base = devm_platform_ioremap_resource(pdev, 0); 2201 if (IS_ERR(base)) 2202 return dev_err_probe(dev, PTR_ERR(base), 2203 "can't ioremap resource\n"); 2204 2205 map = devm_regmap_init_mmio(dev, base, &a1_periphs_regmap_cfg); 2206 if (IS_ERR(map)) 2207 return dev_err_probe(dev, PTR_ERR(map), 2208 "can't init regmap mmio region\n"); 2209 2210 /* Populate regmap for the regmap backed clocks */ 2211 for (i = 0; i < ARRAY_SIZE(a1_periphs_regmaps); i++) 2212 a1_periphs_regmaps[i]->map = map; 2213 2214 for (clkid = 0; clkid < a1_periphs_clks.num; clkid++) { 2215 err = devm_clk_hw_register(dev, a1_periphs_clks.hws[clkid]); 2216 if (err) 2217 return dev_err_probe(dev, err, 2218 "clock[%d] registration failed\n", 2219 clkid); 2220 } 2221 2222 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 2223 &a1_periphs_clks); 2224 } 2225 2226 static const struct of_device_id a1_periphs_clkc_match_table[] = { 2227 { .compatible = "amlogic,a1-peripherals-clkc", }, 2228 {} 2229 }; 2230 MODULE_DEVICE_TABLE(of, a1_periphs_clkc_match_table); 2231 2232 static struct platform_driver a1_periphs_clkc_driver = { 2233 .probe = meson_a1_periphs_probe, 2234 .driver = { 2235 .name = "a1-peripherals-clkc", 2236 .of_match_table = a1_periphs_clkc_match_table, 2237 }, 2238 }; 2239 2240 module_platform_driver(a1_periphs_clkc_driver); 2241 MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>"); 2242 MODULE_AUTHOR("Dmitry Rokosov <ddrokosov@sberdevices.ru>"); 2243 MODULE_LICENSE("GPL"); 2244