1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022 MediaTek Inc. 4 * Author: Edward-JW Yang <edward-jw.yang@mediatek.com> 5 */ 6 7 #ifndef __CLK_PLLFH_H 8 #define __CLK_PLLFH_H 9 10 #include "clk-pll.h" 11 12 struct fh_pll_state { 13 void __iomem *base; 14 u32 fh_enable; 15 u32 ssc_rate; 16 }; 17 18 struct fh_pll_data { 19 int pll_id; 20 int fh_id; 21 u32 fhx_offset; 22 u32 dds_mask; 23 u32 slope0_value; 24 u32 slope1_value; 25 u32 sfstrx_en; 26 u32 frddsx_en; 27 u32 fhctlx_en; 28 u32 tgl_org; 29 u32 dvfs_tri; 30 u32 pcwchg; 31 u32 dt_val; 32 u32 df_val; 33 u32 updnlmt_shft; 34 u32 msk_frddsx_dys; 35 u32 msk_frddsx_dts; 36 }; 37 38 struct mtk_pllfh_data { 39 struct fh_pll_state state; 40 const struct fh_pll_data data; 41 }; 42 43 struct fh_pll_regs { 44 void __iomem *reg_hp_en; 45 void __iomem *reg_clk_con; 46 void __iomem *reg_rst_con; 47 void __iomem *reg_slope0; 48 void __iomem *reg_slope1; 49 void __iomem *reg_cfg; 50 void __iomem *reg_updnlmt; 51 void __iomem *reg_dds; 52 void __iomem *reg_dvfs; 53 void __iomem *reg_mon; 54 }; 55 56 struct mtk_fh { 57 struct mtk_clk_pll clk_pll; 58 struct fh_pll_regs regs; 59 struct mtk_pllfh_data *pllfh_data; 60 const struct fh_operation *ops; 61 spinlock_t *lock; 62 }; 63 64 struct fh_operation { 65 int (*hopping)(struct mtk_fh *fh, unsigned int new_dds, 66 unsigned int postdiv); 67 int (*ssc_enable)(struct mtk_fh *fh, u32 rate); 68 }; 69 70 int mtk_clk_register_pllfhs(struct device_node *node, 71 const struct mtk_pll_data *plls, int num_plls, 72 struct mtk_pllfh_data *pllfhs, int num_pllfhs, 73 struct clk_hw_onecell_data *clk_data); 74 75 void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls, 76 struct mtk_pllfh_data *pllfhs, int num_fhs, 77 struct clk_hw_onecell_data *clk_data); 78 79 void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs, 80 int num_pllfhs); 81 82 #endif /* __CLK_PLLFH_H */ 83