xref: /openbmc/linux/drivers/clk/mediatek/clk-pllfh.c (revision e9adcfec) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2022 MediaTek Inc.
4  * Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
5  */
6 
7 #include <linux/of.h>
8 #include <linux/of_address.h>
9 #include <linux/io.h>
10 #include <linux/slab.h>
11 #include <linux/clkdev.h>
12 #include <linux/delay.h>
13 
14 #include "clk-mtk.h"
15 #include "clk-pllfh.h"
16 #include "clk-fhctl.h"
17 
18 static DEFINE_SPINLOCK(pllfh_lock);
19 
20 inline struct mtk_fh *to_mtk_fh(struct clk_hw *hw)
21 {
22 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
23 
24 	return container_of(pll, struct mtk_fh, clk_pll);
25 }
26 
27 static int mtk_fhctl_set_rate(struct clk_hw *hw, unsigned long rate,
28 			      unsigned long parent_rate)
29 {
30 	struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
31 	struct mtk_fh *fh = to_mtk_fh(hw);
32 	u32 pcw = 0;
33 	u32 postdiv;
34 
35 	mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
36 
37 	return fh->ops->hopping(fh, pcw, postdiv);
38 }
39 
40 static const struct clk_ops mtk_pllfh_ops = {
41 	.is_prepared	= mtk_pll_is_prepared,
42 	.prepare	= mtk_pll_prepare,
43 	.unprepare	= mtk_pll_unprepare,
44 	.recalc_rate	= mtk_pll_recalc_rate,
45 	.round_rate	= mtk_pll_round_rate,
46 	.set_rate	= mtk_fhctl_set_rate,
47 };
48 
49 static struct mtk_pllfh_data *get_pllfh_by_id(struct mtk_pllfh_data *pllfhs,
50 					      int num_fhs, int pll_id)
51 {
52 	int i;
53 
54 	for (i = 0; i < num_fhs; i++)
55 		if (pllfhs[i].data.pll_id == pll_id)
56 			return &pllfhs[i];
57 
58 	return NULL;
59 }
60 
61 void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs,
62 		    int num_fhs)
63 {
64 	void __iomem *base;
65 	struct device_node *node;
66 	u32 num_clocks, pll_id, ssc_rate;
67 	int offset, i;
68 
69 	node = of_find_compatible_node(NULL, NULL, compatible_node);
70 	if (!node) {
71 		pr_err("cannot find \"%s\"\n", compatible_node);
72 		return;
73 	}
74 
75 	base = of_iomap(node, 0);
76 	if (!base) {
77 		pr_err("%s(): ioremap failed\n", __func__);
78 		return;
79 	}
80 
81 	num_clocks = of_clk_get_parent_count(node);
82 	if (!num_clocks) {
83 		pr_err("%s(): failed to get clocks property\n", __func__);
84 		return;
85 	}
86 
87 	for (i = 0; i < num_clocks; i++) {
88 		struct mtk_pllfh_data *pllfh;
89 
90 		offset = i * 2;
91 
92 		of_property_read_u32_index(node, "clocks", offset + 1, &pll_id);
93 		of_property_read_u32_index(node,
94 					   "mediatek,hopping-ssc-percent",
95 					   i, &ssc_rate);
96 
97 		pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll_id);
98 		if (!pllfh)
99 			continue;
100 
101 		pllfh->state.fh_enable = 1;
102 		pllfh->state.ssc_rate = ssc_rate;
103 		pllfh->state.base = base;
104 	}
105 }
106 
107 static void pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data)
108 {
109 	struct fh_pll_regs *regs = &fh->regs;
110 	const struct fhctl_offset *offset;
111 	void __iomem *base = pllfh_data->state.base;
112 	void __iomem *fhx_base = base + pllfh_data->data.fhx_offset;
113 
114 	offset = fhctl_get_offset_table();
115 
116 	regs->reg_hp_en = base + offset->offset_hp_en;
117 	regs->reg_clk_con = base + offset->offset_clk_con;
118 	regs->reg_rst_con = base + offset->offset_rst_con;
119 	regs->reg_slope0 = base + offset->offset_slope0;
120 	regs->reg_slope1 = base + offset->offset_slope1;
121 
122 	regs->reg_cfg = fhx_base + offset->offset_cfg;
123 	regs->reg_updnlmt = fhx_base + offset->offset_updnlmt;
124 	regs->reg_dds = fhx_base + offset->offset_dds;
125 	regs->reg_dvfs = fhx_base + offset->offset_dvfs;
126 	regs->reg_mon = fhx_base + offset->offset_mon;
127 
128 	fh->pllfh_data = pllfh_data;
129 	fh->lock = &pllfh_lock;
130 
131 	fh->ops = fhctl_get_ops();
132 }
133 
134 static bool fhctl_is_supported_and_enabled(const struct mtk_pllfh_data *pllfh)
135 {
136 	return pllfh && (pllfh->state.fh_enable == 1);
137 }
138 
139 static struct clk_hw *
140 mtk_clk_register_pllfh(const struct mtk_pll_data *pll_data,
141 		       struct mtk_pllfh_data *pllfh_data, void __iomem *base)
142 {
143 	struct clk_hw *hw;
144 	struct mtk_fh *fh;
145 
146 	fh = kzalloc(sizeof(*fh), GFP_KERNEL);
147 	if (!fh)
148 		return ERR_PTR(-ENOMEM);
149 
150 	pllfh_init(fh, pllfh_data);
151 
152 	hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base,
153 				      &mtk_pllfh_ops);
154 
155 	if (IS_ERR(hw))
156 		kfree(fh);
157 	else
158 		fhctl_hw_init(fh);
159 
160 	return hw;
161 }
162 
163 static void mtk_clk_unregister_pllfh(struct clk_hw *hw)
164 {
165 	struct mtk_fh *fh;
166 
167 	if (!hw)
168 		return;
169 
170 	fh = to_mtk_fh(hw);
171 
172 	clk_hw_unregister(hw);
173 	kfree(fh);
174 }
175 
176 int mtk_clk_register_pllfhs(struct device_node *node,
177 			    const struct mtk_pll_data *plls, int num_plls,
178 			    struct mtk_pllfh_data *pllfhs, int num_fhs,
179 			    struct clk_hw_onecell_data *clk_data)
180 {
181 	void __iomem *base;
182 	int i;
183 	struct clk_hw *hw;
184 
185 	base = of_iomap(node, 0);
186 	if (!base) {
187 		pr_err("%s(): ioremap failed\n", __func__);
188 		return -EINVAL;
189 	}
190 
191 	for (i = 0; i < num_plls; i++) {
192 		const struct mtk_pll_data *pll = &plls[i];
193 		struct mtk_pllfh_data *pllfh;
194 		bool use_fhctl;
195 
196 		pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);
197 		use_fhctl = fhctl_is_supported_and_enabled(pllfh);
198 
199 		if (use_fhctl)
200 			hw = mtk_clk_register_pllfh(pll, pllfh, base);
201 		else
202 			hw = mtk_clk_register_pll(pll, base);
203 
204 		if (IS_ERR(hw)) {
205 			pr_err("Failed to register %s clk %s: %ld\n",
206 			       use_fhctl ? "fhpll" : "pll", pll->name,
207 			       PTR_ERR(hw));
208 			goto err;
209 		}
210 
211 		clk_data->hws[pll->id] = hw;
212 	}
213 
214 	return 0;
215 
216 err:
217 	while (--i >= 0) {
218 		const struct mtk_pll_data *pll = &plls[i];
219 		struct mtk_pllfh_data *pllfh;
220 		bool use_fhctl;
221 
222 		pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);
223 		use_fhctl = fhctl_is_supported_and_enabled(pllfh);
224 
225 		if (use_fhctl)
226 			mtk_clk_unregister_pllfh(clk_data->hws[pll->id]);
227 		else
228 			mtk_clk_unregister_pll(clk_data->hws[pll->id]);
229 
230 		clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
231 	}
232 
233 	iounmap(base);
234 
235 	return PTR_ERR(hw);
236 }
237 
238 void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls,
239 			       struct mtk_pllfh_data *pllfhs, int num_fhs,
240 			       struct clk_hw_onecell_data *clk_data)
241 {
242 	void __iomem *base = NULL, *fhctl_base = NULL;
243 	int i;
244 
245 	if (!clk_data)
246 		return;
247 
248 	for (i = num_plls; i > 0; i--) {
249 		const struct mtk_pll_data *pll = &plls[i - 1];
250 		struct mtk_pllfh_data *pllfh;
251 		bool use_fhctl;
252 
253 		if (IS_ERR_OR_NULL(clk_data->hws[pll->id]))
254 			continue;
255 
256 		pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);
257 		use_fhctl = fhctl_is_supported_and_enabled(pllfh);
258 
259 		if (use_fhctl) {
260 			fhctl_base = pllfh->state.base;
261 			mtk_clk_unregister_pllfh(clk_data->hws[pll->id]);
262 		} else {
263 			base = mtk_clk_pll_get_base(clk_data->hws[pll->id],
264 						    pll);
265 			mtk_clk_unregister_pll(clk_data->hws[pll->id]);
266 		}
267 
268 		clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
269 	}
270 
271 	if (fhctl_base)
272 		iounmap(fhctl_base);
273 
274 	iounmap(base);
275 }
276