1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: James Liao <jamesjj.liao@mediatek.com> 5 */ 6 7 #ifndef __DRV_CLK_MTK_PLL_H 8 #define __DRV_CLK_MTK_PLL_H 9 10 #include <linux/types.h> 11 12 struct clk_ops; 13 struct clk_onecell_data; 14 struct device_node; 15 16 struct mtk_pll_div_table { 17 u32 div; 18 unsigned long freq; 19 }; 20 21 #define HAVE_RST_BAR BIT(0) 22 #define PLL_AO BIT(1) 23 24 struct mtk_pll_data { 25 int id; 26 const char *name; 27 u32 reg; 28 u32 pwr_reg; 29 u32 en_mask; 30 u32 pd_reg; 31 u32 tuner_reg; 32 u32 tuner_en_reg; 33 u8 tuner_en_bit; 34 int pd_shift; 35 unsigned int flags; 36 const struct clk_ops *ops; 37 u32 rst_bar_mask; 38 unsigned long fmin; 39 unsigned long fmax; 40 int pcwbits; 41 int pcwibits; 42 u32 pcw_reg; 43 int pcw_shift; 44 u32 pcw_chg_reg; 45 const struct mtk_pll_div_table *div_table; 46 const char *parent_name; 47 u32 en_reg; 48 u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ 49 }; 50 51 void mtk_clk_register_plls(struct device_node *node, 52 const struct mtk_pll_data *plls, int num_plls, 53 struct clk_onecell_data *clk_data); 54 void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls, 55 struct clk_onecell_data *clk_data); 56 57 #endif /* __DRV_CLK_MTK_PLL_H */ 58