1*39691fb6SChen-Yu Tsai /* SPDX-License-Identifier: GPL-2.0-only */ 2*39691fb6SChen-Yu Tsai /* 3*39691fb6SChen-Yu Tsai * Copyright (c) 2014 MediaTek Inc. 4*39691fb6SChen-Yu Tsai * Author: James Liao <jamesjj.liao@mediatek.com> 5*39691fb6SChen-Yu Tsai */ 6*39691fb6SChen-Yu Tsai 7*39691fb6SChen-Yu Tsai #ifndef __DRV_CLK_MTK_PLL_H 8*39691fb6SChen-Yu Tsai #define __DRV_CLK_MTK_PLL_H 9*39691fb6SChen-Yu Tsai 10*39691fb6SChen-Yu Tsai #include <linux/types.h> 11*39691fb6SChen-Yu Tsai 12*39691fb6SChen-Yu Tsai struct clk_ops; 13*39691fb6SChen-Yu Tsai struct clk_onecell_data; 14*39691fb6SChen-Yu Tsai struct device_node; 15*39691fb6SChen-Yu Tsai 16*39691fb6SChen-Yu Tsai struct mtk_pll_div_table { 17*39691fb6SChen-Yu Tsai u32 div; 18*39691fb6SChen-Yu Tsai unsigned long freq; 19*39691fb6SChen-Yu Tsai }; 20*39691fb6SChen-Yu Tsai 21*39691fb6SChen-Yu Tsai #define HAVE_RST_BAR BIT(0) 22*39691fb6SChen-Yu Tsai #define PLL_AO BIT(1) 23*39691fb6SChen-Yu Tsai 24*39691fb6SChen-Yu Tsai struct mtk_pll_data { 25*39691fb6SChen-Yu Tsai int id; 26*39691fb6SChen-Yu Tsai const char *name; 27*39691fb6SChen-Yu Tsai u32 reg; 28*39691fb6SChen-Yu Tsai u32 pwr_reg; 29*39691fb6SChen-Yu Tsai u32 en_mask; 30*39691fb6SChen-Yu Tsai u32 pd_reg; 31*39691fb6SChen-Yu Tsai u32 tuner_reg; 32*39691fb6SChen-Yu Tsai u32 tuner_en_reg; 33*39691fb6SChen-Yu Tsai u8 tuner_en_bit; 34*39691fb6SChen-Yu Tsai int pd_shift; 35*39691fb6SChen-Yu Tsai unsigned int flags; 36*39691fb6SChen-Yu Tsai const struct clk_ops *ops; 37*39691fb6SChen-Yu Tsai u32 rst_bar_mask; 38*39691fb6SChen-Yu Tsai unsigned long fmin; 39*39691fb6SChen-Yu Tsai unsigned long fmax; 40*39691fb6SChen-Yu Tsai int pcwbits; 41*39691fb6SChen-Yu Tsai int pcwibits; 42*39691fb6SChen-Yu Tsai u32 pcw_reg; 43*39691fb6SChen-Yu Tsai int pcw_shift; 44*39691fb6SChen-Yu Tsai u32 pcw_chg_reg; 45*39691fb6SChen-Yu Tsai const struct mtk_pll_div_table *div_table; 46*39691fb6SChen-Yu Tsai const char *parent_name; 47*39691fb6SChen-Yu Tsai u32 en_reg; 48*39691fb6SChen-Yu Tsai u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */ 49*39691fb6SChen-Yu Tsai }; 50*39691fb6SChen-Yu Tsai 51*39691fb6SChen-Yu Tsai void mtk_clk_register_plls(struct device_node *node, 52*39691fb6SChen-Yu Tsai const struct mtk_pll_data *plls, int num_plls, 53*39691fb6SChen-Yu Tsai struct clk_onecell_data *clk_data); 54*39691fb6SChen-Yu Tsai 55*39691fb6SChen-Yu Tsai #endif /* __DRV_CLK_MTK_PLL_H */ 56