1 /* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: James Liao <jamesjj.liao@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/clkdev.h> 20 #include <linux/delay.h> 21 22 #include "clk-mtk.h" 23 24 #define REG_CON0 0 25 #define REG_CON1 4 26 27 #define CON0_BASE_EN BIT(0) 28 #define CON0_PWR_ON BIT(0) 29 #define CON0_ISO_EN BIT(1) 30 #define PCW_CHG_MASK BIT(31) 31 32 #define AUDPLL_TUNER_EN BIT(31) 33 34 #define POSTDIV_MASK 0x7 35 36 /* default 7 bits integer, can be overridden with pcwibits. */ 37 #define INTEGER_BITS 7 38 39 /* 40 * MediaTek PLLs are configured through their pcw value. The pcw value describes 41 * a divider in the PLL feedback loop which consists of 7 bits for the integer 42 * part and the remaining bits (if present) for the fractional part. Also they 43 * have a 3 bit power-of-two post divider. 44 */ 45 46 struct mtk_clk_pll { 47 struct clk_hw hw; 48 void __iomem *base_addr; 49 void __iomem *pd_addr; 50 void __iomem *pwr_addr; 51 void __iomem *tuner_addr; 52 void __iomem *tuner_en_addr; 53 void __iomem *pcw_addr; 54 void __iomem *pcw_chg_addr; 55 const struct mtk_pll_data *data; 56 }; 57 58 static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw) 59 { 60 return container_of(hw, struct mtk_clk_pll, hw); 61 } 62 63 static int mtk_pll_is_prepared(struct clk_hw *hw) 64 { 65 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 66 67 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; 68 } 69 70 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, 71 u32 pcw, int postdiv) 72 { 73 int pcwbits = pll->data->pcwbits; 74 int pcwfbits = 0; 75 int ibits; 76 u64 vco; 77 u8 c = 0; 78 79 /* The fractional part of the PLL divider. */ 80 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; 81 if (pcwbits > ibits) 82 pcwfbits = pcwbits - ibits; 83 84 vco = (u64)fin * pcw; 85 86 if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0))) 87 c = 1; 88 89 vco >>= pcwfbits; 90 91 if (c) 92 vco++; 93 94 return ((unsigned long)vco + postdiv - 1) / postdiv; 95 } 96 97 static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll) 98 { 99 u32 r; 100 101 if (pll->tuner_en_addr) { 102 r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); 103 writel(r, pll->tuner_en_addr); 104 } else if (pll->tuner_addr) { 105 r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; 106 writel(r, pll->tuner_addr); 107 } 108 } 109 110 static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll) 111 { 112 u32 r; 113 114 if (pll->tuner_en_addr) { 115 r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit); 116 writel(r, pll->tuner_en_addr); 117 } else if (pll->tuner_addr) { 118 r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; 119 writel(r, pll->tuner_addr); 120 } 121 } 122 123 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, 124 int postdiv) 125 { 126 u32 chg, val; 127 128 /* disable tuner */ 129 __mtk_pll_tuner_disable(pll); 130 131 /* set postdiv */ 132 val = readl(pll->pd_addr); 133 val &= ~(POSTDIV_MASK << pll->data->pd_shift); 134 val |= (ffs(postdiv) - 1) << pll->data->pd_shift; 135 136 /* postdiv and pcw need to set at the same time if on same register */ 137 if (pll->pd_addr != pll->pcw_addr) { 138 writel(val, pll->pd_addr); 139 val = readl(pll->pcw_addr); 140 } 141 142 /* set pcw */ 143 val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1, 144 pll->data->pcw_shift); 145 val |= pcw << pll->data->pcw_shift; 146 writel(val, pll->pcw_addr); 147 chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; 148 writel(chg, pll->pcw_chg_addr); 149 if (pll->tuner_addr) 150 writel(val + 1, pll->tuner_addr); 151 152 /* restore tuner_en */ 153 __mtk_pll_tuner_enable(pll); 154 155 udelay(20); 156 } 157 158 /* 159 * mtk_pll_calc_values - calculate good values for a given input frequency. 160 * @pll: The pll 161 * @pcw: The pcw value (output) 162 * @postdiv: The post divider (output) 163 * @freq: The desired target frequency 164 * @fin: The input frequency 165 * 166 */ 167 static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, 168 u32 freq, u32 fin) 169 { 170 unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ); 171 const struct mtk_pll_div_table *div_table = pll->data->div_table; 172 u64 _pcw; 173 int ibits; 174 u32 val; 175 176 if (freq > pll->data->fmax) 177 freq = pll->data->fmax; 178 179 if (div_table) { 180 if (freq > div_table[0].freq) 181 freq = div_table[0].freq; 182 183 for (val = 0; div_table[val + 1].freq != 0; val++) { 184 if (freq > div_table[val + 1].freq) 185 break; 186 } 187 *postdiv = 1 << val; 188 } else { 189 for (val = 0; val < 5; val++) { 190 *postdiv = 1 << val; 191 if ((u64)freq * *postdiv >= fmin) 192 break; 193 } 194 } 195 196 /* _pcw = freq * postdiv / fin * 2^pcwfbits */ 197 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; 198 _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits); 199 do_div(_pcw, fin); 200 201 *pcw = (u32)_pcw; 202 } 203 204 static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 205 unsigned long parent_rate) 206 { 207 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 208 u32 pcw = 0; 209 u32 postdiv; 210 211 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); 212 mtk_pll_set_rate_regs(pll, pcw, postdiv); 213 214 return 0; 215 } 216 217 static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, 218 unsigned long parent_rate) 219 { 220 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 221 u32 postdiv; 222 u32 pcw; 223 224 postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK; 225 postdiv = 1 << postdiv; 226 227 pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift; 228 pcw &= GENMASK(pll->data->pcwbits - 1, 0); 229 230 return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv); 231 } 232 233 static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 234 unsigned long *prate) 235 { 236 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 237 u32 pcw = 0; 238 int postdiv; 239 240 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate); 241 242 return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv); 243 } 244 245 static int mtk_pll_prepare(struct clk_hw *hw) 246 { 247 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 248 u32 r; 249 250 r = readl(pll->pwr_addr) | CON0_PWR_ON; 251 writel(r, pll->pwr_addr); 252 udelay(1); 253 254 r = readl(pll->pwr_addr) & ~CON0_ISO_EN; 255 writel(r, pll->pwr_addr); 256 udelay(1); 257 258 r = readl(pll->base_addr + REG_CON0); 259 r |= pll->data->en_mask; 260 writel(r, pll->base_addr + REG_CON0); 261 262 __mtk_pll_tuner_enable(pll); 263 264 udelay(20); 265 266 if (pll->data->flags & HAVE_RST_BAR) { 267 r = readl(pll->base_addr + REG_CON0); 268 r |= pll->data->rst_bar_mask; 269 writel(r, pll->base_addr + REG_CON0); 270 } 271 272 return 0; 273 } 274 275 static void mtk_pll_unprepare(struct clk_hw *hw) 276 { 277 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 278 u32 r; 279 280 if (pll->data->flags & HAVE_RST_BAR) { 281 r = readl(pll->base_addr + REG_CON0); 282 r &= ~pll->data->rst_bar_mask; 283 writel(r, pll->base_addr + REG_CON0); 284 } 285 286 __mtk_pll_tuner_disable(pll); 287 288 r = readl(pll->base_addr + REG_CON0); 289 r &= ~CON0_BASE_EN; 290 writel(r, pll->base_addr + REG_CON0); 291 292 r = readl(pll->pwr_addr) | CON0_ISO_EN; 293 writel(r, pll->pwr_addr); 294 295 r = readl(pll->pwr_addr) & ~CON0_PWR_ON; 296 writel(r, pll->pwr_addr); 297 } 298 299 static const struct clk_ops mtk_pll_ops = { 300 .is_prepared = mtk_pll_is_prepared, 301 .prepare = mtk_pll_prepare, 302 .unprepare = mtk_pll_unprepare, 303 .recalc_rate = mtk_pll_recalc_rate, 304 .round_rate = mtk_pll_round_rate, 305 .set_rate = mtk_pll_set_rate, 306 }; 307 308 static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data, 309 void __iomem *base) 310 { 311 struct mtk_clk_pll *pll; 312 struct clk_init_data init = {}; 313 struct clk *clk; 314 const char *parent_name = "clk26m"; 315 316 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 317 if (!pll) 318 return ERR_PTR(-ENOMEM); 319 320 pll->base_addr = base + data->reg; 321 pll->pwr_addr = base + data->pwr_reg; 322 pll->pd_addr = base + data->pd_reg; 323 pll->pcw_addr = base + data->pcw_reg; 324 if (data->pcw_chg_reg) 325 pll->pcw_chg_addr = base + data->pcw_chg_reg; 326 else 327 pll->pcw_chg_addr = pll->base_addr + REG_CON1; 328 if (data->tuner_reg) 329 pll->tuner_addr = base + data->tuner_reg; 330 if (data->tuner_en_reg) 331 pll->tuner_en_addr = base + data->tuner_en_reg; 332 pll->hw.init = &init; 333 pll->data = data; 334 335 init.name = data->name; 336 init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0; 337 init.ops = &mtk_pll_ops; 338 if (data->parent_name) 339 init.parent_names = &data->parent_name; 340 else 341 init.parent_names = &parent_name; 342 init.num_parents = 1; 343 344 clk = clk_register(NULL, &pll->hw); 345 346 if (IS_ERR(clk)) 347 kfree(pll); 348 349 return clk; 350 } 351 352 void mtk_clk_register_plls(struct device_node *node, 353 const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data) 354 { 355 void __iomem *base; 356 int i; 357 struct clk *clk; 358 359 base = of_iomap(node, 0); 360 if (!base) { 361 pr_err("%s(): ioremap failed\n", __func__); 362 return; 363 } 364 365 for (i = 0; i < num_plls; i++) { 366 const struct mtk_pll_data *pll = &plls[i]; 367 368 clk = mtk_clk_register_pll(pll, base); 369 370 if (IS_ERR(clk)) { 371 pr_err("Failed to register clk %s: %ld\n", 372 pll->name, PTR_ERR(clk)); 373 continue; 374 } 375 376 clk_data->clks[pll->id] = clk; 377 } 378 } 379