19741b1a6SJames Liao /* 29741b1a6SJames Liao * Copyright (c) 2014 MediaTek Inc. 39741b1a6SJames Liao * Author: James Liao <jamesjj.liao@mediatek.com> 49741b1a6SJames Liao * 59741b1a6SJames Liao * This program is free software; you can redistribute it and/or modify 69741b1a6SJames Liao * it under the terms of the GNU General Public License version 2 as 79741b1a6SJames Liao * published by the Free Software Foundation. 89741b1a6SJames Liao * 99741b1a6SJames Liao * This program is distributed in the hope that it will be useful, 109741b1a6SJames Liao * but WITHOUT ANY WARRANTY; without even the implied warranty of 119741b1a6SJames Liao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 129741b1a6SJames Liao * GNU General Public License for more details. 139741b1a6SJames Liao */ 149741b1a6SJames Liao 159741b1a6SJames Liao #include <linux/of.h> 169741b1a6SJames Liao #include <linux/of_address.h> 179741b1a6SJames Liao #include <linux/io.h> 189741b1a6SJames Liao #include <linux/slab.h> 199741b1a6SJames Liao #include <linux/clkdev.h> 209741b1a6SJames Liao #include <linux/delay.h> 219741b1a6SJames Liao 229741b1a6SJames Liao #include "clk-mtk.h" 239741b1a6SJames Liao 249741b1a6SJames Liao #define REG_CON0 0 259741b1a6SJames Liao #define REG_CON1 4 269741b1a6SJames Liao 279741b1a6SJames Liao #define CON0_BASE_EN BIT(0) 289741b1a6SJames Liao #define CON0_PWR_ON BIT(0) 299741b1a6SJames Liao #define CON0_ISO_EN BIT(1) 309741b1a6SJames Liao #define CON0_PCW_CHG BIT(31) 319741b1a6SJames Liao 329741b1a6SJames Liao #define AUDPLL_TUNER_EN BIT(31) 339741b1a6SJames Liao 349741b1a6SJames Liao #define POSTDIV_MASK 0x7 359741b1a6SJames Liao #define INTEGER_BITS 7 369741b1a6SJames Liao 379741b1a6SJames Liao /* 389741b1a6SJames Liao * MediaTek PLLs are configured through their pcw value. The pcw value describes 399741b1a6SJames Liao * a divider in the PLL feedback loop which consists of 7 bits for the integer 409741b1a6SJames Liao * part and the remaining bits (if present) for the fractional part. Also they 419741b1a6SJames Liao * have a 3 bit power-of-two post divider. 429741b1a6SJames Liao */ 439741b1a6SJames Liao 449741b1a6SJames Liao struct mtk_clk_pll { 459741b1a6SJames Liao struct clk_hw hw; 469741b1a6SJames Liao void __iomem *base_addr; 479741b1a6SJames Liao void __iomem *pd_addr; 489741b1a6SJames Liao void __iomem *pwr_addr; 499741b1a6SJames Liao void __iomem *tuner_addr; 509741b1a6SJames Liao void __iomem *pcw_addr; 519741b1a6SJames Liao const struct mtk_pll_data *data; 529741b1a6SJames Liao }; 539741b1a6SJames Liao 549741b1a6SJames Liao static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw) 559741b1a6SJames Liao { 569741b1a6SJames Liao return container_of(hw, struct mtk_clk_pll, hw); 579741b1a6SJames Liao } 589741b1a6SJames Liao 599741b1a6SJames Liao static int mtk_pll_is_prepared(struct clk_hw *hw) 609741b1a6SJames Liao { 619741b1a6SJames Liao struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 629741b1a6SJames Liao 639741b1a6SJames Liao return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; 649741b1a6SJames Liao } 659741b1a6SJames Liao 669741b1a6SJames Liao static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, 679741b1a6SJames Liao u32 pcw, int postdiv) 689741b1a6SJames Liao { 699741b1a6SJames Liao int pcwbits = pll->data->pcwbits; 709741b1a6SJames Liao int pcwfbits; 719741b1a6SJames Liao u64 vco; 729741b1a6SJames Liao u8 c = 0; 739741b1a6SJames Liao 749741b1a6SJames Liao /* The fractional part of the PLL divider. */ 759741b1a6SJames Liao pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0; 769741b1a6SJames Liao 779741b1a6SJames Liao vco = (u64)fin * pcw; 789741b1a6SJames Liao 799741b1a6SJames Liao if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0))) 809741b1a6SJames Liao c = 1; 819741b1a6SJames Liao 829741b1a6SJames Liao vco >>= pcwfbits; 839741b1a6SJames Liao 849741b1a6SJames Liao if (c) 859741b1a6SJames Liao vco++; 869741b1a6SJames Liao 879741b1a6SJames Liao return ((unsigned long)vco + postdiv - 1) / postdiv; 889741b1a6SJames Liao } 899741b1a6SJames Liao 909741b1a6SJames Liao static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, 919741b1a6SJames Liao int postdiv) 929741b1a6SJames Liao { 93b3be457eSJames Liao u32 con1, val; 949741b1a6SJames Liao int pll_en; 959741b1a6SJames Liao 969741b1a6SJames Liao pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; 979741b1a6SJames Liao 98b3be457eSJames Liao /* set postdiv */ 99b3be457eSJames Liao val = readl(pll->pd_addr); 100b3be457eSJames Liao val &= ~(POSTDIV_MASK << pll->data->pd_shift); 101b3be457eSJames Liao val |= (ffs(postdiv) - 1) << pll->data->pd_shift; 1029741b1a6SJames Liao 103b3be457eSJames Liao /* postdiv and pcw need to set at the same time if on same register */ 104b3be457eSJames Liao if (pll->pd_addr != pll->pcw_addr) { 105b3be457eSJames Liao writel(val, pll->pd_addr); 106b3be457eSJames Liao val = readl(pll->pcw_addr); 107b3be457eSJames Liao } 108b3be457eSJames Liao 109b3be457eSJames Liao /* set pcw */ 1109741b1a6SJames Liao val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1, 1119741b1a6SJames Liao pll->data->pcw_shift); 1129741b1a6SJames Liao val |= pcw << pll->data->pcw_shift; 1139741b1a6SJames Liao writel(val, pll->pcw_addr); 1149741b1a6SJames Liao 1159741b1a6SJames Liao con1 = readl(pll->base_addr + REG_CON1); 1169741b1a6SJames Liao 1179741b1a6SJames Liao if (pll_en) 1189741b1a6SJames Liao con1 |= CON0_PCW_CHG; 1199741b1a6SJames Liao 1209741b1a6SJames Liao writel(con1, pll->base_addr + REG_CON1); 1219741b1a6SJames Liao if (pll->tuner_addr) 1229741b1a6SJames Liao writel(con1 + 1, pll->tuner_addr); 1239741b1a6SJames Liao 1249741b1a6SJames Liao if (pll_en) 1259741b1a6SJames Liao udelay(20); 1269741b1a6SJames Liao } 1279741b1a6SJames Liao 1289741b1a6SJames Liao /* 1299741b1a6SJames Liao * mtk_pll_calc_values - calculate good values for a given input frequency. 1309741b1a6SJames Liao * @pll: The pll 1319741b1a6SJames Liao * @pcw: The pcw value (output) 1329741b1a6SJames Liao * @postdiv: The post divider (output) 1339741b1a6SJames Liao * @freq: The desired target frequency 1349741b1a6SJames Liao * @fin: The input frequency 1359741b1a6SJames Liao * 1369741b1a6SJames Liao */ 1379741b1a6SJames Liao static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, 1389741b1a6SJames Liao u32 freq, u32 fin) 1399741b1a6SJames Liao { 1409741b1a6SJames Liao unsigned long fmin = 1000 * MHZ; 14175ce0cdbSJames Liao const struct mtk_pll_div_table *div_table = pll->data->div_table; 1429741b1a6SJames Liao u64 _pcw; 1439741b1a6SJames Liao u32 val; 1449741b1a6SJames Liao 1459741b1a6SJames Liao if (freq > pll->data->fmax) 1469741b1a6SJames Liao freq = pll->data->fmax; 1479741b1a6SJames Liao 14875ce0cdbSJames Liao if (div_table) { 14975ce0cdbSJames Liao if (freq > div_table[0].freq) 15075ce0cdbSJames Liao freq = div_table[0].freq; 15175ce0cdbSJames Liao 15275ce0cdbSJames Liao for (val = 0; div_table[val + 1].freq != 0; val++) { 15375ce0cdbSJames Liao if (freq > div_table[val + 1].freq) 15475ce0cdbSJames Liao break; 15575ce0cdbSJames Liao } 15675ce0cdbSJames Liao *postdiv = 1 << val; 15775ce0cdbSJames Liao } else { 158196de71aSJames Liao for (val = 0; val < 5; val++) { 1599741b1a6SJames Liao *postdiv = 1 << val; 160196de71aSJames Liao if ((u64)freq * *postdiv >= fmin) 1619741b1a6SJames Liao break; 1629741b1a6SJames Liao } 16375ce0cdbSJames Liao } 1649741b1a6SJames Liao 1659741b1a6SJames Liao /* _pcw = freq * postdiv / fin * 2^pcwfbits */ 1669741b1a6SJames Liao _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS); 1679741b1a6SJames Liao do_div(_pcw, fin); 1689741b1a6SJames Liao 1699741b1a6SJames Liao *pcw = (u32)_pcw; 1709741b1a6SJames Liao } 1719741b1a6SJames Liao 1729741b1a6SJames Liao static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 1739741b1a6SJames Liao unsigned long parent_rate) 1749741b1a6SJames Liao { 1759741b1a6SJames Liao struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 1769741b1a6SJames Liao u32 pcw = 0; 1779741b1a6SJames Liao u32 postdiv; 1789741b1a6SJames Liao 1799741b1a6SJames Liao mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); 1809741b1a6SJames Liao mtk_pll_set_rate_regs(pll, pcw, postdiv); 1819741b1a6SJames Liao 1829741b1a6SJames Liao return 0; 1839741b1a6SJames Liao } 1849741b1a6SJames Liao 1859741b1a6SJames Liao static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, 1869741b1a6SJames Liao unsigned long parent_rate) 1879741b1a6SJames Liao { 1889741b1a6SJames Liao struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 1899741b1a6SJames Liao u32 postdiv; 1909741b1a6SJames Liao u32 pcw; 1919741b1a6SJames Liao 1929741b1a6SJames Liao postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK; 1939741b1a6SJames Liao postdiv = 1 << postdiv; 1949741b1a6SJames Liao 1959741b1a6SJames Liao pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift; 1969741b1a6SJames Liao pcw &= GENMASK(pll->data->pcwbits - 1, 0); 1979741b1a6SJames Liao 1989741b1a6SJames Liao return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv); 1999741b1a6SJames Liao } 2009741b1a6SJames Liao 2019741b1a6SJames Liao static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 2029741b1a6SJames Liao unsigned long *prate) 2039741b1a6SJames Liao { 2049741b1a6SJames Liao struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 2059741b1a6SJames Liao u32 pcw = 0; 2069741b1a6SJames Liao int postdiv; 2079741b1a6SJames Liao 2089741b1a6SJames Liao mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate); 2099741b1a6SJames Liao 2109741b1a6SJames Liao return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv); 2119741b1a6SJames Liao } 2129741b1a6SJames Liao 2139741b1a6SJames Liao static int mtk_pll_prepare(struct clk_hw *hw) 2149741b1a6SJames Liao { 2159741b1a6SJames Liao struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 2169741b1a6SJames Liao u32 r; 2179741b1a6SJames Liao 2189741b1a6SJames Liao r = readl(pll->pwr_addr) | CON0_PWR_ON; 2199741b1a6SJames Liao writel(r, pll->pwr_addr); 2209741b1a6SJames Liao udelay(1); 2219741b1a6SJames Liao 2229741b1a6SJames Liao r = readl(pll->pwr_addr) & ~CON0_ISO_EN; 2239741b1a6SJames Liao writel(r, pll->pwr_addr); 2249741b1a6SJames Liao udelay(1); 2259741b1a6SJames Liao 2269741b1a6SJames Liao r = readl(pll->base_addr + REG_CON0); 2279741b1a6SJames Liao r |= pll->data->en_mask; 2289741b1a6SJames Liao writel(r, pll->base_addr + REG_CON0); 2299741b1a6SJames Liao 2309741b1a6SJames Liao if (pll->tuner_addr) { 2319741b1a6SJames Liao r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; 2329741b1a6SJames Liao writel(r, pll->tuner_addr); 2339741b1a6SJames Liao } 2349741b1a6SJames Liao 2359741b1a6SJames Liao udelay(20); 2369741b1a6SJames Liao 2379741b1a6SJames Liao if (pll->data->flags & HAVE_RST_BAR) { 2389741b1a6SJames Liao r = readl(pll->base_addr + REG_CON0); 2399741b1a6SJames Liao r |= pll->data->rst_bar_mask; 2409741b1a6SJames Liao writel(r, pll->base_addr + REG_CON0); 2419741b1a6SJames Liao } 2429741b1a6SJames Liao 2439741b1a6SJames Liao return 0; 2449741b1a6SJames Liao } 2459741b1a6SJames Liao 2469741b1a6SJames Liao static void mtk_pll_unprepare(struct clk_hw *hw) 2479741b1a6SJames Liao { 2489741b1a6SJames Liao struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 2499741b1a6SJames Liao u32 r; 2509741b1a6SJames Liao 2519741b1a6SJames Liao if (pll->data->flags & HAVE_RST_BAR) { 2529741b1a6SJames Liao r = readl(pll->base_addr + REG_CON0); 2539741b1a6SJames Liao r &= ~pll->data->rst_bar_mask; 2549741b1a6SJames Liao writel(r, pll->base_addr + REG_CON0); 2559741b1a6SJames Liao } 2569741b1a6SJames Liao 2579741b1a6SJames Liao if (pll->tuner_addr) { 2589741b1a6SJames Liao r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; 2599741b1a6SJames Liao writel(r, pll->tuner_addr); 2609741b1a6SJames Liao } 2619741b1a6SJames Liao 2629741b1a6SJames Liao r = readl(pll->base_addr + REG_CON0); 2639741b1a6SJames Liao r &= ~CON0_BASE_EN; 2649741b1a6SJames Liao writel(r, pll->base_addr + REG_CON0); 2659741b1a6SJames Liao 2669741b1a6SJames Liao r = readl(pll->pwr_addr) | CON0_ISO_EN; 2679741b1a6SJames Liao writel(r, pll->pwr_addr); 2689741b1a6SJames Liao 2699741b1a6SJames Liao r = readl(pll->pwr_addr) & ~CON0_PWR_ON; 2709741b1a6SJames Liao writel(r, pll->pwr_addr); 2719741b1a6SJames Liao } 2729741b1a6SJames Liao 2739741b1a6SJames Liao static const struct clk_ops mtk_pll_ops = { 2749741b1a6SJames Liao .is_prepared = mtk_pll_is_prepared, 2759741b1a6SJames Liao .prepare = mtk_pll_prepare, 2769741b1a6SJames Liao .unprepare = mtk_pll_unprepare, 2779741b1a6SJames Liao .recalc_rate = mtk_pll_recalc_rate, 2789741b1a6SJames Liao .round_rate = mtk_pll_round_rate, 2799741b1a6SJames Liao .set_rate = mtk_pll_set_rate, 2809741b1a6SJames Liao }; 2819741b1a6SJames Liao 2829741b1a6SJames Liao static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data, 2839741b1a6SJames Liao void __iomem *base) 2849741b1a6SJames Liao { 2859741b1a6SJames Liao struct mtk_clk_pll *pll; 28695f58981SRicky Liang struct clk_init_data init = {}; 2879741b1a6SJames Liao struct clk *clk; 2889741b1a6SJames Liao const char *parent_name = "clk26m"; 2899741b1a6SJames Liao 2909741b1a6SJames Liao pll = kzalloc(sizeof(*pll), GFP_KERNEL); 2919741b1a6SJames Liao if (!pll) 2929741b1a6SJames Liao return ERR_PTR(-ENOMEM); 2939741b1a6SJames Liao 2949741b1a6SJames Liao pll->base_addr = base + data->reg; 2959741b1a6SJames Liao pll->pwr_addr = base + data->pwr_reg; 2969741b1a6SJames Liao pll->pd_addr = base + data->pd_reg; 2979741b1a6SJames Liao pll->pcw_addr = base + data->pcw_reg; 2989741b1a6SJames Liao if (data->tuner_reg) 2999741b1a6SJames Liao pll->tuner_addr = base + data->tuner_reg; 3009741b1a6SJames Liao pll->hw.init = &init; 3019741b1a6SJames Liao pll->data = data; 3029741b1a6SJames Liao 3039741b1a6SJames Liao init.name = data->name; 3049741b1a6SJames Liao init.ops = &mtk_pll_ops; 3059741b1a6SJames Liao init.parent_names = &parent_name; 3069741b1a6SJames Liao init.num_parents = 1; 3079741b1a6SJames Liao 3089741b1a6SJames Liao clk = clk_register(NULL, &pll->hw); 3099741b1a6SJames Liao 3109741b1a6SJames Liao if (IS_ERR(clk)) 3119741b1a6SJames Liao kfree(pll); 3129741b1a6SJames Liao 3139741b1a6SJames Liao return clk; 3149741b1a6SJames Liao } 3159741b1a6SJames Liao 316928f3bfbSJames Liao void mtk_clk_register_plls(struct device_node *node, 3179741b1a6SJames Liao const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data) 3189741b1a6SJames Liao { 3199741b1a6SJames Liao void __iomem *base; 320cdb2bab7SJames Liao int i; 3219741b1a6SJames Liao struct clk *clk; 3229741b1a6SJames Liao 3239741b1a6SJames Liao base = of_iomap(node, 0); 3249741b1a6SJames Liao if (!base) { 3259741b1a6SJames Liao pr_err("%s(): ioremap failed\n", __func__); 3269741b1a6SJames Liao return; 3279741b1a6SJames Liao } 3289741b1a6SJames Liao 3299741b1a6SJames Liao for (i = 0; i < num_plls; i++) { 3309741b1a6SJames Liao const struct mtk_pll_data *pll = &plls[i]; 3319741b1a6SJames Liao 3329741b1a6SJames Liao clk = mtk_clk_register_pll(pll, base); 3339741b1a6SJames Liao 3349741b1a6SJames Liao if (IS_ERR(clk)) { 3359741b1a6SJames Liao pr_err("Failed to register clk %s: %ld\n", 3369741b1a6SJames Liao pll->name, PTR_ERR(clk)); 3379741b1a6SJames Liao continue; 3389741b1a6SJames Liao } 3399741b1a6SJames Liao 3409741b1a6SJames Liao clk_data->clks[pll->id] = clk; 3419741b1a6SJames Liao } 3429741b1a6SJames Liao } 343