11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 29741b1a6SJames Liao /* 39741b1a6SJames Liao * Copyright (c) 2014 MediaTek Inc. 49741b1a6SJames Liao * Author: James Liao <jamesjj.liao@mediatek.com> 59741b1a6SJames Liao */ 69741b1a6SJames Liao 79741b1a6SJames Liao #include <linux/of.h> 89741b1a6SJames Liao #include <linux/of_address.h> 99741b1a6SJames Liao #include <linux/io.h> 1032b028fbSMiles Chen #include <linux/module.h> 119741b1a6SJames Liao #include <linux/slab.h> 129741b1a6SJames Liao #include <linux/clkdev.h> 139741b1a6SJames Liao #include <linux/delay.h> 149741b1a6SJames Liao 159741b1a6SJames Liao #include "clk-mtk.h" 1639691fb6SChen-Yu Tsai #include "clk-pll.h" 179741b1a6SJames Liao 189741b1a6SJames Liao #define REG_CON0 0 199741b1a6SJames Liao #define REG_CON1 4 209741b1a6SJames Liao 219741b1a6SJames Liao #define CON0_BASE_EN BIT(0) 229741b1a6SJames Liao #define CON0_PWR_ON BIT(0) 239741b1a6SJames Liao #define CON0_ISO_EN BIT(1) 2423fe31deSWeiyi Lu #define PCW_CHG_MASK BIT(31) 259741b1a6SJames Liao 269741b1a6SJames Liao #define AUDPLL_TUNER_EN BIT(31) 279741b1a6SJames Liao 289741b1a6SJames Liao #define POSTDIV_MASK 0x7 299d7e1a82SOwen Chen 309d7e1a82SOwen Chen /* default 7 bits integer, can be overridden with pcwibits. */ 319741b1a6SJames Liao #define INTEGER_BITS 7 329741b1a6SJames Liao 339741b1a6SJames Liao /* 349741b1a6SJames Liao * MediaTek PLLs are configured through their pcw value. The pcw value describes 359741b1a6SJames Liao * a divider in the PLL feedback loop which consists of 7 bits for the integer 369741b1a6SJames Liao * part and the remaining bits (if present) for the fractional part. Also they 379741b1a6SJames Liao * have a 3 bit power-of-two post divider. 389741b1a6SJames Liao */ 399741b1a6SJames Liao 409741b1a6SJames Liao struct mtk_clk_pll { 419741b1a6SJames Liao struct clk_hw hw; 429741b1a6SJames Liao void __iomem *base_addr; 439741b1a6SJames Liao void __iomem *pd_addr; 449741b1a6SJames Liao void __iomem *pwr_addr; 459741b1a6SJames Liao void __iomem *tuner_addr; 46e2f744a8Sweiyi.lu@mediatek.com void __iomem *tuner_en_addr; 479741b1a6SJames Liao void __iomem *pcw_addr; 4823fe31deSWeiyi Lu void __iomem *pcw_chg_addr; 49f384c447SChun-Jie Chen void __iomem *en_addr; 509741b1a6SJames Liao const struct mtk_pll_data *data; 519741b1a6SJames Liao }; 529741b1a6SJames Liao 539741b1a6SJames Liao static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw) 549741b1a6SJames Liao { 559741b1a6SJames Liao return container_of(hw, struct mtk_clk_pll, hw); 569741b1a6SJames Liao } 579741b1a6SJames Liao 589741b1a6SJames Liao static int mtk_pll_is_prepared(struct clk_hw *hw) 599741b1a6SJames Liao { 609741b1a6SJames Liao struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 619741b1a6SJames Liao 62f384c447SChun-Jie Chen return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0; 639741b1a6SJames Liao } 649741b1a6SJames Liao 659741b1a6SJames Liao static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, 669741b1a6SJames Liao u32 pcw, int postdiv) 679741b1a6SJames Liao { 689741b1a6SJames Liao int pcwbits = pll->data->pcwbits; 699d7e1a82SOwen Chen int pcwfbits = 0; 709d7e1a82SOwen Chen int ibits; 719741b1a6SJames Liao u64 vco; 729741b1a6SJames Liao u8 c = 0; 739741b1a6SJames Liao 749741b1a6SJames Liao /* The fractional part of the PLL divider. */ 759d7e1a82SOwen Chen ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; 769d7e1a82SOwen Chen if (pcwbits > ibits) 779d7e1a82SOwen Chen pcwfbits = pcwbits - ibits; 789741b1a6SJames Liao 799741b1a6SJames Liao vco = (u64)fin * pcw; 809741b1a6SJames Liao 819741b1a6SJames Liao if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0))) 829741b1a6SJames Liao c = 1; 839741b1a6SJames Liao 849741b1a6SJames Liao vco >>= pcwfbits; 859741b1a6SJames Liao 869741b1a6SJames Liao if (c) 879741b1a6SJames Liao vco++; 889741b1a6SJames Liao 899741b1a6SJames Liao return ((unsigned long)vco + postdiv - 1) / postdiv; 909741b1a6SJames Liao } 919741b1a6SJames Liao 92be17ca6aSOwen Chen static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll) 93be17ca6aSOwen Chen { 94be17ca6aSOwen Chen u32 r; 95be17ca6aSOwen Chen 96be17ca6aSOwen Chen if (pll->tuner_en_addr) { 97be17ca6aSOwen Chen r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); 98be17ca6aSOwen Chen writel(r, pll->tuner_en_addr); 99be17ca6aSOwen Chen } else if (pll->tuner_addr) { 100be17ca6aSOwen Chen r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; 101be17ca6aSOwen Chen writel(r, pll->tuner_addr); 102be17ca6aSOwen Chen } 103be17ca6aSOwen Chen } 104be17ca6aSOwen Chen 105be17ca6aSOwen Chen static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll) 106be17ca6aSOwen Chen { 107be17ca6aSOwen Chen u32 r; 108be17ca6aSOwen Chen 109be17ca6aSOwen Chen if (pll->tuner_en_addr) { 110be17ca6aSOwen Chen r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit); 111be17ca6aSOwen Chen writel(r, pll->tuner_en_addr); 112be17ca6aSOwen Chen } else if (pll->tuner_addr) { 113be17ca6aSOwen Chen r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; 114be17ca6aSOwen Chen writel(r, pll->tuner_addr); 115be17ca6aSOwen Chen } 116be17ca6aSOwen Chen } 117be17ca6aSOwen Chen 1189741b1a6SJames Liao static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, 1199741b1a6SJames Liao int postdiv) 1209741b1a6SJames Liao { 12123fe31deSWeiyi Lu u32 chg, val; 1229741b1a6SJames Liao 123be17ca6aSOwen Chen /* disable tuner */ 124be17ca6aSOwen Chen __mtk_pll_tuner_disable(pll); 125be17ca6aSOwen Chen 126b3be457eSJames Liao /* set postdiv */ 127b3be457eSJames Liao val = readl(pll->pd_addr); 128b3be457eSJames Liao val &= ~(POSTDIV_MASK << pll->data->pd_shift); 129b3be457eSJames Liao val |= (ffs(postdiv) - 1) << pll->data->pd_shift; 1309741b1a6SJames Liao 131b3be457eSJames Liao /* postdiv and pcw need to set at the same time if on same register */ 132b3be457eSJames Liao if (pll->pd_addr != pll->pcw_addr) { 133b3be457eSJames Liao writel(val, pll->pd_addr); 134b3be457eSJames Liao val = readl(pll->pcw_addr); 135b3be457eSJames Liao } 136b3be457eSJames Liao 137b3be457eSJames Liao /* set pcw */ 1389741b1a6SJames Liao val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1, 1399741b1a6SJames Liao pll->data->pcw_shift); 1409741b1a6SJames Liao val |= pcw << pll->data->pcw_shift; 1419741b1a6SJames Liao writel(val, pll->pcw_addr); 142dac5d672SJames Liao chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; 14323fe31deSWeiyi Lu writel(chg, pll->pcw_chg_addr); 1449741b1a6SJames Liao if (pll->tuner_addr) 14523fe31deSWeiyi Lu writel(val + 1, pll->tuner_addr); 1469741b1a6SJames Liao 147be17ca6aSOwen Chen /* restore tuner_en */ 148be17ca6aSOwen Chen __mtk_pll_tuner_enable(pll); 149be17ca6aSOwen Chen 1509741b1a6SJames Liao udelay(20); 1519741b1a6SJames Liao } 1529741b1a6SJames Liao 1539741b1a6SJames Liao /* 1549741b1a6SJames Liao * mtk_pll_calc_values - calculate good values for a given input frequency. 1559741b1a6SJames Liao * @pll: The pll 1569741b1a6SJames Liao * @pcw: The pcw value (output) 1579741b1a6SJames Liao * @postdiv: The post divider (output) 1589741b1a6SJames Liao * @freq: The desired target frequency 1599741b1a6SJames Liao * @fin: The input frequency 1609741b1a6SJames Liao * 1619741b1a6SJames Liao */ 1629741b1a6SJames Liao static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, 1639741b1a6SJames Liao u32 freq, u32 fin) 1649741b1a6SJames Liao { 1659d7e1a82SOwen Chen unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ); 16675ce0cdbSJames Liao const struct mtk_pll_div_table *div_table = pll->data->div_table; 1679741b1a6SJames Liao u64 _pcw; 1689d7e1a82SOwen Chen int ibits; 1699741b1a6SJames Liao u32 val; 1709741b1a6SJames Liao 1719741b1a6SJames Liao if (freq > pll->data->fmax) 1729741b1a6SJames Liao freq = pll->data->fmax; 1739741b1a6SJames Liao 17475ce0cdbSJames Liao if (div_table) { 17575ce0cdbSJames Liao if (freq > div_table[0].freq) 17675ce0cdbSJames Liao freq = div_table[0].freq; 17775ce0cdbSJames Liao 17875ce0cdbSJames Liao for (val = 0; div_table[val + 1].freq != 0; val++) { 17975ce0cdbSJames Liao if (freq > div_table[val + 1].freq) 18075ce0cdbSJames Liao break; 18175ce0cdbSJames Liao } 18275ce0cdbSJames Liao *postdiv = 1 << val; 18375ce0cdbSJames Liao } else { 184196de71aSJames Liao for (val = 0; val < 5; val++) { 1859741b1a6SJames Liao *postdiv = 1 << val; 186196de71aSJames Liao if ((u64)freq * *postdiv >= fmin) 1879741b1a6SJames Liao break; 1889741b1a6SJames Liao } 18975ce0cdbSJames Liao } 1909741b1a6SJames Liao 1919741b1a6SJames Liao /* _pcw = freq * postdiv / fin * 2^pcwfbits */ 1929d7e1a82SOwen Chen ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; 1939d7e1a82SOwen Chen _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits); 1949741b1a6SJames Liao do_div(_pcw, fin); 1959741b1a6SJames Liao 1969741b1a6SJames Liao *pcw = (u32)_pcw; 1979741b1a6SJames Liao } 1989741b1a6SJames Liao 1999741b1a6SJames Liao static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 2009741b1a6SJames Liao unsigned long parent_rate) 2019741b1a6SJames Liao { 2029741b1a6SJames Liao struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 2039741b1a6SJames Liao u32 pcw = 0; 2049741b1a6SJames Liao u32 postdiv; 2059741b1a6SJames Liao 2069741b1a6SJames Liao mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); 2079741b1a6SJames Liao mtk_pll_set_rate_regs(pll, pcw, postdiv); 2089741b1a6SJames Liao 2099741b1a6SJames Liao return 0; 2109741b1a6SJames Liao } 2119741b1a6SJames Liao 2129741b1a6SJames Liao static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, 2139741b1a6SJames Liao unsigned long parent_rate) 2149741b1a6SJames Liao { 2159741b1a6SJames Liao struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 2169741b1a6SJames Liao u32 postdiv; 2179741b1a6SJames Liao u32 pcw; 2189741b1a6SJames Liao 2199741b1a6SJames Liao postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK; 2209741b1a6SJames Liao postdiv = 1 << postdiv; 2219741b1a6SJames Liao 2229741b1a6SJames Liao pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift; 2239741b1a6SJames Liao pcw &= GENMASK(pll->data->pcwbits - 1, 0); 2249741b1a6SJames Liao 2259741b1a6SJames Liao return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv); 2269741b1a6SJames Liao } 2279741b1a6SJames Liao 2289741b1a6SJames Liao static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate, 2299741b1a6SJames Liao unsigned long *prate) 2309741b1a6SJames Liao { 2319741b1a6SJames Liao struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 2329741b1a6SJames Liao u32 pcw = 0; 2339741b1a6SJames Liao int postdiv; 2349741b1a6SJames Liao 2359741b1a6SJames Liao mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate); 2369741b1a6SJames Liao 2379741b1a6SJames Liao return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv); 2389741b1a6SJames Liao } 2399741b1a6SJames Liao 2409741b1a6SJames Liao static int mtk_pll_prepare(struct clk_hw *hw) 2419741b1a6SJames Liao { 2429741b1a6SJames Liao struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 2439741b1a6SJames Liao u32 r; 2447cc4e1bbSChun-Jie Chen u32 div_en_mask; 2459741b1a6SJames Liao 2469741b1a6SJames Liao r = readl(pll->pwr_addr) | CON0_PWR_ON; 2479741b1a6SJames Liao writel(r, pll->pwr_addr); 2489741b1a6SJames Liao udelay(1); 2499741b1a6SJames Liao 2509741b1a6SJames Liao r = readl(pll->pwr_addr) & ~CON0_ISO_EN; 2519741b1a6SJames Liao writel(r, pll->pwr_addr); 2529741b1a6SJames Liao udelay(1); 2539741b1a6SJames Liao 254f384c447SChun-Jie Chen r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit); 255f384c447SChun-Jie Chen writel(r, pll->en_addr); 2569741b1a6SJames Liao 2577cc4e1bbSChun-Jie Chen div_en_mask = pll->data->en_mask & ~CON0_BASE_EN; 2587cc4e1bbSChun-Jie Chen if (div_en_mask) { 2597cc4e1bbSChun-Jie Chen r = readl(pll->base_addr + REG_CON0) | div_en_mask; 2607cc4e1bbSChun-Jie Chen writel(r, pll->base_addr + REG_CON0); 2617cc4e1bbSChun-Jie Chen } 2627cc4e1bbSChun-Jie Chen 263be17ca6aSOwen Chen __mtk_pll_tuner_enable(pll); 2649741b1a6SJames Liao 2659741b1a6SJames Liao udelay(20); 2669741b1a6SJames Liao 2679741b1a6SJames Liao if (pll->data->flags & HAVE_RST_BAR) { 2689741b1a6SJames Liao r = readl(pll->base_addr + REG_CON0); 2699741b1a6SJames Liao r |= pll->data->rst_bar_mask; 2709741b1a6SJames Liao writel(r, pll->base_addr + REG_CON0); 2719741b1a6SJames Liao } 2729741b1a6SJames Liao 2739741b1a6SJames Liao return 0; 2749741b1a6SJames Liao } 2759741b1a6SJames Liao 2769741b1a6SJames Liao static void mtk_pll_unprepare(struct clk_hw *hw) 2779741b1a6SJames Liao { 2789741b1a6SJames Liao struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 2799741b1a6SJames Liao u32 r; 2807cc4e1bbSChun-Jie Chen u32 div_en_mask; 2819741b1a6SJames Liao 2829741b1a6SJames Liao if (pll->data->flags & HAVE_RST_BAR) { 2839741b1a6SJames Liao r = readl(pll->base_addr + REG_CON0); 2849741b1a6SJames Liao r &= ~pll->data->rst_bar_mask; 2859741b1a6SJames Liao writel(r, pll->base_addr + REG_CON0); 2869741b1a6SJames Liao } 2879741b1a6SJames Liao 288be17ca6aSOwen Chen __mtk_pll_tuner_disable(pll); 2899741b1a6SJames Liao 2907cc4e1bbSChun-Jie Chen div_en_mask = pll->data->en_mask & ~CON0_BASE_EN; 2917cc4e1bbSChun-Jie Chen if (div_en_mask) { 2927cc4e1bbSChun-Jie Chen r = readl(pll->base_addr + REG_CON0) & ~div_en_mask; 2937cc4e1bbSChun-Jie Chen writel(r, pll->base_addr + REG_CON0); 2947cc4e1bbSChun-Jie Chen } 2957cc4e1bbSChun-Jie Chen 296f384c447SChun-Jie Chen r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit); 297f384c447SChun-Jie Chen writel(r, pll->en_addr); 2989741b1a6SJames Liao 2999741b1a6SJames Liao r = readl(pll->pwr_addr) | CON0_ISO_EN; 3009741b1a6SJames Liao writel(r, pll->pwr_addr); 3019741b1a6SJames Liao 3029741b1a6SJames Liao r = readl(pll->pwr_addr) & ~CON0_PWR_ON; 3039741b1a6SJames Liao writel(r, pll->pwr_addr); 3049741b1a6SJames Liao } 3059741b1a6SJames Liao 3069741b1a6SJames Liao static const struct clk_ops mtk_pll_ops = { 3079741b1a6SJames Liao .is_prepared = mtk_pll_is_prepared, 3089741b1a6SJames Liao .prepare = mtk_pll_prepare, 3099741b1a6SJames Liao .unprepare = mtk_pll_unprepare, 3109741b1a6SJames Liao .recalc_rate = mtk_pll_recalc_rate, 3119741b1a6SJames Liao .round_rate = mtk_pll_round_rate, 3129741b1a6SJames Liao .set_rate = mtk_pll_set_rate, 3139741b1a6SJames Liao }; 3149741b1a6SJames Liao 3159741b1a6SJames Liao static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data, 3169741b1a6SJames Liao void __iomem *base) 3179741b1a6SJames Liao { 3189741b1a6SJames Liao struct mtk_clk_pll *pll; 31995f58981SRicky Liang struct clk_init_data init = {}; 3209741b1a6SJames Liao struct clk *clk; 3219741b1a6SJames Liao const char *parent_name = "clk26m"; 3229741b1a6SJames Liao 3239741b1a6SJames Liao pll = kzalloc(sizeof(*pll), GFP_KERNEL); 3249741b1a6SJames Liao if (!pll) 3259741b1a6SJames Liao return ERR_PTR(-ENOMEM); 3269741b1a6SJames Liao 3279741b1a6SJames Liao pll->base_addr = base + data->reg; 3289741b1a6SJames Liao pll->pwr_addr = base + data->pwr_reg; 3299741b1a6SJames Liao pll->pd_addr = base + data->pd_reg; 3309741b1a6SJames Liao pll->pcw_addr = base + data->pcw_reg; 33123fe31deSWeiyi Lu if (data->pcw_chg_reg) 33223fe31deSWeiyi Lu pll->pcw_chg_addr = base + data->pcw_chg_reg; 33323fe31deSWeiyi Lu else 33423fe31deSWeiyi Lu pll->pcw_chg_addr = pll->base_addr + REG_CON1; 3359741b1a6SJames Liao if (data->tuner_reg) 3369741b1a6SJames Liao pll->tuner_addr = base + data->tuner_reg; 337cb95c169SChun-Jie Chen if (data->tuner_en_reg || data->tuner_en_bit) 338e2f744a8Sweiyi.lu@mediatek.com pll->tuner_en_addr = base + data->tuner_en_reg; 339f384c447SChun-Jie Chen if (data->en_reg) 340f384c447SChun-Jie Chen pll->en_addr = base + data->en_reg; 341f384c447SChun-Jie Chen else 342f384c447SChun-Jie Chen pll->en_addr = pll->base_addr + REG_CON0; 3439741b1a6SJames Liao pll->hw.init = &init; 3449741b1a6SJames Liao pll->data = data; 3459741b1a6SJames Liao 3469741b1a6SJames Liao init.name = data->name; 347e9862118SShunli Wang init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0; 3489741b1a6SJames Liao init.ops = &mtk_pll_ops; 349c955bf39SChen Zhong if (data->parent_name) 350c955bf39SChen Zhong init.parent_names = &data->parent_name; 351c955bf39SChen Zhong else 3529741b1a6SJames Liao init.parent_names = &parent_name; 3539741b1a6SJames Liao init.num_parents = 1; 3549741b1a6SJames Liao 3559741b1a6SJames Liao clk = clk_register(NULL, &pll->hw); 3569741b1a6SJames Liao 3579741b1a6SJames Liao if (IS_ERR(clk)) 3589741b1a6SJames Liao kfree(pll); 3599741b1a6SJames Liao 3609741b1a6SJames Liao return clk; 3619741b1a6SJames Liao } 3629741b1a6SJames Liao 363*6dd19906SChen-Yu Tsai static void mtk_clk_unregister_pll(struct clk *clk) 364*6dd19906SChen-Yu Tsai { 365*6dd19906SChen-Yu Tsai struct clk_hw *hw; 366*6dd19906SChen-Yu Tsai struct mtk_clk_pll *pll; 367*6dd19906SChen-Yu Tsai 368*6dd19906SChen-Yu Tsai hw = __clk_get_hw(clk); 369*6dd19906SChen-Yu Tsai if (!hw) 370*6dd19906SChen-Yu Tsai return; 371*6dd19906SChen-Yu Tsai 372*6dd19906SChen-Yu Tsai pll = to_mtk_clk_pll(hw); 373*6dd19906SChen-Yu Tsai 374*6dd19906SChen-Yu Tsai clk_unregister(clk); 375*6dd19906SChen-Yu Tsai kfree(pll); 376*6dd19906SChen-Yu Tsai } 377*6dd19906SChen-Yu Tsai 378928f3bfbSJames Liao void mtk_clk_register_plls(struct device_node *node, 3799741b1a6SJames Liao const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data) 3809741b1a6SJames Liao { 3819741b1a6SJames Liao void __iomem *base; 382cdb2bab7SJames Liao int i; 3839741b1a6SJames Liao struct clk *clk; 3849741b1a6SJames Liao 3859741b1a6SJames Liao base = of_iomap(node, 0); 3869741b1a6SJames Liao if (!base) { 3879741b1a6SJames Liao pr_err("%s(): ioremap failed\n", __func__); 3889741b1a6SJames Liao return; 3899741b1a6SJames Liao } 3909741b1a6SJames Liao 3919741b1a6SJames Liao for (i = 0; i < num_plls; i++) { 3929741b1a6SJames Liao const struct mtk_pll_data *pll = &plls[i]; 3939741b1a6SJames Liao 3949741b1a6SJames Liao clk = mtk_clk_register_pll(pll, base); 3959741b1a6SJames Liao 3969741b1a6SJames Liao if (IS_ERR(clk)) { 3972403d6f1SChen-Yu Tsai pr_err("Failed to register clk %s: %pe\n", pll->name, clk); 3989741b1a6SJames Liao continue; 3999741b1a6SJames Liao } 4009741b1a6SJames Liao 4019741b1a6SJames Liao clk_data->clks[pll->id] = clk; 4029741b1a6SJames Liao } 4039741b1a6SJames Liao } 40432b028fbSMiles Chen EXPORT_SYMBOL_GPL(mtk_clk_register_plls); 40532b028fbSMiles Chen 406*6dd19906SChen-Yu Tsai static __iomem void *mtk_clk_pll_get_base(struct clk *clk, 407*6dd19906SChen-Yu Tsai const struct mtk_pll_data *data) 408*6dd19906SChen-Yu Tsai { 409*6dd19906SChen-Yu Tsai struct clk_hw *hw = __clk_get_hw(clk); 410*6dd19906SChen-Yu Tsai struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); 411*6dd19906SChen-Yu Tsai 412*6dd19906SChen-Yu Tsai return pll->base_addr - data->reg; 413*6dd19906SChen-Yu Tsai } 414*6dd19906SChen-Yu Tsai 415*6dd19906SChen-Yu Tsai void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls, 416*6dd19906SChen-Yu Tsai struct clk_onecell_data *clk_data) 417*6dd19906SChen-Yu Tsai { 418*6dd19906SChen-Yu Tsai __iomem void *base = NULL; 419*6dd19906SChen-Yu Tsai int i; 420*6dd19906SChen-Yu Tsai 421*6dd19906SChen-Yu Tsai if (!clk_data) 422*6dd19906SChen-Yu Tsai return; 423*6dd19906SChen-Yu Tsai 424*6dd19906SChen-Yu Tsai for (i = num_plls; i > 0; i--) { 425*6dd19906SChen-Yu Tsai const struct mtk_pll_data *pll = &plls[i - 1]; 426*6dd19906SChen-Yu Tsai 427*6dd19906SChen-Yu Tsai if (IS_ERR_OR_NULL(clk_data->clks[pll->id])) 428*6dd19906SChen-Yu Tsai continue; 429*6dd19906SChen-Yu Tsai 430*6dd19906SChen-Yu Tsai /* 431*6dd19906SChen-Yu Tsai * This is quite ugly but unfortunately the clks don't have 432*6dd19906SChen-Yu Tsai * any device tied to them, so there's no place to store the 433*6dd19906SChen-Yu Tsai * pointer to the I/O region base address. We have to fetch 434*6dd19906SChen-Yu Tsai * it from one of the registered clks. 435*6dd19906SChen-Yu Tsai */ 436*6dd19906SChen-Yu Tsai base = mtk_clk_pll_get_base(clk_data->clks[pll->id], pll); 437*6dd19906SChen-Yu Tsai 438*6dd19906SChen-Yu Tsai mtk_clk_unregister_pll(clk_data->clks[pll->id]); 439*6dd19906SChen-Yu Tsai clk_data->clks[pll->id] = ERR_PTR(-ENOENT); 440*6dd19906SChen-Yu Tsai } 441*6dd19906SChen-Yu Tsai 442*6dd19906SChen-Yu Tsai iounmap(base); 443*6dd19906SChen-Yu Tsai } 444*6dd19906SChen-Yu Tsai EXPORT_SYMBOL_GPL(mtk_clk_unregister_plls); 445*6dd19906SChen-Yu Tsai 44632b028fbSMiles Chen MODULE_LICENSE("GPL"); 447