1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Owen Chen <owen.chen@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/compiler_types.h> 10 #include <linux/container_of.h> 11 #include <linux/err.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/regmap.h> 15 #include <linux/spinlock.h> 16 #include <linux/slab.h> 17 18 #include "clk-mux.h" 19 20 struct mtk_clk_mux { 21 struct clk_hw hw; 22 struct regmap *regmap; 23 const struct mtk_mux *data; 24 spinlock_t *lock; 25 bool reparent; 26 }; 27 28 static inline struct mtk_clk_mux *to_mtk_clk_mux(struct clk_hw *hw) 29 { 30 return container_of(hw, struct mtk_clk_mux, hw); 31 } 32 33 static int mtk_clk_mux_enable_setclr(struct clk_hw *hw) 34 { 35 struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); 36 unsigned long flags = 0; 37 38 if (mux->lock) 39 spin_lock_irqsave(mux->lock, flags); 40 else 41 __acquire(mux->lock); 42 43 regmap_write(mux->regmap, mux->data->clr_ofs, 44 BIT(mux->data->gate_shift)); 45 46 /* 47 * If the parent has been changed when the clock was disabled, it will 48 * not be effective yet. Set the update bit to ensure the mux gets 49 * updated. 50 */ 51 if (mux->reparent && mux->data->upd_shift >= 0) { 52 regmap_write(mux->regmap, mux->data->upd_ofs, 53 BIT(mux->data->upd_shift)); 54 mux->reparent = false; 55 } 56 57 if (mux->lock) 58 spin_unlock_irqrestore(mux->lock, flags); 59 else 60 __release(mux->lock); 61 62 return 0; 63 } 64 65 static void mtk_clk_mux_disable_setclr(struct clk_hw *hw) 66 { 67 struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); 68 69 regmap_write(mux->regmap, mux->data->set_ofs, 70 BIT(mux->data->gate_shift)); 71 } 72 73 static int mtk_clk_mux_is_enabled(struct clk_hw *hw) 74 { 75 struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); 76 u32 val; 77 78 regmap_read(mux->regmap, mux->data->mux_ofs, &val); 79 80 return (val & BIT(mux->data->gate_shift)) == 0; 81 } 82 83 static u8 mtk_clk_mux_get_parent(struct clk_hw *hw) 84 { 85 struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); 86 u32 mask = GENMASK(mux->data->mux_width - 1, 0); 87 u32 val; 88 89 regmap_read(mux->regmap, mux->data->mux_ofs, &val); 90 val = (val >> mux->data->mux_shift) & mask; 91 92 return val; 93 } 94 95 static int mtk_clk_mux_set_parent_setclr_lock(struct clk_hw *hw, u8 index) 96 { 97 struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); 98 u32 mask = GENMASK(mux->data->mux_width - 1, 0); 99 u32 val, orig; 100 unsigned long flags = 0; 101 102 if (mux->lock) 103 spin_lock_irqsave(mux->lock, flags); 104 else 105 __acquire(mux->lock); 106 107 regmap_read(mux->regmap, mux->data->mux_ofs, &orig); 108 val = (orig & ~(mask << mux->data->mux_shift)) 109 | (index << mux->data->mux_shift); 110 111 if (val != orig) { 112 regmap_write(mux->regmap, mux->data->clr_ofs, 113 mask << mux->data->mux_shift); 114 regmap_write(mux->regmap, mux->data->set_ofs, 115 index << mux->data->mux_shift); 116 117 if (mux->data->upd_shift >= 0) { 118 regmap_write(mux->regmap, mux->data->upd_ofs, 119 BIT(mux->data->upd_shift)); 120 mux->reparent = true; 121 } 122 } 123 124 if (mux->lock) 125 spin_unlock_irqrestore(mux->lock, flags); 126 else 127 __release(mux->lock); 128 129 return 0; 130 } 131 132 static int mtk_clk_mux_determine_rate(struct clk_hw *hw, 133 struct clk_rate_request *req) 134 { 135 struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); 136 137 return clk_mux_determine_rate_flags(hw, req, mux->data->flags); 138 } 139 140 const struct clk_ops mtk_mux_clr_set_upd_ops = { 141 .get_parent = mtk_clk_mux_get_parent, 142 .set_parent = mtk_clk_mux_set_parent_setclr_lock, 143 .determine_rate = mtk_clk_mux_determine_rate, 144 }; 145 EXPORT_SYMBOL_GPL(mtk_mux_clr_set_upd_ops); 146 147 const struct clk_ops mtk_mux_gate_clr_set_upd_ops = { 148 .enable = mtk_clk_mux_enable_setclr, 149 .disable = mtk_clk_mux_disable_setclr, 150 .is_enabled = mtk_clk_mux_is_enabled, 151 .get_parent = mtk_clk_mux_get_parent, 152 .set_parent = mtk_clk_mux_set_parent_setclr_lock, 153 .determine_rate = mtk_clk_mux_determine_rate, 154 }; 155 EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops); 156 157 static struct clk_hw *mtk_clk_register_mux(const struct mtk_mux *mux, 158 struct regmap *regmap, 159 spinlock_t *lock) 160 { 161 struct mtk_clk_mux *clk_mux; 162 struct clk_init_data init = {}; 163 int ret; 164 165 clk_mux = kzalloc(sizeof(*clk_mux), GFP_KERNEL); 166 if (!clk_mux) 167 return ERR_PTR(-ENOMEM); 168 169 init.name = mux->name; 170 init.flags = mux->flags | CLK_SET_RATE_PARENT; 171 init.parent_names = mux->parent_names; 172 init.num_parents = mux->num_parents; 173 init.ops = mux->ops; 174 175 clk_mux->regmap = regmap; 176 clk_mux->data = mux; 177 clk_mux->lock = lock; 178 clk_mux->hw.init = &init; 179 180 ret = clk_hw_register(NULL, &clk_mux->hw); 181 if (ret) { 182 kfree(clk_mux); 183 return ERR_PTR(ret); 184 } 185 186 return &clk_mux->hw; 187 } 188 189 static void mtk_clk_unregister_mux(struct clk_hw *hw) 190 { 191 struct mtk_clk_mux *mux; 192 if (!hw) 193 return; 194 195 mux = to_mtk_clk_mux(hw); 196 197 clk_hw_unregister(hw); 198 kfree(mux); 199 } 200 201 int mtk_clk_register_muxes(const struct mtk_mux *muxes, 202 int num, struct device_node *node, 203 spinlock_t *lock, 204 struct clk_hw_onecell_data *clk_data) 205 { 206 struct regmap *regmap; 207 struct clk_hw *hw; 208 int i; 209 210 regmap = device_node_to_regmap(node); 211 if (IS_ERR(regmap)) { 212 pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap); 213 return PTR_ERR(regmap); 214 } 215 216 for (i = 0; i < num; i++) { 217 const struct mtk_mux *mux = &muxes[i]; 218 219 if (!IS_ERR_OR_NULL(clk_data->hws[mux->id])) { 220 pr_warn("%pOF: Trying to register duplicate clock ID: %d\n", 221 node, mux->id); 222 continue; 223 } 224 225 hw = mtk_clk_register_mux(mux, regmap, lock); 226 227 if (IS_ERR(hw)) { 228 pr_err("Failed to register clk %s: %pe\n", mux->name, 229 hw); 230 goto err; 231 } 232 233 clk_data->hws[mux->id] = hw; 234 } 235 236 return 0; 237 238 err: 239 while (--i >= 0) { 240 const struct mtk_mux *mux = &muxes[i]; 241 242 if (IS_ERR_OR_NULL(clk_data->hws[mux->id])) 243 continue; 244 245 mtk_clk_unregister_mux(clk_data->hws[mux->id]); 246 clk_data->hws[mux->id] = ERR_PTR(-ENOENT); 247 } 248 249 return PTR_ERR(hw); 250 } 251 EXPORT_SYMBOL_GPL(mtk_clk_register_muxes); 252 253 void mtk_clk_unregister_muxes(const struct mtk_mux *muxes, int num, 254 struct clk_hw_onecell_data *clk_data) 255 { 256 int i; 257 258 if (!clk_data) 259 return; 260 261 for (i = num; i > 0; i--) { 262 const struct mtk_mux *mux = &muxes[i - 1]; 263 264 if (IS_ERR_OR_NULL(clk_data->hws[mux->id])) 265 continue; 266 267 mtk_clk_unregister_mux(clk_data->hws[mux->id]); 268 clk_data->hws[mux->id] = ERR_PTR(-ENOENT); 269 } 270 } 271 EXPORT_SYMBOL_GPL(mtk_clk_unregister_muxes); 272 273 /* 274 * This clock notifier is called when the frequency of the parent 275 * PLL clock is to be changed. The idea is to switch the parent to a 276 * stable clock, such as the main oscillator, while the PLL frequency 277 * stabilizes. 278 */ 279 static int mtk_clk_mux_notifier_cb(struct notifier_block *nb, 280 unsigned long event, void *_data) 281 { 282 struct clk_notifier_data *data = _data; 283 struct clk_hw *hw = __clk_get_hw(data->clk); 284 struct mtk_mux_nb *mux_nb = to_mtk_mux_nb(nb); 285 int ret = 0; 286 287 switch (event) { 288 case PRE_RATE_CHANGE: 289 mux_nb->original_index = mux_nb->ops->get_parent(hw); 290 ret = mux_nb->ops->set_parent(hw, mux_nb->bypass_index); 291 break; 292 case POST_RATE_CHANGE: 293 case ABORT_RATE_CHANGE: 294 ret = mux_nb->ops->set_parent(hw, mux_nb->original_index); 295 break; 296 } 297 298 return notifier_from_errno(ret); 299 } 300 301 int devm_mtk_clk_mux_notifier_register(struct device *dev, struct clk *clk, 302 struct mtk_mux_nb *mux_nb) 303 { 304 mux_nb->nb.notifier_call = mtk_clk_mux_notifier_cb; 305 306 return devm_clk_notifier_register(dev, clk, &mux_nb->nb); 307 } 308 EXPORT_SYMBOL_GPL(devm_mtk_clk_mux_notifier_register); 309 310 MODULE_LICENSE("GPL"); 311