1 /* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: James Liao <jamesjj.liao@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #ifndef __DRV_CLK_MTK_H 16 #define __DRV_CLK_MTK_H 17 18 #include <linux/regmap.h> 19 #include <linux/bitops.h> 20 #include <linux/clk.h> 21 #include <linux/clk-provider.h> 22 23 #define MAX_MUX_GATE_BIT 31 24 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1) 25 26 #define MHZ (1000 * 1000) 27 28 struct mtk_fixed_factor { 29 int id; 30 const char *name; 31 const char *parent_name; 32 int mult; 33 int div; 34 }; 35 36 #define FACTOR(_id, _name, _parent, _mult, _div) { \ 37 .id = _id, \ 38 .name = _name, \ 39 .parent_name = _parent, \ 40 .mult = _mult, \ 41 .div = _div, \ 42 } 43 44 extern void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, 45 int num, struct clk_onecell_data *clk_data); 46 47 struct mtk_composite { 48 int id; 49 const char *name; 50 const char * const *parent_names; 51 const char *parent; 52 unsigned flags; 53 54 uint32_t mux_reg; 55 uint32_t divider_reg; 56 uint32_t gate_reg; 57 58 signed char mux_shift; 59 signed char mux_width; 60 signed char gate_shift; 61 62 signed char divider_shift; 63 signed char divider_width; 64 65 signed char num_parents; 66 }; 67 68 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) { \ 69 .id = _id, \ 70 .name = _name, \ 71 .mux_reg = _reg, \ 72 .mux_shift = _shift, \ 73 .mux_width = _width, \ 74 .gate_reg = _reg, \ 75 .gate_shift = _gate, \ 76 .divider_shift = -1, \ 77 .parent_names = _parents, \ 78 .num_parents = ARRAY_SIZE(_parents), \ 79 .flags = CLK_SET_RATE_PARENT, \ 80 } 81 82 #define MUX(_id, _name, _parents, _reg, _shift, _width) { \ 83 .id = _id, \ 84 .name = _name, \ 85 .mux_reg = _reg, \ 86 .mux_shift = _shift, \ 87 .mux_width = _width, \ 88 .gate_shift = -1, \ 89 .divider_shift = -1, \ 90 .parent_names = _parents, \ 91 .num_parents = ARRAY_SIZE(_parents), \ 92 .flags = CLK_SET_RATE_PARENT, \ 93 } 94 95 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) { \ 96 .id = _id, \ 97 .parent = _parent, \ 98 .name = _name, \ 99 .divider_reg = _div_reg, \ 100 .divider_shift = _div_shift, \ 101 .divider_width = _div_width, \ 102 .gate_reg = _gate_reg, \ 103 .gate_shift = _gate_shift, \ 104 .mux_shift = -1, \ 105 .flags = 0, \ 106 } 107 108 struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, 109 void __iomem *base, spinlock_t *lock); 110 111 void mtk_clk_register_composites(const struct mtk_composite *mcs, 112 int num, void __iomem *base, spinlock_t *lock, 113 struct clk_onecell_data *clk_data); 114 115 struct mtk_gate_regs { 116 u32 sta_ofs; 117 u32 clr_ofs; 118 u32 set_ofs; 119 }; 120 121 struct mtk_gate { 122 int id; 123 const char *name; 124 const char *parent_name; 125 const struct mtk_gate_regs *regs; 126 int shift; 127 const struct clk_ops *ops; 128 }; 129 130 int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks, 131 int num, struct clk_onecell_data *clk_data); 132 133 struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); 134 135 #define HAVE_RST_BAR BIT(0) 136 137 struct mtk_pll_data { 138 int id; 139 const char *name; 140 uint32_t reg; 141 uint32_t pwr_reg; 142 uint32_t en_mask; 143 uint32_t pd_reg; 144 uint32_t tuner_reg; 145 int pd_shift; 146 unsigned int flags; 147 const struct clk_ops *ops; 148 u32 rst_bar_mask; 149 unsigned long fmax; 150 int pcwbits; 151 uint32_t pcw_reg; 152 int pcw_shift; 153 }; 154 155 void __init mtk_clk_register_plls(struct device_node *node, 156 const struct mtk_pll_data *plls, int num_plls, 157 struct clk_onecell_data *clk_data); 158 159 #ifdef CONFIG_RESET_CONTROLLER 160 void mtk_register_reset_controller(struct device_node *np, 161 unsigned int num_regs, int regofs); 162 #else 163 static inline void mtk_register_reset_controller(struct device_node *np, 164 unsigned int num_regs, int regofs) 165 { 166 } 167 #endif 168 169 #endif /* __DRV_CLK_MTK_H */ 170