1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: James Liao <jamesjj.liao@mediatek.com> 5 */ 6 7 #ifndef __DRV_CLK_MTK_H 8 #define __DRV_CLK_MTK_H 9 10 #include <linux/regmap.h> 11 #include <linux/bitops.h> 12 #include <linux/clk-provider.h> 13 14 struct clk; 15 struct clk_onecell_data; 16 17 #define MAX_MUX_GATE_BIT 31 18 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1) 19 20 #define MHZ (1000 * 1000) 21 22 struct mtk_fixed_clk { 23 int id; 24 const char *name; 25 const char *parent; 26 unsigned long rate; 27 }; 28 29 #define FIXED_CLK(_id, _name, _parent, _rate) { \ 30 .id = _id, \ 31 .name = _name, \ 32 .parent = _parent, \ 33 .rate = _rate, \ 34 } 35 36 void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, 37 int num, struct clk_onecell_data *clk_data); 38 39 struct mtk_fixed_factor { 40 int id; 41 const char *name; 42 const char *parent_name; 43 int mult; 44 int div; 45 }; 46 47 #define FACTOR(_id, _name, _parent, _mult, _div) { \ 48 .id = _id, \ 49 .name = _name, \ 50 .parent_name = _parent, \ 51 .mult = _mult, \ 52 .div = _div, \ 53 } 54 55 void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, 56 int num, struct clk_onecell_data *clk_data); 57 58 struct mtk_composite { 59 int id; 60 const char *name; 61 const char * const *parent_names; 62 const char *parent; 63 unsigned flags; 64 65 uint32_t mux_reg; 66 uint32_t divider_reg; 67 uint32_t gate_reg; 68 69 signed char mux_shift; 70 signed char mux_width; 71 signed char gate_shift; 72 73 signed char divider_shift; 74 signed char divider_width; 75 76 u8 mux_flags; 77 78 signed char num_parents; 79 }; 80 81 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ 82 _width, _gate, _flags, _muxflags) { \ 83 .id = _id, \ 84 .name = _name, \ 85 .mux_reg = _reg, \ 86 .mux_shift = _shift, \ 87 .mux_width = _width, \ 88 .gate_reg = _reg, \ 89 .gate_shift = _gate, \ 90 .divider_shift = -1, \ 91 .parent_names = _parents, \ 92 .num_parents = ARRAY_SIZE(_parents), \ 93 .flags = _flags, \ 94 .mux_flags = _muxflags, \ 95 } 96 97 /* 98 * In case the rate change propagation to parent clocks is undesirable, 99 * this macro allows to specify the clock flags manually. 100 */ 101 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ 102 _gate, _flags) \ 103 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \ 104 _shift, _width, _gate, _flags, 0) 105 106 /* 107 * Unless necessary, all MUX_GATE clocks propagate rate changes to their 108 * parent clock by default. 109 */ 110 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ 111 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ 112 _gate, CLK_SET_RATE_PARENT) 113 114 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ 115 MUX_FLAGS(_id, _name, _parents, _reg, \ 116 _shift, _width, CLK_SET_RATE_PARENT) 117 118 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ 119 .id = _id, \ 120 .name = _name, \ 121 .mux_reg = _reg, \ 122 .mux_shift = _shift, \ 123 .mux_width = _width, \ 124 .gate_shift = -1, \ 125 .divider_shift = -1, \ 126 .parent_names = _parents, \ 127 .num_parents = ARRAY_SIZE(_parents), \ 128 .flags = _flags, \ 129 } 130 131 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \ 132 _div_width, _div_shift) { \ 133 .id = _id, \ 134 .parent = _parent, \ 135 .name = _name, \ 136 .divider_reg = _div_reg, \ 137 .divider_shift = _div_shift, \ 138 .divider_width = _div_width, \ 139 .gate_reg = _gate_reg, \ 140 .gate_shift = _gate_shift, \ 141 .mux_shift = -1, \ 142 .flags = 0, \ 143 } 144 145 struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, 146 void __iomem *base, spinlock_t *lock); 147 148 void mtk_clk_register_composites(const struct mtk_composite *mcs, 149 int num, void __iomem *base, spinlock_t *lock, 150 struct clk_onecell_data *clk_data); 151 152 struct mtk_gate_regs { 153 u32 sta_ofs; 154 u32 clr_ofs; 155 u32 set_ofs; 156 }; 157 158 struct mtk_gate { 159 int id; 160 const char *name; 161 const char *parent_name; 162 const struct mtk_gate_regs *regs; 163 int shift; 164 const struct clk_ops *ops; 165 unsigned long flags; 166 }; 167 168 int mtk_clk_register_gates(struct device_node *node, 169 const struct mtk_gate *clks, int num, 170 struct clk_onecell_data *clk_data); 171 172 struct mtk_clk_divider { 173 int id; 174 const char *name; 175 const char *parent_name; 176 unsigned long flags; 177 178 u32 div_reg; 179 unsigned char div_shift; 180 unsigned char div_width; 181 unsigned char clk_divider_flags; 182 const struct clk_div_table *clk_div_table; 183 }; 184 185 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ 186 .id = _id, \ 187 .name = _name, \ 188 .parent_name = _parent, \ 189 .div_reg = _reg, \ 190 .div_shift = _shift, \ 191 .div_width = _width, \ 192 } 193 194 void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, 195 int num, void __iomem *base, spinlock_t *lock, 196 struct clk_onecell_data *clk_data); 197 198 struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); 199 200 #define HAVE_RST_BAR BIT(0) 201 #define PLL_AO BIT(1) 202 203 struct mtk_pll_div_table { 204 u32 div; 205 unsigned long freq; 206 }; 207 208 struct mtk_pll_data { 209 int id; 210 const char *name; 211 uint32_t reg; 212 uint32_t pwr_reg; 213 uint32_t en_mask; 214 uint32_t pd_reg; 215 uint32_t tuner_reg; 216 uint32_t tuner_en_reg; 217 uint8_t tuner_en_bit; 218 int pd_shift; 219 unsigned int flags; 220 const struct clk_ops *ops; 221 u32 rst_bar_mask; 222 unsigned long fmin; 223 unsigned long fmax; 224 int pcwbits; 225 int pcwibits; 226 uint32_t pcw_reg; 227 int pcw_shift; 228 uint32_t pcw_chg_reg; 229 const struct mtk_pll_div_table *div_table; 230 const char *parent_name; 231 }; 232 233 void mtk_clk_register_plls(struct device_node *node, 234 const struct mtk_pll_data *plls, int num_plls, 235 struct clk_onecell_data *clk_data); 236 237 struct clk *mtk_clk_register_ref2usb_tx(const char *name, 238 const char *parent_name, void __iomem *reg); 239 240 void mtk_register_reset_controller(struct device_node *np, 241 unsigned int num_regs, int regofs); 242 243 #endif /* __DRV_CLK_MTK_H */ 244