1 /* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: James Liao <jamesjj.liao@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #ifndef __DRV_CLK_MTK_H 16 #define __DRV_CLK_MTK_H 17 18 #include <linux/regmap.h> 19 #include <linux/bitops.h> 20 #include <linux/clk-provider.h> 21 22 struct clk; 23 struct clk_onecell_data; 24 25 #define MAX_MUX_GATE_BIT 31 26 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1) 27 28 #define MHZ (1000 * 1000) 29 30 struct mtk_fixed_clk { 31 int id; 32 const char *name; 33 const char *parent; 34 unsigned long rate; 35 }; 36 37 #define FIXED_CLK(_id, _name, _parent, _rate) { \ 38 .id = _id, \ 39 .name = _name, \ 40 .parent = _parent, \ 41 .rate = _rate, \ 42 } 43 44 void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, 45 int num, struct clk_onecell_data *clk_data); 46 47 struct mtk_fixed_factor { 48 int id; 49 const char *name; 50 const char *parent_name; 51 int mult; 52 int div; 53 }; 54 55 #define FACTOR(_id, _name, _parent, _mult, _div) { \ 56 .id = _id, \ 57 .name = _name, \ 58 .parent_name = _parent, \ 59 .mult = _mult, \ 60 .div = _div, \ 61 } 62 63 void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, 64 int num, struct clk_onecell_data *clk_data); 65 66 struct mtk_composite { 67 int id; 68 const char *name; 69 const char * const *parent_names; 70 const char *parent; 71 unsigned flags; 72 73 uint32_t mux_reg; 74 uint32_t divider_reg; 75 uint32_t gate_reg; 76 77 signed char mux_shift; 78 signed char mux_width; 79 signed char gate_shift; 80 81 signed char divider_shift; 82 signed char divider_width; 83 84 u8 mux_flags; 85 86 signed char num_parents; 87 }; 88 89 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ 90 _width, _gate, _flags, _muxflags) { \ 91 .id = _id, \ 92 .name = _name, \ 93 .mux_reg = _reg, \ 94 .mux_shift = _shift, \ 95 .mux_width = _width, \ 96 .gate_reg = _reg, \ 97 .gate_shift = _gate, \ 98 .divider_shift = -1, \ 99 .parent_names = _parents, \ 100 .num_parents = ARRAY_SIZE(_parents), \ 101 .flags = _flags, \ 102 .mux_flags = _muxflags, \ 103 } 104 105 /* 106 * In case the rate change propagation to parent clocks is undesirable, 107 * this macro allows to specify the clock flags manually. 108 */ 109 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ 110 _gate, _flags) \ 111 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \ 112 _shift, _width, _gate, _flags, 0) 113 114 /* 115 * Unless necessary, all MUX_GATE clocks propagate rate changes to their 116 * parent clock by default. 117 */ 118 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ 119 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ 120 _gate, CLK_SET_RATE_PARENT) 121 122 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ 123 MUX_FLAGS(_id, _name, _parents, _reg, \ 124 _shift, _width, CLK_SET_RATE_PARENT) 125 126 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ 127 .id = _id, \ 128 .name = _name, \ 129 .mux_reg = _reg, \ 130 .mux_shift = _shift, \ 131 .mux_width = _width, \ 132 .gate_shift = -1, \ 133 .divider_shift = -1, \ 134 .parent_names = _parents, \ 135 .num_parents = ARRAY_SIZE(_parents), \ 136 .flags = _flags, \ 137 } 138 139 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \ 140 _div_width, _div_shift) { \ 141 .id = _id, \ 142 .parent = _parent, \ 143 .name = _name, \ 144 .divider_reg = _div_reg, \ 145 .divider_shift = _div_shift, \ 146 .divider_width = _div_width, \ 147 .gate_reg = _gate_reg, \ 148 .gate_shift = _gate_shift, \ 149 .mux_shift = -1, \ 150 .flags = 0, \ 151 } 152 153 struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, 154 void __iomem *base, spinlock_t *lock); 155 156 void mtk_clk_register_composites(const struct mtk_composite *mcs, 157 int num, void __iomem *base, spinlock_t *lock, 158 struct clk_onecell_data *clk_data); 159 160 struct mtk_gate_regs { 161 u32 sta_ofs; 162 u32 clr_ofs; 163 u32 set_ofs; 164 }; 165 166 struct mtk_gate { 167 int id; 168 const char *name; 169 const char *parent_name; 170 const struct mtk_gate_regs *regs; 171 int shift; 172 const struct clk_ops *ops; 173 unsigned long flags; 174 }; 175 176 int mtk_clk_register_gates(struct device_node *node, 177 const struct mtk_gate *clks, int num, 178 struct clk_onecell_data *clk_data); 179 180 struct mtk_clk_divider { 181 int id; 182 const char *name; 183 const char *parent_name; 184 unsigned long flags; 185 186 u32 div_reg; 187 unsigned char div_shift; 188 unsigned char div_width; 189 unsigned char clk_divider_flags; 190 const struct clk_div_table *clk_div_table; 191 }; 192 193 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ 194 .id = _id, \ 195 .name = _name, \ 196 .parent_name = _parent, \ 197 .div_reg = _reg, \ 198 .div_shift = _shift, \ 199 .div_width = _width, \ 200 } 201 202 void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, 203 int num, void __iomem *base, spinlock_t *lock, 204 struct clk_onecell_data *clk_data); 205 206 struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); 207 208 #define HAVE_RST_BAR BIT(0) 209 #define PLL_AO BIT(1) 210 211 struct mtk_pll_div_table { 212 u32 div; 213 unsigned long freq; 214 }; 215 216 struct mtk_pll_data { 217 int id; 218 const char *name; 219 uint32_t reg; 220 uint32_t pwr_reg; 221 uint32_t en_mask; 222 uint32_t pd_reg; 223 uint32_t tuner_reg; 224 uint32_t tuner_en_reg; 225 uint8_t tuner_en_bit; 226 int pd_shift; 227 unsigned int flags; 228 const struct clk_ops *ops; 229 u32 rst_bar_mask; 230 unsigned long fmin; 231 unsigned long fmax; 232 int pcwbits; 233 int pcwibits; 234 uint32_t pcw_reg; 235 int pcw_shift; 236 uint32_t pcw_chg_reg; 237 const struct mtk_pll_div_table *div_table; 238 const char *parent_name; 239 }; 240 241 void mtk_clk_register_plls(struct device_node *node, 242 const struct mtk_pll_data *plls, int num_plls, 243 struct clk_onecell_data *clk_data); 244 245 struct clk *mtk_clk_register_ref2usb_tx(const char *name, 246 const char *parent_name, void __iomem *reg); 247 248 void mtk_register_reset_controller(struct device_node *np, 249 unsigned int num_regs, int regofs); 250 251 #endif /* __DRV_CLK_MTK_H */ 252