1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: James Liao <jamesjj.liao@mediatek.com> 5 */ 6 7 #ifndef __DRV_CLK_MTK_H 8 #define __DRV_CLK_MTK_H 9 10 #include <linux/clk-provider.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/spinlock.h> 14 #include <linux/types.h> 15 16 #include "reset.h" 17 18 #define MAX_MUX_GATE_BIT 31 19 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1) 20 21 #define MHZ (1000 * 1000) 22 23 struct platform_device; 24 25 struct mtk_fixed_clk { 26 int id; 27 const char *name; 28 const char *parent; 29 unsigned long rate; 30 }; 31 32 #define FIXED_CLK(_id, _name, _parent, _rate) { \ 33 .id = _id, \ 34 .name = _name, \ 35 .parent = _parent, \ 36 .rate = _rate, \ 37 } 38 39 int mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num, 40 struct clk_hw_onecell_data *clk_data); 41 void mtk_clk_unregister_fixed_clks(const struct mtk_fixed_clk *clks, int num, 42 struct clk_hw_onecell_data *clk_data); 43 44 struct mtk_fixed_factor { 45 int id; 46 const char *name; 47 const char *parent_name; 48 int mult; 49 int div; 50 unsigned long flags; 51 }; 52 53 #define FACTOR_FLAGS(_id, _name, _parent, _mult, _div, _fl) { \ 54 .id = _id, \ 55 .name = _name, \ 56 .parent_name = _parent, \ 57 .mult = _mult, \ 58 .div = _div, \ 59 .flags = _fl, \ 60 } 61 62 #define FACTOR(_id, _name, _parent, _mult, _div) \ 63 FACTOR_FLAGS(_id, _name, _parent, _mult, _div, CLK_SET_RATE_PARENT) 64 65 int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num, 66 struct clk_hw_onecell_data *clk_data); 67 void mtk_clk_unregister_factors(const struct mtk_fixed_factor *clks, int num, 68 struct clk_hw_onecell_data *clk_data); 69 70 struct mtk_composite { 71 int id; 72 const char *name; 73 const char * const *parent_names; 74 const char *parent; 75 unsigned flags; 76 77 uint32_t mux_reg; 78 uint32_t divider_reg; 79 uint32_t gate_reg; 80 81 signed char mux_shift; 82 signed char mux_width; 83 signed char gate_shift; 84 85 signed char divider_shift; 86 signed char divider_width; 87 88 u8 mux_flags; 89 90 signed char num_parents; 91 }; 92 93 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ 94 _width, _gate, _flags, _muxflags) { \ 95 .id = _id, \ 96 .name = _name, \ 97 .mux_reg = _reg, \ 98 .mux_shift = _shift, \ 99 .mux_width = _width, \ 100 .gate_reg = _reg, \ 101 .gate_shift = _gate, \ 102 .divider_shift = -1, \ 103 .parent_names = _parents, \ 104 .num_parents = ARRAY_SIZE(_parents), \ 105 .flags = _flags, \ 106 .mux_flags = _muxflags, \ 107 } 108 109 /* 110 * In case the rate change propagation to parent clocks is undesirable, 111 * this macro allows to specify the clock flags manually. 112 */ 113 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ 114 _gate, _flags) \ 115 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \ 116 _shift, _width, _gate, _flags, 0) 117 118 /* 119 * Unless necessary, all MUX_GATE clocks propagate rate changes to their 120 * parent clock by default. 121 */ 122 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ 123 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ 124 _gate, CLK_SET_RATE_PARENT) 125 126 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ 127 MUX_FLAGS(_id, _name, _parents, _reg, \ 128 _shift, _width, CLK_SET_RATE_PARENT) 129 130 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ 131 .id = _id, \ 132 .name = _name, \ 133 .mux_reg = _reg, \ 134 .mux_shift = _shift, \ 135 .mux_width = _width, \ 136 .gate_shift = -1, \ 137 .divider_shift = -1, \ 138 .parent_names = _parents, \ 139 .num_parents = ARRAY_SIZE(_parents), \ 140 .flags = _flags, \ 141 } 142 143 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \ 144 _div_width, _div_shift) { \ 145 .id = _id, \ 146 .parent = _parent, \ 147 .name = _name, \ 148 .divider_reg = _div_reg, \ 149 .divider_shift = _div_shift, \ 150 .divider_width = _div_width, \ 151 .gate_reg = _gate_reg, \ 152 .gate_shift = _gate_shift, \ 153 .mux_shift = -1, \ 154 .flags = 0, \ 155 } 156 157 int mtk_clk_register_composites(const struct mtk_composite *mcs, int num, 158 void __iomem *base, spinlock_t *lock, 159 struct clk_hw_onecell_data *clk_data); 160 void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num, 161 struct clk_hw_onecell_data *clk_data); 162 163 struct mtk_clk_divider { 164 int id; 165 const char *name; 166 const char *parent_name; 167 unsigned long flags; 168 169 u32 div_reg; 170 unsigned char div_shift; 171 unsigned char div_width; 172 unsigned char clk_divider_flags; 173 const struct clk_div_table *clk_div_table; 174 }; 175 176 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ 177 .id = _id, \ 178 .name = _name, \ 179 .parent_name = _parent, \ 180 .div_reg = _reg, \ 181 .div_shift = _shift, \ 182 .div_width = _width, \ 183 } 184 185 int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, 186 void __iomem *base, spinlock_t *lock, 187 struct clk_hw_onecell_data *clk_data); 188 void mtk_clk_unregister_dividers(const struct mtk_clk_divider *mcds, int num, 189 struct clk_hw_onecell_data *clk_data); 190 191 struct clk_hw_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); 192 struct clk_hw_onecell_data *mtk_devm_alloc_clk_data(struct device *dev, 193 unsigned int clk_num); 194 void mtk_free_clk_data(struct clk_hw_onecell_data *clk_data); 195 196 struct clk_hw *mtk_clk_register_ref2usb_tx(const char *name, 197 const char *parent_name, void __iomem *reg); 198 void mtk_clk_unregister_ref2usb_tx(struct clk_hw *hw); 199 200 struct mtk_clk_desc { 201 const struct mtk_gate *clks; 202 size_t num_clks; 203 const struct mtk_clk_rst_desc *rst_desc; 204 }; 205 206 int mtk_clk_simple_probe(struct platform_device *pdev); 207 int mtk_clk_simple_remove(struct platform_device *pdev); 208 209 #endif /* __DRV_CLK_MTK_H */ 210