1 /* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: James Liao <jamesjj.liao@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #ifndef __DRV_CLK_MTK_H 16 #define __DRV_CLK_MTK_H 17 18 #include <linux/regmap.h> 19 #include <linux/bitops.h> 20 #include <linux/clk-provider.h> 21 22 struct clk; 23 24 #define MAX_MUX_GATE_BIT 31 25 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1) 26 27 #define MHZ (1000 * 1000) 28 29 struct mtk_fixed_clk { 30 int id; 31 const char *name; 32 const char *parent; 33 unsigned long rate; 34 }; 35 36 #define FIXED_CLK(_id, _name, _parent, _rate) { \ 37 .id = _id, \ 38 .name = _name, \ 39 .parent = _parent, \ 40 .rate = _rate, \ 41 } 42 43 void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, 44 int num, struct clk_onecell_data *clk_data); 45 46 struct mtk_fixed_factor { 47 int id; 48 const char *name; 49 const char *parent_name; 50 int mult; 51 int div; 52 }; 53 54 #define FACTOR(_id, _name, _parent, _mult, _div) { \ 55 .id = _id, \ 56 .name = _name, \ 57 .parent_name = _parent, \ 58 .mult = _mult, \ 59 .div = _div, \ 60 } 61 62 void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, 63 int num, struct clk_onecell_data *clk_data); 64 65 struct mtk_composite { 66 int id; 67 const char *name; 68 const char * const *parent_names; 69 const char *parent; 70 unsigned flags; 71 72 uint32_t mux_reg; 73 uint32_t divider_reg; 74 uint32_t gate_reg; 75 76 signed char mux_shift; 77 signed char mux_width; 78 signed char gate_shift; 79 80 signed char divider_shift; 81 signed char divider_width; 82 83 signed char num_parents; 84 }; 85 86 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) { \ 87 .id = _id, \ 88 .name = _name, \ 89 .mux_reg = _reg, \ 90 .mux_shift = _shift, \ 91 .mux_width = _width, \ 92 .gate_reg = _reg, \ 93 .gate_shift = _gate, \ 94 .divider_shift = -1, \ 95 .parent_names = _parents, \ 96 .num_parents = ARRAY_SIZE(_parents), \ 97 .flags = CLK_SET_RATE_PARENT, \ 98 } 99 100 #define MUX(_id, _name, _parents, _reg, _shift, _width) { \ 101 .id = _id, \ 102 .name = _name, \ 103 .mux_reg = _reg, \ 104 .mux_shift = _shift, \ 105 .mux_width = _width, \ 106 .gate_shift = -1, \ 107 .divider_shift = -1, \ 108 .parent_names = _parents, \ 109 .num_parents = ARRAY_SIZE(_parents), \ 110 .flags = CLK_SET_RATE_PARENT, \ 111 } 112 113 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) { \ 114 .id = _id, \ 115 .parent = _parent, \ 116 .name = _name, \ 117 .divider_reg = _div_reg, \ 118 .divider_shift = _div_shift, \ 119 .divider_width = _div_width, \ 120 .gate_reg = _gate_reg, \ 121 .gate_shift = _gate_shift, \ 122 .mux_shift = -1, \ 123 .flags = 0, \ 124 } 125 126 struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, 127 void __iomem *base, spinlock_t *lock); 128 129 void mtk_clk_register_composites(const struct mtk_composite *mcs, 130 int num, void __iomem *base, spinlock_t *lock, 131 struct clk_onecell_data *clk_data); 132 133 struct mtk_gate_regs { 134 u32 sta_ofs; 135 u32 clr_ofs; 136 u32 set_ofs; 137 }; 138 139 struct mtk_gate { 140 int id; 141 const char *name; 142 const char *parent_name; 143 const struct mtk_gate_regs *regs; 144 int shift; 145 const struct clk_ops *ops; 146 }; 147 148 int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks, 149 int num, struct clk_onecell_data *clk_data); 150 151 struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); 152 153 #define HAVE_RST_BAR BIT(0) 154 155 struct mtk_pll_div_table { 156 u32 div; 157 unsigned long freq; 158 }; 159 160 struct mtk_pll_data { 161 int id; 162 const char *name; 163 uint32_t reg; 164 uint32_t pwr_reg; 165 uint32_t en_mask; 166 uint32_t pd_reg; 167 uint32_t tuner_reg; 168 int pd_shift; 169 unsigned int flags; 170 const struct clk_ops *ops; 171 u32 rst_bar_mask; 172 unsigned long fmax; 173 int pcwbits; 174 uint32_t pcw_reg; 175 int pcw_shift; 176 const struct mtk_pll_div_table *div_table; 177 }; 178 179 void mtk_clk_register_plls(struct device_node *node, 180 const struct mtk_pll_data *plls, int num_plls, 181 struct clk_onecell_data *clk_data); 182 183 struct clk *mtk_clk_register_ref2usb_tx(const char *name, 184 const char *parent_name, void __iomem *reg); 185 186 #ifdef CONFIG_RESET_CONTROLLER 187 void mtk_register_reset_controller(struct device_node *np, 188 unsigned int num_regs, int regofs); 189 #else 190 static inline void mtk_register_reset_controller(struct device_node *np, 191 unsigned int num_regs, int regofs) 192 { 193 } 194 #endif 195 196 #endif /* __DRV_CLK_MTK_H */ 197