1 /* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: James Liao <jamesjj.liao@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #ifndef __DRV_CLK_MTK_H 16 #define __DRV_CLK_MTK_H 17 18 #include <linux/regmap.h> 19 #include <linux/bitops.h> 20 #include <linux/clk-provider.h> 21 22 struct clk; 23 24 #define MAX_MUX_GATE_BIT 31 25 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1) 26 27 #define MHZ (1000 * 1000) 28 29 struct mtk_fixed_clk { 30 int id; 31 const char *name; 32 const char *parent; 33 unsigned long rate; 34 }; 35 36 #define FIXED_CLK(_id, _name, _parent, _rate) { \ 37 .id = _id, \ 38 .name = _name, \ 39 .parent = _parent, \ 40 .rate = _rate, \ 41 } 42 43 void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, 44 int num, struct clk_onecell_data *clk_data); 45 46 struct mtk_fixed_factor { 47 int id; 48 const char *name; 49 const char *parent_name; 50 int mult; 51 int div; 52 }; 53 54 #define FACTOR(_id, _name, _parent, _mult, _div) { \ 55 .id = _id, \ 56 .name = _name, \ 57 .parent_name = _parent, \ 58 .mult = _mult, \ 59 .div = _div, \ 60 } 61 62 void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, 63 int num, struct clk_onecell_data *clk_data); 64 65 struct mtk_composite { 66 int id; 67 const char *name; 68 const char * const *parent_names; 69 const char *parent; 70 unsigned flags; 71 72 uint32_t mux_reg; 73 uint32_t divider_reg; 74 uint32_t gate_reg; 75 76 signed char mux_shift; 77 signed char mux_width; 78 signed char gate_shift; 79 80 signed char divider_shift; 81 signed char divider_width; 82 83 signed char num_parents; 84 }; 85 86 /* 87 * In case the rate change propagation to parent clocks is undesirable, 88 * this macro allows to specify the clock flags manually. 89 */ 90 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) { \ 91 .id = _id, \ 92 .name = _name, \ 93 .mux_reg = _reg, \ 94 .mux_shift = _shift, \ 95 .mux_width = _width, \ 96 .gate_reg = _reg, \ 97 .gate_shift = _gate, \ 98 .divider_shift = -1, \ 99 .parent_names = _parents, \ 100 .num_parents = ARRAY_SIZE(_parents), \ 101 .flags = _flags, \ 102 } 103 104 /* 105 * Unless necessary, all MUX_GATE clocks propagate rate changes to their 106 * parent clock by default. 107 */ 108 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ 109 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, CLK_SET_RATE_PARENT) 110 111 #define MUX(_id, _name, _parents, _reg, _shift, _width) { \ 112 .id = _id, \ 113 .name = _name, \ 114 .mux_reg = _reg, \ 115 .mux_shift = _shift, \ 116 .mux_width = _width, \ 117 .gate_shift = -1, \ 118 .divider_shift = -1, \ 119 .parent_names = _parents, \ 120 .num_parents = ARRAY_SIZE(_parents), \ 121 .flags = CLK_SET_RATE_PARENT, \ 122 } 123 124 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) { \ 125 .id = _id, \ 126 .parent = _parent, \ 127 .name = _name, \ 128 .divider_reg = _div_reg, \ 129 .divider_shift = _div_shift, \ 130 .divider_width = _div_width, \ 131 .gate_reg = _gate_reg, \ 132 .gate_shift = _gate_shift, \ 133 .mux_shift = -1, \ 134 .flags = 0, \ 135 } 136 137 struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, 138 void __iomem *base, spinlock_t *lock); 139 140 void mtk_clk_register_composites(const struct mtk_composite *mcs, 141 int num, void __iomem *base, spinlock_t *lock, 142 struct clk_onecell_data *clk_data); 143 144 struct mtk_gate_regs { 145 u32 sta_ofs; 146 u32 clr_ofs; 147 u32 set_ofs; 148 }; 149 150 struct mtk_gate { 151 int id; 152 const char *name; 153 const char *parent_name; 154 const struct mtk_gate_regs *regs; 155 int shift; 156 const struct clk_ops *ops; 157 }; 158 159 int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks, 160 int num, struct clk_onecell_data *clk_data); 161 162 struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); 163 164 #define HAVE_RST_BAR BIT(0) 165 166 struct mtk_pll_div_table { 167 u32 div; 168 unsigned long freq; 169 }; 170 171 struct mtk_pll_data { 172 int id; 173 const char *name; 174 uint32_t reg; 175 uint32_t pwr_reg; 176 uint32_t en_mask; 177 uint32_t pd_reg; 178 uint32_t tuner_reg; 179 int pd_shift; 180 unsigned int flags; 181 const struct clk_ops *ops; 182 u32 rst_bar_mask; 183 unsigned long fmax; 184 int pcwbits; 185 uint32_t pcw_reg; 186 int pcw_shift; 187 const struct mtk_pll_div_table *div_table; 188 }; 189 190 void mtk_clk_register_plls(struct device_node *node, 191 const struct mtk_pll_data *plls, int num_plls, 192 struct clk_onecell_data *clk_data); 193 194 struct clk *mtk_clk_register_ref2usb_tx(const char *name, 195 const char *parent_name, void __iomem *reg); 196 197 #ifdef CONFIG_RESET_CONTROLLER 198 void mtk_register_reset_controller(struct device_node *np, 199 unsigned int num_regs, int regofs); 200 #else 201 static inline void mtk_register_reset_controller(struct device_node *np, 202 unsigned int num_regs, int regofs) 203 { 204 } 205 #endif 206 207 #endif /* __DRV_CLK_MTK_H */ 208