1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: James Liao <jamesjj.liao@mediatek.com> 5 */ 6 7 #ifndef __DRV_CLK_MTK_H 8 #define __DRV_CLK_MTK_H 9 10 #include <linux/clk-provider.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/spinlock.h> 14 #include <linux/types.h> 15 16 #define MAX_MUX_GATE_BIT 31 17 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1) 18 19 #define MHZ (1000 * 1000) 20 21 struct platform_device; 22 23 struct mtk_fixed_clk { 24 int id; 25 const char *name; 26 const char *parent; 27 unsigned long rate; 28 }; 29 30 #define FIXED_CLK(_id, _name, _parent, _rate) { \ 31 .id = _id, \ 32 .name = _name, \ 33 .parent = _parent, \ 34 .rate = _rate, \ 35 } 36 37 int mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num, 38 struct clk_hw_onecell_data *clk_data); 39 void mtk_clk_unregister_fixed_clks(const struct mtk_fixed_clk *clks, int num, 40 struct clk_hw_onecell_data *clk_data); 41 42 struct mtk_fixed_factor { 43 int id; 44 const char *name; 45 const char *parent_name; 46 int mult; 47 int div; 48 }; 49 50 #define FACTOR(_id, _name, _parent, _mult, _div) { \ 51 .id = _id, \ 52 .name = _name, \ 53 .parent_name = _parent, \ 54 .mult = _mult, \ 55 .div = _div, \ 56 } 57 58 int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num, 59 struct clk_hw_onecell_data *clk_data); 60 void mtk_clk_unregister_factors(const struct mtk_fixed_factor *clks, int num, 61 struct clk_hw_onecell_data *clk_data); 62 63 struct mtk_composite { 64 int id; 65 const char *name; 66 const char * const *parent_names; 67 const char *parent; 68 unsigned flags; 69 70 uint32_t mux_reg; 71 uint32_t divider_reg; 72 uint32_t gate_reg; 73 74 signed char mux_shift; 75 signed char mux_width; 76 signed char gate_shift; 77 78 signed char divider_shift; 79 signed char divider_width; 80 81 u8 mux_flags; 82 83 signed char num_parents; 84 }; 85 86 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ 87 _width, _gate, _flags, _muxflags) { \ 88 .id = _id, \ 89 .name = _name, \ 90 .mux_reg = _reg, \ 91 .mux_shift = _shift, \ 92 .mux_width = _width, \ 93 .gate_reg = _reg, \ 94 .gate_shift = _gate, \ 95 .divider_shift = -1, \ 96 .parent_names = _parents, \ 97 .num_parents = ARRAY_SIZE(_parents), \ 98 .flags = _flags, \ 99 .mux_flags = _muxflags, \ 100 } 101 102 /* 103 * In case the rate change propagation to parent clocks is undesirable, 104 * this macro allows to specify the clock flags manually. 105 */ 106 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ 107 _gate, _flags) \ 108 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \ 109 _shift, _width, _gate, _flags, 0) 110 111 /* 112 * Unless necessary, all MUX_GATE clocks propagate rate changes to their 113 * parent clock by default. 114 */ 115 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ 116 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ 117 _gate, CLK_SET_RATE_PARENT) 118 119 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ 120 MUX_FLAGS(_id, _name, _parents, _reg, \ 121 _shift, _width, CLK_SET_RATE_PARENT) 122 123 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ 124 .id = _id, \ 125 .name = _name, \ 126 .mux_reg = _reg, \ 127 .mux_shift = _shift, \ 128 .mux_width = _width, \ 129 .gate_shift = -1, \ 130 .divider_shift = -1, \ 131 .parent_names = _parents, \ 132 .num_parents = ARRAY_SIZE(_parents), \ 133 .flags = _flags, \ 134 } 135 136 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \ 137 _div_width, _div_shift) { \ 138 .id = _id, \ 139 .parent = _parent, \ 140 .name = _name, \ 141 .divider_reg = _div_reg, \ 142 .divider_shift = _div_shift, \ 143 .divider_width = _div_width, \ 144 .gate_reg = _gate_reg, \ 145 .gate_shift = _gate_shift, \ 146 .mux_shift = -1, \ 147 .flags = 0, \ 148 } 149 150 int mtk_clk_register_composites(const struct mtk_composite *mcs, int num, 151 void __iomem *base, spinlock_t *lock, 152 struct clk_hw_onecell_data *clk_data); 153 void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num, 154 struct clk_hw_onecell_data *clk_data); 155 156 struct mtk_clk_divider { 157 int id; 158 const char *name; 159 const char *parent_name; 160 unsigned long flags; 161 162 u32 div_reg; 163 unsigned char div_shift; 164 unsigned char div_width; 165 unsigned char clk_divider_flags; 166 const struct clk_div_table *clk_div_table; 167 }; 168 169 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ 170 .id = _id, \ 171 .name = _name, \ 172 .parent_name = _parent, \ 173 .div_reg = _reg, \ 174 .div_shift = _shift, \ 175 .div_width = _width, \ 176 } 177 178 int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num, 179 void __iomem *base, spinlock_t *lock, 180 struct clk_hw_onecell_data *clk_data); 181 void mtk_clk_unregister_dividers(const struct mtk_clk_divider *mcds, int num, 182 struct clk_hw_onecell_data *clk_data); 183 184 struct clk_hw_onecell_data *mtk_alloc_clk_data(unsigned int clk_num); 185 void mtk_free_clk_data(struct clk_hw_onecell_data *clk_data); 186 187 struct clk_hw *mtk_clk_register_ref2usb_tx(const char *name, 188 const char *parent_name, void __iomem *reg); 189 190 void mtk_register_reset_controller(struct device_node *np, 191 unsigned int num_regs, int regofs); 192 193 void mtk_register_reset_controller_set_clr(struct device_node *np, 194 unsigned int num_regs, int regofs); 195 196 struct mtk_clk_desc { 197 const struct mtk_gate *clks; 198 size_t num_clks; 199 }; 200 201 int mtk_clk_simple_probe(struct platform_device *pdev); 202 int mtk_clk_simple_remove(struct platform_device *pdev); 203 204 #endif /* __DRV_CLK_MTK_H */ 205