10fd4939aSFabien Parent // SPDX-License-Identifier: GPL-2.0 20fd4939aSFabien Parent /* 30fd4939aSFabien Parent * Copyright (c) 2019 MediaTek Inc. 40fd4939aSFabien Parent * Author: James Liao <jamesjj.liao@mediatek.com> 50fd4939aSFabien Parent * Fabien Parent <fparent@baylibre.com> 6b8390192SAngeloGioacchino Del Regno * Copyright (c) 2023 Collabora Ltd. 70fd4939aSFabien Parent */ 80fd4939aSFabien Parent 90fd4939aSFabien Parent #include <linux/clk-provider.h> 10*a96cbb14SRob Herring #include <linux/mod_devicetable.h> 110fd4939aSFabien Parent #include <linux/platform_device.h> 120fd4939aSFabien Parent 130fd4939aSFabien Parent #include "clk-mtk.h" 140fd4939aSFabien Parent #include "clk-gate.h" 150fd4939aSFabien Parent 160fd4939aSFabien Parent #include <dt-bindings/clock/mt8516-clk.h> 170fd4939aSFabien Parent 180fd4939aSFabien Parent static const struct mtk_gate_regs aud_cg_regs = { 190fd4939aSFabien Parent .set_ofs = 0x0, 200fd4939aSFabien Parent .clr_ofs = 0x0, 210fd4939aSFabien Parent .sta_ofs = 0x0, 220fd4939aSFabien Parent }; 230fd4939aSFabien Parent 244c85e20bSAngeloGioacchino Del Regno #define GATE_AUD(_id, _name, _parent, _shift) \ 254c85e20bSAngeloGioacchino Del Regno GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 260fd4939aSFabien Parent 27b8390192SAngeloGioacchino Del Regno static const struct mtk_gate aud_clks[] = { 280fd4939aSFabien Parent GATE_AUD(CLK_AUD_AFE, "aud_afe", "clk26m_ck", 2), 290fd4939aSFabien Parent GATE_AUD(CLK_AUD_I2S, "aud_i2s", "i2s_infra_bck", 6), 300fd4939aSFabien Parent GATE_AUD(CLK_AUD_22M, "aud_22m", "rg_aud_engen1", 8), 310fd4939aSFabien Parent GATE_AUD(CLK_AUD_24M, "aud_24m", "rg_aud_engen2", 9), 320fd4939aSFabien Parent GATE_AUD(CLK_AUD_INTDIR, "aud_intdir", "rg_aud_spdif_in", 15), 330fd4939aSFabien Parent GATE_AUD(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "rg_aud_engen2", 18), 340fd4939aSFabien Parent GATE_AUD(CLK_AUD_APLL_TUNER, "aud_apll_tuner", "rg_aud_engen1", 19), 350fd4939aSFabien Parent GATE_AUD(CLK_AUD_HDMI, "aud_hdmi", "apll12_div4", 20), 360fd4939aSFabien Parent GATE_AUD(CLK_AUD_SPDF, "aud_spdf", "apll12_div6", 21), 370fd4939aSFabien Parent GATE_AUD(CLK_AUD_ADC, "aud_adc", "aud_afe", 24), 380fd4939aSFabien Parent GATE_AUD(CLK_AUD_DAC, "aud_dac", "aud_afe", 25), 390fd4939aSFabien Parent GATE_AUD(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "aud_afe", 26), 400fd4939aSFabien Parent GATE_AUD(CLK_AUD_TML, "aud_tml", "aud_afe", 27), 410fd4939aSFabien Parent }; 420fd4939aSFabien Parent 43b8390192SAngeloGioacchino Del Regno static const struct mtk_clk_desc aud_desc = { 44b8390192SAngeloGioacchino Del Regno .clks = aud_clks, 45b8390192SAngeloGioacchino Del Regno .num_clks = ARRAY_SIZE(aud_clks), 46b8390192SAngeloGioacchino Del Regno }; 470fd4939aSFabien Parent 48b8390192SAngeloGioacchino Del Regno static const struct of_device_id of_match_clk_mt8516_aud[] = { 49b8390192SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8516-audsys", .data = &aud_desc }, 50b8390192SAngeloGioacchino Del Regno { /* sentinel */ } 51b8390192SAngeloGioacchino Del Regno }; 5265c9ad77SAngeloGioacchino Del Regno MODULE_DEVICE_TABLE(of, of_match_clk_mt8516_aud); 530fd4939aSFabien Parent 54b8390192SAngeloGioacchino Del Regno static struct platform_driver clk_mt8516_aud_drv = { 55b8390192SAngeloGioacchino Del Regno .probe = mtk_clk_simple_probe, 5661ca6ee7SUwe Kleine-König .remove_new = mtk_clk_simple_remove, 57b8390192SAngeloGioacchino Del Regno .driver = { 58b8390192SAngeloGioacchino Del Regno .name = "clk-mt8516-aud", 59b8390192SAngeloGioacchino Del Regno .of_match_table = of_match_clk_mt8516_aud, 60b8390192SAngeloGioacchino Del Regno }, 61b8390192SAngeloGioacchino Del Regno }; 62164d240dSAngeloGioacchino Del Regno module_platform_driver(clk_mt8516_aud_drv); 630fd4939aSFabien Parent 64b8390192SAngeloGioacchino Del Regno MODULE_DESCRIPTION("MediaTek MT8516 audiosys clocks driver"); 65b8390192SAngeloGioacchino Del Regno MODULE_LICENSE("GPL"); 66