1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2022 MediaTek Inc.
4  * Copyright (C) 2023 Collabora Ltd.
5  *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6  */
7 
8 #include <dt-bindings/clock/mediatek,mt8365-clk.h>
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/of.h>
14 #include <linux/of_address.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
18 
19 #include "clk-gate.h"
20 #include "clk-mtk.h"
21 #include "clk-mux.h"
22 
23 static DEFINE_SPINLOCK(mt8365_clk_lock);
24 
25 static const struct mtk_fixed_clk top_fixed_clks[] = {
26 	FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
27 	FIXED_CLK(CLK_TOP_I2S0_BCK, "i2s0_bck", NULL, 26000000),
28 	FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m",
29 		  75000000),
30 	FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", "clk26m", 75000000),
31 	FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m",
32 		  52500000),
33 };
34 
35 static const struct mtk_fixed_factor top_divs[] = {
36 	FACTOR(CLK_TOP_SYS_26M_D2, "sys_26m_d2", "clk26m", 1, 2),
37 	FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
38 	FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
39 	FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
40 	FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
41 	FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32),
42 	FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
43 	FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6),
44 	FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
45 	FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
46 	FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
47 	FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
48 	FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
49 	FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
50 	FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
51 	FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
52 	FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ_en", 1, 2),
53 	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
54 	FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
55 	FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
56 	FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
57 	FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
58 	FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
59 	FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
60 	FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll", 1, 96),
61 	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
62 	FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
63 	FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
64 	FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
65 	FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
66 	FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1),
67 	FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
68 	FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
69 	FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
70 	FACTOR(CLK_TOP_LVDSPLL_D16, "lvdspll_d16", "lvdspll", 1, 16),
71 	FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "usb20_en", 1, 13),
72 	FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4),
73 	FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", "usb20_192m_ck", 1, 8),
74 	FACTOR(CLK_TOP_USB20_192M_D16, "usb20_192m_d16", "usb20_192m_ck",
75 	       1, 16),
76 	FACTOR(CLK_TOP_USB20_192M_D32, "usb20_192m_d32", "usb20_192m_ck",
77 	       1, 32),
78 	FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
79 	FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
80 	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4),
81 	FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8),
82 	FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
83 	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
84 	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4),
85 	FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, 8),
86 	FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
87 	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
88 	FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", "dsppll", 1, 1),
89 	FACTOR(CLK_TOP_DSPPLL_D2, "dsppll_d2", "dsppll", 1, 2),
90 	FACTOR(CLK_TOP_DSPPLL_D4, "dsppll_d4", "dsppll", 1, 4),
91 	FACTOR(CLK_TOP_DSPPLL_D8, "dsppll_d8", "dsppll", 1, 8),
92 	FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 1),
93 	FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1, 52),
94 };
95 
96 static const char * const axi_parents[] = {
97 	"clk26m",
98 	"syspll_d7",
99 	"syspll1_d4",
100 	"syspll3_d2"
101 };
102 
103 static const char * const mem_parents[] = {
104 	"clk26m",
105 	"mmpll_ck",
106 	"syspll_d3",
107 	"syspll1_d2"
108 };
109 
110 static const char * const mm_parents[] = {
111 	"clk26m",
112 	"mmpll_ck",
113 	"syspll1_d2",
114 	"syspll_d5",
115 	"syspll1_d4",
116 	"univpll_d5",
117 	"univpll1_d2",
118 	"mmpll_d2"
119 };
120 
121 static const char * const scp_parents[] = {
122 	"clk26m",
123 	"syspll4_d2",
124 	"univpll2_d2",
125 	"syspll1_d2",
126 	"univpll1_d2",
127 	"syspll_d3",
128 	"univpll_d3"
129 };
130 
131 static const char * const mfg_parents[] = {
132 	"clk26m",
133 	"mfgpll_ck",
134 	"syspll_d3",
135 	"univpll_d3"
136 };
137 
138 static const char * const atb_parents[] = {
139 	"clk26m",
140 	"syspll1_d4",
141 	"syspll1_d2"
142 };
143 
144 static const char * const camtg_parents[] = {
145 	"clk26m",
146 	"usb20_192m_d8",
147 	"univpll2_d8",
148 	"usb20_192m_d4",
149 	"univpll2_d32",
150 	"usb20_192m_d16",
151 	"usb20_192m_d32"
152 };
153 
154 static const char * const uart_parents[] = {
155 	"clk26m",
156 	"univpll2_d8"
157 };
158 
159 static const char * const spi_parents[] = {
160 	"clk26m",
161 	"univpll2_d2",
162 	"univpll2_d4",
163 	"univpll2_d8"
164 };
165 
166 static const char * const msdc50_0_hc_parents[] = {
167 	"clk26m",
168 	"syspll1_d2",
169 	"univpll1_d4",
170 	"syspll2_d2"
171 };
172 
173 static const char * const msdc50_0_parents[] = {
174 	"clk26m",
175 	"msdcpll_ck",
176 	"univpll1_d2",
177 	"syspll1_d2",
178 	"univpll_d5",
179 	"syspll2_d2",
180 	"univpll1_d4",
181 	"syspll4_d2"
182 };
183 
184 static const char * const msdc50_2_parents[] = {
185 	"clk26m",
186 	"msdcpll_ck",
187 	"univpll_d3",
188 	"univpll1_d2",
189 	"syspll1_d2",
190 	"univpll2_d2",
191 	"syspll2_d2",
192 	"univpll1_d4"
193 };
194 
195 static const char * const msdc30_1_parents[] = {
196 	"clk26m",
197 	"msdcpll_d2",
198 	"univpll2_d2",
199 	"syspll2_d2",
200 	"univpll1_d4",
201 	"syspll1_d4",
202 	"syspll2_d4",
203 	"univpll2_d8"
204 };
205 
206 static const char * const audio_parents[] = {
207 	"clk26m",
208 	"syspll3_d4",
209 	"syspll4_d4",
210 	"syspll1_d16"
211 };
212 
213 static const char * const aud_intbus_parents[] = {
214 	"clk26m",
215 	"syspll1_d4",
216 	"syspll4_d2"
217 };
218 
219 static const char * const aud_1_parents[] = {
220 	"clk26m",
221 	"apll1_ck"
222 };
223 
224 static const char * const aud_2_parents[] = {
225 	"clk26m",
226 	"apll2_ck"
227 };
228 
229 static const char * const aud_engen1_parents[] = {
230 	"clk26m",
231 	"apll1_d2",
232 	"apll1_d4",
233 	"apll1_d8"
234 };
235 
236 static const char * const aud_engen2_parents[] = {
237 	"clk26m",
238 	"apll2_d2",
239 	"apll2_d4",
240 	"apll2_d8"
241 };
242 
243 static const char * const aud_spdif_parents[] = {
244 	"clk26m",
245 	"univpll_d2"
246 };
247 
248 static const char * const disp_pwm_parents[] = {
249 	"clk26m",
250 	"univpll2_d4"
251 };
252 
253 static const char * const dxcc_parents[] = {
254 	"clk26m",
255 	"syspll1_d2",
256 	"syspll1_d4",
257 	"syspll1_d8"
258 };
259 
260 static const char * const ssusb_sys_parents[] = {
261 	"clk26m",
262 	"univpll3_d4",
263 	"univpll2_d4",
264 	"univpll3_d2"
265 };
266 
267 static const char * const spm_parents[] = {
268 	"clk26m",
269 	"syspll1_d8"
270 };
271 
272 static const char * const i2c_parents[] = {
273 	"clk26m",
274 	"univpll3_d4",
275 	"univpll3_d2",
276 	"syspll1_d8",
277 	"syspll2_d8"
278 };
279 
280 static const char * const pwm_parents[] = {
281 	"clk26m",
282 	"univpll3_d4",
283 	"syspll1_d8"
284 };
285 
286 static const char * const senif_parents[] = {
287 	"clk26m",
288 	"univpll1_d4",
289 	"univpll1_d2",
290 	"univpll2_d2"
291 };
292 
293 static const char * const aes_fde_parents[] = {
294 	"clk26m",
295 	"msdcpll_ck",
296 	"univpll_d3",
297 	"univpll2_d2",
298 	"univpll1_d2",
299 	"syspll1_d2"
300 };
301 
302 static const char * const dpi0_parents[] = {
303 	"clk26m",
304 	"lvdspll_d2",
305 	"lvdspll_d4",
306 	"lvdspll_d8",
307 	"lvdspll_d16"
308 };
309 
310 static const char * const dsp_parents[] = {
311 	"clk26m",
312 	"sys_26m_d2",
313 	"dsppll_ck",
314 	"dsppll_d2",
315 	"dsppll_d4",
316 	"dsppll_d8"
317 };
318 
319 static const char * const nfi2x_parents[] = {
320 	"clk26m",
321 	"syspll2_d2",
322 	"syspll_d7",
323 	"syspll_d3",
324 	"syspll2_d4",
325 	"msdcpll_d2",
326 	"univpll1_d2",
327 	"univpll_d5"
328 };
329 
330 static const char * const nfiecc_parents[] = {
331 	"clk26m",
332 	"syspll4_d2",
333 	"univpll2_d4",
334 	"syspll_d7",
335 	"univpll1_d2",
336 	"syspll1_d2",
337 	"univpll2_d2",
338 	"syspll_d5"
339 };
340 
341 static const char * const ecc_parents[] = {
342 	"clk26m",
343 	"univpll2_d2",
344 	"univpll1_d2",
345 	"univpll_d3",
346 	"syspll_d2"
347 };
348 
349 static const char * const eth_parents[] = {
350 	"clk26m",
351 	"univpll2_d8",
352 	"syspll4_d4",
353 	"syspll1_d8",
354 	"syspll4_d2"
355 };
356 
357 static const char * const gcpu_parents[] = {
358 	"clk26m",
359 	"univpll_d3",
360 	"univpll2_d2",
361 	"syspll_d3",
362 	"syspll2_d2"
363 };
364 
365 static const char * const gcpu_cpm_parents[] = {
366 	"clk26m",
367 	"univpll2_d2",
368 	"syspll2_d2"
369 };
370 
371 static const char * const apu_parents[] = {
372 	"clk26m",
373 	"univpll_d2",
374 	"apupll_ck",
375 	"mmpll_ck",
376 	"syspll_d3",
377 	"univpll1_d2",
378 	"syspll1_d2",
379 	"syspll1_d4"
380 };
381 
382 static const char * const mbist_diag_parents[] = {
383 	"clk26m",
384 	"syspll4_d4",
385 	"univpll2_d8"
386 };
387 
388 static const char * const apll_i2s_parents[] = {
389 	"aud_1_sel",
390 	"aud_2_sel"
391 };
392 
393 static struct mtk_composite top_misc_muxes[] = {
394 	/* CLK_CFG_11 */
395 	MUX_GATE(CLK_TOP_MBIST_DIAG_SEL, "mbist_diag_sel", mbist_diag_parents,
396 		 0x0ec, 0, 2, 7),
397 	/* Audio MUX */
398 	MUX(CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", apll_i2s_parents, 0x0320, 11, 1),
399 	MUX(CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", apll_i2s_parents, 0x0320, 12, 1),
400 	MUX(CLK_TOP_APLL_I2S2_SEL, "apll_i2s2_sel", apll_i2s_parents, 0x0320, 13, 1),
401 	MUX(CLK_TOP_APLL_I2S3_SEL, "apll_i2s3_sel", apll_i2s_parents, 0x0320, 14, 1),
402 	MUX(CLK_TOP_APLL_TDMOUT_SEL, "apll_tdmout_sel", apll_i2s_parents, 0x0320, 15, 1),
403 	MUX(CLK_TOP_APLL_TDMIN_SEL, "apll_tdmin_sel", apll_i2s_parents, 0x0320, 16, 1),
404 	MUX(CLK_TOP_APLL_SPDIF_SEL, "apll_spdif_sel", apll_i2s_parents, 0x0320, 17, 1),
405 };
406 
407 #define CLK_CFG_UPDATE 0x004
408 #define CLK_CFG_UPDATE1 0x008
409 
410 static const struct mtk_mux top_muxes[] = {
411 	/* CLK_CFG_0 */
412 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
413 				   0x040, 0x044, 0x048, 0, 2, 7, CLK_CFG_UPDATE,
414 				   0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
415 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040,
416 			     0x044, 0x048, 8, 2, 15, CLK_CFG_UPDATE, 1),
417 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044,
418 			     0x048, 16, 3, 23, CLK_CFG_UPDATE, 2),
419 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x040,
420 			     0x044, 0x048, 24, 3, 31, CLK_CFG_UPDATE, 3),
421 	/* CLK_CFG_1 */
422 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050,
423 			     0x054, 0x058, 0, 2, 7, CLK_CFG_UPDATE, 4),
424 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x050,
425 			     0x054, 0x058, 8, 2, 15, CLK_CFG_UPDATE, 5),
426 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
427 			     0x050, 0x054, 0x058, 16, 3, 23, CLK_CFG_UPDATE, 6),
428 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,
429 			     0x050, 0x054, 0x058, 24, 3, 31, CLK_CFG_UPDATE, 7),
430 	/* CLK_CFG_2 */
431 	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060,
432 			     0x064, 0x068, 0, 1, 7, CLK_CFG_UPDATE, 8),
433 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060,
434 			     0x064, 0x068, 8, 2, 15, CLK_CFG_UPDATE, 9),
435 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, "msdc50_0_hc_sel",
436 				   msdc50_0_hc_parents, 0x060, 0x064, 0x068, 16, 2,
437 				   23, CLK_CFG_UPDATE, 10, 0),
438 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, "msdc2_2_hc_sel",
439 				   msdc50_0_hc_parents, 0x060, 0x064, 0x068, 24, 2,
440 				   31, CLK_CFG_UPDATE, 11, 0),
441 	/* CLK_CFG_3 */
442 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
443 				   msdc50_0_parents, 0x070, 0x074, 0x078, 0, 3, 7,
444 				   CLK_CFG_UPDATE, 12, 0),
445 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, "msdc50_2_sel",
446 				   msdc50_2_parents, 0x070, 0x074, 0x078, 8, 3, 15,
447 				   CLK_CFG_UPDATE, 13, 0),
448 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
449 				   msdc30_1_parents, 0x070, 0x074, 0x078, 16, 3, 23,
450 				   CLK_CFG_UPDATE, 14, 0),
451 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
452 			     0x070, 0x074, 0x078, 24, 2, 31, CLK_CFG_UPDATE,
453 			     15),
454 	/* CLK_CFG_4 */
455 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
456 			     aud_intbus_parents, 0x080, 0x084, 0x088, 0, 2, 7,
457 			     CLK_CFG_UPDATE, 16),
458 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
459 			     0x080, 0x084, 0x088, 8, 1, 15, CLK_CFG_UPDATE, 17),
460 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents,
461 			     0x080, 0x084, 0x088, 16, 1, 23, CLK_CFG_UPDATE,
462 			     18),
463 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
464 			     aud_engen1_parents, 0x080, 0x084, 0x088, 24, 2, 31,
465 			     CLK_CFG_UPDATE, 19),
466 	/* CLK_CFG_5 */
467 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel",
468 			     aud_engen2_parents, 0x090, 0x094, 0x098, 0, 2, 7,
469 			     CLK_CFG_UPDATE, 20),
470 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SPDIF_SEL, "aud_spdif_sel",
471 			     aud_spdif_parents, 0x090, 0x094, 0x098, 8, 1, 15,
472 			     CLK_CFG_UPDATE, 21),
473 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
474 			     disp_pwm_parents, 0x090, 0x094, 0x098, 16, 2, 23,
475 			     CLK_CFG_UPDATE, 22),
476 	/* CLK_CFG_6 */
477 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents,
478 				   0x0a0, 0x0a4, 0x0a8, 0, 2, 7, CLK_CFG_UPDATE,
479 				   24, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
480 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_SYS_SEL, "ssusb_sys_sel",
481 			     ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 8, 2, 15,
482 			     CLK_CFG_UPDATE, 25),
483 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel",
484 			     ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 16, 2, 23,
485 			     CLK_CFG_UPDATE, 26),
486 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", spm_parents,
487 				   0x0a0, 0x0a4, 0x0a8, 24, 1, 31, CLK_CFG_UPDATE,
488 				   27, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
489 	/* CLK_CFG_7 */
490 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x0b0,
491 			     0x0b4, 0x0b8, 0, 3, 7, CLK_CFG_UPDATE, 28),
492 	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0b0,
493 			     0x0b4, 0x0b8, 8, 2, 15, CLK_CFG_UPDATE, 29),
494 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENIF_SEL, "senif_sel", senif_parents,
495 			     0x0b0, 0x0b4, 0x0b8, 16, 2, 23, CLK_CFG_UPDATE,
496 			     30),
497 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel",
498 			     aes_fde_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31,
499 			     CLK_CFG_UPDATE, 31),
500 	/* CLK_CFG_8 */
501 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", senif_parents,
502 			     0x0c0, 0x0c4, 0x0c8, 0, 2, 7, CLK_CFG_UPDATE1, 0),
503 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0c0,
504 			     0x0c4, 0x0c8, 8, 3, 15, CLK_CFG_UPDATE1, 1),
505 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi0_parents, 0x0c0,
506 			     0x0c4, 0x0c8, 16, 3, 23, CLK_CFG_UPDATE1, 2),
507 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel", dsp_parents, 0x0c0,
508 			     0x0c4, 0x0c8, 24, 3, 31, CLK_CFG_UPDATE1, 3),
509 	/* CLK_CFG_9 */
510 	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
511 			     0x0d0, 0x0d4, 0x0d8, 0, 3, 7, CLK_CFG_UPDATE1, 4),
512 	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
513 			     0x0d0, 0x0d4, 0x0d8, 8, 3, 15, CLK_CFG_UPDATE1, 5),
514 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel", ecc_parents, 0x0d0,
515 			     0x0d4, 0x0d8, 16, 3, 23, CLK_CFG_UPDATE1, 6),
516 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x0d0,
517 			     0x0d4, 0x0d8, 24, 3, 31, CLK_CFG_UPDATE1, 7),
518 	/* CLK_CFG_10 */
519 	MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0e0,
520 			     0x0e4, 0x0e8, 0, 3, 7, CLK_CFG_UPDATE1, 8),
521 	MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_CPM_SEL, "gcpu_cpm_sel",
522 			     gcpu_cpm_parents, 0x0e0, 0x0e4, 0x0e8, 8, 2, 15,
523 			     CLK_CFG_UPDATE1, 9),
524 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_SEL, "apu_sel", apu_parents, 0x0e0,
525 			     0x0e4, 0x0e8, 16, 3, 23, CLK_CFG_UPDATE1, 10),
526 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_IF_SEL, "apu_if_sel", apu_parents,
527 			     0x0e0, 0x0e4, 0x0e8, 24, 3, 31, CLK_CFG_UPDATE1,
528 			     11),
529 };
530 
531 static const char * const mcu_bus_parents[] = {
532 	"clk26m",
533 	"armpll",
534 	"mainpll",
535 	"univpll_d2"
536 };
537 
538 static struct mtk_composite mcu_muxes[] = {
539 	/* bus_pll_divider_cfg */
540 	MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
541 		       9, 2, -1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
542 };
543 
544 #define DIV_ADJ_F(_id, _name, _parent, _reg, _shift, _width, _flags) {	\
545 		.id = _id,					\
546 		.name = _name,					\
547 		.parent_name = _parent,				\
548 		.div_reg = _reg,				\
549 		.div_shift = _shift,				\
550 		.div_width = _width,				\
551 		.clk_divider_flags = _flags,			\
552 }
553 
554 static const struct mtk_clk_divider top_adj_divs[] = {
555 	DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "apll_i2s0_sel",
556 		  0x324, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
557 	DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "apll_i2s1_sel",
558 		  0x324, 8, 8, CLK_DIVIDER_ROUND_CLOSEST),
559 	DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "apll_i2s2_sel",
560 		  0x324, 16, 8, CLK_DIVIDER_ROUND_CLOSEST),
561 	DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "apll_i2s3_sel",
562 		  0x324, 24, 8, CLK_DIVIDER_ROUND_CLOSEST),
563 	DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "apll_tdmout_sel",
564 		  0x328, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
565 	DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll_tdmout_sel",
566 		  0x328, 8, 8, CLK_DIVIDER_ROUND_CLOSEST),
567 	DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "apll_tdmin_sel",
568 		  0x328, 16, 8, CLK_DIVIDER_ROUND_CLOSEST),
569 	DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll_tdmin_sel",
570 		  0x328, 24, 8, CLK_DIVIDER_ROUND_CLOSEST),
571 	DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "apll_spdif_sel",
572 		  0x32c, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
573 };
574 
575 static const struct mtk_gate_regs top0_cg_regs = {
576 	.set_ofs = 0,
577 	.clr_ofs = 0,
578 	.sta_ofs = 0,
579 };
580 
581 static const struct mtk_gate_regs top1_cg_regs = {
582 	.set_ofs = 0x104,
583 	.clr_ofs = 0x104,
584 	.sta_ofs = 0x104,
585 };
586 
587 static const struct mtk_gate_regs top2_cg_regs = {
588 	.set_ofs = 0x320,
589 	.clr_ofs = 0x320,
590 	.sta_ofs = 0x320,
591 };
592 
593 #define GATE_TOP0(_id, _name, _parent, _shift)			\
594 	GATE_MTK(_id, _name, _parent, &top0_cg_regs,		\
595 		 _shift, &mtk_clk_gate_ops_no_setclr)
596 
597 #define GATE_TOP1(_id, _name, _parent, _shift)			\
598 	GATE_MTK(_id, _name, _parent, &top1_cg_regs,		\
599 		 _shift, &mtk_clk_gate_ops_no_setclr_inv)
600 
601 #define GATE_TOP2(_id, _name, _parent, _shift)			\
602 	GATE_MTK(_id, _name, _parent, &top2_cg_regs,		\
603 		 _shift, &mtk_clk_gate_ops_no_setclr_inv)
604 
605 static const struct mtk_gate top_clk_gates[] = {
606 	GATE_TOP0(CLK_TOP_CONN_32K, "conn_32k", "clk32k", 10),
607 	GATE_TOP0(CLK_TOP_CONN_26M, "conn_26m", "clk26m", 11),
608 	GATE_TOP0(CLK_TOP_DSP_32K, "dsp_32k", "clk32k", 16),
609 	GATE_TOP0(CLK_TOP_DSP_26M, "dsp_26m", "clk26m", 17),
610 	GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_192m_d4", 8),
611 	GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "usb20_192m_d4", 9),
612 	GATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, "lvdstx_dig_en", "lvdstx_dig_cts", 20),
613 	GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, "vpll_dpix_en", "vpll_dpix", 21),
614 	GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, "ssusb_top_ck_en", NULL, 22),
615 	GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, "ssusb_phy_ck_en", NULL, 23),
616 	GATE_TOP2(CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0),
617 	GATE_TOP2(CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 1),
618 	GATE_TOP2(CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 2),
619 	GATE_TOP2(CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 3),
620 	GATE_TOP2(CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 4),
621 	GATE_TOP2(CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b", 5),
622 	GATE_TOP2(CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 6),
623 	GATE_TOP2(CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 7),
624 	GATE_TOP2(CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 8),
625 };
626 
627 static const struct mtk_gate_regs ifr2_cg_regs = {
628 	.set_ofs = 0x80,
629 	.clr_ofs = 0x84,
630 	.sta_ofs = 0x90,
631 };
632 
633 static const struct mtk_gate_regs ifr3_cg_regs = {
634 	.set_ofs = 0x88,
635 	.clr_ofs = 0x8c,
636 	.sta_ofs = 0x94,
637 };
638 
639 static const struct mtk_gate_regs ifr4_cg_regs = {
640 	.set_ofs = 0xa4,
641 	.clr_ofs = 0xa8,
642 	.sta_ofs = 0xac,
643 };
644 
645 static const struct mtk_gate_regs ifr5_cg_regs = {
646 	.set_ofs = 0xc0,
647 	.clr_ofs = 0xc4,
648 	.sta_ofs = 0xc8,
649 };
650 
651 static const struct mtk_gate_regs ifr6_cg_regs = {
652 	.set_ofs = 0xd0,
653 	.clr_ofs = 0xd4,
654 	.sta_ofs = 0xd8,
655 };
656 
657 #define GATE_IFRX(_id, _name, _parent, _shift, _regs)	\
658 	GATE_MTK(_id, _name, _parent, _regs, _shift,	\
659 		 &mtk_clk_gate_ops_setclr)
660 
661 #define GATE_IFR2(_id, _name, _parent, _shift)		\
662 	GATE_IFRX(_id, _name, _parent, _shift, &ifr2_cg_regs)
663 
664 #define GATE_IFR3(_id, _name, _parent, _shift)		\
665 	GATE_IFRX(_id, _name, _parent, _shift, &ifr3_cg_regs)
666 
667 #define GATE_IFR4(_id, _name, _parent, _shift)		\
668 	GATE_IFRX(_id, _name, _parent, _shift, &ifr4_cg_regs)
669 
670 #define GATE_IFR5(_id, _name, _parent, _shift)		\
671 	GATE_IFRX(_id, _name, _parent, _shift, &ifr5_cg_regs)
672 
673 #define GATE_IFR6(_id, _name, _parent, _shift)		\
674 	GATE_IFRX(_id, _name, _parent, _shift, &ifr6_cg_regs)
675 
676 static const struct mtk_gate ifr_clks[] = {
677 	/* IFR2 */
678 	GATE_IFR2(CLK_IFR_PMIC_TMR, "ifr_pmic_tmr", "clk26m", 0),
679 	GATE_IFR2(CLK_IFR_PMIC_AP, "ifr_pmic_ap", "clk26m", 1),
680 	GATE_IFR2(CLK_IFR_PMIC_MD, "ifr_pmic_md", "clk26m", 2),
681 	GATE_IFR2(CLK_IFR_PMIC_CONN, "ifr_pmic_conn", "clk26m", 3),
682 	GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_sel", 8),
683 	GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_sel", 9),
684 	GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_sel", 10),
685 	GATE_IFR2(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "axi_sel", 15),
686 	GATE_IFR2(CLK_IFR_PWM1, "ifr_pwm1", "pwm_sel", 16),
687 	GATE_IFR2(CLK_IFR_PWM2, "ifr_pwm2", "pwm_sel", 17),
688 	GATE_IFR2(CLK_IFR_PWM3, "ifr_pwm3", "pwm_sel", 18),
689 	GATE_IFR2(CLK_IFR_PWM4, "ifr_pwm4", "pwm_sel", 19),
690 	GATE_IFR2(CLK_IFR_PWM5, "ifr_pwm5", "pwm_sel", 20),
691 	GATE_IFR2(CLK_IFR_PWM, "ifr_pwm", "pwm_sel", 21),
692 	GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "uart_sel", 22),
693 	GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "uart_sel", 23),
694 	GATE_IFR2(CLK_IFR_UART2, "ifr_uart2", "uart_sel", 24),
695 	GATE_IFR2(CLK_IFR_DSP_UART, "ifr_dsp_uart", "uart_sel", 26),
696 	GATE_IFR2(CLK_IFR_GCE_26M, "ifr_gce_26m", "clk26m", 27),
697 	GATE_IFR2(CLK_IFR_CQ_DMA_FPC, "ifr_cq_dma_fpc", "axi_sel", 28),
698 	GATE_IFR2(CLK_IFR_BTIF, "ifr_btif", "axi_sel", 31),
699 	/* IFR3 */
700 	GATE_IFR3(CLK_IFR_SPI0, "ifr_spi0", "spi_sel", 1),
701 	GATE_IFR3(CLK_IFR_MSDC0_HCLK, "ifr_msdc0", "msdc50_0_hc_sel", 2),
702 	GATE_IFR3(CLK_IFR_MSDC2_HCLK, "ifr_msdc2", "msdc2_2_hc_sel", 3),
703 	GATE_IFR3(CLK_IFR_MSDC1_HCLK, "ifr_msdc1", "axi_sel", 4),
704 	GATE_IFR3(CLK_IFR_DVFSRC, "ifr_dvfsrc", "clk26m", 7),
705 	GATE_IFR3(CLK_IFR_GCPU, "ifr_gcpu", "axi_sel", 8),
706 	GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_sel", 9),
707 	GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "clk26m", 10),
708 	GATE_IFR3(CLK_IFR_CPUM, "ifr_cpum", "clk26m", 11),
709 	GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "clk26m", 14),
710 	GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_sel", 18),
711 	GATE_IFR3(CLK_IFR_DEBUGSYS, "ifr_debugsys", "axi_sel", 24),
712 	GATE_IFR3(CLK_IFR_AUDIO, "ifr_audio", "axi_sel", 25),
713 	/* IFR4 */
714 	GATE_IFR4(CLK_IFR_PWM_FBCLK6, "ifr_pwm_fbclk6", "pwm_sel", 0),
715 	GATE_IFR4(CLK_IFR_DISP_PWM, "ifr_disp_pwm", "disp_pwm_sel", 2),
716 	GATE_IFR4(CLK_IFR_AUD_26M_BK, "ifr_aud_26m_bk", "clk26m", 4),
717 	GATE_IFR4(CLK_IFR_CQ_DMA, "ifr_cq_dma", "axi_sel", 27),
718 	/* IFR5 */
719 	GATE_IFR5(CLK_IFR_MSDC0_SF, "ifr_msdc0_sf", "msdc50_0_sel", 0),
720 	GATE_IFR5(CLK_IFR_MSDC1_SF, "ifr_msdc1_sf", "msdc50_0_sel", 1),
721 	GATE_IFR5(CLK_IFR_MSDC2_SF, "ifr_msdc2_sf", "msdc50_0_sel", 2),
722 	GATE_IFR5(CLK_IFR_AP_MSDC0, "ifr_ap_msdc0", "msdc50_0_sel", 7),
723 	GATE_IFR5(CLK_IFR_MD_MSDC0, "ifr_md_msdc0", "msdc50_0_sel", 8),
724 	GATE_IFR5(CLK_IFR_MSDC0_SRC, "ifr_msdc0_src", "msdc50_0_sel", 9),
725 	GATE_IFR5(CLK_IFR_MSDC1_SRC, "ifr_msdc1_src", "msdc30_1_sel", 10),
726 	GATE_IFR5(CLK_IFR_MSDC2_SRC, "ifr_msdc2_src", "msdc50_2_sel", 11),
727 	GATE_IFR5(CLK_IFR_PWRAP_TMR, "ifr_pwrap_tmr", "clk26m", 12),
728 	GATE_IFR5(CLK_IFR_PWRAP_SPI, "ifr_pwrap_spi", "clk26m", 13),
729 	GATE_IFR5(CLK_IFR_PWRAP_SYS, "ifr_pwrap_sys", "clk26m", 14),
730 	GATE_MTK_FLAGS(CLK_IFR_MCU_PM_BK, "ifr_mcu_pm_bk", NULL, &ifr5_cg_regs,
731 			17, &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED),
732 	GATE_IFR5(CLK_IFR_IRRX_26M, "ifr_irrx_26m", "clk26m", 22),
733 	GATE_IFR5(CLK_IFR_IRRX_32K, "ifr_irrx_32k", "clk32k", 23),
734 	GATE_IFR5(CLK_IFR_I2C0_AXI, "ifr_i2c0_axi", "i2c_sel", 24),
735 	GATE_IFR5(CLK_IFR_I2C1_AXI, "ifr_i2c1_axi", "i2c_sel", 25),
736 	GATE_IFR5(CLK_IFR_I2C2_AXI, "ifr_i2c2_axi", "i2c_sel", 26),
737 	GATE_IFR5(CLK_IFR_I2C3_AXI, "ifr_i2c3_axi", "i2c_sel", 27),
738 	GATE_IFR5(CLK_IFR_NIC_AXI, "ifr_nic_axi", "axi_sel", 28),
739 	GATE_IFR5(CLK_IFR_NIC_SLV_AXI, "ifr_nic_slv_axi", "axi_sel", 29),
740 	GATE_IFR5(CLK_IFR_APU_AXI, "ifr_apu_axi", "axi_sel", 30),
741 	/* IFR6 */
742 	GATE_IFR6(CLK_IFR_NFIECC, "ifr_nfiecc", "nfiecc_sel", 0),
743 	GATE_IFR6(CLK_IFR_NFI1X_BK, "ifr_nfi1x_bk", "nfi2x_sel", 1),
744 	GATE_IFR6(CLK_IFR_NFIECC_BK, "ifr_nfiecc_bk", "nfi2x_sel", 2),
745 	GATE_IFR6(CLK_IFR_NFI_BK, "ifr_nfi_bk", "axi_sel", 3),
746 	GATE_IFR6(CLK_IFR_MSDC2_AP_BK, "ifr_msdc2_ap_bk", "axi_sel", 4),
747 	GATE_IFR6(CLK_IFR_MSDC2_MD_BK, "ifr_msdc2_md_bk", "axi_sel", 5),
748 	GATE_IFR6(CLK_IFR_MSDC2_BK, "ifr_msdc2_bk", "axi_sel", 6),
749 	GATE_IFR6(CLK_IFR_SUSB_133_BK, "ifr_susb_133_bk", "axi_sel", 7),
750 	GATE_IFR6(CLK_IFR_SUSB_66_BK, "ifr_susb_66_bk", "axi_sel", 8),
751 	GATE_IFR6(CLK_IFR_SSUSB_SYS, "ifr_ssusb_sys", "ssusb_sys_sel", 9),
752 	GATE_IFR6(CLK_IFR_SSUSB_REF, "ifr_ssusb_ref", "ssusb_sys_sel", 10),
753 	GATE_IFR6(CLK_IFR_SSUSB_XHCI, "ifr_ssusb_xhci", "ssusb_xhci_sel", 11),
754 };
755 
756 static const struct mtk_gate_regs peri_cg_regs = {
757 	.set_ofs = 0x20c,
758 	.clr_ofs = 0x20c,
759 	.sta_ofs = 0x20c,
760 };
761 
762 static const struct mtk_gate peri_clks[] = {
763 	GATE_MTK(CLK_PERIAXI, "periaxi", "axi_sel", &peri_cg_regs, 31,
764 		 &mtk_clk_gate_ops_no_setclr),
765 };
766 
767 static const struct mtk_clk_desc topck_desc = {
768 	.clks = top_clk_gates,
769 	.num_clks = ARRAY_SIZE(top_clk_gates),
770 	.fixed_clks = top_fixed_clks,
771 	.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
772 	.factor_clks = top_divs,
773 	.num_factor_clks = ARRAY_SIZE(top_divs),
774 	.mux_clks = top_muxes,
775 	.num_mux_clks = ARRAY_SIZE(top_muxes),
776 	.composite_clks = top_misc_muxes,
777 	.num_composite_clks = ARRAY_SIZE(top_misc_muxes),
778 	.divider_clks = top_adj_divs,
779 	.num_divider_clks = ARRAY_SIZE(top_adj_divs),
780 	.clk_lock = &mt8365_clk_lock,
781 };
782 
783 static const struct mtk_clk_desc infra_desc = {
784 	.clks = ifr_clks,
785 	.num_clks = ARRAY_SIZE(ifr_clks),
786 };
787 
788 static const struct mtk_clk_desc peri_desc = {
789 	.clks = peri_clks,
790 	.num_clks = ARRAY_SIZE(peri_clks),
791 };
792 
793 static const struct mtk_clk_desc mcu_desc = {
794 	.composite_clks = mcu_muxes,
795 	.num_composite_clks = ARRAY_SIZE(mcu_muxes),
796 	.clk_lock = &mt8365_clk_lock,
797 };
798 
799 static const struct of_device_id of_match_clk_mt8365[] = {
800 	{ .compatible = "mediatek,mt8365-topckgen", .data = &topck_desc },
801 	{ .compatible = "mediatek,mt8365-infracfg", .data = &infra_desc },
802 	{ .compatible = "mediatek,mt8365-pericfg", .data = &peri_desc },
803 	{ .compatible = "mediatek,mt8365-mcucfg", .data = &mcu_desc },
804 	{ /* sentinel */ }
805 };
806 MODULE_DEVICE_TABLE(of, of_match_clk_mt8365);
807 
808 static struct platform_driver clk_mt8365_drv = {
809 	.driver = {
810 		.name = "clk-mt8365",
811 		.of_match_table = of_match_clk_mt8365,
812 	},
813 	.probe = mtk_clk_simple_probe,
814 	.remove_new = mtk_clk_simple_remove,
815 };
816 module_platform_driver(clk_mt8365_drv);
817 MODULE_LICENSE("GPL");
818