1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <dt-bindings/clock/mediatek,mt8365-clk.h> 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/of_device.h> 14 #include <linux/platform_device.h> 15 #include <linux/slab.h> 16 17 #include "clk-gate.h" 18 #include "clk-mtk.h" 19 #include "clk-mux.h" 20 #include "clk-pll.h" 21 22 static DEFINE_SPINLOCK(mt8365_clk_lock); 23 24 static const struct mtk_fixed_clk top_fixed_clks[] = { 25 FIXED_CLK(CLK_TOP_I2S0_BCK, "i2s0_bck", NULL, 26000000), 26 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m", 27 75000000), 28 FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", "clk26m", 75000000), 29 FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m", 30 52500000), 31 }; 32 33 static const struct mtk_fixed_factor top_divs[] = { 34 FACTOR(CLK_TOP_SYS_26M_D2, "sys_26m_d2", "clk26m", 1, 2), 35 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 36 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4), 37 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8), 38 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16), 39 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32), 40 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3), 41 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6), 42 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12), 43 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24), 44 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 45 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10), 46 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20), 47 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7), 48 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14), 49 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28), 50 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ_en", 1, 2), 51 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 52 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4), 53 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8), 54 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 55 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6), 56 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12), 57 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24), 58 FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll", 1, 96), 59 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 60 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10), 61 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20), 62 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), 63 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), 64 FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1), 65 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), 66 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), 67 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), 68 FACTOR(CLK_TOP_LVDSPLL_D16, "lvdspll_d16", "lvdspll", 1, 16), 69 FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "usb20_en", 1, 13), 70 FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4), 71 FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", "usb20_192m_ck", 1, 8), 72 FACTOR(CLK_TOP_USB20_192M_D16, "usb20_192m_d16", "usb20_192m_ck", 73 1, 16), 74 FACTOR(CLK_TOP_USB20_192M_D32, "usb20_192m_d32", "usb20_192m_ck", 75 1, 32), 76 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 77 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2), 78 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4), 79 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8), 80 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), 81 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2), 82 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4), 83 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, 8), 84 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 85 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 86 FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", "dsppll", 1, 1), 87 FACTOR(CLK_TOP_DSPPLL_D2, "dsppll_d2", "dsppll", 1, 2), 88 FACTOR(CLK_TOP_DSPPLL_D4, "dsppll_d4", "dsppll", 1, 4), 89 FACTOR(CLK_TOP_DSPPLL_D8, "dsppll_d8", "dsppll", 1, 8), 90 FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 1), 91 FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1, 52), 92 }; 93 94 static const char * const axi_parents[] = { 95 "clk26m", 96 "syspll_d7", 97 "syspll1_d4", 98 "syspll3_d2" 99 }; 100 101 static const char * const mem_parents[] = { 102 "clk26m", 103 "mmpll_ck", 104 "syspll_d3", 105 "syspll1_d2" 106 }; 107 108 static const char * const mm_parents[] = { 109 "clk26m", 110 "mmpll_ck", 111 "syspll1_d2", 112 "syspll_d5", 113 "syspll1_d4", 114 "univpll_d5", 115 "univpll1_d2", 116 "mmpll_d2" 117 }; 118 119 static const char * const scp_parents[] = { 120 "clk26m", 121 "syspll4_d2", 122 "univpll2_d2", 123 "syspll1_d2", 124 "univpll1_d2", 125 "syspll_d3", 126 "univpll_d3" 127 }; 128 129 static const char * const mfg_parents[] = { 130 "clk26m", 131 "mfgpll_ck", 132 "syspll_d3", 133 "univpll_d3" 134 }; 135 136 static const char * const atb_parents[] = { 137 "clk26m", 138 "syspll1_d4", 139 "syspll1_d2" 140 }; 141 142 static const char * const camtg_parents[] = { 143 "clk26m", 144 "usb20_192m_d8", 145 "univpll2_d8", 146 "usb20_192m_d4", 147 "univpll2_d32", 148 "usb20_192m_d16", 149 "usb20_192m_d32" 150 }; 151 152 static const char * const uart_parents[] = { 153 "clk26m", 154 "univpll2_d8" 155 }; 156 157 static const char * const spi_parents[] = { 158 "clk26m", 159 "univpll2_d2", 160 "univpll2_d4", 161 "univpll2_d8" 162 }; 163 164 static const char * const msdc50_0_hc_parents[] = { 165 "clk26m", 166 "syspll1_d2", 167 "univpll1_d4", 168 "syspll2_d2" 169 }; 170 171 static const char * const msdc50_0_parents[] = { 172 "clk26m", 173 "msdcpll_ck", 174 "univpll1_d2", 175 "syspll1_d2", 176 "univpll_d5", 177 "syspll2_d2", 178 "univpll1_d4", 179 "syspll4_d2" 180 }; 181 182 static const char * const msdc50_2_parents[] = { 183 "clk26m", 184 "msdcpll_ck", 185 "univpll_d3", 186 "univpll1_d2", 187 "syspll1_d2", 188 "univpll2_d2", 189 "syspll2_d2", 190 "univpll1_d4" 191 }; 192 193 static const char * const msdc30_1_parents[] = { 194 "clk26m", 195 "msdcpll_d2", 196 "univpll2_d2", 197 "syspll2_d2", 198 "univpll1_d4", 199 "syspll1_d4", 200 "syspll2_d4", 201 "univpll2_d8" 202 }; 203 204 static const char * const audio_parents[] = { 205 "clk26m", 206 "syspll3_d4", 207 "syspll4_d4", 208 "syspll1_d16" 209 }; 210 211 static const char * const aud_intbus_parents[] = { 212 "clk26m", 213 "syspll1_d4", 214 "syspll4_d2" 215 }; 216 217 static const char * const aud_1_parents[] = { 218 "clk26m", 219 "apll1_ck" 220 }; 221 222 static const char * const aud_2_parents[] = { 223 "clk26m", 224 "apll2_ck" 225 }; 226 227 static const char * const aud_engen1_parents[] = { 228 "clk26m", 229 "apll1_d2", 230 "apll1_d4", 231 "apll1_d8" 232 }; 233 234 static const char * const aud_engen2_parents[] = { 235 "clk26m", 236 "apll2_d2", 237 "apll2_d4", 238 "apll2_d8" 239 }; 240 241 static const char * const aud_spdif_parents[] = { 242 "clk26m", 243 "univpll_d2" 244 }; 245 246 static const char * const disp_pwm_parents[] = { 247 "clk26m", 248 "univpll2_d4" 249 }; 250 251 static const char * const dxcc_parents[] = { 252 "clk26m", 253 "syspll1_d2", 254 "syspll1_d4", 255 "syspll1_d8" 256 }; 257 258 static const char * const ssusb_sys_parents[] = { 259 "clk26m", 260 "univpll3_d4", 261 "univpll2_d4", 262 "univpll3_d2" 263 }; 264 265 static const char * const spm_parents[] = { 266 "clk26m", 267 "syspll1_d8" 268 }; 269 270 static const char * const i2c_parents[] = { 271 "clk26m", 272 "univpll3_d4", 273 "univpll3_d2", 274 "syspll1_d8", 275 "syspll2_d8" 276 }; 277 278 static const char * const pwm_parents[] = { 279 "clk26m", 280 "univpll3_d4", 281 "syspll1_d8" 282 }; 283 284 static const char * const senif_parents[] = { 285 "clk26m", 286 "univpll1_d4", 287 "univpll1_d2", 288 "univpll2_d2" 289 }; 290 291 static const char * const aes_fde_parents[] = { 292 "clk26m", 293 "msdcpll_ck", 294 "univpll_d3", 295 "univpll2_d2", 296 "univpll1_d2", 297 "syspll1_d2" 298 }; 299 300 static const char * const dpi0_parents[] = { 301 "clk26m", 302 "lvdspll_d2", 303 "lvdspll_d4", 304 "lvdspll_d8", 305 "lvdspll_d16" 306 }; 307 308 static const char * const dsp_parents[] = { 309 "clk26m", 310 "sys_26m_d2", 311 "dsppll_ck", 312 "dsppll_d2", 313 "dsppll_d4", 314 "dsppll_d8" 315 }; 316 317 static const char * const nfi2x_parents[] = { 318 "clk26m", 319 "syspll2_d2", 320 "syspll_d7", 321 "syspll_d3", 322 "syspll2_d4", 323 "msdcpll_d2", 324 "univpll1_d2", 325 "univpll_d5" 326 }; 327 328 static const char * const nfiecc_parents[] = { 329 "clk26m", 330 "syspll4_d2", 331 "univpll2_d4", 332 "syspll_d7", 333 "univpll1_d2", 334 "syspll1_d2", 335 "univpll2_d2", 336 "syspll_d5" 337 }; 338 339 static const char * const ecc_parents[] = { 340 "clk26m", 341 "univpll2_d2", 342 "univpll1_d2", 343 "univpll_d3", 344 "syspll_d2" 345 }; 346 347 static const char * const eth_parents[] = { 348 "clk26m", 349 "univpll2_d8", 350 "syspll4_d4", 351 "syspll1_d8", 352 "syspll4_d2" 353 }; 354 355 static const char * const gcpu_parents[] = { 356 "clk26m", 357 "univpll_d3", 358 "univpll2_d2", 359 "syspll_d3", 360 "syspll2_d2" 361 }; 362 363 static const char * const gcpu_cpm_parents[] = { 364 "clk26m", 365 "univpll2_d2", 366 "syspll2_d2" 367 }; 368 369 static const char * const apu_parents[] = { 370 "clk26m", 371 "univpll_d2", 372 "apupll_ck", 373 "mmpll_ck", 374 "syspll_d3", 375 "univpll1_d2", 376 "syspll1_d2", 377 "syspll1_d4" 378 }; 379 380 static const char * const mbist_diag_parents[] = { 381 "clk26m", 382 "syspll4_d4", 383 "univpll2_d8" 384 }; 385 386 static const char * const apll_i2s0_parents[] = { 387 "aud_1_sel", 388 "aud_2_sel" 389 }; 390 391 static struct mtk_composite top_misc_mux_gates[] = { 392 /* CLK_CFG_11 */ 393 MUX_GATE(CLK_TOP_MBIST_DIAG_SEL, "mbist_diag_sel", mbist_diag_parents, 394 0x0ec, 0, 2, 7), 395 }; 396 397 struct mt8365_clk_audio_mux { 398 int id; 399 const char *name; 400 u8 shift; 401 }; 402 403 static struct mt8365_clk_audio_mux top_misc_muxes[] = { 404 { CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", 11}, 405 { CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", 12}, 406 { CLK_TOP_APLL_I2S2_SEL, "apll_i2s2_sel", 13}, 407 { CLK_TOP_APLL_I2S3_SEL, "apll_i2s3_sel", 14}, 408 { CLK_TOP_APLL_TDMOUT_SEL, "apll_tdmout_sel", 15}, 409 { CLK_TOP_APLL_TDMIN_SEL, "apll_tdmin_sel", 16}, 410 { CLK_TOP_APLL_SPDIF_SEL, "apll_spdif_sel", 17}, 411 }; 412 413 #define CLK_CFG_UPDATE 0x004 414 #define CLK_CFG_UPDATE1 0x008 415 416 static const struct mtk_mux top_muxes[] = { 417 /* CLK_CFG_0 */ 418 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 419 0x040, 0x044, 0x048, 0, 2, 7, CLK_CFG_UPDATE, 420 0, CLK_IS_CRITICAL), 421 MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 422 0x044, 0x048, 8, 2, 15, CLK_CFG_UPDATE, 1), 423 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044, 424 0x048, 16, 3, 23, CLK_CFG_UPDATE, 2), 425 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x040, 426 0x044, 0x048, 24, 3, 31, CLK_CFG_UPDATE, 3), 427 /* CLK_CFG_1 */ 428 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050, 429 0x054, 0x058, 0, 2, 7, CLK_CFG_UPDATE, 4), 430 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x050, 431 0x054, 0x058, 8, 2, 15, CLK_CFG_UPDATE, 5), 432 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 433 0x050, 0x054, 0x058, 16, 3, 23, CLK_CFG_UPDATE, 6), 434 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents, 435 0x050, 0x054, 0x058, 24, 3, 31, CLK_CFG_UPDATE, 7), 436 /* CLK_CFG_2 */ 437 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060, 438 0x064, 0x068, 0, 1, 7, CLK_CFG_UPDATE, 8), 439 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060, 440 0x064, 0x068, 8, 2, 15, CLK_CFG_UPDATE, 9), 441 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HC_SEL, "msdc50_0_hc_sel", 442 msdc50_0_hc_parents, 0x060, 0x064, 0x068, 16, 2, 443 23, CLK_CFG_UPDATE, 10), 444 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC2_2_HC_SEL, "msdc2_2_hc_sel", 445 msdc50_0_hc_parents, 0x060, 0x064, 0x068, 24, 2, 446 31, CLK_CFG_UPDATE, 11), 447 /* CLK_CFG_3 */ 448 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 449 msdc50_0_parents, 0x070, 0x074, 0x078, 0, 3, 7, 450 CLK_CFG_UPDATE, 12), 451 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_2_SEL, "msdc50_2_sel", 452 msdc50_2_parents, 0x070, 0x074, 0x078, 8, 3, 15, 453 CLK_CFG_UPDATE, 13), 454 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 455 msdc30_1_parents, 0x070, 0x074, 0x078, 16, 3, 23, 456 CLK_CFG_UPDATE, 14), 457 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 458 0x070, 0x074, 0x078, 24, 2, 31, CLK_CFG_UPDATE, 459 15), 460 /* CLK_CFG_4 */ 461 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", 462 aud_intbus_parents, 0x080, 0x084, 0x088, 0, 2, 7, 463 CLK_CFG_UPDATE, 16), 464 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 465 0x080, 0x084, 0x088, 8, 1, 15, CLK_CFG_UPDATE, 17), 466 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 467 0x080, 0x084, 0x088, 16, 1, 23, CLK_CFG_UPDATE, 468 18), 469 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", 470 aud_engen1_parents, 0x080, 0x084, 0x088, 24, 2, 31, 471 CLK_CFG_UPDATE, 19), 472 /* CLK_CFG_5 */ 473 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", 474 aud_engen2_parents, 0x090, 0x094, 0x098, 0, 2, 7, 475 CLK_CFG_UPDATE, 20), 476 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SPDIF_SEL, "aud_spdif_sel", 477 aud_spdif_parents, 0x090, 0x094, 0x098, 8, 1, 15, 478 CLK_CFG_UPDATE, 21), 479 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel", 480 disp_pwm_parents, 0x090, 0x094, 0x098, 16, 2, 23, 481 CLK_CFG_UPDATE, 22), 482 /* CLK_CFG_6 */ 483 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents, 484 0x0a0, 0x0a4, 0x0a8, 0, 2, 7, CLK_CFG_UPDATE, 485 24, CLK_IS_CRITICAL), 486 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_SYS_SEL, "ssusb_sys_sel", 487 ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 8, 2, 15, 488 CLK_CFG_UPDATE, 25), 489 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel", 490 ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 16, 2, 23, 491 CLK_CFG_UPDATE, 26), 492 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", spm_parents, 493 0x0a0, 0x0a4, 0x0a8, 24, 1, 31, 494 CLK_CFG_UPDATE, 27, CLK_IS_CRITICAL), 495 /* CLK_CFG_7 */ 496 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x0b0, 497 0x0b4, 0x0b8, 0, 3, 7, CLK_CFG_UPDATE, 28), 498 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0b0, 499 0x0b4, 0x0b8, 8, 2, 15, CLK_CFG_UPDATE, 29), 500 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENIF_SEL, "senif_sel", senif_parents, 501 0x0b0, 0x0b4, 0x0b8, 16, 2, 23, CLK_CFG_UPDATE, 502 30), 503 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel", 504 aes_fde_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 505 CLK_CFG_UPDATE, 31), 506 /* CLK_CFG_8 */ 507 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", senif_parents, 508 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, CLK_CFG_UPDATE1, 0), 509 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0c0, 510 0x0c4, 0x0c8, 8, 3, 15, CLK_CFG_UPDATE1, 1), 511 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi0_parents, 0x0c0, 512 0x0c4, 0x0c8, 16, 3, 23, CLK_CFG_UPDATE1, 2), 513 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel", dsp_parents, 0x0c0, 514 0x0c4, 0x0c8, 24, 3, 31, CLK_CFG_UPDATE1, 3), 515 /* CLK_CFG_9 */ 516 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 517 0x0d0, 0x0d4, 0x0d8, 0, 3, 7, CLK_CFG_UPDATE1, 4), 518 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents, 519 0x0d0, 0x0d4, 0x0d8, 8, 3, 15, CLK_CFG_UPDATE1, 5), 520 MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel", ecc_parents, 0x0d0, 521 0x0d4, 0x0d8, 16, 3, 23, CLK_CFG_UPDATE1, 6), 522 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x0d0, 523 0x0d4, 0x0d8, 24, 3, 31, CLK_CFG_UPDATE1, 7), 524 /* CLK_CFG_10 */ 525 MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0e0, 526 0x0e4, 0x0e8, 0, 3, 7, CLK_CFG_UPDATE1, 8), 527 MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_CPM_SEL, "gcpu_cpm_sel", 528 gcpu_cpm_parents, 0x0e0, 0x0e4, 0x0e8, 8, 2, 15, 529 CLK_CFG_UPDATE1, 9), 530 MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_SEL, "apu_sel", apu_parents, 0x0e0, 531 0x0e4, 0x0e8, 16, 3, 23, CLK_CFG_UPDATE1, 10), 532 MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_IF_SEL, "apu_if_sel", apu_parents, 533 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, CLK_CFG_UPDATE1, 534 11), 535 }; 536 537 static const char * const mcu_bus_parents[] = { 538 "clk26m", 539 "armpll", 540 "mainpll", 541 "univpll_d2" 542 }; 543 544 static struct mtk_composite mcu_muxes[] = { 545 /* bus_pll_divider_cfg */ 546 MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 547 9, 2, -1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 548 }; 549 550 #define DIV_ADJ_F(_id, _name, _parent, _reg, _shift, _width, _flags) { \ 551 .id = _id, \ 552 .name = _name, \ 553 .parent_name = _parent, \ 554 .div_reg = _reg, \ 555 .div_shift = _shift, \ 556 .div_width = _width, \ 557 .clk_divider_flags = _flags, \ 558 } 559 560 static const struct mtk_clk_divider top_adj_divs[] = { 561 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "apll_i2s0_sel", 562 0x324, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), 563 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "apll_i2s1_sel", 564 0x324, 8, 8, CLK_DIVIDER_ROUND_CLOSEST), 565 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "apll_i2s2_sel", 566 0x324, 16, 8, CLK_DIVIDER_ROUND_CLOSEST), 567 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "apll_i2s3_sel", 568 0x324, 24, 8, CLK_DIVIDER_ROUND_CLOSEST), 569 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "apll_spdif_sel", 570 0x32c, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), 571 }; 572 573 struct mtk_simple_gate { 574 int id; 575 const char *name; 576 const char *parent; 577 u32 reg; 578 u8 shift; 579 unsigned long gate_flags; 580 }; 581 582 static const struct mtk_simple_gate top_clk_gates[] = { 583 { CLK_TOP_CONN_32K, "conn_32k", "clk32k", 0x0, 10, CLK_GATE_SET_TO_DISABLE }, 584 { CLK_TOP_CONN_26M, "conn_26m", "clk26m", 0x0, 11, CLK_GATE_SET_TO_DISABLE }, 585 { CLK_TOP_DSP_32K, "dsp_32k", "clk32k", 0x0, 16, CLK_GATE_SET_TO_DISABLE }, 586 { CLK_TOP_DSP_26M, "dsp_26m", "clk26m", 0x0, 17, CLK_GATE_SET_TO_DISABLE }, 587 { CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_192m_d4", 0x104, 8, 0 }, 588 { CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "usb20_192m_d4", 0x104, 9, 0 }, 589 { CLK_TOP_LVDSTX_CLKDIG_EN, "lvdstx_dig_en", "lvdstx_dig_cts", 0x104, 20, 0 }, 590 { CLK_TOP_VPLL_DPIX_EN, "vpll_dpix_en", "vpll_dpix", 0x104, 21, 0 }, 591 { CLK_TOP_SSUSB_TOP_CK_EN, "ssusb_top_ck_en", NULL, 0x104, 22, 0 }, 592 { CLK_TOP_SSUSB_PHY_CK_EN, "ssusb_phy_ck_en", NULL, 0x104, 23, 0 }, 593 { CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0x320, 0, 0 }, 594 { CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 0x320, 1, 0 }, 595 { CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 0x320, 2, 0 }, 596 { CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 0x320, 3, 0 }, 597 { CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 0x320, 4, 0 }, 598 { CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b", 0x320, 5, 0 }, 599 { CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 0x320, 6, 0 }, 600 { CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 0x320, 7, 0 }, 601 { CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 0x320, 8, 0 }, 602 }; 603 604 static const struct mtk_gate_regs ifr2_cg_regs = { 605 .set_ofs = 0x80, 606 .clr_ofs = 0x84, 607 .sta_ofs = 0x90, 608 }; 609 610 static const struct mtk_gate_regs ifr3_cg_regs = { 611 .set_ofs = 0x88, 612 .clr_ofs = 0x8c, 613 .sta_ofs = 0x94, 614 }; 615 616 static const struct mtk_gate_regs ifr4_cg_regs = { 617 .set_ofs = 0xa4, 618 .clr_ofs = 0xa8, 619 .sta_ofs = 0xac, 620 }; 621 622 static const struct mtk_gate_regs ifr5_cg_regs = { 623 .set_ofs = 0xc0, 624 .clr_ofs = 0xc4, 625 .sta_ofs = 0xc8, 626 }; 627 628 static const struct mtk_gate_regs ifr6_cg_regs = { 629 .set_ofs = 0xd0, 630 .clr_ofs = 0xd4, 631 .sta_ofs = 0xd8, 632 }; 633 634 #define GATE_IFR2(_id, _name, _parent, _shift) { \ 635 .id = _id, \ 636 .name = _name, \ 637 .parent_name = _parent, \ 638 .regs = &ifr2_cg_regs, \ 639 .shift = _shift, \ 640 .ops = &mtk_clk_gate_ops_setclr, \ 641 } 642 643 #define GATE_IFR3(_id, _name, _parent, _shift) { \ 644 .id = _id, \ 645 .name = _name, \ 646 .parent_name = _parent, \ 647 .regs = &ifr3_cg_regs, \ 648 .shift = _shift, \ 649 .ops = &mtk_clk_gate_ops_setclr, \ 650 } 651 652 #define GATE_IFR4(_id, _name, _parent, _shift) { \ 653 .id = _id, \ 654 .name = _name, \ 655 .parent_name = _parent, \ 656 .regs = &ifr4_cg_regs, \ 657 .shift = _shift, \ 658 .ops = &mtk_clk_gate_ops_setclr, \ 659 } 660 661 #define GATE_IFR5(_id, _name, _parent, _shift) { \ 662 .id = _id, \ 663 .name = _name, \ 664 .parent_name = _parent, \ 665 .regs = &ifr5_cg_regs, \ 666 .shift = _shift, \ 667 .ops = &mtk_clk_gate_ops_setclr, \ 668 } 669 670 #define GATE_IFR6(_id, _name, _parent, _shift) { \ 671 .id = _id, \ 672 .name = _name, \ 673 .parent_name = _parent, \ 674 .regs = &ifr6_cg_regs, \ 675 .shift = _shift, \ 676 .ops = &mtk_clk_gate_ops_setclr, \ 677 } 678 679 static const struct mtk_gate ifr_clks[] = { 680 /* IFR2 */ 681 GATE_IFR2(CLK_IFR_PMIC_TMR, "ifr_pmic_tmr", "clk26m", 0), 682 GATE_IFR2(CLK_IFR_PMIC_AP, "ifr_pmic_ap", "clk26m", 1), 683 GATE_IFR2(CLK_IFR_PMIC_MD, "ifr_pmic_md", "clk26m", 2), 684 GATE_IFR2(CLK_IFR_PMIC_CONN, "ifr_pmic_conn", "clk26m", 3), 685 GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_sel", 8), 686 GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_sel", 9), 687 GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_sel", 10), 688 GATE_IFR2(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "axi_sel", 15), 689 GATE_IFR2(CLK_IFR_PWM1, "ifr_pwm1", "pwm_sel", 16), 690 GATE_IFR2(CLK_IFR_PWM2, "ifr_pwm2", "pwm_sel", 17), 691 GATE_IFR2(CLK_IFR_PWM3, "ifr_pwm3", "pwm_sel", 18), 692 GATE_IFR2(CLK_IFR_PWM4, "ifr_pwm4", "pwm_sel", 19), 693 GATE_IFR2(CLK_IFR_PWM5, "ifr_pwm5", "pwm_sel", 20), 694 GATE_IFR2(CLK_IFR_PWM, "ifr_pwm", "pwm_sel", 21), 695 GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "uart_sel", 22), 696 GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "uart_sel", 23), 697 GATE_IFR2(CLK_IFR_UART2, "ifr_uart2", "uart_sel", 24), 698 GATE_IFR2(CLK_IFR_DSP_UART, "ifr_dsp_uart", "uart_sel", 26), 699 GATE_IFR2(CLK_IFR_GCE_26M, "ifr_gce_26m", "clk26m", 27), 700 GATE_IFR2(CLK_IFR_CQ_DMA_FPC, "ifr_cq_dma_fpc", "axi_sel", 28), 701 GATE_IFR2(CLK_IFR_BTIF, "ifr_btif", "axi_sel", 31), 702 /* IFR3 */ 703 GATE_IFR3(CLK_IFR_SPI0, "ifr_spi0", "spi_sel", 1), 704 GATE_IFR3(CLK_IFR_MSDC0_HCLK, "ifr_msdc0", "msdc50_0_hc_sel", 2), 705 GATE_IFR3(CLK_IFR_MSDC2_HCLK, "ifr_msdc2", "msdc2_2_hc_sel", 3), 706 GATE_IFR3(CLK_IFR_MSDC1_HCLK, "ifr_msdc1", "axi_sel", 4), 707 GATE_IFR3(CLK_IFR_DVFSRC, "ifr_dvfsrc", "clk26m", 7), 708 GATE_IFR3(CLK_IFR_GCPU, "ifr_gcpu", "axi_sel", 8), 709 GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_sel", 9), 710 GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "clk26m", 10), 711 GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "clk26m", 14), 712 GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_sel", 18), 713 GATE_IFR3(CLK_IFR_DEBUGSYS, "ifr_debugsys", "axi_sel", 24), 714 GATE_IFR3(CLK_IFR_AUDIO, "ifr_audio", "axi_sel", 25), 715 /* IFR4 */ 716 GATE_IFR4(CLK_IFR_PWM_FBCLK6, "ifr_pwm_fbclk6", "pwm_sel", 0), 717 GATE_IFR4(CLK_IFR_DISP_PWM, "ifr_disp_pwm", "disp_pwm_sel", 2), 718 GATE_IFR4(CLK_IFR_AUD_26M_BK, "ifr_aud_26m_bk", "clk26m", 4), 719 GATE_IFR4(CLK_IFR_CQ_DMA, "ifr_cq_dma", "axi_sel", 27), 720 /* IFR5 */ 721 GATE_IFR5(CLK_IFR_MSDC0_SF, "ifr_msdc0_sf", "msdc50_0_sel", 0), 722 GATE_IFR5(CLK_IFR_MSDC1_SF, "ifr_msdc1_sf", "msdc50_0_sel", 1), 723 GATE_IFR5(CLK_IFR_MSDC2_SF, "ifr_msdc2_sf", "msdc50_0_sel", 2), 724 GATE_IFR5(CLK_IFR_AP_MSDC0, "ifr_ap_msdc0", "msdc50_0_sel", 7), 725 GATE_IFR5(CLK_IFR_MD_MSDC0, "ifr_md_msdc0", "msdc50_0_sel", 8), 726 GATE_IFR5(CLK_IFR_MSDC0_SRC, "ifr_msdc0_src", "msdc50_0_sel", 9), 727 GATE_IFR5(CLK_IFR_MSDC1_SRC, "ifr_msdc1_src", "msdc30_1_sel", 10), 728 GATE_IFR5(CLK_IFR_MSDC2_SRC, "ifr_msdc2_src", "msdc50_2_sel", 11), 729 GATE_IFR5(CLK_IFR_PWRAP_TMR, "ifr_pwrap_tmr", "clk26m", 12), 730 GATE_IFR5(CLK_IFR_PWRAP_SPI, "ifr_pwrap_spi", "clk26m", 13), 731 GATE_IFR5(CLK_IFR_PWRAP_SYS, "ifr_pwrap_sys", "clk26m", 14), 732 GATE_IFR5(CLK_IFR_IRRX_26M, "ifr_irrx_26m", "clk26m", 22), 733 GATE_IFR5(CLK_IFR_IRRX_32K, "ifr_irrx_32k", "clk32k", 23), 734 GATE_IFR5(CLK_IFR_I2C0_AXI, "ifr_i2c0_axi", "i2c_sel", 24), 735 GATE_IFR5(CLK_IFR_I2C1_AXI, "ifr_i2c1_axi", "i2c_sel", 25), 736 GATE_IFR5(CLK_IFR_I2C2_AXI, "ifr_i2c2_axi", "i2c_sel", 26), 737 GATE_IFR5(CLK_IFR_I2C3_AXI, "ifr_i2c3_axi", "i2c_sel", 27), 738 GATE_IFR5(CLK_IFR_NIC_AXI, "ifr_nic_axi", "axi_sel", 28), 739 GATE_IFR5(CLK_IFR_NIC_SLV_AXI, "ifr_nic_slv_axi", "axi_sel", 29), 740 GATE_IFR5(CLK_IFR_APU_AXI, "ifr_apu_axi", "axi_sel", 30), 741 /* IFR6 */ 742 GATE_IFR6(CLK_IFR_NFIECC, "ifr_nfiecc", "nfiecc_sel", 0), 743 GATE_IFR6(CLK_IFR_NFI1X_BK, "ifr_nfi1x_bk", "nfi2x_sel", 1), 744 GATE_IFR6(CLK_IFR_NFIECC_BK, "ifr_nfiecc_bk", "nfi2x_sel", 2), 745 GATE_IFR6(CLK_IFR_NFI_BK, "ifr_nfi_bk", "axi_sel", 3), 746 GATE_IFR6(CLK_IFR_MSDC2_AP_BK, "ifr_msdc2_ap_bk", "axi_sel", 4), 747 GATE_IFR6(CLK_IFR_MSDC2_MD_BK, "ifr_msdc2_md_bk", "axi_sel", 5), 748 GATE_IFR6(CLK_IFR_MSDC2_BK, "ifr_msdc2_bk", "axi_sel", 6), 749 GATE_IFR6(CLK_IFR_SUSB_133_BK, "ifr_susb_133_bk", "axi_sel", 7), 750 GATE_IFR6(CLK_IFR_SUSB_66_BK, "ifr_susb_66_bk", "axi_sel", 8), 751 GATE_IFR6(CLK_IFR_SSUSB_SYS, "ifr_ssusb_sys", "ssusb_sys_sel", 9), 752 GATE_IFR6(CLK_IFR_SSUSB_REF, "ifr_ssusb_ref", "ssusb_sys_sel", 10), 753 GATE_IFR6(CLK_IFR_SSUSB_XHCI, "ifr_ssusb_xhci", "ssusb_xhci_sel", 11), 754 }; 755 756 static const struct mtk_simple_gate peri_clks[] = { 757 { CLK_PERIAXI, "periaxi", "axi_sel", 0x20c, 31, 0 }, 758 }; 759 760 #define MT8365_PLL_FMAX (3800UL * MHZ) 761 #define MT8365_PLL_FMIN (1500UL * MHZ) 762 #define CON0_MT8365_RST_BAR BIT(23) 763 764 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 765 _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ 766 _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table, \ 767 _rst_bar_mask, _pcw_chg_reg) { \ 768 .id = _id, \ 769 .name = _name, \ 770 .reg = _reg, \ 771 .pwr_reg = _pwr_reg, \ 772 .en_mask = _en_mask, \ 773 .flags = _flags, \ 774 .rst_bar_mask = _rst_bar_mask, \ 775 .fmax = MT8365_PLL_FMAX, \ 776 .fmin = MT8365_PLL_FMIN, \ 777 .pcwbits = _pcwbits, \ 778 .pcwibits = 8, \ 779 .pd_reg = _pd_reg, \ 780 .pd_shift = _pd_shift, \ 781 .tuner_reg = _tuner_reg, \ 782 .tuner_en_reg = _tuner_en_reg, \ 783 .tuner_en_bit = _tuner_en_bit, \ 784 .pcw_reg = _pcw_reg, \ 785 .pcw_shift = _pcw_shift, \ 786 .pcw_chg_reg = _pcw_chg_reg, \ 787 .div_table = _div_table, \ 788 } 789 790 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 791 _pd_reg, _pd_shift, _tuner_reg, \ 792 _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ 793 _pcw_shift, _rst_bar_mask, _pcw_chg_reg) \ 794 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 795 _pcwbits, _pd_reg, _pd_shift, \ 796 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 797 _pcw_reg, _pcw_shift, NULL, _rst_bar_mask, \ 798 _pcw_chg_reg) \ 799 800 static const struct mtk_pll_div_table armpll_div_table[] = { 801 { .div = 0, .freq = MT8365_PLL_FMAX }, 802 { .div = 1, .freq = 1500 * MHZ }, 803 { .div = 2, .freq = 750 * MHZ }, 804 { .div = 3, .freq = 375 * MHZ }, 805 { .div = 4, .freq = 182500000 }, 806 { } /* sentinel */ 807 }; 808 809 static const struct mtk_pll_div_table mfgpll_div_table[] = { 810 { .div = 0, .freq = MT8365_PLL_FMAX }, 811 { .div = 1, .freq = 1600 * MHZ }, 812 { .div = 2, .freq = 800 * MHZ }, 813 { .div = 3, .freq = 400 * MHZ }, 814 { .div = 4, .freq = 200 * MHZ }, 815 { } /* sentinel */ 816 }; 817 818 static const struct mtk_pll_div_table dsppll_div_table[] = { 819 { .div = 0, .freq = MT8365_PLL_FMAX }, 820 { .div = 1, .freq = 1600 * MHZ }, 821 { .div = 2, .freq = 600 * MHZ }, 822 { .div = 3, .freq = 400 * MHZ }, 823 { .div = 4, .freq = 200 * MHZ }, 824 { } /* sentinel */ 825 }; 826 827 static const struct mtk_pll_data plls[] = { 828 PLL_B(CLK_APMIXED_ARMPLL, "armpll", 0x030C, 0x0318, 0x00000001, PLL_AO, 829 22, 0x0310, 24, 0, 0, 0, 0x0310, 0, armpll_div_table, 0, 0), 830 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0228, 0x0234, 0xFF000001, 831 HAVE_RST_BAR, 22, 0x022C, 24, 0, 0, 0, 0x022C, 0, 832 CON0_MT8365_RST_BAR, 0), 833 PLL(CLK_APMIXED_UNIVPLL, "univpll2", 0x0208, 0x0214, 0xFF000001, 834 HAVE_RST_BAR, 22, 0x020C, 24, 0, 0, 0, 0x020C, 0, 835 CON0_MT8365_RST_BAR, 0), 836 PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0218, 0x0224, 0x00000001, 0, 22, 837 0x021C, 24, 0, 0, 0, 0x021C, 0, mfgpll_div_table, 0, 0), 838 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035C, 0x00000001, 0, 22, 839 0x0354, 24, 0, 0, 0, 0x0354, 0, 0, 0), 840 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0330, 0x033C, 0x00000001, 0, 22, 841 0x0334, 24, 0, 0, 0, 0x0334, 0, 0, 0), 842 PLL(CLK_APMIXED_APLL1, "apll1", 0x031C, 0x032C, 0x00000001, 0, 32, 843 0x0320, 24, 0x0040, 0x000C, 0, 0x0324, 0, 0, 0x0320), 844 PLL(CLK_APMIXED_APLL2, "apll2", 0x0360, 0x0370, 0x00000001, 0, 32, 845 0x0364, 24, 0x004C, 0x000C, 5, 0x0368, 0, 0, 0x0364), 846 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0374, 0x0380, 0x00000001, 0, 22, 847 0x0378, 24, 0, 0, 0, 0x0378, 0, 0, 0), 848 PLL_B(CLK_APMIXED_DSPPLL, "dsppll", 0x0390, 0x039C, 0x00000001, 0, 22, 849 0x0394, 24, 0, 0, 0, 0x0394, 0, dsppll_div_table, 0, 0), 850 PLL(CLK_APMIXED_APUPLL, "apupll", 0x03A0, 0x03AC, 0x00000001, 0, 22, 851 0x03A4, 24, 0, 0, 0, 0x03A4, 0, 0, 0), 852 }; 853 854 static int clk_mt8365_apmixed_probe(struct platform_device *pdev) 855 { 856 void __iomem *base; 857 struct clk_hw_onecell_data *clk_data; 858 struct device_node *node = pdev->dev.of_node; 859 struct device *dev = &pdev->dev; 860 struct clk_hw *hw; 861 int ret; 862 863 base = devm_platform_ioremap_resource(pdev, 0); 864 if (IS_ERR(base)) 865 return PTR_ERR(base); 866 867 clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); 868 if (!clk_data) 869 return -ENOMEM; 870 871 hw = devm_clk_hw_register_gate(dev, "univ_en", "univpll2", 0, 872 base + 0x204, 0, 0, NULL); 873 if (IS_ERR(hw)) 874 return PTR_ERR(hw); 875 clk_data->hws[CLK_APMIXED_UNIV_EN] = hw; 876 877 hw = devm_clk_hw_register_gate(dev, "usb20_en", "univ_en", 0, 878 base + 0x204, 1, 0, NULL); 879 if (IS_ERR(hw)) 880 return PTR_ERR(hw); 881 clk_data->hws[CLK_APMIXED_USB20_EN] = hw; 882 883 ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 884 if (ret) 885 return ret; 886 887 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 888 if (ret) 889 goto unregister_plls; 890 891 return 0; 892 893 unregister_plls: 894 mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); 895 896 return ret; 897 } 898 899 static int 900 clk_mt8365_register_mtk_simple_gates(struct device *dev, void __iomem *base, 901 struct clk_hw_onecell_data *clk_data, 902 const struct mtk_simple_gate *gates, 903 unsigned int num_gates) 904 { 905 unsigned int i; 906 907 for (i = 0; i != num_gates; ++i) { 908 const struct mtk_simple_gate *gate = &gates[i]; 909 struct clk_hw *hw; 910 911 hw = devm_clk_hw_register_gate(dev, gate->name, gate->parent, 0, 912 base + gate->reg, gate->shift, 913 gate->gate_flags, NULL); 914 if (IS_ERR(hw)) 915 return PTR_ERR(hw); 916 917 clk_data->hws[gate->id] = hw; 918 } 919 920 return 0; 921 } 922 923 static int clk_mt8365_top_probe(struct platform_device *pdev) 924 { 925 void __iomem *base; 926 struct clk_hw_onecell_data *clk_data; 927 struct device_node *node = pdev->dev.of_node; 928 struct device *dev = &pdev->dev; 929 int ret; 930 int i; 931 932 base = devm_platform_ioremap_resource(pdev, 0); 933 if (IS_ERR(base)) 934 return PTR_ERR(base); 935 936 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 937 if (!clk_data) 938 return -ENOMEM; 939 940 ret = mtk_clk_register_fixed_clks(top_fixed_clks, 941 ARRAY_SIZE(top_fixed_clks), clk_data); 942 if (ret) 943 goto free_clk_data; 944 945 ret = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), 946 clk_data); 947 if (ret) 948 goto unregister_fixed_clks; 949 950 ret = mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, 951 &mt8365_clk_lock, clk_data); 952 if (ret) 953 goto unregister_factors; 954 955 ret = mtk_clk_register_composites(top_misc_mux_gates, 956 ARRAY_SIZE(top_misc_mux_gates), base, 957 &mt8365_clk_lock, clk_data); 958 if (ret) 959 goto unregister_muxes; 960 961 for (i = 0; i != ARRAY_SIZE(top_misc_muxes); ++i) { 962 struct mt8365_clk_audio_mux *mux = &top_misc_muxes[i]; 963 struct clk_hw *hw; 964 965 hw = devm_clk_hw_register_mux(dev, mux->name, apll_i2s0_parents, 966 ARRAY_SIZE(apll_i2s0_parents), 967 CLK_SET_RATE_PARENT, base + 0x320, 968 mux->shift, 1, 0, NULL); 969 if (IS_ERR(hw)) { 970 ret = PTR_ERR(hw); 971 goto unregister_composites; 972 } 973 974 clk_data->hws[mux->id] = hw; 975 } 976 977 ret = mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), 978 base, &mt8365_clk_lock, clk_data); 979 if (ret) 980 goto unregister_composites; 981 982 ret = clk_mt8365_register_mtk_simple_gates(dev, base, clk_data, 983 top_clk_gates, 984 ARRAY_SIZE(top_clk_gates)); 985 if (ret) 986 goto unregister_dividers; 987 988 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 989 if (ret) 990 goto unregister_dividers; 991 992 return 0; 993 unregister_dividers: 994 mtk_clk_unregister_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), 995 clk_data); 996 unregister_composites: 997 mtk_clk_unregister_composites(top_misc_mux_gates, 998 ARRAY_SIZE(top_misc_mux_gates), clk_data); 999 unregister_muxes: 1000 mtk_clk_unregister_muxes(top_muxes, ARRAY_SIZE(top_muxes), clk_data); 1001 unregister_factors: 1002 mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); 1003 unregister_fixed_clks: 1004 mtk_clk_unregister_fixed_clks(top_fixed_clks, 1005 ARRAY_SIZE(top_fixed_clks), clk_data); 1006 free_clk_data: 1007 mtk_free_clk_data(clk_data); 1008 1009 return ret; 1010 } 1011 1012 static int clk_mt8365_infra_probe(struct platform_device *pdev) 1013 { 1014 struct clk_hw_onecell_data *clk_data; 1015 struct device_node *node = pdev->dev.of_node; 1016 int ret; 1017 1018 clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK); 1019 if (!clk_data) 1020 return -ENOMEM; 1021 1022 ret = mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks), 1023 clk_data); 1024 if (ret) 1025 goto free_clk_data; 1026 1027 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1028 if (ret) 1029 goto unregister_gates; 1030 1031 return 0; 1032 1033 unregister_gates: 1034 mtk_clk_unregister_gates(ifr_clks, ARRAY_SIZE(ifr_clks), clk_data); 1035 free_clk_data: 1036 mtk_free_clk_data(clk_data); 1037 1038 return ret; 1039 } 1040 1041 static int clk_mt8365_peri_probe(struct platform_device *pdev) 1042 { 1043 void __iomem *base; 1044 struct clk_hw_onecell_data *clk_data; 1045 struct device *dev = &pdev->dev; 1046 struct device_node *node = dev->of_node; 1047 int ret; 1048 1049 base = devm_platform_ioremap_resource(pdev, 0); 1050 if (IS_ERR(base)) 1051 return PTR_ERR(base); 1052 1053 clk_data = mtk_devm_alloc_clk_data(dev, CLK_PERI_NR_CLK); 1054 if (!clk_data) 1055 return -ENOMEM; 1056 1057 ret = clk_mt8365_register_mtk_simple_gates(dev, base, clk_data, 1058 peri_clks, 1059 ARRAY_SIZE(peri_clks)); 1060 if (ret) 1061 return ret; 1062 1063 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1064 1065 return ret; 1066 } 1067 1068 static int clk_mt8365_mcu_probe(struct platform_device *pdev) 1069 { 1070 struct clk_hw_onecell_data *clk_data; 1071 struct device_node *node = pdev->dev.of_node; 1072 void __iomem *base; 1073 int ret; 1074 1075 base = devm_platform_ioremap_resource(pdev, 0); 1076 if (IS_ERR(base)) 1077 return PTR_ERR(base); 1078 1079 clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); 1080 if (!clk_data) 1081 return -ENOMEM; 1082 1083 ret = mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), 1084 base, &mt8365_clk_lock, clk_data); 1085 if (ret) 1086 goto free_clk_data; 1087 1088 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1089 if (ret) 1090 goto unregister_composites; 1091 1092 return 0; 1093 1094 unregister_composites: 1095 mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), 1096 clk_data); 1097 free_clk_data: 1098 mtk_free_clk_data(clk_data); 1099 1100 return ret; 1101 } 1102 1103 static const struct of_device_id of_match_clk_mt8365[] = { 1104 { 1105 .compatible = "mediatek,mt8365-apmixedsys", 1106 .data = clk_mt8365_apmixed_probe, 1107 }, { 1108 .compatible = "mediatek,mt8365-topckgen", 1109 .data = clk_mt8365_top_probe, 1110 }, { 1111 .compatible = "mediatek,mt8365-infracfg", 1112 .data = clk_mt8365_infra_probe, 1113 }, { 1114 .compatible = "mediatek,mt8365-pericfg", 1115 .data = clk_mt8365_peri_probe, 1116 }, { 1117 .compatible = "mediatek,mt8365-mcucfg", 1118 .data = clk_mt8365_mcu_probe, 1119 }, { 1120 /* sentinel */ 1121 } 1122 }; 1123 1124 static int clk_mt8365_probe(struct platform_device *pdev) 1125 { 1126 int (*clk_probe)(struct platform_device *pdev); 1127 int ret; 1128 1129 clk_probe = of_device_get_match_data(&pdev->dev); 1130 if (!clk_probe) 1131 return -EINVAL; 1132 1133 ret = clk_probe(pdev); 1134 if (ret) 1135 dev_err(&pdev->dev, 1136 "%s: could not register clock provider: %d\n", 1137 pdev->name, ret); 1138 1139 return ret; 1140 } 1141 1142 static struct platform_driver clk_mt8365_drv = { 1143 .probe = clk_mt8365_probe, 1144 .driver = { 1145 .name = "clk-mt8365", 1146 .of_match_table = of_match_clk_mt8365, 1147 }, 1148 }; 1149 1150 static int __init clk_mt8365_init(void) 1151 { 1152 return platform_driver_register(&clk_mt8365_drv); 1153 } 1154 arch_initcall(clk_mt8365_init); 1155 MODULE_LICENSE("GPL"); 1156