1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Copyright (C) 2023 Collabora Ltd. 5 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 6 */ 7 8 #include <dt-bindings/clock/mediatek,mt8365-clk.h> 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/delay.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/slab.h> 18 19 #include "clk-gate.h" 20 #include "clk-mtk.h" 21 #include "clk-mux.h" 22 23 static DEFINE_SPINLOCK(mt8365_clk_lock); 24 25 static const struct mtk_fixed_clk top_fixed_clks[] = { 26 FIXED_CLK(CLK_TOP_I2S0_BCK, "i2s0_bck", NULL, 26000000), 27 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m", 28 75000000), 29 FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", "clk26m", 75000000), 30 FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m", 31 52500000), 32 }; 33 34 static const struct mtk_fixed_factor top_divs[] = { 35 FACTOR(CLK_TOP_SYS_26M_D2, "sys_26m_d2", "clk26m", 1, 2), 36 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 37 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4), 38 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8), 39 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16), 40 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32), 41 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3), 42 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6), 43 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12), 44 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24), 45 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 46 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10), 47 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20), 48 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7), 49 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14), 50 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28), 51 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ_en", 1, 2), 52 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 53 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4), 54 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8), 55 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 56 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6), 57 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12), 58 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24), 59 FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll", 1, 96), 60 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 61 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10), 62 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20), 63 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), 64 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), 65 FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1), 66 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), 67 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), 68 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), 69 FACTOR(CLK_TOP_LVDSPLL_D16, "lvdspll_d16", "lvdspll", 1, 16), 70 FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "usb20_en", 1, 13), 71 FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4), 72 FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", "usb20_192m_ck", 1, 8), 73 FACTOR(CLK_TOP_USB20_192M_D16, "usb20_192m_d16", "usb20_192m_ck", 74 1, 16), 75 FACTOR(CLK_TOP_USB20_192M_D32, "usb20_192m_d32", "usb20_192m_ck", 76 1, 32), 77 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 78 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2), 79 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4), 80 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8), 81 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), 82 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2), 83 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4), 84 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, 8), 85 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 86 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 87 FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", "dsppll", 1, 1), 88 FACTOR(CLK_TOP_DSPPLL_D2, "dsppll_d2", "dsppll", 1, 2), 89 FACTOR(CLK_TOP_DSPPLL_D4, "dsppll_d4", "dsppll", 1, 4), 90 FACTOR(CLK_TOP_DSPPLL_D8, "dsppll_d8", "dsppll", 1, 8), 91 FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 1), 92 FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1, 52), 93 }; 94 95 static const char * const axi_parents[] = { 96 "clk26m", 97 "syspll_d7", 98 "syspll1_d4", 99 "syspll3_d2" 100 }; 101 102 static const char * const mem_parents[] = { 103 "clk26m", 104 "mmpll_ck", 105 "syspll_d3", 106 "syspll1_d2" 107 }; 108 109 static const char * const mm_parents[] = { 110 "clk26m", 111 "mmpll_ck", 112 "syspll1_d2", 113 "syspll_d5", 114 "syspll1_d4", 115 "univpll_d5", 116 "univpll1_d2", 117 "mmpll_d2" 118 }; 119 120 static const char * const scp_parents[] = { 121 "clk26m", 122 "syspll4_d2", 123 "univpll2_d2", 124 "syspll1_d2", 125 "univpll1_d2", 126 "syspll_d3", 127 "univpll_d3" 128 }; 129 130 static const char * const mfg_parents[] = { 131 "clk26m", 132 "mfgpll_ck", 133 "syspll_d3", 134 "univpll_d3" 135 }; 136 137 static const char * const atb_parents[] = { 138 "clk26m", 139 "syspll1_d4", 140 "syspll1_d2" 141 }; 142 143 static const char * const camtg_parents[] = { 144 "clk26m", 145 "usb20_192m_d8", 146 "univpll2_d8", 147 "usb20_192m_d4", 148 "univpll2_d32", 149 "usb20_192m_d16", 150 "usb20_192m_d32" 151 }; 152 153 static const char * const uart_parents[] = { 154 "clk26m", 155 "univpll2_d8" 156 }; 157 158 static const char * const spi_parents[] = { 159 "clk26m", 160 "univpll2_d2", 161 "univpll2_d4", 162 "univpll2_d8" 163 }; 164 165 static const char * const msdc50_0_hc_parents[] = { 166 "clk26m", 167 "syspll1_d2", 168 "univpll1_d4", 169 "syspll2_d2" 170 }; 171 172 static const char * const msdc50_0_parents[] = { 173 "clk26m", 174 "msdcpll_ck", 175 "univpll1_d2", 176 "syspll1_d2", 177 "univpll_d5", 178 "syspll2_d2", 179 "univpll1_d4", 180 "syspll4_d2" 181 }; 182 183 static const char * const msdc50_2_parents[] = { 184 "clk26m", 185 "msdcpll_ck", 186 "univpll_d3", 187 "univpll1_d2", 188 "syspll1_d2", 189 "univpll2_d2", 190 "syspll2_d2", 191 "univpll1_d4" 192 }; 193 194 static const char * const msdc30_1_parents[] = { 195 "clk26m", 196 "msdcpll_d2", 197 "univpll2_d2", 198 "syspll2_d2", 199 "univpll1_d4", 200 "syspll1_d4", 201 "syspll2_d4", 202 "univpll2_d8" 203 }; 204 205 static const char * const audio_parents[] = { 206 "clk26m", 207 "syspll3_d4", 208 "syspll4_d4", 209 "syspll1_d16" 210 }; 211 212 static const char * const aud_intbus_parents[] = { 213 "clk26m", 214 "syspll1_d4", 215 "syspll4_d2" 216 }; 217 218 static const char * const aud_1_parents[] = { 219 "clk26m", 220 "apll1_ck" 221 }; 222 223 static const char * const aud_2_parents[] = { 224 "clk26m", 225 "apll2_ck" 226 }; 227 228 static const char * const aud_engen1_parents[] = { 229 "clk26m", 230 "apll1_d2", 231 "apll1_d4", 232 "apll1_d8" 233 }; 234 235 static const char * const aud_engen2_parents[] = { 236 "clk26m", 237 "apll2_d2", 238 "apll2_d4", 239 "apll2_d8" 240 }; 241 242 static const char * const aud_spdif_parents[] = { 243 "clk26m", 244 "univpll_d2" 245 }; 246 247 static const char * const disp_pwm_parents[] = { 248 "clk26m", 249 "univpll2_d4" 250 }; 251 252 static const char * const dxcc_parents[] = { 253 "clk26m", 254 "syspll1_d2", 255 "syspll1_d4", 256 "syspll1_d8" 257 }; 258 259 static const char * const ssusb_sys_parents[] = { 260 "clk26m", 261 "univpll3_d4", 262 "univpll2_d4", 263 "univpll3_d2" 264 }; 265 266 static const char * const spm_parents[] = { 267 "clk26m", 268 "syspll1_d8" 269 }; 270 271 static const char * const i2c_parents[] = { 272 "clk26m", 273 "univpll3_d4", 274 "univpll3_d2", 275 "syspll1_d8", 276 "syspll2_d8" 277 }; 278 279 static const char * const pwm_parents[] = { 280 "clk26m", 281 "univpll3_d4", 282 "syspll1_d8" 283 }; 284 285 static const char * const senif_parents[] = { 286 "clk26m", 287 "univpll1_d4", 288 "univpll1_d2", 289 "univpll2_d2" 290 }; 291 292 static const char * const aes_fde_parents[] = { 293 "clk26m", 294 "msdcpll_ck", 295 "univpll_d3", 296 "univpll2_d2", 297 "univpll1_d2", 298 "syspll1_d2" 299 }; 300 301 static const char * const dpi0_parents[] = { 302 "clk26m", 303 "lvdspll_d2", 304 "lvdspll_d4", 305 "lvdspll_d8", 306 "lvdspll_d16" 307 }; 308 309 static const char * const dsp_parents[] = { 310 "clk26m", 311 "sys_26m_d2", 312 "dsppll_ck", 313 "dsppll_d2", 314 "dsppll_d4", 315 "dsppll_d8" 316 }; 317 318 static const char * const nfi2x_parents[] = { 319 "clk26m", 320 "syspll2_d2", 321 "syspll_d7", 322 "syspll_d3", 323 "syspll2_d4", 324 "msdcpll_d2", 325 "univpll1_d2", 326 "univpll_d5" 327 }; 328 329 static const char * const nfiecc_parents[] = { 330 "clk26m", 331 "syspll4_d2", 332 "univpll2_d4", 333 "syspll_d7", 334 "univpll1_d2", 335 "syspll1_d2", 336 "univpll2_d2", 337 "syspll_d5" 338 }; 339 340 static const char * const ecc_parents[] = { 341 "clk26m", 342 "univpll2_d2", 343 "univpll1_d2", 344 "univpll_d3", 345 "syspll_d2" 346 }; 347 348 static const char * const eth_parents[] = { 349 "clk26m", 350 "univpll2_d8", 351 "syspll4_d4", 352 "syspll1_d8", 353 "syspll4_d2" 354 }; 355 356 static const char * const gcpu_parents[] = { 357 "clk26m", 358 "univpll_d3", 359 "univpll2_d2", 360 "syspll_d3", 361 "syspll2_d2" 362 }; 363 364 static const char * const gcpu_cpm_parents[] = { 365 "clk26m", 366 "univpll2_d2", 367 "syspll2_d2" 368 }; 369 370 static const char * const apu_parents[] = { 371 "clk26m", 372 "univpll_d2", 373 "apupll_ck", 374 "mmpll_ck", 375 "syspll_d3", 376 "univpll1_d2", 377 "syspll1_d2", 378 "syspll1_d4" 379 }; 380 381 static const char * const mbist_diag_parents[] = { 382 "clk26m", 383 "syspll4_d4", 384 "univpll2_d8" 385 }; 386 387 static const char * const apll_i2s_parents[] = { 388 "aud_1_sel", 389 "aud_2_sel" 390 }; 391 392 static struct mtk_composite top_misc_muxes[] = { 393 /* CLK_CFG_11 */ 394 MUX_GATE(CLK_TOP_MBIST_DIAG_SEL, "mbist_diag_sel", mbist_diag_parents, 395 0x0ec, 0, 2, 7), 396 /* Audio MUX */ 397 MUX(CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", apll_i2s_parents, 0x0320, 11, 1), 398 MUX(CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", apll_i2s_parents, 0x0320, 12, 1), 399 MUX(CLK_TOP_APLL_I2S2_SEL, "apll_i2s2_sel", apll_i2s_parents, 0x0320, 13, 1), 400 MUX(CLK_TOP_APLL_I2S3_SEL, "apll_i2s3_sel", apll_i2s_parents, 0x0320, 14, 1), 401 MUX(CLK_TOP_APLL_TDMOUT_SEL, "apll_tdmout_sel", apll_i2s_parents, 0x0320, 15, 1), 402 MUX(CLK_TOP_APLL_TDMIN_SEL, "apll_tdmin_sel", apll_i2s_parents, 0x0320, 16, 1), 403 MUX(CLK_TOP_APLL_SPDIF_SEL, "apll_spdif_sel", apll_i2s_parents, 0x0320, 17, 1), 404 }; 405 406 #define CLK_CFG_UPDATE 0x004 407 #define CLK_CFG_UPDATE1 0x008 408 409 static const struct mtk_mux top_muxes[] = { 410 /* CLK_CFG_0 */ 411 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 412 0x040, 0x044, 0x048, 0, 2, 7, CLK_CFG_UPDATE, 413 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 414 MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 415 0x044, 0x048, 8, 2, 15, CLK_CFG_UPDATE, 1), 416 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044, 417 0x048, 16, 3, 23, CLK_CFG_UPDATE, 2), 418 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x040, 419 0x044, 0x048, 24, 3, 31, CLK_CFG_UPDATE, 3), 420 /* CLK_CFG_1 */ 421 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050, 422 0x054, 0x058, 0, 2, 7, CLK_CFG_UPDATE, 4), 423 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x050, 424 0x054, 0x058, 8, 2, 15, CLK_CFG_UPDATE, 5), 425 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 426 0x050, 0x054, 0x058, 16, 3, 23, CLK_CFG_UPDATE, 6), 427 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents, 428 0x050, 0x054, 0x058, 24, 3, 31, CLK_CFG_UPDATE, 7), 429 /* CLK_CFG_2 */ 430 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060, 431 0x064, 0x068, 0, 1, 7, CLK_CFG_UPDATE, 8), 432 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060, 433 0x064, 0x068, 8, 2, 15, CLK_CFG_UPDATE, 9), 434 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HC_SEL, "msdc50_0_hc_sel", 435 msdc50_0_hc_parents, 0x060, 0x064, 0x068, 16, 2, 436 23, CLK_CFG_UPDATE, 10), 437 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC2_2_HC_SEL, "msdc2_2_hc_sel", 438 msdc50_0_hc_parents, 0x060, 0x064, 0x068, 24, 2, 439 31, CLK_CFG_UPDATE, 11), 440 /* CLK_CFG_3 */ 441 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 442 msdc50_0_parents, 0x070, 0x074, 0x078, 0, 3, 7, 443 CLK_CFG_UPDATE, 12), 444 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_2_SEL, "msdc50_2_sel", 445 msdc50_2_parents, 0x070, 0x074, 0x078, 8, 3, 15, 446 CLK_CFG_UPDATE, 13), 447 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 448 msdc30_1_parents, 0x070, 0x074, 0x078, 16, 3, 23, 449 CLK_CFG_UPDATE, 14), 450 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 451 0x070, 0x074, 0x078, 24, 2, 31, CLK_CFG_UPDATE, 452 15), 453 /* CLK_CFG_4 */ 454 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", 455 aud_intbus_parents, 0x080, 0x084, 0x088, 0, 2, 7, 456 CLK_CFG_UPDATE, 16), 457 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 458 0x080, 0x084, 0x088, 8, 1, 15, CLK_CFG_UPDATE, 17), 459 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 460 0x080, 0x084, 0x088, 16, 1, 23, CLK_CFG_UPDATE, 461 18), 462 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", 463 aud_engen1_parents, 0x080, 0x084, 0x088, 24, 2, 31, 464 CLK_CFG_UPDATE, 19), 465 /* CLK_CFG_5 */ 466 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", 467 aud_engen2_parents, 0x090, 0x094, 0x098, 0, 2, 7, 468 CLK_CFG_UPDATE, 20), 469 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SPDIF_SEL, "aud_spdif_sel", 470 aud_spdif_parents, 0x090, 0x094, 0x098, 8, 1, 15, 471 CLK_CFG_UPDATE, 21), 472 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel", 473 disp_pwm_parents, 0x090, 0x094, 0x098, 16, 2, 23, 474 CLK_CFG_UPDATE, 22), 475 /* CLK_CFG_6 */ 476 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents, 477 0x0a0, 0x0a4, 0x0a8, 0, 2, 7, CLK_CFG_UPDATE, 478 24, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 479 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_SYS_SEL, "ssusb_sys_sel", 480 ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 8, 2, 15, 481 CLK_CFG_UPDATE, 25), 482 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel", 483 ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 16, 2, 23, 484 CLK_CFG_UPDATE, 26), 485 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", spm_parents, 486 0x0a0, 0x0a4, 0x0a8, 24, 1, 31, CLK_CFG_UPDATE, 487 27, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), 488 /* CLK_CFG_7 */ 489 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x0b0, 490 0x0b4, 0x0b8, 0, 3, 7, CLK_CFG_UPDATE, 28), 491 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0b0, 492 0x0b4, 0x0b8, 8, 2, 15, CLK_CFG_UPDATE, 29), 493 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENIF_SEL, "senif_sel", senif_parents, 494 0x0b0, 0x0b4, 0x0b8, 16, 2, 23, CLK_CFG_UPDATE, 495 30), 496 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel", 497 aes_fde_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 498 CLK_CFG_UPDATE, 31), 499 /* CLK_CFG_8 */ 500 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", senif_parents, 501 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, CLK_CFG_UPDATE1, 0), 502 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0c0, 503 0x0c4, 0x0c8, 8, 3, 15, CLK_CFG_UPDATE1, 1), 504 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi0_parents, 0x0c0, 505 0x0c4, 0x0c8, 16, 3, 23, CLK_CFG_UPDATE1, 2), 506 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel", dsp_parents, 0x0c0, 507 0x0c4, 0x0c8, 24, 3, 31, CLK_CFG_UPDATE1, 3), 508 /* CLK_CFG_9 */ 509 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 510 0x0d0, 0x0d4, 0x0d8, 0, 3, 7, CLK_CFG_UPDATE1, 4), 511 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents, 512 0x0d0, 0x0d4, 0x0d8, 8, 3, 15, CLK_CFG_UPDATE1, 5), 513 MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel", ecc_parents, 0x0d0, 514 0x0d4, 0x0d8, 16, 3, 23, CLK_CFG_UPDATE1, 6), 515 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x0d0, 516 0x0d4, 0x0d8, 24, 3, 31, CLK_CFG_UPDATE1, 7), 517 /* CLK_CFG_10 */ 518 MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0e0, 519 0x0e4, 0x0e8, 0, 3, 7, CLK_CFG_UPDATE1, 8), 520 MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_CPM_SEL, "gcpu_cpm_sel", 521 gcpu_cpm_parents, 0x0e0, 0x0e4, 0x0e8, 8, 2, 15, 522 CLK_CFG_UPDATE1, 9), 523 MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_SEL, "apu_sel", apu_parents, 0x0e0, 524 0x0e4, 0x0e8, 16, 3, 23, CLK_CFG_UPDATE1, 10), 525 MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_IF_SEL, "apu_if_sel", apu_parents, 526 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, CLK_CFG_UPDATE1, 527 11), 528 }; 529 530 static const char * const mcu_bus_parents[] = { 531 "clk26m", 532 "armpll", 533 "mainpll", 534 "univpll_d2" 535 }; 536 537 static struct mtk_composite mcu_muxes[] = { 538 /* bus_pll_divider_cfg */ 539 MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 540 9, 2, -1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 541 }; 542 543 #define DIV_ADJ_F(_id, _name, _parent, _reg, _shift, _width, _flags) { \ 544 .id = _id, \ 545 .name = _name, \ 546 .parent_name = _parent, \ 547 .div_reg = _reg, \ 548 .div_shift = _shift, \ 549 .div_width = _width, \ 550 .clk_divider_flags = _flags, \ 551 } 552 553 static const struct mtk_clk_divider top_adj_divs[] = { 554 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "apll_i2s0_sel", 555 0x324, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), 556 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "apll_i2s1_sel", 557 0x324, 8, 8, CLK_DIVIDER_ROUND_CLOSEST), 558 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "apll_i2s2_sel", 559 0x324, 16, 8, CLK_DIVIDER_ROUND_CLOSEST), 560 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "apll_i2s3_sel", 561 0x324, 24, 8, CLK_DIVIDER_ROUND_CLOSEST), 562 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "apll_spdif_sel", 563 0x32c, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), 564 }; 565 566 static const struct mtk_gate_regs top0_cg_regs = { 567 .set_ofs = 0, 568 .clr_ofs = 0, 569 .sta_ofs = 0, 570 }; 571 572 static const struct mtk_gate_regs top1_cg_regs = { 573 .set_ofs = 0x104, 574 .clr_ofs = 0x104, 575 .sta_ofs = 0x104, 576 }; 577 578 static const struct mtk_gate_regs top2_cg_regs = { 579 .set_ofs = 0x320, 580 .clr_ofs = 0x320, 581 .sta_ofs = 0x320, 582 }; 583 584 #define GATE_TOP0(_id, _name, _parent, _shift) \ 585 GATE_MTK(_id, _name, _parent, &top0_cg_regs, \ 586 _shift, &mtk_clk_gate_ops_no_setclr_inv) 587 588 #define GATE_TOP1(_id, _name, _parent, _shift) \ 589 GATE_MTK(_id, _name, _parent, &top1_cg_regs, \ 590 _shift, &mtk_clk_gate_ops_no_setclr) 591 592 #define GATE_TOP2(_id, _name, _parent, _shift) \ 593 GATE_MTK(_id, _name, _parent, &top2_cg_regs, \ 594 _shift, &mtk_clk_gate_ops_no_setclr) 595 596 static const struct mtk_gate top_clk_gates[] = { 597 GATE_TOP0(CLK_TOP_CONN_32K, "conn_32k", "clk32k", 10), 598 GATE_TOP0(CLK_TOP_CONN_26M, "conn_26m", "clk26m", 11), 599 GATE_TOP0(CLK_TOP_DSP_32K, "dsp_32k", "clk32k", 16), 600 GATE_TOP0(CLK_TOP_DSP_26M, "dsp_26m", "clk26m", 17), 601 GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_192m_d4", 8), 602 GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "usb20_192m_d4", 9), 603 GATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, "lvdstx_dig_en", "lvdstx_dig_cts", 20), 604 GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, "vpll_dpix_en", "vpll_dpix", 21), 605 GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, "ssusb_top_ck_en", NULL, 22), 606 GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, "ssusb_phy_ck_en", NULL, 23), 607 GATE_TOP2(CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0), 608 GATE_TOP2(CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 1), 609 GATE_TOP2(CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 2), 610 GATE_TOP2(CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 3), 611 GATE_TOP2(CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 4), 612 GATE_TOP2(CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b", 5), 613 GATE_TOP2(CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 6), 614 GATE_TOP2(CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 7), 615 GATE_TOP2(CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 8), 616 }; 617 618 static const struct mtk_gate_regs ifr2_cg_regs = { 619 .set_ofs = 0x80, 620 .clr_ofs = 0x84, 621 .sta_ofs = 0x90, 622 }; 623 624 static const struct mtk_gate_regs ifr3_cg_regs = { 625 .set_ofs = 0x88, 626 .clr_ofs = 0x8c, 627 .sta_ofs = 0x94, 628 }; 629 630 static const struct mtk_gate_regs ifr4_cg_regs = { 631 .set_ofs = 0xa4, 632 .clr_ofs = 0xa8, 633 .sta_ofs = 0xac, 634 }; 635 636 static const struct mtk_gate_regs ifr5_cg_regs = { 637 .set_ofs = 0xc0, 638 .clr_ofs = 0xc4, 639 .sta_ofs = 0xc8, 640 }; 641 642 static const struct mtk_gate_regs ifr6_cg_regs = { 643 .set_ofs = 0xd0, 644 .clr_ofs = 0xd4, 645 .sta_ofs = 0xd8, 646 }; 647 648 #define GATE_IFRX(_id, _name, _parent, _shift, _regs) \ 649 GATE_MTK(_id, _name, _parent, _regs, _shift, \ 650 &mtk_clk_gate_ops_setclr) 651 652 #define GATE_IFR2(_id, _name, _parent, _shift) \ 653 GATE_IFRX(_id, _name, _parent, _shift, &ifr2_cg_regs) 654 655 #define GATE_IFR3(_id, _name, _parent, _shift) \ 656 GATE_IFRX(_id, _name, _parent, _shift, &ifr3_cg_regs) 657 658 #define GATE_IFR4(_id, _name, _parent, _shift) \ 659 GATE_IFRX(_id, _name, _parent, _shift, &ifr4_cg_regs) 660 661 #define GATE_IFR5(_id, _name, _parent, _shift) \ 662 GATE_IFRX(_id, _name, _parent, _shift, &ifr5_cg_regs) 663 664 #define GATE_IFR6(_id, _name, _parent, _shift) \ 665 GATE_IFRX(_id, _name, _parent, _shift, &ifr6_cg_regs) 666 667 static const struct mtk_gate ifr_clks[] = { 668 /* IFR2 */ 669 GATE_IFR2(CLK_IFR_PMIC_TMR, "ifr_pmic_tmr", "clk26m", 0), 670 GATE_IFR2(CLK_IFR_PMIC_AP, "ifr_pmic_ap", "clk26m", 1), 671 GATE_IFR2(CLK_IFR_PMIC_MD, "ifr_pmic_md", "clk26m", 2), 672 GATE_IFR2(CLK_IFR_PMIC_CONN, "ifr_pmic_conn", "clk26m", 3), 673 GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_sel", 8), 674 GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_sel", 9), 675 GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_sel", 10), 676 GATE_IFR2(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "axi_sel", 15), 677 GATE_IFR2(CLK_IFR_PWM1, "ifr_pwm1", "pwm_sel", 16), 678 GATE_IFR2(CLK_IFR_PWM2, "ifr_pwm2", "pwm_sel", 17), 679 GATE_IFR2(CLK_IFR_PWM3, "ifr_pwm3", "pwm_sel", 18), 680 GATE_IFR2(CLK_IFR_PWM4, "ifr_pwm4", "pwm_sel", 19), 681 GATE_IFR2(CLK_IFR_PWM5, "ifr_pwm5", "pwm_sel", 20), 682 GATE_IFR2(CLK_IFR_PWM, "ifr_pwm", "pwm_sel", 21), 683 GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "uart_sel", 22), 684 GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "uart_sel", 23), 685 GATE_IFR2(CLK_IFR_UART2, "ifr_uart2", "uart_sel", 24), 686 GATE_IFR2(CLK_IFR_DSP_UART, "ifr_dsp_uart", "uart_sel", 26), 687 GATE_IFR2(CLK_IFR_GCE_26M, "ifr_gce_26m", "clk26m", 27), 688 GATE_IFR2(CLK_IFR_CQ_DMA_FPC, "ifr_cq_dma_fpc", "axi_sel", 28), 689 GATE_IFR2(CLK_IFR_BTIF, "ifr_btif", "axi_sel", 31), 690 /* IFR3 */ 691 GATE_IFR3(CLK_IFR_SPI0, "ifr_spi0", "spi_sel", 1), 692 GATE_IFR3(CLK_IFR_MSDC0_HCLK, "ifr_msdc0", "msdc50_0_hc_sel", 2), 693 GATE_IFR3(CLK_IFR_MSDC2_HCLK, "ifr_msdc2", "msdc2_2_hc_sel", 3), 694 GATE_IFR3(CLK_IFR_MSDC1_HCLK, "ifr_msdc1", "axi_sel", 4), 695 GATE_IFR3(CLK_IFR_DVFSRC, "ifr_dvfsrc", "clk26m", 7), 696 GATE_IFR3(CLK_IFR_GCPU, "ifr_gcpu", "axi_sel", 8), 697 GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_sel", 9), 698 GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "clk26m", 10), 699 GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "clk26m", 14), 700 GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_sel", 18), 701 GATE_IFR3(CLK_IFR_DEBUGSYS, "ifr_debugsys", "axi_sel", 24), 702 GATE_IFR3(CLK_IFR_AUDIO, "ifr_audio", "axi_sel", 25), 703 /* IFR4 */ 704 GATE_IFR4(CLK_IFR_PWM_FBCLK6, "ifr_pwm_fbclk6", "pwm_sel", 0), 705 GATE_IFR4(CLK_IFR_DISP_PWM, "ifr_disp_pwm", "disp_pwm_sel", 2), 706 GATE_IFR4(CLK_IFR_AUD_26M_BK, "ifr_aud_26m_bk", "clk26m", 4), 707 GATE_IFR4(CLK_IFR_CQ_DMA, "ifr_cq_dma", "axi_sel", 27), 708 /* IFR5 */ 709 GATE_IFR5(CLK_IFR_MSDC0_SF, "ifr_msdc0_sf", "msdc50_0_sel", 0), 710 GATE_IFR5(CLK_IFR_MSDC1_SF, "ifr_msdc1_sf", "msdc50_0_sel", 1), 711 GATE_IFR5(CLK_IFR_MSDC2_SF, "ifr_msdc2_sf", "msdc50_0_sel", 2), 712 GATE_IFR5(CLK_IFR_AP_MSDC0, "ifr_ap_msdc0", "msdc50_0_sel", 7), 713 GATE_IFR5(CLK_IFR_MD_MSDC0, "ifr_md_msdc0", "msdc50_0_sel", 8), 714 GATE_IFR5(CLK_IFR_MSDC0_SRC, "ifr_msdc0_src", "msdc50_0_sel", 9), 715 GATE_IFR5(CLK_IFR_MSDC1_SRC, "ifr_msdc1_src", "msdc30_1_sel", 10), 716 GATE_IFR5(CLK_IFR_MSDC2_SRC, "ifr_msdc2_src", "msdc50_2_sel", 11), 717 GATE_IFR5(CLK_IFR_PWRAP_TMR, "ifr_pwrap_tmr", "clk26m", 12), 718 GATE_IFR5(CLK_IFR_PWRAP_SPI, "ifr_pwrap_spi", "clk26m", 13), 719 GATE_IFR5(CLK_IFR_PWRAP_SYS, "ifr_pwrap_sys", "clk26m", 14), 720 GATE_IFR5(CLK_IFR_IRRX_26M, "ifr_irrx_26m", "clk26m", 22), 721 GATE_IFR5(CLK_IFR_IRRX_32K, "ifr_irrx_32k", "clk32k", 23), 722 GATE_IFR5(CLK_IFR_I2C0_AXI, "ifr_i2c0_axi", "i2c_sel", 24), 723 GATE_IFR5(CLK_IFR_I2C1_AXI, "ifr_i2c1_axi", "i2c_sel", 25), 724 GATE_IFR5(CLK_IFR_I2C2_AXI, "ifr_i2c2_axi", "i2c_sel", 26), 725 GATE_IFR5(CLK_IFR_I2C3_AXI, "ifr_i2c3_axi", "i2c_sel", 27), 726 GATE_IFR5(CLK_IFR_NIC_AXI, "ifr_nic_axi", "axi_sel", 28), 727 GATE_IFR5(CLK_IFR_NIC_SLV_AXI, "ifr_nic_slv_axi", "axi_sel", 29), 728 GATE_IFR5(CLK_IFR_APU_AXI, "ifr_apu_axi", "axi_sel", 30), 729 /* IFR6 */ 730 GATE_IFR6(CLK_IFR_NFIECC, "ifr_nfiecc", "nfiecc_sel", 0), 731 GATE_IFR6(CLK_IFR_NFI1X_BK, "ifr_nfi1x_bk", "nfi2x_sel", 1), 732 GATE_IFR6(CLK_IFR_NFIECC_BK, "ifr_nfiecc_bk", "nfi2x_sel", 2), 733 GATE_IFR6(CLK_IFR_NFI_BK, "ifr_nfi_bk", "axi_sel", 3), 734 GATE_IFR6(CLK_IFR_MSDC2_AP_BK, "ifr_msdc2_ap_bk", "axi_sel", 4), 735 GATE_IFR6(CLK_IFR_MSDC2_MD_BK, "ifr_msdc2_md_bk", "axi_sel", 5), 736 GATE_IFR6(CLK_IFR_MSDC2_BK, "ifr_msdc2_bk", "axi_sel", 6), 737 GATE_IFR6(CLK_IFR_SUSB_133_BK, "ifr_susb_133_bk", "axi_sel", 7), 738 GATE_IFR6(CLK_IFR_SUSB_66_BK, "ifr_susb_66_bk", "axi_sel", 8), 739 GATE_IFR6(CLK_IFR_SSUSB_SYS, "ifr_ssusb_sys", "ssusb_sys_sel", 9), 740 GATE_IFR6(CLK_IFR_SSUSB_REF, "ifr_ssusb_ref", "ssusb_sys_sel", 10), 741 GATE_IFR6(CLK_IFR_SSUSB_XHCI, "ifr_ssusb_xhci", "ssusb_xhci_sel", 11), 742 }; 743 744 static const struct mtk_gate_regs peri_cg_regs = { 745 .set_ofs = 0x20c, 746 .clr_ofs = 0x20c, 747 .sta_ofs = 0x20c, 748 }; 749 750 static const struct mtk_gate peri_clks[] = { 751 GATE_MTK(CLK_PERIAXI, "periaxi", "axi_sel", &peri_cg_regs, 31, 752 &mtk_clk_gate_ops_no_setclr), 753 }; 754 755 static const struct mtk_clk_desc topck_desc = { 756 .clks = top_clk_gates, 757 .num_clks = ARRAY_SIZE(top_clk_gates), 758 .fixed_clks = top_fixed_clks, 759 .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), 760 .factor_clks = top_divs, 761 .num_factor_clks = ARRAY_SIZE(top_divs), 762 .mux_clks = top_muxes, 763 .num_mux_clks = ARRAY_SIZE(top_muxes), 764 .composite_clks = top_misc_muxes, 765 .num_composite_clks = ARRAY_SIZE(top_misc_muxes), 766 .divider_clks = top_adj_divs, 767 .num_divider_clks = ARRAY_SIZE(top_adj_divs), 768 .clk_lock = &mt8365_clk_lock, 769 }; 770 771 static const struct mtk_clk_desc infra_desc = { 772 .clks = ifr_clks, 773 .num_clks = ARRAY_SIZE(ifr_clks), 774 }; 775 776 static const struct mtk_clk_desc peri_desc = { 777 .clks = peri_clks, 778 .num_clks = ARRAY_SIZE(peri_clks), 779 }; 780 781 static const struct mtk_clk_desc mcu_desc = { 782 .composite_clks = mcu_muxes, 783 .num_composite_clks = ARRAY_SIZE(mcu_muxes), 784 .clk_lock = &mt8365_clk_lock, 785 }; 786 787 static const struct of_device_id of_match_clk_mt8365[] = { 788 { .compatible = "mediatek,mt8365-topckgen", .data = &topck_desc }, 789 { .compatible = "mediatek,mt8365-infracfg", .data = &infra_desc }, 790 { .compatible = "mediatek,mt8365-pericfg", .data = &peri_desc }, 791 { .compatible = "mediatek,mt8365-mcucfg", .data = &mcu_desc }, 792 { /* sentinel */ } 793 }; 794 MODULE_DEVICE_TABLE(of, of_match_clk_mt8365); 795 796 static struct platform_driver clk_mt8365_drv = { 797 .driver = { 798 .name = "clk-mt8365", 799 .of_match_table = of_match_clk_mt8365, 800 }, 801 .probe = mtk_clk_simple_probe, 802 .remove = mtk_clk_simple_remove, 803 }; 804 module_platform_driver(clk_mt8365_drv); 805 MODULE_LICENSE("GPL"); 806