1d46adccbSFabien Parent // SPDX-License-Identifier: GPL-2.0 2d46adccbSFabien Parent /* 3d46adccbSFabien Parent * Copyright (C) 2022 MediaTek Inc. 4d46adccbSFabien Parent */ 5d46adccbSFabien Parent 6d46adccbSFabien Parent #include <dt-bindings/clock/mediatek,mt8365-clk.h> 7d46adccbSFabien Parent #include <linux/clk.h> 8d46adccbSFabien Parent #include <linux/clk-provider.h> 9d46adccbSFabien Parent #include <linux/delay.h> 10d46adccbSFabien Parent #include <linux/mfd/syscon.h> 11d46adccbSFabien Parent #include <linux/of.h> 12d46adccbSFabien Parent #include <linux/of_address.h> 13d46adccbSFabien Parent #include <linux/of_device.h> 14d46adccbSFabien Parent #include <linux/platform_device.h> 15d46adccbSFabien Parent #include <linux/slab.h> 16d46adccbSFabien Parent 17d46adccbSFabien Parent #include "clk-gate.h" 18d46adccbSFabien Parent #include "clk-mtk.h" 19d46adccbSFabien Parent #include "clk-mux.h" 20d46adccbSFabien Parent #include "clk-pll.h" 21d46adccbSFabien Parent 22d46adccbSFabien Parent static DEFINE_SPINLOCK(mt8365_clk_lock); 23d46adccbSFabien Parent 24d46adccbSFabien Parent static const struct mtk_fixed_clk top_fixed_clks[] = { 25d46adccbSFabien Parent FIXED_CLK(CLK_TOP_I2S0_BCK, "i2s0_bck", NULL, 26000000), 26d46adccbSFabien Parent FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m", 27d46adccbSFabien Parent 75000000), 28d46adccbSFabien Parent FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", "clk26m", 75000000), 29d46adccbSFabien Parent FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m", 30d46adccbSFabien Parent 52500000), 31d46adccbSFabien Parent }; 32d46adccbSFabien Parent 33d46adccbSFabien Parent static const struct mtk_fixed_factor top_divs[] = { 34d46adccbSFabien Parent FACTOR(CLK_TOP_SYS_26M_D2, "sys_26m_d2", "clk26m", 1, 2), 35d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2), 36d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4), 37d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8), 38d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16), 39d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32), 40d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3), 41d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6), 42d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12), 43d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24), 44d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5), 45d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10), 46d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20), 47d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7), 48d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14), 49d46adccbSFabien Parent FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28), 50d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ_en", 1, 2), 51d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), 52d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4), 53d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8), 54d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 55d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6), 56d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12), 57d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24), 58d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll", 1, 96), 59d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 60d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10), 61d46adccbSFabien Parent FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20), 62d46adccbSFabien Parent FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), 63d46adccbSFabien Parent FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), 64d46adccbSFabien Parent FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1), 65d46adccbSFabien Parent FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), 66d46adccbSFabien Parent FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), 67d46adccbSFabien Parent FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), 68d46adccbSFabien Parent FACTOR(CLK_TOP_LVDSPLL_D16, "lvdspll_d16", "lvdspll", 1, 16), 69d46adccbSFabien Parent FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "usb20_en", 1, 13), 70d46adccbSFabien Parent FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4), 71d46adccbSFabien Parent FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", "usb20_192m_ck", 1, 8), 72d46adccbSFabien Parent FACTOR(CLK_TOP_USB20_192M_D16, "usb20_192m_d16", "usb20_192m_ck", 73d46adccbSFabien Parent 1, 16), 74d46adccbSFabien Parent FACTOR(CLK_TOP_USB20_192M_D32, "usb20_192m_d32", "usb20_192m_ck", 75d46adccbSFabien Parent 1, 32), 76d46adccbSFabien Parent FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 77d46adccbSFabien Parent FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2), 78d46adccbSFabien Parent FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4), 79d46adccbSFabien Parent FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8), 80d46adccbSFabien Parent FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), 81d46adccbSFabien Parent FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2), 82d46adccbSFabien Parent FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4), 83d46adccbSFabien Parent FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, 8), 84d46adccbSFabien Parent FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 85d46adccbSFabien Parent FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 86d46adccbSFabien Parent FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", "dsppll", 1, 1), 87d46adccbSFabien Parent FACTOR(CLK_TOP_DSPPLL_D2, "dsppll_d2", "dsppll", 1, 2), 88d46adccbSFabien Parent FACTOR(CLK_TOP_DSPPLL_D4, "dsppll_d4", "dsppll", 1, 4), 89d46adccbSFabien Parent FACTOR(CLK_TOP_DSPPLL_D8, "dsppll_d8", "dsppll", 1, 8), 90d46adccbSFabien Parent FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 1), 91d46adccbSFabien Parent FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1, 52), 92d46adccbSFabien Parent }; 93d46adccbSFabien Parent 94d46adccbSFabien Parent static const char * const axi_parents[] = { 95d46adccbSFabien Parent "clk26m", 96d46adccbSFabien Parent "syspll_d7", 97d46adccbSFabien Parent "syspll1_d4", 98d46adccbSFabien Parent "syspll3_d2" 99d46adccbSFabien Parent }; 100d46adccbSFabien Parent 101d46adccbSFabien Parent static const char * const mem_parents[] = { 102d46adccbSFabien Parent "clk26m", 103d46adccbSFabien Parent "mmpll_ck", 104d46adccbSFabien Parent "syspll_d3", 105d46adccbSFabien Parent "syspll1_d2" 106d46adccbSFabien Parent }; 107d46adccbSFabien Parent 108d46adccbSFabien Parent static const char * const mm_parents[] = { 109d46adccbSFabien Parent "clk26m", 110d46adccbSFabien Parent "mmpll_ck", 111d46adccbSFabien Parent "syspll1_d2", 112d46adccbSFabien Parent "syspll_d5", 113d46adccbSFabien Parent "syspll1_d4", 114d46adccbSFabien Parent "univpll_d5", 115d46adccbSFabien Parent "univpll1_d2", 116d46adccbSFabien Parent "mmpll_d2" 117d46adccbSFabien Parent }; 118d46adccbSFabien Parent 119d46adccbSFabien Parent static const char * const scp_parents[] = { 120d46adccbSFabien Parent "clk26m", 121d46adccbSFabien Parent "syspll4_d2", 122d46adccbSFabien Parent "univpll2_d2", 123d46adccbSFabien Parent "syspll1_d2", 124d46adccbSFabien Parent "univpll1_d2", 125d46adccbSFabien Parent "syspll_d3", 126d46adccbSFabien Parent "univpll_d3" 127d46adccbSFabien Parent }; 128d46adccbSFabien Parent 129d46adccbSFabien Parent static const char * const mfg_parents[] = { 130d46adccbSFabien Parent "clk26m", 131d46adccbSFabien Parent "mfgpll_ck", 132d46adccbSFabien Parent "syspll_d3", 133d46adccbSFabien Parent "univpll_d3" 134d46adccbSFabien Parent }; 135d46adccbSFabien Parent 136d46adccbSFabien Parent static const char * const atb_parents[] = { 137d46adccbSFabien Parent "clk26m", 138d46adccbSFabien Parent "syspll1_d4", 139d46adccbSFabien Parent "syspll1_d2" 140d46adccbSFabien Parent }; 141d46adccbSFabien Parent 142d46adccbSFabien Parent static const char * const camtg_parents[] = { 143d46adccbSFabien Parent "clk26m", 144d46adccbSFabien Parent "usb20_192m_d8", 145d46adccbSFabien Parent "univpll2_d8", 146d46adccbSFabien Parent "usb20_192m_d4", 147d46adccbSFabien Parent "univpll2_d32", 148d46adccbSFabien Parent "usb20_192m_d16", 149d46adccbSFabien Parent "usb20_192m_d32" 150d46adccbSFabien Parent }; 151d46adccbSFabien Parent 152d46adccbSFabien Parent static const char * const uart_parents[] = { 153d46adccbSFabien Parent "clk26m", 154d46adccbSFabien Parent "univpll2_d8" 155d46adccbSFabien Parent }; 156d46adccbSFabien Parent 157d46adccbSFabien Parent static const char * const spi_parents[] = { 158d46adccbSFabien Parent "clk26m", 159d46adccbSFabien Parent "univpll2_d2", 160d46adccbSFabien Parent "univpll2_d4", 161d46adccbSFabien Parent "univpll2_d8" 162d46adccbSFabien Parent }; 163d46adccbSFabien Parent 164d46adccbSFabien Parent static const char * const msdc50_0_hc_parents[] = { 165d46adccbSFabien Parent "clk26m", 166d46adccbSFabien Parent "syspll1_d2", 167d46adccbSFabien Parent "univpll1_d4", 168d46adccbSFabien Parent "syspll2_d2" 169d46adccbSFabien Parent }; 170d46adccbSFabien Parent 171d46adccbSFabien Parent static const char * const msdc50_0_parents[] = { 172d46adccbSFabien Parent "clk26m", 173d46adccbSFabien Parent "msdcpll_ck", 174d46adccbSFabien Parent "univpll1_d2", 175d46adccbSFabien Parent "syspll1_d2", 176d46adccbSFabien Parent "univpll_d5", 177d46adccbSFabien Parent "syspll2_d2", 178d46adccbSFabien Parent "univpll1_d4", 179d46adccbSFabien Parent "syspll4_d2" 180d46adccbSFabien Parent }; 181d46adccbSFabien Parent 182d46adccbSFabien Parent static const char * const msdc50_2_parents[] = { 183d46adccbSFabien Parent "clk26m", 184d46adccbSFabien Parent "msdcpll_ck", 185d46adccbSFabien Parent "univpll_d3", 186d46adccbSFabien Parent "univpll1_d2", 187d46adccbSFabien Parent "syspll1_d2", 188d46adccbSFabien Parent "univpll2_d2", 189d46adccbSFabien Parent "syspll2_d2", 190d46adccbSFabien Parent "univpll1_d4" 191d46adccbSFabien Parent }; 192d46adccbSFabien Parent 193d46adccbSFabien Parent static const char * const msdc30_1_parents[] = { 194d46adccbSFabien Parent "clk26m", 195d46adccbSFabien Parent "msdcpll_d2", 196d46adccbSFabien Parent "univpll2_d2", 197d46adccbSFabien Parent "syspll2_d2", 198d46adccbSFabien Parent "univpll1_d4", 199d46adccbSFabien Parent "syspll1_d4", 200d46adccbSFabien Parent "syspll2_d4", 201d46adccbSFabien Parent "univpll2_d8" 202d46adccbSFabien Parent }; 203d46adccbSFabien Parent 204d46adccbSFabien Parent static const char * const audio_parents[] = { 205d46adccbSFabien Parent "clk26m", 206d46adccbSFabien Parent "syspll3_d4", 207d46adccbSFabien Parent "syspll4_d4", 208d46adccbSFabien Parent "syspll1_d16" 209d46adccbSFabien Parent }; 210d46adccbSFabien Parent 211d46adccbSFabien Parent static const char * const aud_intbus_parents[] = { 212d46adccbSFabien Parent "clk26m", 213d46adccbSFabien Parent "syspll1_d4", 214d46adccbSFabien Parent "syspll4_d2" 215d46adccbSFabien Parent }; 216d46adccbSFabien Parent 217d46adccbSFabien Parent static const char * const aud_1_parents[] = { 218d46adccbSFabien Parent "clk26m", 219d46adccbSFabien Parent "apll1_ck" 220d46adccbSFabien Parent }; 221d46adccbSFabien Parent 222d46adccbSFabien Parent static const char * const aud_2_parents[] = { 223d46adccbSFabien Parent "clk26m", 224d46adccbSFabien Parent "apll2_ck" 225d46adccbSFabien Parent }; 226d46adccbSFabien Parent 227d46adccbSFabien Parent static const char * const aud_engen1_parents[] = { 228d46adccbSFabien Parent "clk26m", 229d46adccbSFabien Parent "apll1_d2", 230d46adccbSFabien Parent "apll1_d4", 231d46adccbSFabien Parent "apll1_d8" 232d46adccbSFabien Parent }; 233d46adccbSFabien Parent 234d46adccbSFabien Parent static const char * const aud_engen2_parents[] = { 235d46adccbSFabien Parent "clk26m", 236d46adccbSFabien Parent "apll2_d2", 237d46adccbSFabien Parent "apll2_d4", 238d46adccbSFabien Parent "apll2_d8" 239d46adccbSFabien Parent }; 240d46adccbSFabien Parent 241d46adccbSFabien Parent static const char * const aud_spdif_parents[] = { 242d46adccbSFabien Parent "clk26m", 243d46adccbSFabien Parent "univpll_d2" 244d46adccbSFabien Parent }; 245d46adccbSFabien Parent 246d46adccbSFabien Parent static const char * const disp_pwm_parents[] = { 247d46adccbSFabien Parent "clk26m", 248d46adccbSFabien Parent "univpll2_d4" 249d46adccbSFabien Parent }; 250d46adccbSFabien Parent 251d46adccbSFabien Parent static const char * const dxcc_parents[] = { 252d46adccbSFabien Parent "clk26m", 253d46adccbSFabien Parent "syspll1_d2", 254d46adccbSFabien Parent "syspll1_d4", 255d46adccbSFabien Parent "syspll1_d8" 256d46adccbSFabien Parent }; 257d46adccbSFabien Parent 258d46adccbSFabien Parent static const char * const ssusb_sys_parents[] = { 259d46adccbSFabien Parent "clk26m", 260d46adccbSFabien Parent "univpll3_d4", 261d46adccbSFabien Parent "univpll2_d4", 262d46adccbSFabien Parent "univpll3_d2" 263d46adccbSFabien Parent }; 264d46adccbSFabien Parent 265d46adccbSFabien Parent static const char * const spm_parents[] = { 266d46adccbSFabien Parent "clk26m", 267d46adccbSFabien Parent "syspll1_d8" 268d46adccbSFabien Parent }; 269d46adccbSFabien Parent 270d46adccbSFabien Parent static const char * const i2c_parents[] = { 271d46adccbSFabien Parent "clk26m", 272d46adccbSFabien Parent "univpll3_d4", 273d46adccbSFabien Parent "univpll3_d2", 274d46adccbSFabien Parent "syspll1_d8", 275d46adccbSFabien Parent "syspll2_d8" 276d46adccbSFabien Parent }; 277d46adccbSFabien Parent 278d46adccbSFabien Parent static const char * const pwm_parents[] = { 279d46adccbSFabien Parent "clk26m", 280d46adccbSFabien Parent "univpll3_d4", 281d46adccbSFabien Parent "syspll1_d8" 282d46adccbSFabien Parent }; 283d46adccbSFabien Parent 284d46adccbSFabien Parent static const char * const senif_parents[] = { 285d46adccbSFabien Parent "clk26m", 286d46adccbSFabien Parent "univpll1_d4", 287d46adccbSFabien Parent "univpll1_d2", 288d46adccbSFabien Parent "univpll2_d2" 289d46adccbSFabien Parent }; 290d46adccbSFabien Parent 291d46adccbSFabien Parent static const char * const aes_fde_parents[] = { 292d46adccbSFabien Parent "clk26m", 293d46adccbSFabien Parent "msdcpll_ck", 294d46adccbSFabien Parent "univpll_d3", 295d46adccbSFabien Parent "univpll2_d2", 296d46adccbSFabien Parent "univpll1_d2", 297d46adccbSFabien Parent "syspll1_d2" 298d46adccbSFabien Parent }; 299d46adccbSFabien Parent 300d46adccbSFabien Parent static const char * const dpi0_parents[] = { 301d46adccbSFabien Parent "clk26m", 302d46adccbSFabien Parent "lvdspll_d2", 303d46adccbSFabien Parent "lvdspll_d4", 304d46adccbSFabien Parent "lvdspll_d8", 305d46adccbSFabien Parent "lvdspll_d16" 306d46adccbSFabien Parent }; 307d46adccbSFabien Parent 308d46adccbSFabien Parent static const char * const dsp_parents[] = { 309d46adccbSFabien Parent "clk26m", 310d46adccbSFabien Parent "sys_26m_d2", 311d46adccbSFabien Parent "dsppll_ck", 312d46adccbSFabien Parent "dsppll_d2", 313d46adccbSFabien Parent "dsppll_d4", 314d46adccbSFabien Parent "dsppll_d8" 315d46adccbSFabien Parent }; 316d46adccbSFabien Parent 317d46adccbSFabien Parent static const char * const nfi2x_parents[] = { 318d46adccbSFabien Parent "clk26m", 319d46adccbSFabien Parent "syspll2_d2", 320d46adccbSFabien Parent "syspll_d7", 321d46adccbSFabien Parent "syspll_d3", 322d46adccbSFabien Parent "syspll2_d4", 323d46adccbSFabien Parent "msdcpll_d2", 324d46adccbSFabien Parent "univpll1_d2", 325d46adccbSFabien Parent "univpll_d5" 326d46adccbSFabien Parent }; 327d46adccbSFabien Parent 328d46adccbSFabien Parent static const char * const nfiecc_parents[] = { 329d46adccbSFabien Parent "clk26m", 330d46adccbSFabien Parent "syspll4_d2", 331d46adccbSFabien Parent "univpll2_d4", 332d46adccbSFabien Parent "syspll_d7", 333d46adccbSFabien Parent "univpll1_d2", 334d46adccbSFabien Parent "syspll1_d2", 335d46adccbSFabien Parent "univpll2_d2", 336d46adccbSFabien Parent "syspll_d5" 337d46adccbSFabien Parent }; 338d46adccbSFabien Parent 339d46adccbSFabien Parent static const char * const ecc_parents[] = { 340d46adccbSFabien Parent "clk26m", 341d46adccbSFabien Parent "univpll2_d2", 342d46adccbSFabien Parent "univpll1_d2", 343d46adccbSFabien Parent "univpll_d3", 344d46adccbSFabien Parent "syspll_d2" 345d46adccbSFabien Parent }; 346d46adccbSFabien Parent 347d46adccbSFabien Parent static const char * const eth_parents[] = { 348d46adccbSFabien Parent "clk26m", 349d46adccbSFabien Parent "univpll2_d8", 350d46adccbSFabien Parent "syspll4_d4", 351d46adccbSFabien Parent "syspll1_d8", 352d46adccbSFabien Parent "syspll4_d2" 353d46adccbSFabien Parent }; 354d46adccbSFabien Parent 355d46adccbSFabien Parent static const char * const gcpu_parents[] = { 356d46adccbSFabien Parent "clk26m", 357d46adccbSFabien Parent "univpll_d3", 358d46adccbSFabien Parent "univpll2_d2", 359d46adccbSFabien Parent "syspll_d3", 360d46adccbSFabien Parent "syspll2_d2" 361d46adccbSFabien Parent }; 362d46adccbSFabien Parent 363d46adccbSFabien Parent static const char * const gcpu_cpm_parents[] = { 364d46adccbSFabien Parent "clk26m", 365d46adccbSFabien Parent "univpll2_d2", 366d46adccbSFabien Parent "syspll2_d2" 367d46adccbSFabien Parent }; 368d46adccbSFabien Parent 369d46adccbSFabien Parent static const char * const apu_parents[] = { 370d46adccbSFabien Parent "clk26m", 371d46adccbSFabien Parent "univpll_d2", 372d46adccbSFabien Parent "apupll_ck", 373d46adccbSFabien Parent "mmpll_ck", 374d46adccbSFabien Parent "syspll_d3", 375d46adccbSFabien Parent "univpll1_d2", 376d46adccbSFabien Parent "syspll1_d2", 377d46adccbSFabien Parent "syspll1_d4" 378d46adccbSFabien Parent }; 379d46adccbSFabien Parent 380d46adccbSFabien Parent static const char * const mbist_diag_parents[] = { 381d46adccbSFabien Parent "clk26m", 382d46adccbSFabien Parent "syspll4_d4", 383d46adccbSFabien Parent "univpll2_d8" 384d46adccbSFabien Parent }; 385d46adccbSFabien Parent 386d46adccbSFabien Parent static const char * const apll_i2s0_parents[] = { 387d46adccbSFabien Parent "aud_1_sel", 388d46adccbSFabien Parent "aud_2_sel" 389d46adccbSFabien Parent }; 390d46adccbSFabien Parent 391d46adccbSFabien Parent static struct mtk_composite top_misc_mux_gates[] = { 392d46adccbSFabien Parent /* CLK_CFG_11 */ 393d46adccbSFabien Parent MUX_GATE(CLK_TOP_MBIST_DIAG_SEL, "mbist_diag_sel", mbist_diag_parents, 394d46adccbSFabien Parent 0x0ec, 0, 2, 7), 395d46adccbSFabien Parent }; 396d46adccbSFabien Parent 397d46adccbSFabien Parent struct mt8365_clk_audio_mux { 398d46adccbSFabien Parent int id; 399d46adccbSFabien Parent const char *name; 400d46adccbSFabien Parent u8 shift; 401d46adccbSFabien Parent }; 402d46adccbSFabien Parent 403d46adccbSFabien Parent static struct mt8365_clk_audio_mux top_misc_muxes[] = { 404d46adccbSFabien Parent { CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", 11}, 405d46adccbSFabien Parent { CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", 12}, 406d46adccbSFabien Parent { CLK_TOP_APLL_I2S2_SEL, "apll_i2s2_sel", 13}, 407d46adccbSFabien Parent { CLK_TOP_APLL_I2S3_SEL, "apll_i2s3_sel", 14}, 408d46adccbSFabien Parent { CLK_TOP_APLL_TDMOUT_SEL, "apll_tdmout_sel", 15}, 409d46adccbSFabien Parent { CLK_TOP_APLL_TDMIN_SEL, "apll_tdmin_sel", 16}, 410d46adccbSFabien Parent { CLK_TOP_APLL_SPDIF_SEL, "apll_spdif_sel", 17}, 411d46adccbSFabien Parent }; 412d46adccbSFabien Parent 413d46adccbSFabien Parent #define CLK_CFG_UPDATE 0x004 414d46adccbSFabien Parent #define CLK_CFG_UPDATE1 0x008 415d46adccbSFabien Parent 416d46adccbSFabien Parent static const struct mtk_mux top_muxes[] = { 417d46adccbSFabien Parent /* CLK_CFG_0 */ 418d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 419d46adccbSFabien Parent 0x040, 0x044, 0x048, 0, 2, 7, CLK_CFG_UPDATE, 420d46adccbSFabien Parent 0, CLK_IS_CRITICAL), 421d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 422d46adccbSFabien Parent 0x044, 0x048, 8, 2, 15, CLK_CFG_UPDATE, 1), 423d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044, 424d46adccbSFabien Parent 0x048, 16, 3, 23, CLK_CFG_UPDATE, 2), 425d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x040, 426d46adccbSFabien Parent 0x044, 0x048, 24, 3, 31, CLK_CFG_UPDATE, 3), 427d46adccbSFabien Parent /* CLK_CFG_1 */ 428d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050, 429d46adccbSFabien Parent 0x054, 0x058, 0, 2, 7, CLK_CFG_UPDATE, 4), 430d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x050, 431d46adccbSFabien Parent 0x054, 0x058, 8, 2, 15, CLK_CFG_UPDATE, 5), 432d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 433d46adccbSFabien Parent 0x050, 0x054, 0x058, 16, 3, 23, CLK_CFG_UPDATE, 6), 434d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents, 435d46adccbSFabien Parent 0x050, 0x054, 0x058, 24, 3, 31, CLK_CFG_UPDATE, 7), 436d46adccbSFabien Parent /* CLK_CFG_2 */ 437d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060, 438d46adccbSFabien Parent 0x064, 0x068, 0, 1, 7, CLK_CFG_UPDATE, 8), 439d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060, 440d46adccbSFabien Parent 0x064, 0x068, 8, 2, 15, CLK_CFG_UPDATE, 9), 441d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HC_SEL, "msdc50_0_hc_sel", 442d46adccbSFabien Parent msdc50_0_hc_parents, 0x060, 0x064, 0x068, 16, 2, 443d46adccbSFabien Parent 23, CLK_CFG_UPDATE, 10), 444d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC2_2_HC_SEL, "msdc2_2_hc_sel", 445d46adccbSFabien Parent msdc50_0_hc_parents, 0x060, 0x064, 0x068, 24, 2, 446d46adccbSFabien Parent 31, CLK_CFG_UPDATE, 11), 447d46adccbSFabien Parent /* CLK_CFG_3 */ 448d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 449d46adccbSFabien Parent msdc50_0_parents, 0x070, 0x074, 0x078, 0, 3, 7, 450d46adccbSFabien Parent CLK_CFG_UPDATE, 12), 451d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_2_SEL, "msdc50_2_sel", 452d46adccbSFabien Parent msdc50_2_parents, 0x070, 0x074, 0x078, 8, 3, 15, 453d46adccbSFabien Parent CLK_CFG_UPDATE, 13), 454d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 455d46adccbSFabien Parent msdc30_1_parents, 0x070, 0x074, 0x078, 16, 3, 23, 456d46adccbSFabien Parent CLK_CFG_UPDATE, 14), 457d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 458d46adccbSFabien Parent 0x070, 0x074, 0x078, 24, 2, 31, CLK_CFG_UPDATE, 459d46adccbSFabien Parent 15), 460d46adccbSFabien Parent /* CLK_CFG_4 */ 461d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", 462d46adccbSFabien Parent aud_intbus_parents, 0x080, 0x084, 0x088, 0, 2, 7, 463d46adccbSFabien Parent CLK_CFG_UPDATE, 16), 464d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 465d46adccbSFabien Parent 0x080, 0x084, 0x088, 8, 1, 15, CLK_CFG_UPDATE, 17), 466d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 467d46adccbSFabien Parent 0x080, 0x084, 0x088, 16, 1, 23, CLK_CFG_UPDATE, 468d46adccbSFabien Parent 18), 469d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", 470d46adccbSFabien Parent aud_engen1_parents, 0x080, 0x084, 0x088, 24, 2, 31, 471d46adccbSFabien Parent CLK_CFG_UPDATE, 19), 472d46adccbSFabien Parent /* CLK_CFG_5 */ 473d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", 474d46adccbSFabien Parent aud_engen2_parents, 0x090, 0x094, 0x098, 0, 2, 7, 475d46adccbSFabien Parent CLK_CFG_UPDATE, 20), 476d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SPDIF_SEL, "aud_spdif_sel", 477d46adccbSFabien Parent aud_spdif_parents, 0x090, 0x094, 0x098, 8, 1, 15, 478d46adccbSFabien Parent CLK_CFG_UPDATE, 21), 479d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel", 480d46adccbSFabien Parent disp_pwm_parents, 0x090, 0x094, 0x098, 16, 2, 23, 481d46adccbSFabien Parent CLK_CFG_UPDATE, 22), 482d46adccbSFabien Parent /* CLK_CFG_6 */ 483d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents, 484d46adccbSFabien Parent 0x0a0, 0x0a4, 0x0a8, 0, 2, 7, CLK_CFG_UPDATE, 485d46adccbSFabien Parent 24, CLK_IS_CRITICAL), 486d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_SYS_SEL, "ssusb_sys_sel", 487d46adccbSFabien Parent ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 8, 2, 15, 488d46adccbSFabien Parent CLK_CFG_UPDATE, 25), 489d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel", 490d46adccbSFabien Parent ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 16, 2, 23, 491d46adccbSFabien Parent CLK_CFG_UPDATE, 26), 492d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", spm_parents, 493d46adccbSFabien Parent 0x0a0, 0x0a4, 0x0a8, 24, 1, 31, 494d46adccbSFabien Parent CLK_CFG_UPDATE, 27, CLK_IS_CRITICAL), 495d46adccbSFabien Parent /* CLK_CFG_7 */ 496d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x0b0, 497d46adccbSFabien Parent 0x0b4, 0x0b8, 0, 3, 7, CLK_CFG_UPDATE, 28), 498d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0b0, 499d46adccbSFabien Parent 0x0b4, 0x0b8, 8, 2, 15, CLK_CFG_UPDATE, 29), 500d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_SENIF_SEL, "senif_sel", senif_parents, 501d46adccbSFabien Parent 0x0b0, 0x0b4, 0x0b8, 16, 2, 23, CLK_CFG_UPDATE, 502d46adccbSFabien Parent 30), 503d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel", 504d46adccbSFabien Parent aes_fde_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 505d46adccbSFabien Parent CLK_CFG_UPDATE, 31), 506d46adccbSFabien Parent /* CLK_CFG_8 */ 507d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", senif_parents, 508d46adccbSFabien Parent 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, CLK_CFG_UPDATE1, 0), 509d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0c0, 510d46adccbSFabien Parent 0x0c4, 0x0c8, 8, 3, 15, CLK_CFG_UPDATE1, 1), 511d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi0_parents, 0x0c0, 512d46adccbSFabien Parent 0x0c4, 0x0c8, 16, 3, 23, CLK_CFG_UPDATE1, 2), 513d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel", dsp_parents, 0x0c0, 514d46adccbSFabien Parent 0x0c4, 0x0c8, 24, 3, 31, CLK_CFG_UPDATE1, 3), 515d46adccbSFabien Parent /* CLK_CFG_9 */ 516d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 517d46adccbSFabien Parent 0x0d0, 0x0d4, 0x0d8, 0, 3, 7, CLK_CFG_UPDATE1, 4), 518d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents, 519d46adccbSFabien Parent 0x0d0, 0x0d4, 0x0d8, 8, 3, 15, CLK_CFG_UPDATE1, 5), 520d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel", ecc_parents, 0x0d0, 521d46adccbSFabien Parent 0x0d4, 0x0d8, 16, 3, 23, CLK_CFG_UPDATE1, 6), 522d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x0d0, 523d46adccbSFabien Parent 0x0d4, 0x0d8, 24, 3, 31, CLK_CFG_UPDATE1, 7), 524d46adccbSFabien Parent /* CLK_CFG_10 */ 525d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0e0, 526d46adccbSFabien Parent 0x0e4, 0x0e8, 0, 3, 7, CLK_CFG_UPDATE1, 8), 527d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_CPM_SEL, "gcpu_cpm_sel", 528d46adccbSFabien Parent gcpu_cpm_parents, 0x0e0, 0x0e4, 0x0e8, 8, 2, 15, 529d46adccbSFabien Parent CLK_CFG_UPDATE1, 9), 530d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_SEL, "apu_sel", apu_parents, 0x0e0, 531d46adccbSFabien Parent 0x0e4, 0x0e8, 16, 3, 23, CLK_CFG_UPDATE1, 10), 532d46adccbSFabien Parent MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_IF_SEL, "apu_if_sel", apu_parents, 533d46adccbSFabien Parent 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, CLK_CFG_UPDATE1, 534d46adccbSFabien Parent 11), 535d46adccbSFabien Parent }; 536d46adccbSFabien Parent 537d46adccbSFabien Parent static const char * const mcu_bus_parents[] = { 538d46adccbSFabien Parent "clk26m", 539d46adccbSFabien Parent "armpll", 540d46adccbSFabien Parent "mainpll", 541d46adccbSFabien Parent "univpll_d2" 542d46adccbSFabien Parent }; 543d46adccbSFabien Parent 544d46adccbSFabien Parent static struct mtk_composite mcu_muxes[] = { 545d46adccbSFabien Parent /* bus_pll_divider_cfg */ 546d46adccbSFabien Parent MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 547d46adccbSFabien Parent 9, 2, -1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 548d46adccbSFabien Parent }; 549d46adccbSFabien Parent 550d46adccbSFabien Parent #define DIV_ADJ_F(_id, _name, _parent, _reg, _shift, _width, _flags) { \ 551d46adccbSFabien Parent .id = _id, \ 552d46adccbSFabien Parent .name = _name, \ 553d46adccbSFabien Parent .parent_name = _parent, \ 554d46adccbSFabien Parent .div_reg = _reg, \ 555d46adccbSFabien Parent .div_shift = _shift, \ 556d46adccbSFabien Parent .div_width = _width, \ 557d46adccbSFabien Parent .clk_divider_flags = _flags, \ 558d46adccbSFabien Parent } 559d46adccbSFabien Parent 560d46adccbSFabien Parent static const struct mtk_clk_divider top_adj_divs[] = { 561d46adccbSFabien Parent DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "apll_i2s0_sel", 562d46adccbSFabien Parent 0x324, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), 563d46adccbSFabien Parent DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "apll_i2s1_sel", 564d46adccbSFabien Parent 0x324, 8, 8, CLK_DIVIDER_ROUND_CLOSEST), 565d46adccbSFabien Parent DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "apll_i2s2_sel", 566d46adccbSFabien Parent 0x324, 16, 8, CLK_DIVIDER_ROUND_CLOSEST), 567d46adccbSFabien Parent DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "apll_i2s3_sel", 568d46adccbSFabien Parent 0x324, 24, 8, CLK_DIVIDER_ROUND_CLOSEST), 569d46adccbSFabien Parent DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "apll_spdif_sel", 570d46adccbSFabien Parent 0x32c, 0, 8, CLK_DIVIDER_ROUND_CLOSEST), 571d46adccbSFabien Parent }; 572d46adccbSFabien Parent 573d46adccbSFabien Parent struct mtk_simple_gate { 574d46adccbSFabien Parent int id; 575d46adccbSFabien Parent const char *name; 576d46adccbSFabien Parent const char *parent; 577d46adccbSFabien Parent u32 reg; 578d46adccbSFabien Parent u8 shift; 579d46adccbSFabien Parent unsigned long gate_flags; 580d46adccbSFabien Parent }; 581d46adccbSFabien Parent 582d46adccbSFabien Parent static const struct mtk_simple_gate top_clk_gates[] = { 583d46adccbSFabien Parent { CLK_TOP_CONN_32K, "conn_32k", "clk32k", 0x0, 10, CLK_GATE_SET_TO_DISABLE }, 584d46adccbSFabien Parent { CLK_TOP_CONN_26M, "conn_26m", "clk26m", 0x0, 11, CLK_GATE_SET_TO_DISABLE }, 585d46adccbSFabien Parent { CLK_TOP_DSP_32K, "dsp_32k", "clk32k", 0x0, 16, CLK_GATE_SET_TO_DISABLE }, 586d46adccbSFabien Parent { CLK_TOP_DSP_26M, "dsp_26m", "clk26m", 0x0, 17, CLK_GATE_SET_TO_DISABLE }, 587d46adccbSFabien Parent { CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_192m_d4", 0x104, 8, 0 }, 588d46adccbSFabien Parent { CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "usb20_192m_d4", 0x104, 9, 0 }, 589d46adccbSFabien Parent { CLK_TOP_LVDSTX_CLKDIG_EN, "lvdstx_dig_en", "lvdstx_dig_cts", 0x104, 20, 0 }, 590d46adccbSFabien Parent { CLK_TOP_VPLL_DPIX_EN, "vpll_dpix_en", "vpll_dpix", 0x104, 21, 0 }, 591d46adccbSFabien Parent { CLK_TOP_SSUSB_TOP_CK_EN, "ssusb_top_ck_en", NULL, 0x104, 22, 0 }, 592d46adccbSFabien Parent { CLK_TOP_SSUSB_PHY_CK_EN, "ssusb_phy_ck_en", NULL, 0x104, 23, 0 }, 593d46adccbSFabien Parent { CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0x320, 0, 0 }, 594d46adccbSFabien Parent { CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 0x320, 1, 0 }, 595d46adccbSFabien Parent { CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 0x320, 2, 0 }, 596d46adccbSFabien Parent { CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 0x320, 3, 0 }, 597d46adccbSFabien Parent { CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 0x320, 4, 0 }, 598d46adccbSFabien Parent { CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b", 0x320, 5, 0 }, 599d46adccbSFabien Parent { CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 0x320, 6, 0 }, 600d46adccbSFabien Parent { CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 0x320, 7, 0 }, 601d46adccbSFabien Parent { CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 0x320, 8, 0 }, 602d46adccbSFabien Parent }; 603d46adccbSFabien Parent 604d46adccbSFabien Parent static const struct mtk_gate_regs ifr2_cg_regs = { 605d46adccbSFabien Parent .set_ofs = 0x80, 606d46adccbSFabien Parent .clr_ofs = 0x84, 607d46adccbSFabien Parent .sta_ofs = 0x90, 608d46adccbSFabien Parent }; 609d46adccbSFabien Parent 610d46adccbSFabien Parent static const struct mtk_gate_regs ifr3_cg_regs = { 611d46adccbSFabien Parent .set_ofs = 0x88, 612d46adccbSFabien Parent .clr_ofs = 0x8c, 613d46adccbSFabien Parent .sta_ofs = 0x94, 614d46adccbSFabien Parent }; 615d46adccbSFabien Parent 616d46adccbSFabien Parent static const struct mtk_gate_regs ifr4_cg_regs = { 617d46adccbSFabien Parent .set_ofs = 0xa4, 618d46adccbSFabien Parent .clr_ofs = 0xa8, 619d46adccbSFabien Parent .sta_ofs = 0xac, 620d46adccbSFabien Parent }; 621d46adccbSFabien Parent 622d46adccbSFabien Parent static const struct mtk_gate_regs ifr5_cg_regs = { 623d46adccbSFabien Parent .set_ofs = 0xc0, 624d46adccbSFabien Parent .clr_ofs = 0xc4, 625d46adccbSFabien Parent .sta_ofs = 0xc8, 626d46adccbSFabien Parent }; 627d46adccbSFabien Parent 628d46adccbSFabien Parent static const struct mtk_gate_regs ifr6_cg_regs = { 629d46adccbSFabien Parent .set_ofs = 0xd0, 630d46adccbSFabien Parent .clr_ofs = 0xd4, 631d46adccbSFabien Parent .sta_ofs = 0xd8, 632d46adccbSFabien Parent }; 633d46adccbSFabien Parent 634d46adccbSFabien Parent #define GATE_IFR2(_id, _name, _parent, _shift) { \ 635d46adccbSFabien Parent .id = _id, \ 636d46adccbSFabien Parent .name = _name, \ 637d46adccbSFabien Parent .parent_name = _parent, \ 638d46adccbSFabien Parent .regs = &ifr2_cg_regs, \ 639d46adccbSFabien Parent .shift = _shift, \ 640d46adccbSFabien Parent .ops = &mtk_clk_gate_ops_setclr, \ 641d46adccbSFabien Parent } 642d46adccbSFabien Parent 643d46adccbSFabien Parent #define GATE_IFR3(_id, _name, _parent, _shift) { \ 644d46adccbSFabien Parent .id = _id, \ 645d46adccbSFabien Parent .name = _name, \ 646d46adccbSFabien Parent .parent_name = _parent, \ 647d46adccbSFabien Parent .regs = &ifr3_cg_regs, \ 648d46adccbSFabien Parent .shift = _shift, \ 649d46adccbSFabien Parent .ops = &mtk_clk_gate_ops_setclr, \ 650d46adccbSFabien Parent } 651d46adccbSFabien Parent 652d46adccbSFabien Parent #define GATE_IFR4(_id, _name, _parent, _shift) { \ 653d46adccbSFabien Parent .id = _id, \ 654d46adccbSFabien Parent .name = _name, \ 655d46adccbSFabien Parent .parent_name = _parent, \ 656d46adccbSFabien Parent .regs = &ifr4_cg_regs, \ 657d46adccbSFabien Parent .shift = _shift, \ 658d46adccbSFabien Parent .ops = &mtk_clk_gate_ops_setclr, \ 659d46adccbSFabien Parent } 660d46adccbSFabien Parent 661d46adccbSFabien Parent #define GATE_IFR5(_id, _name, _parent, _shift) { \ 662d46adccbSFabien Parent .id = _id, \ 663d46adccbSFabien Parent .name = _name, \ 664d46adccbSFabien Parent .parent_name = _parent, \ 665d46adccbSFabien Parent .regs = &ifr5_cg_regs, \ 666d46adccbSFabien Parent .shift = _shift, \ 667d46adccbSFabien Parent .ops = &mtk_clk_gate_ops_setclr, \ 668d46adccbSFabien Parent } 669d46adccbSFabien Parent 670d46adccbSFabien Parent #define GATE_IFR6(_id, _name, _parent, _shift) { \ 671d46adccbSFabien Parent .id = _id, \ 672d46adccbSFabien Parent .name = _name, \ 673d46adccbSFabien Parent .parent_name = _parent, \ 674d46adccbSFabien Parent .regs = &ifr6_cg_regs, \ 675d46adccbSFabien Parent .shift = _shift, \ 676d46adccbSFabien Parent .ops = &mtk_clk_gate_ops_setclr, \ 677d46adccbSFabien Parent } 678d46adccbSFabien Parent 679d46adccbSFabien Parent static const struct mtk_gate ifr_clks[] = { 680d46adccbSFabien Parent /* IFR2 */ 681d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PMIC_TMR, "ifr_pmic_tmr", "clk26m", 0), 682d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PMIC_AP, "ifr_pmic_ap", "clk26m", 1), 683d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PMIC_MD, "ifr_pmic_md", "clk26m", 2), 684d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PMIC_CONN, "ifr_pmic_conn", "clk26m", 3), 685d46adccbSFabien Parent GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_sel", 8), 686d46adccbSFabien Parent GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_sel", 9), 687d46adccbSFabien Parent GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_sel", 10), 688d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "axi_sel", 15), 689d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PWM1, "ifr_pwm1", "pwm_sel", 16), 690d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PWM2, "ifr_pwm2", "pwm_sel", 17), 691d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PWM3, "ifr_pwm3", "pwm_sel", 18), 692d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PWM4, "ifr_pwm4", "pwm_sel", 19), 693d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PWM5, "ifr_pwm5", "pwm_sel", 20), 694d46adccbSFabien Parent GATE_IFR2(CLK_IFR_PWM, "ifr_pwm", "pwm_sel", 21), 695d46adccbSFabien Parent GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "uart_sel", 22), 696d46adccbSFabien Parent GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "uart_sel", 23), 697d46adccbSFabien Parent GATE_IFR2(CLK_IFR_UART2, "ifr_uart2", "uart_sel", 24), 698d46adccbSFabien Parent GATE_IFR2(CLK_IFR_DSP_UART, "ifr_dsp_uart", "uart_sel", 26), 699d46adccbSFabien Parent GATE_IFR2(CLK_IFR_GCE_26M, "ifr_gce_26m", "clk26m", 27), 700d46adccbSFabien Parent GATE_IFR2(CLK_IFR_CQ_DMA_FPC, "ifr_cq_dma_fpc", "axi_sel", 28), 701d46adccbSFabien Parent GATE_IFR2(CLK_IFR_BTIF, "ifr_btif", "axi_sel", 31), 702d46adccbSFabien Parent /* IFR3 */ 703d46adccbSFabien Parent GATE_IFR3(CLK_IFR_SPI0, "ifr_spi0", "spi_sel", 1), 704d46adccbSFabien Parent GATE_IFR3(CLK_IFR_MSDC0_HCLK, "ifr_msdc0", "msdc50_0_hc_sel", 2), 705d46adccbSFabien Parent GATE_IFR3(CLK_IFR_MSDC2_HCLK, "ifr_msdc2", "msdc2_2_hc_sel", 3), 706d46adccbSFabien Parent GATE_IFR3(CLK_IFR_MSDC1_HCLK, "ifr_msdc1", "axi_sel", 4), 707d46adccbSFabien Parent GATE_IFR3(CLK_IFR_DVFSRC, "ifr_dvfsrc", "clk26m", 7), 708d46adccbSFabien Parent GATE_IFR3(CLK_IFR_GCPU, "ifr_gcpu", "axi_sel", 8), 709d46adccbSFabien Parent GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_sel", 9), 710d46adccbSFabien Parent GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "clk26m", 10), 711d46adccbSFabien Parent GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "clk26m", 14), 712d46adccbSFabien Parent GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_sel", 18), 713d46adccbSFabien Parent GATE_IFR3(CLK_IFR_DEBUGSYS, "ifr_debugsys", "axi_sel", 24), 714d46adccbSFabien Parent GATE_IFR3(CLK_IFR_AUDIO, "ifr_audio", "axi_sel", 25), 715d46adccbSFabien Parent /* IFR4 */ 716d46adccbSFabien Parent GATE_IFR4(CLK_IFR_PWM_FBCLK6, "ifr_pwm_fbclk6", "pwm_sel", 0), 717d46adccbSFabien Parent GATE_IFR4(CLK_IFR_DISP_PWM, "ifr_disp_pwm", "disp_pwm_sel", 2), 718d46adccbSFabien Parent GATE_IFR4(CLK_IFR_AUD_26M_BK, "ifr_aud_26m_bk", "clk26m", 4), 719d46adccbSFabien Parent GATE_IFR4(CLK_IFR_CQ_DMA, "ifr_cq_dma", "axi_sel", 27), 720d46adccbSFabien Parent /* IFR5 */ 721d46adccbSFabien Parent GATE_IFR5(CLK_IFR_MSDC0_SF, "ifr_msdc0_sf", "msdc50_0_sel", 0), 722d46adccbSFabien Parent GATE_IFR5(CLK_IFR_MSDC1_SF, "ifr_msdc1_sf", "msdc50_0_sel", 1), 723d46adccbSFabien Parent GATE_IFR5(CLK_IFR_MSDC2_SF, "ifr_msdc2_sf", "msdc50_0_sel", 2), 724d46adccbSFabien Parent GATE_IFR5(CLK_IFR_AP_MSDC0, "ifr_ap_msdc0", "msdc50_0_sel", 7), 725d46adccbSFabien Parent GATE_IFR5(CLK_IFR_MD_MSDC0, "ifr_md_msdc0", "msdc50_0_sel", 8), 726d46adccbSFabien Parent GATE_IFR5(CLK_IFR_MSDC0_SRC, "ifr_msdc0_src", "msdc50_0_sel", 9), 727d46adccbSFabien Parent GATE_IFR5(CLK_IFR_MSDC1_SRC, "ifr_msdc1_src", "msdc30_1_sel", 10), 728d46adccbSFabien Parent GATE_IFR5(CLK_IFR_MSDC2_SRC, "ifr_msdc2_src", "msdc50_2_sel", 11), 729d46adccbSFabien Parent GATE_IFR5(CLK_IFR_PWRAP_TMR, "ifr_pwrap_tmr", "clk26m", 12), 730d46adccbSFabien Parent GATE_IFR5(CLK_IFR_PWRAP_SPI, "ifr_pwrap_spi", "clk26m", 13), 731d46adccbSFabien Parent GATE_IFR5(CLK_IFR_PWRAP_SYS, "ifr_pwrap_sys", "clk26m", 14), 732d46adccbSFabien Parent GATE_IFR5(CLK_IFR_IRRX_26M, "ifr_irrx_26m", "clk26m", 22), 733d46adccbSFabien Parent GATE_IFR5(CLK_IFR_IRRX_32K, "ifr_irrx_32k", "clk32k", 23), 734d46adccbSFabien Parent GATE_IFR5(CLK_IFR_I2C0_AXI, "ifr_i2c0_axi", "i2c_sel", 24), 735d46adccbSFabien Parent GATE_IFR5(CLK_IFR_I2C1_AXI, "ifr_i2c1_axi", "i2c_sel", 25), 736d46adccbSFabien Parent GATE_IFR5(CLK_IFR_I2C2_AXI, "ifr_i2c2_axi", "i2c_sel", 26), 737d46adccbSFabien Parent GATE_IFR5(CLK_IFR_I2C3_AXI, "ifr_i2c3_axi", "i2c_sel", 27), 738d46adccbSFabien Parent GATE_IFR5(CLK_IFR_NIC_AXI, "ifr_nic_axi", "axi_sel", 28), 739d46adccbSFabien Parent GATE_IFR5(CLK_IFR_NIC_SLV_AXI, "ifr_nic_slv_axi", "axi_sel", 29), 740d46adccbSFabien Parent GATE_IFR5(CLK_IFR_APU_AXI, "ifr_apu_axi", "axi_sel", 30), 741d46adccbSFabien Parent /* IFR6 */ 742d46adccbSFabien Parent GATE_IFR6(CLK_IFR_NFIECC, "ifr_nfiecc", "nfiecc_sel", 0), 743d46adccbSFabien Parent GATE_IFR6(CLK_IFR_NFI1X_BK, "ifr_nfi1x_bk", "nfi2x_sel", 1), 744d46adccbSFabien Parent GATE_IFR6(CLK_IFR_NFIECC_BK, "ifr_nfiecc_bk", "nfi2x_sel", 2), 745d46adccbSFabien Parent GATE_IFR6(CLK_IFR_NFI_BK, "ifr_nfi_bk", "axi_sel", 3), 746d46adccbSFabien Parent GATE_IFR6(CLK_IFR_MSDC2_AP_BK, "ifr_msdc2_ap_bk", "axi_sel", 4), 747d46adccbSFabien Parent GATE_IFR6(CLK_IFR_MSDC2_MD_BK, "ifr_msdc2_md_bk", "axi_sel", 5), 748d46adccbSFabien Parent GATE_IFR6(CLK_IFR_MSDC2_BK, "ifr_msdc2_bk", "axi_sel", 6), 749d46adccbSFabien Parent GATE_IFR6(CLK_IFR_SUSB_133_BK, "ifr_susb_133_bk", "axi_sel", 7), 750d46adccbSFabien Parent GATE_IFR6(CLK_IFR_SUSB_66_BK, "ifr_susb_66_bk", "axi_sel", 8), 751d46adccbSFabien Parent GATE_IFR6(CLK_IFR_SSUSB_SYS, "ifr_ssusb_sys", "ssusb_sys_sel", 9), 752d46adccbSFabien Parent GATE_IFR6(CLK_IFR_SSUSB_REF, "ifr_ssusb_ref", "ssusb_sys_sel", 10), 753d46adccbSFabien Parent GATE_IFR6(CLK_IFR_SSUSB_XHCI, "ifr_ssusb_xhci", "ssusb_xhci_sel", 11), 754d46adccbSFabien Parent }; 755d46adccbSFabien Parent 756d46adccbSFabien Parent static const struct mtk_simple_gate peri_clks[] = { 757d46adccbSFabien Parent { CLK_PERIAXI, "periaxi", "axi_sel", 0x20c, 31, 0 }, 758d46adccbSFabien Parent }; 759d46adccbSFabien Parent 760d46adccbSFabien Parent #define MT8365_PLL_FMAX (3800UL * MHZ) 761d46adccbSFabien Parent #define MT8365_PLL_FMIN (1500UL * MHZ) 762d46adccbSFabien Parent #define CON0_MT8365_RST_BAR BIT(23) 763d46adccbSFabien Parent 764d46adccbSFabien Parent #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 765d46adccbSFabien Parent _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ 766d46adccbSFabien Parent _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table, \ 767d46adccbSFabien Parent _rst_bar_mask, _pcw_chg_reg) { \ 768d46adccbSFabien Parent .id = _id, \ 769d46adccbSFabien Parent .name = _name, \ 770d46adccbSFabien Parent .reg = _reg, \ 771d46adccbSFabien Parent .pwr_reg = _pwr_reg, \ 772d46adccbSFabien Parent .en_mask = _en_mask, \ 773d46adccbSFabien Parent .flags = _flags, \ 774d46adccbSFabien Parent .rst_bar_mask = _rst_bar_mask, \ 775d46adccbSFabien Parent .fmax = MT8365_PLL_FMAX, \ 776d46adccbSFabien Parent .fmin = MT8365_PLL_FMIN, \ 777d46adccbSFabien Parent .pcwbits = _pcwbits, \ 778d46adccbSFabien Parent .pcwibits = 8, \ 779d46adccbSFabien Parent .pd_reg = _pd_reg, \ 780d46adccbSFabien Parent .pd_shift = _pd_shift, \ 781d46adccbSFabien Parent .tuner_reg = _tuner_reg, \ 782d46adccbSFabien Parent .tuner_en_reg = _tuner_en_reg, \ 783d46adccbSFabien Parent .tuner_en_bit = _tuner_en_bit, \ 784d46adccbSFabien Parent .pcw_reg = _pcw_reg, \ 785d46adccbSFabien Parent .pcw_shift = _pcw_shift, \ 786d46adccbSFabien Parent .pcw_chg_reg = _pcw_chg_reg, \ 787d46adccbSFabien Parent .div_table = _div_table, \ 788d46adccbSFabien Parent } 789d46adccbSFabien Parent 790d46adccbSFabien Parent #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ 791d46adccbSFabien Parent _pd_reg, _pd_shift, _tuner_reg, \ 792d46adccbSFabien Parent _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ 793d46adccbSFabien Parent _pcw_shift, _rst_bar_mask, _pcw_chg_reg) \ 794d46adccbSFabien Parent PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 795d46adccbSFabien Parent _pcwbits, _pd_reg, _pd_shift, \ 796d46adccbSFabien Parent _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 797d46adccbSFabien Parent _pcw_reg, _pcw_shift, NULL, _rst_bar_mask, \ 798d46adccbSFabien Parent _pcw_chg_reg) \ 799d46adccbSFabien Parent 800d46adccbSFabien Parent static const struct mtk_pll_div_table armpll_div_table[] = { 801d46adccbSFabien Parent { .div = 0, .freq = MT8365_PLL_FMAX }, 802d46adccbSFabien Parent { .div = 1, .freq = 1500 * MHZ }, 803d46adccbSFabien Parent { .div = 2, .freq = 750 * MHZ }, 804d46adccbSFabien Parent { .div = 3, .freq = 375 * MHZ }, 805d46adccbSFabien Parent { .div = 4, .freq = 182500000 }, 806d46adccbSFabien Parent { } /* sentinel */ 807d46adccbSFabien Parent }; 808d46adccbSFabien Parent 809d46adccbSFabien Parent static const struct mtk_pll_div_table mfgpll_div_table[] = { 810d46adccbSFabien Parent { .div = 0, .freq = MT8365_PLL_FMAX }, 811d46adccbSFabien Parent { .div = 1, .freq = 1600 * MHZ }, 812d46adccbSFabien Parent { .div = 2, .freq = 800 * MHZ }, 813d46adccbSFabien Parent { .div = 3, .freq = 400 * MHZ }, 814d46adccbSFabien Parent { .div = 4, .freq = 200 * MHZ }, 815d46adccbSFabien Parent { } /* sentinel */ 816d46adccbSFabien Parent }; 817d46adccbSFabien Parent 818d46adccbSFabien Parent static const struct mtk_pll_div_table dsppll_div_table[] = { 819d46adccbSFabien Parent { .div = 0, .freq = MT8365_PLL_FMAX }, 820d46adccbSFabien Parent { .div = 1, .freq = 1600 * MHZ }, 821d46adccbSFabien Parent { .div = 2, .freq = 600 * MHZ }, 822d46adccbSFabien Parent { .div = 3, .freq = 400 * MHZ }, 823d46adccbSFabien Parent { .div = 4, .freq = 200 * MHZ }, 824d46adccbSFabien Parent { } /* sentinel */ 825d46adccbSFabien Parent }; 826d46adccbSFabien Parent 827d46adccbSFabien Parent static const struct mtk_pll_data plls[] = { 828d46adccbSFabien Parent PLL_B(CLK_APMIXED_ARMPLL, "armpll", 0x030C, 0x0318, 0x00000001, PLL_AO, 829d46adccbSFabien Parent 22, 0x0310, 24, 0, 0, 0, 0x0310, 0, armpll_div_table, 0, 0), 830d46adccbSFabien Parent PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0228, 0x0234, 0xFF000001, 831d46adccbSFabien Parent HAVE_RST_BAR, 22, 0x022C, 24, 0, 0, 0, 0x022C, 0, 832d46adccbSFabien Parent CON0_MT8365_RST_BAR, 0), 833d46adccbSFabien Parent PLL(CLK_APMIXED_UNIVPLL, "univpll2", 0x0208, 0x0214, 0xFF000001, 834d46adccbSFabien Parent HAVE_RST_BAR, 22, 0x020C, 24, 0, 0, 0, 0x020C, 0, 835d46adccbSFabien Parent CON0_MT8365_RST_BAR, 0), 836d46adccbSFabien Parent PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0218, 0x0224, 0x00000001, 0, 22, 837d46adccbSFabien Parent 0x021C, 24, 0, 0, 0, 0x021C, 0, mfgpll_div_table, 0, 0), 838d46adccbSFabien Parent PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035C, 0x00000001, 0, 22, 839d46adccbSFabien Parent 0x0354, 24, 0, 0, 0, 0x0354, 0, 0, 0), 840d46adccbSFabien Parent PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0330, 0x033C, 0x00000001, 0, 22, 841d46adccbSFabien Parent 0x0334, 24, 0, 0, 0, 0x0334, 0, 0, 0), 842d46adccbSFabien Parent PLL(CLK_APMIXED_APLL1, "apll1", 0x031C, 0x032C, 0x00000001, 0, 32, 843d46adccbSFabien Parent 0x0320, 24, 0x0040, 0x000C, 0, 0x0324, 0, 0, 0x0320), 844d46adccbSFabien Parent PLL(CLK_APMIXED_APLL2, "apll2", 0x0360, 0x0370, 0x00000001, 0, 32, 845d46adccbSFabien Parent 0x0364, 24, 0x004C, 0x000C, 5, 0x0368, 0, 0, 0x0364), 846d46adccbSFabien Parent PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0374, 0x0380, 0x00000001, 0, 22, 847d46adccbSFabien Parent 0x0378, 24, 0, 0, 0, 0x0378, 0, 0, 0), 848d46adccbSFabien Parent PLL_B(CLK_APMIXED_DSPPLL, "dsppll", 0x0390, 0x039C, 0x00000001, 0, 22, 849d46adccbSFabien Parent 0x0394, 24, 0, 0, 0, 0x0394, 0, dsppll_div_table, 0, 0), 850d46adccbSFabien Parent PLL(CLK_APMIXED_APUPLL, "apupll", 0x03A0, 0x03AC, 0x00000001, 0, 22, 851d46adccbSFabien Parent 0x03A4, 24, 0, 0, 0, 0x03A4, 0, 0, 0), 852d46adccbSFabien Parent }; 853d46adccbSFabien Parent 854d46adccbSFabien Parent static int clk_mt8365_apmixed_probe(struct platform_device *pdev) 855d46adccbSFabien Parent { 856d46adccbSFabien Parent void __iomem *base; 857d46adccbSFabien Parent struct clk_hw_onecell_data *clk_data; 858d46adccbSFabien Parent struct device_node *node = pdev->dev.of_node; 859d46adccbSFabien Parent struct device *dev = &pdev->dev; 860d46adccbSFabien Parent struct clk_hw *hw; 861d46adccbSFabien Parent int ret; 862d46adccbSFabien Parent 863d46adccbSFabien Parent base = devm_platform_ioremap_resource(pdev, 0); 864d46adccbSFabien Parent if (IS_ERR(base)) 865d46adccbSFabien Parent return PTR_ERR(base); 866d46adccbSFabien Parent 867d46adccbSFabien Parent clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); 868d46adccbSFabien Parent if (!clk_data) 869d46adccbSFabien Parent return -ENOMEM; 870d46adccbSFabien Parent 871d46adccbSFabien Parent hw = devm_clk_hw_register_gate(dev, "univ_en", "univpll2", 0, 872d46adccbSFabien Parent base + 0x204, 0, 0, NULL); 873d46adccbSFabien Parent if (IS_ERR(hw)) 874d46adccbSFabien Parent return PTR_ERR(hw); 875d46adccbSFabien Parent clk_data->hws[CLK_APMIXED_UNIV_EN] = hw; 876d46adccbSFabien Parent 877d46adccbSFabien Parent hw = devm_clk_hw_register_gate(dev, "usb20_en", "univ_en", 0, 878d46adccbSFabien Parent base + 0x204, 1, 0, NULL); 879d46adccbSFabien Parent if (IS_ERR(hw)) 880d46adccbSFabien Parent return PTR_ERR(hw); 881d46adccbSFabien Parent clk_data->hws[CLK_APMIXED_USB20_EN] = hw; 882d46adccbSFabien Parent 883d46adccbSFabien Parent ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 884d46adccbSFabien Parent if (ret) 885d46adccbSFabien Parent return ret; 886d46adccbSFabien Parent 887d46adccbSFabien Parent ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 888d46adccbSFabien Parent if (ret) 889d46adccbSFabien Parent goto unregister_plls; 890d46adccbSFabien Parent 891d46adccbSFabien Parent return 0; 892d46adccbSFabien Parent 893d46adccbSFabien Parent unregister_plls: 894d46adccbSFabien Parent mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); 895d46adccbSFabien Parent 896d46adccbSFabien Parent return ret; 897d46adccbSFabien Parent } 898d46adccbSFabien Parent 899d46adccbSFabien Parent static int 900d46adccbSFabien Parent clk_mt8365_register_mtk_simple_gates(struct device *dev, void __iomem *base, 901d46adccbSFabien Parent struct clk_hw_onecell_data *clk_data, 902d46adccbSFabien Parent const struct mtk_simple_gate *gates, 903d46adccbSFabien Parent unsigned int num_gates) 904d46adccbSFabien Parent { 905d46adccbSFabien Parent unsigned int i; 906d46adccbSFabien Parent 907d46adccbSFabien Parent for (i = 0; i != num_gates; ++i) { 908d46adccbSFabien Parent const struct mtk_simple_gate *gate = &gates[i]; 909d46adccbSFabien Parent struct clk_hw *hw; 910d46adccbSFabien Parent 911d46adccbSFabien Parent hw = devm_clk_hw_register_gate(dev, gate->name, gate->parent, 0, 912d46adccbSFabien Parent base + gate->reg, gate->shift, 913d46adccbSFabien Parent gate->gate_flags, NULL); 914d46adccbSFabien Parent if (IS_ERR(hw)) 915d46adccbSFabien Parent return PTR_ERR(hw); 916d46adccbSFabien Parent 917d46adccbSFabien Parent clk_data->hws[gate->id] = hw; 918d46adccbSFabien Parent } 919d46adccbSFabien Parent 920d46adccbSFabien Parent return 0; 921d46adccbSFabien Parent } 922d46adccbSFabien Parent 923d46adccbSFabien Parent static int clk_mt8365_top_probe(struct platform_device *pdev) 924d46adccbSFabien Parent { 925d46adccbSFabien Parent void __iomem *base; 926d46adccbSFabien Parent struct clk_hw_onecell_data *clk_data; 927d46adccbSFabien Parent struct device_node *node = pdev->dev.of_node; 928d46adccbSFabien Parent struct device *dev = &pdev->dev; 929d46adccbSFabien Parent int ret; 930d46adccbSFabien Parent int i; 931d46adccbSFabien Parent 932d46adccbSFabien Parent base = devm_platform_ioremap_resource(pdev, 0); 933d46adccbSFabien Parent if (IS_ERR(base)) 934d46adccbSFabien Parent return PTR_ERR(base); 935d46adccbSFabien Parent 936d46adccbSFabien Parent clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 937d46adccbSFabien Parent if (!clk_data) 938d46adccbSFabien Parent return -ENOMEM; 939d46adccbSFabien Parent 940d46adccbSFabien Parent ret = mtk_clk_register_fixed_clks(top_fixed_clks, 941d46adccbSFabien Parent ARRAY_SIZE(top_fixed_clks), clk_data); 942d46adccbSFabien Parent if (ret) 943d46adccbSFabien Parent goto free_clk_data; 944d46adccbSFabien Parent 945d46adccbSFabien Parent ret = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), 946d46adccbSFabien Parent clk_data); 947d46adccbSFabien Parent if (ret) 948d46adccbSFabien Parent goto unregister_fixed_clks; 949d46adccbSFabien Parent 950*d3d6bd5eSAngeloGioacchino Del Regno ret = mtk_clk_register_muxes(&pdev->dev, top_muxes, 951*d3d6bd5eSAngeloGioacchino Del Regno ARRAY_SIZE(top_muxes), node, 952d46adccbSFabien Parent &mt8365_clk_lock, clk_data); 953d46adccbSFabien Parent if (ret) 954d46adccbSFabien Parent goto unregister_factors; 955d46adccbSFabien Parent 95601a6c1abSAngeloGioacchino Del Regno ret = mtk_clk_register_composites(&pdev->dev, top_misc_mux_gates, 957d46adccbSFabien Parent ARRAY_SIZE(top_misc_mux_gates), base, 958d46adccbSFabien Parent &mt8365_clk_lock, clk_data); 959d46adccbSFabien Parent if (ret) 960d46adccbSFabien Parent goto unregister_muxes; 961d46adccbSFabien Parent 962d46adccbSFabien Parent for (i = 0; i != ARRAY_SIZE(top_misc_muxes); ++i) { 963d46adccbSFabien Parent struct mt8365_clk_audio_mux *mux = &top_misc_muxes[i]; 964d46adccbSFabien Parent struct clk_hw *hw; 965d46adccbSFabien Parent 966d46adccbSFabien Parent hw = devm_clk_hw_register_mux(dev, mux->name, apll_i2s0_parents, 967d46adccbSFabien Parent ARRAY_SIZE(apll_i2s0_parents), 968d46adccbSFabien Parent CLK_SET_RATE_PARENT, base + 0x320, 969d46adccbSFabien Parent mux->shift, 1, 0, NULL); 970d46adccbSFabien Parent if (IS_ERR(hw)) { 971d46adccbSFabien Parent ret = PTR_ERR(hw); 972d46adccbSFabien Parent goto unregister_composites; 973d46adccbSFabien Parent } 974d46adccbSFabien Parent 975d46adccbSFabien Parent clk_data->hws[mux->id] = hw; 976d46adccbSFabien Parent } 977d46adccbSFabien Parent 978d46adccbSFabien Parent ret = mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), 979d46adccbSFabien Parent base, &mt8365_clk_lock, clk_data); 980d46adccbSFabien Parent if (ret) 981d46adccbSFabien Parent goto unregister_composites; 982d46adccbSFabien Parent 983d46adccbSFabien Parent ret = clk_mt8365_register_mtk_simple_gates(dev, base, clk_data, 984d46adccbSFabien Parent top_clk_gates, 985d46adccbSFabien Parent ARRAY_SIZE(top_clk_gates)); 986d46adccbSFabien Parent if (ret) 987d46adccbSFabien Parent goto unregister_dividers; 988d46adccbSFabien Parent 989d46adccbSFabien Parent ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 990d46adccbSFabien Parent if (ret) 991d46adccbSFabien Parent goto unregister_dividers; 992d46adccbSFabien Parent 993d46adccbSFabien Parent return 0; 994d46adccbSFabien Parent unregister_dividers: 995d46adccbSFabien Parent mtk_clk_unregister_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), 996d46adccbSFabien Parent clk_data); 997d46adccbSFabien Parent unregister_composites: 998d46adccbSFabien Parent mtk_clk_unregister_composites(top_misc_mux_gates, 999d46adccbSFabien Parent ARRAY_SIZE(top_misc_mux_gates), clk_data); 1000d46adccbSFabien Parent unregister_muxes: 1001d46adccbSFabien Parent mtk_clk_unregister_muxes(top_muxes, ARRAY_SIZE(top_muxes), clk_data); 1002d46adccbSFabien Parent unregister_factors: 1003d46adccbSFabien Parent mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); 1004d46adccbSFabien Parent unregister_fixed_clks: 1005d46adccbSFabien Parent mtk_clk_unregister_fixed_clks(top_fixed_clks, 1006d46adccbSFabien Parent ARRAY_SIZE(top_fixed_clks), clk_data); 1007d46adccbSFabien Parent free_clk_data: 1008d46adccbSFabien Parent mtk_free_clk_data(clk_data); 1009d46adccbSFabien Parent 1010d46adccbSFabien Parent return ret; 1011d46adccbSFabien Parent } 1012d46adccbSFabien Parent 1013d46adccbSFabien Parent static int clk_mt8365_infra_probe(struct platform_device *pdev) 1014d46adccbSFabien Parent { 1015d46adccbSFabien Parent struct clk_hw_onecell_data *clk_data; 1016d46adccbSFabien Parent struct device_node *node = pdev->dev.of_node; 1017d46adccbSFabien Parent int ret; 1018d46adccbSFabien Parent 1019d46adccbSFabien Parent clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK); 1020d46adccbSFabien Parent if (!clk_data) 1021d46adccbSFabien Parent return -ENOMEM; 1022d46adccbSFabien Parent 102320498d52SAngeloGioacchino Del Regno ret = mtk_clk_register_gates(&pdev->dev, node, ifr_clks, 102420498d52SAngeloGioacchino Del Regno ARRAY_SIZE(ifr_clks), clk_data); 1025d46adccbSFabien Parent if (ret) 1026d46adccbSFabien Parent goto free_clk_data; 1027d46adccbSFabien Parent 1028d46adccbSFabien Parent ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1029d46adccbSFabien Parent if (ret) 1030d46adccbSFabien Parent goto unregister_gates; 1031d46adccbSFabien Parent 1032d46adccbSFabien Parent return 0; 1033d46adccbSFabien Parent 1034d46adccbSFabien Parent unregister_gates: 1035d46adccbSFabien Parent mtk_clk_unregister_gates(ifr_clks, ARRAY_SIZE(ifr_clks), clk_data); 1036d46adccbSFabien Parent free_clk_data: 1037d46adccbSFabien Parent mtk_free_clk_data(clk_data); 1038d46adccbSFabien Parent 1039d46adccbSFabien Parent return ret; 1040d46adccbSFabien Parent } 1041d46adccbSFabien Parent 1042d46adccbSFabien Parent static int clk_mt8365_peri_probe(struct platform_device *pdev) 1043d46adccbSFabien Parent { 1044d46adccbSFabien Parent void __iomem *base; 1045d46adccbSFabien Parent struct clk_hw_onecell_data *clk_data; 1046d46adccbSFabien Parent struct device *dev = &pdev->dev; 1047d46adccbSFabien Parent struct device_node *node = dev->of_node; 1048d46adccbSFabien Parent int ret; 1049d46adccbSFabien Parent 1050d46adccbSFabien Parent base = devm_platform_ioremap_resource(pdev, 0); 1051d46adccbSFabien Parent if (IS_ERR(base)) 1052d46adccbSFabien Parent return PTR_ERR(base); 1053d46adccbSFabien Parent 1054d46adccbSFabien Parent clk_data = mtk_devm_alloc_clk_data(dev, CLK_PERI_NR_CLK); 1055d46adccbSFabien Parent if (!clk_data) 1056d46adccbSFabien Parent return -ENOMEM; 1057d46adccbSFabien Parent 1058d46adccbSFabien Parent ret = clk_mt8365_register_mtk_simple_gates(dev, base, clk_data, 1059d46adccbSFabien Parent peri_clks, 1060d46adccbSFabien Parent ARRAY_SIZE(peri_clks)); 1061d46adccbSFabien Parent if (ret) 1062d46adccbSFabien Parent return ret; 1063d46adccbSFabien Parent 1064d46adccbSFabien Parent ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1065d46adccbSFabien Parent 1066d46adccbSFabien Parent return ret; 1067d46adccbSFabien Parent } 1068d46adccbSFabien Parent 1069d46adccbSFabien Parent static int clk_mt8365_mcu_probe(struct platform_device *pdev) 1070d46adccbSFabien Parent { 1071d46adccbSFabien Parent struct clk_hw_onecell_data *clk_data; 1072d46adccbSFabien Parent struct device_node *node = pdev->dev.of_node; 1073d46adccbSFabien Parent void __iomem *base; 1074d46adccbSFabien Parent int ret; 1075d46adccbSFabien Parent 1076d46adccbSFabien Parent base = devm_platform_ioremap_resource(pdev, 0); 1077d46adccbSFabien Parent if (IS_ERR(base)) 1078d46adccbSFabien Parent return PTR_ERR(base); 1079d46adccbSFabien Parent 1080d46adccbSFabien Parent clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); 1081d46adccbSFabien Parent if (!clk_data) 1082d46adccbSFabien Parent return -ENOMEM; 1083d46adccbSFabien Parent 108401a6c1abSAngeloGioacchino Del Regno ret = mtk_clk_register_composites(&pdev->dev, mcu_muxes, 108501a6c1abSAngeloGioacchino Del Regno ARRAY_SIZE(mcu_muxes), base, 108601a6c1abSAngeloGioacchino Del Regno &mt8365_clk_lock, clk_data); 1087d46adccbSFabien Parent if (ret) 1088d46adccbSFabien Parent goto free_clk_data; 1089d46adccbSFabien Parent 1090d46adccbSFabien Parent ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1091d46adccbSFabien Parent if (ret) 1092d46adccbSFabien Parent goto unregister_composites; 1093d46adccbSFabien Parent 1094d46adccbSFabien Parent return 0; 1095d46adccbSFabien Parent 1096d46adccbSFabien Parent unregister_composites: 1097d46adccbSFabien Parent mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), 1098d46adccbSFabien Parent clk_data); 1099d46adccbSFabien Parent free_clk_data: 1100d46adccbSFabien Parent mtk_free_clk_data(clk_data); 1101d46adccbSFabien Parent 1102d46adccbSFabien Parent return ret; 1103d46adccbSFabien Parent } 1104d46adccbSFabien Parent 1105d46adccbSFabien Parent static const struct of_device_id of_match_clk_mt8365[] = { 1106d46adccbSFabien Parent { 1107d46adccbSFabien Parent .compatible = "mediatek,mt8365-apmixedsys", 1108d46adccbSFabien Parent .data = clk_mt8365_apmixed_probe, 1109d46adccbSFabien Parent }, { 1110d46adccbSFabien Parent .compatible = "mediatek,mt8365-topckgen", 1111d46adccbSFabien Parent .data = clk_mt8365_top_probe, 1112d46adccbSFabien Parent }, { 1113d46adccbSFabien Parent .compatible = "mediatek,mt8365-infracfg", 1114d46adccbSFabien Parent .data = clk_mt8365_infra_probe, 1115d46adccbSFabien Parent }, { 1116d46adccbSFabien Parent .compatible = "mediatek,mt8365-pericfg", 1117d46adccbSFabien Parent .data = clk_mt8365_peri_probe, 1118d46adccbSFabien Parent }, { 1119d46adccbSFabien Parent .compatible = "mediatek,mt8365-mcucfg", 1120d46adccbSFabien Parent .data = clk_mt8365_mcu_probe, 1121d46adccbSFabien Parent }, { 1122d46adccbSFabien Parent /* sentinel */ 1123d46adccbSFabien Parent } 1124d46adccbSFabien Parent }; 1125d46adccbSFabien Parent 1126d46adccbSFabien Parent static int clk_mt8365_probe(struct platform_device *pdev) 1127d46adccbSFabien Parent { 1128d46adccbSFabien Parent int (*clk_probe)(struct platform_device *pdev); 1129d46adccbSFabien Parent int ret; 1130d46adccbSFabien Parent 1131d46adccbSFabien Parent clk_probe = of_device_get_match_data(&pdev->dev); 1132d46adccbSFabien Parent if (!clk_probe) 1133d46adccbSFabien Parent return -EINVAL; 1134d46adccbSFabien Parent 1135d46adccbSFabien Parent ret = clk_probe(pdev); 1136d46adccbSFabien Parent if (ret) 1137d46adccbSFabien Parent dev_err(&pdev->dev, 1138d46adccbSFabien Parent "%s: could not register clock provider: %d\n", 1139d46adccbSFabien Parent pdev->name, ret); 1140d46adccbSFabien Parent 1141d46adccbSFabien Parent return ret; 1142d46adccbSFabien Parent } 1143d46adccbSFabien Parent 1144d46adccbSFabien Parent static struct platform_driver clk_mt8365_drv = { 1145d46adccbSFabien Parent .probe = clk_mt8365_probe, 1146d46adccbSFabien Parent .driver = { 1147d46adccbSFabien Parent .name = "clk-mt8365", 1148d46adccbSFabien Parent .of_match_table = of_match_clk_mt8365, 1149d46adccbSFabien Parent }, 1150d46adccbSFabien Parent }; 1151d46adccbSFabien Parent 1152d46adccbSFabien Parent static int __init clk_mt8365_init(void) 1153d46adccbSFabien Parent { 1154d46adccbSFabien Parent return platform_driver_register(&clk_mt8365_drv); 1155d46adccbSFabien Parent } 1156d46adccbSFabien Parent arch_initcall(clk_mt8365_init); 1157d46adccbSFabien Parent MODULE_LICENSE("GPL"); 1158