1*d46adccbSFabien Parent // SPDX-License-Identifier: GPL-2.0
2*d46adccbSFabien Parent /*
3*d46adccbSFabien Parent  * Copyright (C) 2022 MediaTek Inc.
4*d46adccbSFabien Parent  */
5*d46adccbSFabien Parent 
6*d46adccbSFabien Parent #include <dt-bindings/clock/mediatek,mt8365-clk.h>
7*d46adccbSFabien Parent #include <linux/clk-provider.h>
8*d46adccbSFabien Parent #include <linux/platform_device.h>
9*d46adccbSFabien Parent 
10*d46adccbSFabien Parent #include "clk-gate.h"
11*d46adccbSFabien Parent #include "clk-mtk.h"
12*d46adccbSFabien Parent 
13*d46adccbSFabien Parent static const struct mtk_gate_regs vdec0_cg_regs = {
14*d46adccbSFabien Parent 	.set_ofs = 0x0,
15*d46adccbSFabien Parent 	.clr_ofs = 0x4,
16*d46adccbSFabien Parent 	.sta_ofs = 0x0,
17*d46adccbSFabien Parent };
18*d46adccbSFabien Parent 
19*d46adccbSFabien Parent static const struct mtk_gate_regs vdec1_cg_regs = {
20*d46adccbSFabien Parent 	.set_ofs = 0x8,
21*d46adccbSFabien Parent 	.clr_ofs = 0xc,
22*d46adccbSFabien Parent 	.sta_ofs = 0x8,
23*d46adccbSFabien Parent };
24*d46adccbSFabien Parent 
25*d46adccbSFabien Parent #define GATE_VDEC0(_id, _name, _parent, _shift) \
26*d46adccbSFabien Parent 		GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
27*d46adccbSFabien Parent 			 &mtk_clk_gate_ops_setclr_inv)
28*d46adccbSFabien Parent 
29*d46adccbSFabien Parent #define GATE_VDEC1(_id, _name, _parent, _shift) \
30*d46adccbSFabien Parent 		GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
31*d46adccbSFabien Parent 			 &mtk_clk_gate_ops_setclr_inv)
32*d46adccbSFabien Parent 
33*d46adccbSFabien Parent static const struct mtk_gate vdec_clks[] = {
34*d46adccbSFabien Parent 	/* VDEC0 */
35*d46adccbSFabien Parent 	GATE_VDEC0(CLK_VDEC_VDEC, "vdec_fvdec_ck", "mm_sel", 0),
36*d46adccbSFabien Parent 	/* VDEC1 */
37*d46adccbSFabien Parent 	GATE_VDEC1(CLK_VDEC_LARB1, "vdec_flarb1_ck", "mm_sel", 0),
38*d46adccbSFabien Parent };
39*d46adccbSFabien Parent 
40*d46adccbSFabien Parent static const struct mtk_clk_desc vdec_desc = {
41*d46adccbSFabien Parent 	.clks = vdec_clks,
42*d46adccbSFabien Parent 	.num_clks = ARRAY_SIZE(vdec_clks),
43*d46adccbSFabien Parent };
44*d46adccbSFabien Parent 
45*d46adccbSFabien Parent static const struct of_device_id of_match_clk_mt8365_vdec[] = {
46*d46adccbSFabien Parent 	{
47*d46adccbSFabien Parent 		.compatible = "mediatek,mt8365-vdecsys",
48*d46adccbSFabien Parent 		.data = &vdec_desc,
49*d46adccbSFabien Parent 	}, {
50*d46adccbSFabien Parent 		/* sentinel */
51*d46adccbSFabien Parent 	}
52*d46adccbSFabien Parent };
53*d46adccbSFabien Parent 
54*d46adccbSFabien Parent static struct platform_driver clk_mt8365_vdec_drv = {
55*d46adccbSFabien Parent 	.probe = mtk_clk_simple_probe,
56*d46adccbSFabien Parent 	.remove = mtk_clk_simple_remove,
57*d46adccbSFabien Parent 	.driver = {
58*d46adccbSFabien Parent 		.name = "clk-mt8365-vdec",
59*d46adccbSFabien Parent 		.of_match_table = of_match_clk_mt8365_vdec,
60*d46adccbSFabien Parent 	},
61*d46adccbSFabien Parent };
62*d46adccbSFabien Parent builtin_platform_driver(clk_mt8365_vdec_drv);
63*d46adccbSFabien Parent MODULE_LICENSE("GPL");
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