1d46adccbSFabien Parent // SPDX-License-Identifier: GPL-2.0 2d46adccbSFabien Parent /* 3d46adccbSFabien Parent * Copyright (C) 2022 MediaTek Inc. 4d46adccbSFabien Parent */ 5d46adccbSFabien Parent 6d46adccbSFabien Parent #include <dt-bindings/clock/mediatek,mt8365-clk.h> 7d46adccbSFabien Parent #include <linux/clk-provider.h> 8d46adccbSFabien Parent #include <linux/platform_device.h> 9d46adccbSFabien Parent 10d46adccbSFabien Parent #include "clk-gate.h" 11d46adccbSFabien Parent #include "clk-mtk.h" 12d46adccbSFabien Parent 13d46adccbSFabien Parent static const struct mtk_gate_regs vdec0_cg_regs = { 14d46adccbSFabien Parent .set_ofs = 0x0, 15d46adccbSFabien Parent .clr_ofs = 0x4, 16d46adccbSFabien Parent .sta_ofs = 0x0, 17d46adccbSFabien Parent }; 18d46adccbSFabien Parent 19d46adccbSFabien Parent static const struct mtk_gate_regs vdec1_cg_regs = { 20d46adccbSFabien Parent .set_ofs = 0x8, 21d46adccbSFabien Parent .clr_ofs = 0xc, 22d46adccbSFabien Parent .sta_ofs = 0x8, 23d46adccbSFabien Parent }; 24d46adccbSFabien Parent 25d46adccbSFabien Parent #define GATE_VDEC0(_id, _name, _parent, _shift) \ 26d46adccbSFabien Parent GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \ 27d46adccbSFabien Parent &mtk_clk_gate_ops_setclr_inv) 28d46adccbSFabien Parent 29d46adccbSFabien Parent #define GATE_VDEC1(_id, _name, _parent, _shift) \ 30d46adccbSFabien Parent GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \ 31d46adccbSFabien Parent &mtk_clk_gate_ops_setclr_inv) 32d46adccbSFabien Parent 33d46adccbSFabien Parent static const struct mtk_gate vdec_clks[] = { 34d46adccbSFabien Parent /* VDEC0 */ 35d46adccbSFabien Parent GATE_VDEC0(CLK_VDEC_VDEC, "vdec_fvdec_ck", "mm_sel", 0), 36d46adccbSFabien Parent /* VDEC1 */ 37d46adccbSFabien Parent GATE_VDEC1(CLK_VDEC_LARB1, "vdec_flarb1_ck", "mm_sel", 0), 38d46adccbSFabien Parent }; 39d46adccbSFabien Parent 40d46adccbSFabien Parent static const struct mtk_clk_desc vdec_desc = { 41d46adccbSFabien Parent .clks = vdec_clks, 42d46adccbSFabien Parent .num_clks = ARRAY_SIZE(vdec_clks), 43d46adccbSFabien Parent }; 44d46adccbSFabien Parent 45d46adccbSFabien Parent static const struct of_device_id of_match_clk_mt8365_vdec[] = { 46d46adccbSFabien Parent { 47d46adccbSFabien Parent .compatible = "mediatek,mt8365-vdecsys", 48d46adccbSFabien Parent .data = &vdec_desc, 49d46adccbSFabien Parent }, { 50d46adccbSFabien Parent /* sentinel */ 51d46adccbSFabien Parent } 52d46adccbSFabien Parent }; 5365c9ad77SAngeloGioacchino Del Regno MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_vdec); 54d46adccbSFabien Parent 55d46adccbSFabien Parent static struct platform_driver clk_mt8365_vdec_drv = { 56d46adccbSFabien Parent .probe = mtk_clk_simple_probe, 57*61ca6ee7SUwe Kleine-König .remove_new = mtk_clk_simple_remove, 58d46adccbSFabien Parent .driver = { 59d46adccbSFabien Parent .name = "clk-mt8365-vdec", 60d46adccbSFabien Parent .of_match_table = of_match_clk_mt8365_vdec, 61d46adccbSFabien Parent }, 62d46adccbSFabien Parent }; 63164d240dSAngeloGioacchino Del Regno module_platform_driver(clk_mt8365_vdec_drv); 64d46adccbSFabien Parent MODULE_LICENSE("GPL"); 65