1*d46adccbSFabien Parent // SPDX-License-Identifier: GPL-2.0 2*d46adccbSFabien Parent /* 3*d46adccbSFabien Parent * Copyright (C) 2022 MediaTek Inc. 4*d46adccbSFabien Parent */ 5*d46adccbSFabien Parent 6*d46adccbSFabien Parent #include <dt-bindings/clock/mediatek,mt8365-clk.h> 7*d46adccbSFabien Parent #include <linux/clk-provider.h> 8*d46adccbSFabien Parent #include <linux/platform_device.h> 9*d46adccbSFabien Parent 10*d46adccbSFabien Parent #include "clk-gate.h" 11*d46adccbSFabien Parent #include "clk-mtk.h" 12*d46adccbSFabien Parent 13*d46adccbSFabien Parent static const struct mtk_gate_regs mfg0_cg_regs = { 14*d46adccbSFabien Parent .set_ofs = 0x4, 15*d46adccbSFabien Parent .clr_ofs = 0x8, 16*d46adccbSFabien Parent .sta_ofs = 0x0, 17*d46adccbSFabien Parent }; 18*d46adccbSFabien Parent 19*d46adccbSFabien Parent static const struct mtk_gate_regs mfg1_cg_regs = { 20*d46adccbSFabien Parent .set_ofs = 0x280, 21*d46adccbSFabien Parent .clr_ofs = 0x280, 22*d46adccbSFabien Parent .sta_ofs = 0x280, 23*d46adccbSFabien Parent }; 24*d46adccbSFabien Parent 25*d46adccbSFabien Parent #define GATE_MFG0(_id, _name, _parent, _shift) \ 26*d46adccbSFabien Parent GATE_MTK(_id, _name, _parent, &mfg0_cg_regs, _shift, \ 27*d46adccbSFabien Parent &mtk_clk_gate_ops_setclr) 28*d46adccbSFabien Parent 29*d46adccbSFabien Parent #define GATE_MFG1(_id, _name, _parent, _shift) \ 30*d46adccbSFabien Parent GATE_MTK(_id, _name, _parent, &mfg1_cg_regs, _shift, \ 31*d46adccbSFabien Parent &mtk_clk_gate_ops_no_setclr) 32*d46adccbSFabien Parent 33*d46adccbSFabien Parent static const struct mtk_gate mfg_clks[] = { 34*d46adccbSFabien Parent /* MFG0 */ 35*d46adccbSFabien Parent GATE_MFG0(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0), 36*d46adccbSFabien Parent /* MFG1 */ 37*d46adccbSFabien Parent GATE_MFG1(CLK_MFG_MBIST_DIAG, "mfg_mbist_diag", "mbist_diag_sel", 24), 38*d46adccbSFabien Parent }; 39*d46adccbSFabien Parent 40*d46adccbSFabien Parent static const struct mtk_clk_desc mfg_desc = { 41*d46adccbSFabien Parent .clks = mfg_clks, 42*d46adccbSFabien Parent .num_clks = ARRAY_SIZE(mfg_clks), 43*d46adccbSFabien Parent }; 44*d46adccbSFabien Parent 45*d46adccbSFabien Parent static const struct of_device_id of_match_clk_mt8365_mfg[] = { 46*d46adccbSFabien Parent { 47*d46adccbSFabien Parent .compatible = "mediatek,mt8365-mfgcfg", 48*d46adccbSFabien Parent .data = &mfg_desc, 49*d46adccbSFabien Parent }, { 50*d46adccbSFabien Parent /* sentinel */ 51*d46adccbSFabien Parent } 52*d46adccbSFabien Parent }; 53*d46adccbSFabien Parent 54*d46adccbSFabien Parent static struct platform_driver clk_mt8365_mfg_drv = { 55*d46adccbSFabien Parent .probe = mtk_clk_simple_probe, 56*d46adccbSFabien Parent .remove = mtk_clk_simple_remove, 57*d46adccbSFabien Parent .driver = { 58*d46adccbSFabien Parent .name = "clk-mt8365-mfg", 59*d46adccbSFabien Parent .of_match_table = of_match_clk_mt8365_mfg, 60*d46adccbSFabien Parent }, 61*d46adccbSFabien Parent }; 62*d46adccbSFabien Parent builtin_platform_driver(clk_mt8365_mfg_drv); 63*d46adccbSFabien Parent MODULE_LICENSE("GPL"); 64