1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Copyright (c) 2021 MediaTek Inc.
4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
5 
6 #include "clk-gate.h"
7 #include "clk-mtk.h"
8 #include "clk-mux.h"
9 
10 #include <dt-bindings/clock/mt8195-clk.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 
14 static DEFINE_SPINLOCK(mt8195_clk_lock);
15 
16 static const struct mtk_fixed_clk top_fixed_clks[] = {
17 	FIXED_CLK(CLK_TOP_IN_DGI, "in_dgi", NULL, 165000000),
18 	FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc1", NULL, 248000000),
19 	FIXED_CLK(CLK_TOP_ULPOSC2, "ulposc2", NULL, 326000000),
20 	FIXED_CLK(CLK_TOP_MEM_466M, "mem_466m", NULL, 533000000),
21 	FIXED_CLK(CLK_TOP_MPHONE_SLAVE_B, "mphone_slave_b", NULL, 49152000),
22 	FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL, 250000000),
23 	FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL, "ufs_rx_symbol", NULL, 166000000),
24 	FIXED_CLK(CLK_TOP_UFS_TX_SYMBOL, "ufs_tx_symbol", NULL, 166000000),
25 	FIXED_CLK(CLK_TOP_SSUSB_U3PHY_P1_P_P0, "ssusb_u3phy_p1_p_p0", NULL, 131000000),
26 	FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL1, "ufs_rx_symbol1", NULL, 166000000),
27 	FIXED_CLK(CLK_TOP_FPC, "fpc", NULL, 50000000),
28 	FIXED_CLK(CLK_TOP_HDMIRX_P, "hdmirx_p", NULL, 594000000),
29 };
30 
31 static const struct mtk_fixed_factor top_divs[] = {
32 	FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
33 	FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1, 52),
34 	FACTOR(CLK_TOP_IN_DGI_D2, "in_dgi_d2", "in_dgi", 1, 2),
35 	FACTOR(CLK_TOP_IN_DGI_D4, "in_dgi_d4", "in_dgi", 1, 4),
36 	FACTOR(CLK_TOP_IN_DGI_D6, "in_dgi_d6", "in_dgi", 1, 6),
37 	FACTOR(CLK_TOP_IN_DGI_D8, "in_dgi_d8", "in_dgi", 1, 8),
38 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
39 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
40 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0),
41 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0),
42 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0),
43 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
44 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
45 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
46 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0),
47 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6, 0),
48 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2, 0),
49 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4, 0),
50 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8, 0),
51 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7, 0),
52 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2, 0),
53 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4, 0),
54 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8, 0),
55 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9, 0),
56 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2, 0),
57 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
58 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4, 0),
59 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2, 0),
60 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4, 0),
61 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8, 0),
62 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
63 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
64 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
65 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0),
66 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6, 0),
67 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2, 0),
68 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4, 0),
69 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8, 0),
70 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16, 0),
71 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
72 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13, 0),
73 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4, 0),
74 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8, 0),
75 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16, 0),
76 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32, 0),
77 	FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3),
78 	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
79 	FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3),
80 	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
81 	FACTOR(CLK_TOP_APLL3_D4, "apll3_d4", "apll3", 1, 4),
82 	FACTOR(CLK_TOP_APLL4_D4, "apll4_d4", "apll4", 1, 4),
83 	FACTOR(CLK_TOP_APLL5_D4, "apll5_d4", "apll5", 1, 4),
84 	FACTOR(CLK_TOP_HDMIRX_APLL_D3, "hdmirx_apll_d3", "hdmirx_apll", 1, 3),
85 	FACTOR(CLK_TOP_HDMIRX_APLL_D4, "hdmirx_apll_d4", "hdmirx_apll", 1, 4),
86 	FACTOR(CLK_TOP_HDMIRX_APLL_D6, "hdmirx_apll_d6", "hdmirx_apll", 1, 6),
87 	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
88 	FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
89 	FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
90 	FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
91 	FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
92 	FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
93 	FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
94 	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
95 	FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
96 	FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9),
97 	FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2),
98 	FACTOR(CLK_TOP_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4),
99 	FACTOR(CLK_TOP_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8),
100 	FACTOR(CLK_TOP_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 1, 16),
101 	FACTOR(CLK_TOP_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2),
102 	FACTOR(CLK_TOP_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4),
103 	FACTOR(CLK_TOP_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8),
104 	FACTOR(CLK_TOP_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 1, 16),
105 	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
106 	FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
107 	FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
108 	FACTOR(CLK_TOP_ETHPLL_D2, "ethpll_d2", "ethpll", 1, 2),
109 	FACTOR(CLK_TOP_ETHPLL_D8, "ethpll_d8", "ethpll", 1, 8),
110 	FACTOR(CLK_TOP_ETHPLL_D10, "ethpll_d10", "ethpll", 1, 10),
111 	FACTOR(CLK_TOP_DGIPLL_D2, "dgipll_d2", "dgipll", 1, 2),
112 	FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1", 1, 2),
113 	FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1", 1, 4),
114 	FACTOR(CLK_TOP_ULPOSC1_D7, "ulposc1_d7", "ulposc1", 1, 7),
115 	FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1", 1, 8),
116 	FACTOR(CLK_TOP_ULPOSC1_D10, "ulposc1_d10", "ulposc1", 1, 10),
117 	FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1", 1, 16),
118 	FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll", 1, 2),
119 	FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
120 	FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll", 1, 8),
121 };
122 
123 static const char * const axi_parents[] = {
124 	"clk26m",
125 	"mainpll_d4_d4",
126 	"mainpll_d7_d2",
127 	"mainpll_d4_d2",
128 	"mainpll_d5_d2",
129 	"mainpll_d6_d2",
130 	"ulposc1_d4"
131 };
132 
133 static const char * const spm_parents[] = {
134 	"clk26m",
135 	"ulposc1_d10",
136 	"mainpll_d7_d4",
137 	"clk32k"
138 };
139 
140 static const char * const scp_parents[] = {
141 	"clk26m",
142 	"univpll_d4",
143 	"mainpll_d6",
144 	"univpll_d6",
145 	"univpll_d4_d2",
146 	"mainpll_d4_d2",
147 	"mainpll_d4",
148 	"mainpll_d6_d2"
149 };
150 
151 static const char * const bus_aximem_parents[] = {
152 	"clk26m",
153 	"mainpll_d7_d2",
154 	"mainpll_d4_d2",
155 	"mainpll_d5_d2",
156 	"mainpll_d6"
157 };
158 
159 static const char * const vpp_parents[] = {
160 	"clk26m",
161 	"univpll_d6_d2",
162 	"mainpll_d5_d2",
163 	"mmpll_d6_d2",
164 	"univpll_d5_d2",
165 	"univpll_d4_d2",
166 	"mmpll_d4_d2",
167 	"mmpll_d7",
168 	"univpll_d6",
169 	"mainpll_d4",
170 	"mmpll_d5",
171 	"tvdpll1",
172 	"tvdpll2",
173 	"univpll_d4",
174 	"mmpll_d4"
175 };
176 
177 static const char * const ethdr_parents[] = {
178 	"clk26m",
179 	"univpll_d6_d2",
180 	"mainpll_d5_d2",
181 	"mmpll_d6_d2",
182 	"univpll_d5_d2",
183 	"univpll_d4_d2",
184 	"mmpll_d4_d2",
185 	"mmpll_d7",
186 	"univpll_d6",
187 	"mainpll_d4",
188 	"mmpll_d5_d4",
189 	"tvdpll1",
190 	"tvdpll2",
191 	"univpll_d4",
192 	"mmpll_d4"
193 };
194 
195 static const char * const ipe_parents[] = {
196 	"clk26m",
197 	"imgpll",
198 	"mainpll_d4",
199 	"mmpll_d6",
200 	"univpll_d6",
201 	"mainpll_d6",
202 	"mmpll_d4_d2",
203 	"univpll_d4_d2",
204 	"mainpll_d4_d2",
205 	"mmpll_d6_d2",
206 	"univpll_d5_d2"
207 };
208 
209 static const char * const cam_parents[] = {
210 	"clk26m",
211 	"mainpll_d4",
212 	"mmpll_d4",
213 	"univpll_d4",
214 	"univpll_d5",
215 	"univpll_d6",
216 	"mmpll_d7",
217 	"univpll_d4_d2",
218 	"mainpll_d4_d2",
219 	"imgpll"
220 };
221 
222 static const char * const ccu_parents[] = {
223 	"clk26m",
224 	"univpll_d6",
225 	"mainpll_d4_d2",
226 	"mainpll_d4",
227 	"univpll_d5",
228 	"mainpll_d6",
229 	"mmpll_d6",
230 	"mmpll_d7",
231 	"univpll_d4_d2",
232 	"univpll_d7"
233 };
234 
235 static const char * const img_parents[] = {
236 	"clk26m",
237 	"imgpll",
238 	"univpll_d4",
239 	"mainpll_d4",
240 	"univpll_d5",
241 	"mmpll_d6",
242 	"univpll_d6",
243 	"mainpll_d6",
244 	"mmpll_d4_d2",
245 	"univpll_d4_d2",
246 	"mainpll_d4_d2",
247 	"univpll_d5_d2"
248 };
249 
250 static const char * const camtm_parents[] = {
251 	"clk26m",
252 	"univpll_d4_d4",
253 	"univpll_d6_d2",
254 	"univpll_d6_d4"
255 };
256 
257 static const char * const dsp_parents[] = {
258 	"clk26m",
259 	"univpll_d6_d2",
260 	"univpll_d4_d2",
261 	"univpll_d5",
262 	"univpll_d4",
263 	"mmpll_d4",
264 	"mainpll_d3",
265 	"univpll_d3"
266 };
267 
268 static const char * const dsp1_parents[] = {
269 	"clk26m",
270 	"univpll_d6_d2",
271 	"mainpll_d4_d2",
272 	"univpll_d5",
273 	"mmpll_d5",
274 	"univpll_d4",
275 	"mainpll_d3",
276 	"univpll_d3"
277 };
278 
279 static const char * const dsp2_parents[] = {
280 	"clk26m",
281 	"univpll_d6_d2",
282 	"univpll_d4_d2",
283 	"mainpll_d4",
284 	"univpll_d4",
285 	"mmpll_d4",
286 	"mainpll_d3",
287 	"univpll_d3"
288 };
289 
290 static const char * const ipu_if_parents[] = {
291 	"clk26m",
292 	"univpll_d6_d2",
293 	"univpll_d5_d2",
294 	"mainpll_d4_d2",
295 	"mainpll_d6",
296 	"univpll_d5",
297 	"univpll_d4",
298 	"mmpll_d4"
299 };
300 
301 /*
302  * MFG can be also parented to "univpll_d6" and "univpll_d7":
303  * these have been removed from the parents list to let us
304  * achieve GPU DVFS without any special clock handlers.
305  */
306 static const char * const mfg_parents[] = {
307 	"clk26m",
308 	"mainpll_d5_d2"
309 };
310 
311 static const char * const camtg_parents[] = {
312 	"clk26m",
313 	"univpll_192m_d8",
314 	"univpll_d6_d8",
315 	"univpll_192m_d4",
316 	"univpll_d6_d16",
317 	"clk26m_d2",
318 	"univpll_192m_d16",
319 	"univpll_192m_d32"
320 };
321 
322 static const char * const uart_parents[] = {
323 	"clk26m",
324 	"univpll_d6_d8"
325 };
326 
327 static const char * const spi_parents[] = {
328 	"clk26m",
329 	"mainpll_d5_d4",
330 	"mainpll_d6_d4",
331 	"msdcpll_d4",
332 	"univpll_d6_d2",
333 	"mainpll_d6_d2",
334 	"mainpll_d4_d4",
335 	"univpll_d5_d4"
336 };
337 
338 static const char * const spis_parents[] = {
339 	"clk26m",
340 	"univpll_d6",
341 	"mainpll_d6",
342 	"univpll_d4_d2",
343 	"univpll_d6_d2",
344 	"univpll_d4_d4",
345 	"univpll_d6_d4",
346 	"mainpll_d7_d4"
347 };
348 
349 static const char * const msdc50_0_h_parents[] = {
350 	"clk26m",
351 	"mainpll_d4_d2",
352 	"mainpll_d6_d2"
353 };
354 
355 static const char * const msdc50_0_parents[] = {
356 	"clk26m",
357 	"msdcpll",
358 	"msdcpll_d2",
359 	"univpll_d4_d4",
360 	"mainpll_d6_d2",
361 	"univpll_d4_d2"
362 };
363 
364 static const char * const msdc30_parents[] = {
365 	"clk26m",
366 	"univpll_d6_d2",
367 	"mainpll_d6_d2",
368 	"mainpll_d7_d2",
369 	"msdcpll_d2"
370 };
371 
372 static const char * const intdir_parents[] = {
373 	"clk26m",
374 	"univpll_d6",
375 	"mainpll_d4",
376 	"univpll_d4"
377 };
378 
379 static const char * const aud_intbus_parents[] = {
380 	"clk26m",
381 	"mainpll_d4_d4",
382 	"mainpll_d7_d4"
383 };
384 
385 static const char * const audio_h_parents[] = {
386 	"clk26m",
387 	"univpll_d7",
388 	"apll1",
389 	"apll2"
390 };
391 
392 static const char * const pwrap_ulposc_parents[] = {
393 	"ulposc1_d10",
394 	"clk26m",
395 	"ulposc1_d4",
396 	"ulposc1_d7",
397 	"ulposc1_d8",
398 	"ulposc1_d16",
399 	"mainpll_d4_d8",
400 	"univpll_d5_d8"
401 };
402 
403 static const char * const atb_parents[] = {
404 	"clk26m",
405 	"mainpll_d4_d2",
406 	"mainpll_d5_d2"
407 };
408 
409 static const char * const pwrmcu_parents[] = {
410 	"clk26m",
411 	"mainpll_d7_d2",
412 	"mainpll_d6_d2",
413 	"mainpll_d5_d2",
414 	"mainpll_d9",
415 	"mainpll_d4_d2"
416 };
417 
418 static const char * const dp_parents[] = {
419 	"clk26m",
420 	"tvdpll1_d2",
421 	"tvdpll2_d2",
422 	"tvdpll1_d4",
423 	"tvdpll2_d4",
424 	"tvdpll1_d8",
425 	"tvdpll2_d8",
426 	"tvdpll1_d16",
427 	"tvdpll2_d16"
428 };
429 
430 static const char * const disp_pwm_parents[] = {
431 	"clk26m",
432 	"univpll_d6_d4",
433 	"ulposc1_d2",
434 	"ulposc1_d4",
435 	"ulposc1_d16"
436 };
437 
438 static const char * const usb_parents[] = {
439 	"clk26m",
440 	"univpll_d5_d4",
441 	"univpll_d6_d4",
442 	"univpll_d5_d2"
443 };
444 
445 static const char * const i2c_parents[] = {
446 	"clk26m",
447 	"mainpll_d4_d8",
448 	"univpll_d5_d4"
449 };
450 
451 static const char * const seninf_parents[] = {
452 	"clk26m",
453 	"univpll_d4_d4",
454 	"univpll_d6_d2",
455 	"univpll_d4_d2",
456 	"univpll_d7",
457 	"univpll_d6",
458 	"mmpll_d6",
459 	"univpll_d5"
460 };
461 
462 static const char * const gcpu_parents[] = {
463 	"clk26m",
464 	"mainpll_d6",
465 	"univpll_d4_d2",
466 	"mmpll_d5_d2",
467 	"univpll_d5_d2"
468 };
469 
470 static const char * const dxcc_parents[] = {
471 	"clk26m",
472 	"mainpll_d4_d2",
473 	"mainpll_d4_d4",
474 	"mainpll_d4_d8"
475 };
476 
477 static const char * const dpmaif_parents[] = {
478 	"clk26m",
479 	"univpll_d4_d4",
480 	"mainpll_d6",
481 	"mainpll_d4_d2",
482 	"univpll_d4_d2"
483 };
484 
485 static const char * const aes_fde_parents[] = {
486 	"clk26m",
487 	"mainpll_d4_d2",
488 	"mainpll_d6",
489 	"mainpll_d4_d4",
490 	"univpll_d4_d2",
491 	"univpll_d6"
492 };
493 
494 static const char * const ufs_parents[] = {
495 	"clk26m",
496 	"mainpll_d4_d4",
497 	"mainpll_d4_d8",
498 	"univpll_d4_d4",
499 	"mainpll_d6_d2",
500 	"univpll_d6_d2",
501 	"msdcpll_d2"
502 };
503 
504 static const char * const ufs_tick1us_parents[] = {
505 	"clk26m_d52",
506 	"clk26m"
507 };
508 
509 static const char * const ufs_mp_sap_parents[] = {
510 	"clk26m",
511 	"msdcpll_d16"
512 };
513 
514 static const char * const venc_parents[] = {
515 	"clk26m",
516 	"mmpll_d4_d2",
517 	"mainpll_d6",
518 	"univpll_d4_d2",
519 	"mainpll_d4_d2",
520 	"univpll_d6",
521 	"mmpll_d6",
522 	"mainpll_d5_d2",
523 	"mainpll_d6_d2",
524 	"mmpll_d9",
525 	"univpll_d4_d4",
526 	"mainpll_d4",
527 	"univpll_d4",
528 	"univpll_d5",
529 	"univpll_d5_d2",
530 	"mainpll_d5"
531 };
532 
533 static const char * const vdec_parents[] = {
534 	"clk26m",
535 	"mainpll_d5_d2",
536 	"mmpll_d6_d2",
537 	"univpll_d4_d2",
538 	"mmpll_d4_d2",
539 	"mainpll_d5",
540 	"mmpll_d6",
541 	"mmpll_d5",
542 	"vdecpll",
543 	"univpll_d4",
544 	"mmpll_d4",
545 	"univpll_d6_d2",
546 	"mmpll_d9",
547 	"univpll_d6",
548 	"univpll_d5",
549 	"mainpll_d4"
550 };
551 
552 static const char * const pwm_parents[] = {
553 	"clk26m",
554 	"univpll_d4_d8"
555 };
556 
557 static const char * const mcupm_parents[] = {
558 	"clk26m",
559 	"mainpll_d6_d2",
560 	"mainpll_d7_d4",
561 };
562 
563 static const char * const spmi_parents[] = {
564 	"clk26m",
565 	"clk26m_d2",
566 	"ulposc1_d8",
567 	"ulposc1_d10",
568 	"ulposc1_d16",
569 	"ulposc1_d7",
570 	"clk32k",
571 	"mainpll_d7_d8",
572 	"mainpll_d6_d8",
573 	"mainpll_d5_d8"
574 };
575 
576 static const char * const dvfsrc_parents[] = {
577 	"clk26m",
578 	"ulposc1_d10",
579 	"univpll_d6_d8",
580 	"msdcpll_d16"
581 };
582 
583 static const char * const tl_parents[] = {
584 	"clk26m",
585 	"univpll_d5_d4",
586 	"mainpll_d4_d4"
587 };
588 
589 static const char * const dsi_occ_parents[] = {
590 	"clk26m",
591 	"mainpll_d6_d2",
592 	"univpll_d5_d2",
593 	"univpll_d4_d2"
594 };
595 
596 static const char * const wpe_vpp_parents[] = {
597 	"clk26m",
598 	"mainpll_d5_d2",
599 	"mmpll_d6_d2",
600 	"univpll_d5_d2",
601 	"mainpll_d4_d2",
602 	"univpll_d4_d2",
603 	"mmpll_d4_d2",
604 	"mainpll_d6",
605 	"mmpll_d7",
606 	"univpll_d6",
607 	"mainpll_d5",
608 	"univpll_d5",
609 	"mainpll_d4",
610 	"tvdpll1",
611 	"univpll_d4"
612 };
613 
614 static const char * const hdcp_parents[] = {
615 	"clk26m",
616 	"univpll_d4_d8",
617 	"mainpll_d5_d8",
618 	"univpll_d6_d4"
619 };
620 
621 static const char * const hdcp_24m_parents[] = {
622 	"clk26m",
623 	"univpll_192m_d4",
624 	"univpll_192m_d8",
625 	"univpll_d6_d8"
626 };
627 
628 static const char * const hd20_dacr_ref_parents[] = {
629 	"clk26m",
630 	"univpll_d4_d2",
631 	"univpll_d4_d4",
632 	"univpll_d4_d8"
633 };
634 
635 static const char * const hd20_hdcp_c_parents[] = {
636 	"clk26m",
637 	"msdcpll_d4",
638 	"univpll_d4_d8",
639 	"univpll_d6_d8"
640 };
641 
642 static const char * const hdmi_xtal_parents[] = {
643 	"clk26m",
644 	"clk26m_d2"
645 };
646 
647 static const char * const hdmi_apb_parents[] = {
648 	"clk26m",
649 	"univpll_d6_d4",
650 	"msdcpll_d2"
651 };
652 
653 static const char * const snps_eth_250m_parents[] = {
654 	"clk26m",
655 	"ethpll_d2"
656 };
657 
658 static const char * const snps_eth_62p4m_ptp_parents[] = {
659 	"apll2_d3",
660 	"apll1_d3",
661 	"clk26m",
662 	"ethpll_d8"
663 };
664 
665 static const char * const snps_eth_50m_rmii_parents[] = {
666 	"clk26m",
667 	"ethpll_d10"
668 };
669 
670 static const char * const dgi_out_parents[] = {
671 	"clk26m",
672 	"dgipll",
673 	"dgipll_d2",
674 	"in_dgi",
675 	"in_dgi_d2",
676 	"mmpll_d4_d4"
677 };
678 
679 static const char * const nna_parents[] = {
680 	"clk26m",
681 	"nnapll",
682 	"univpll_d4",
683 	"mainpll_d4",
684 	"univpll_d5",
685 	"mmpll_d6",
686 	"univpll_d6",
687 	"mainpll_d6",
688 	"mmpll_d4_d2",
689 	"univpll_d4_d2",
690 	"mainpll_d4_d2",
691 	"mmpll_d6_d2"
692 };
693 
694 static const char * const adsp_parents[] = {
695 	"clk26m",
696 	"clk26m_d2",
697 	"mainpll_d6",
698 	"mainpll_d5_d2",
699 	"univpll_d4_d4",
700 	"univpll_d4",
701 	"univpll_d6",
702 	"ulposc1",
703 	"adsppll",
704 	"adsppll_d2",
705 	"adsppll_d4",
706 	"adsppll_d8"
707 };
708 
709 static const char * const asm_parents[] = {
710 	"clk26m",
711 	"univpll_d6_d4",
712 	"univpll_d6_d2",
713 	"mainpll_d5_d2"
714 };
715 
716 static const char * const apll1_parents[] = {
717 	"clk26m",
718 	"apll1_d4"
719 };
720 
721 static const char * const apll2_parents[] = {
722 	"clk26m",
723 	"apll2_d4"
724 };
725 
726 static const char * const apll3_parents[] = {
727 	"clk26m",
728 	"apll3_d4"
729 };
730 
731 static const char * const apll4_parents[] = {
732 	"clk26m",
733 	"apll4_d4"
734 };
735 
736 static const char * const apll5_parents[] = {
737 	"clk26m",
738 	"apll5_d4"
739 };
740 
741 static const char * const i2s_parents[] = {
742 	"clk26m",
743 	"apll1",
744 	"apll2",
745 	"apll3",
746 	"apll4",
747 	"apll5",
748 	"hdmirx_apll"
749 };
750 
751 static const char * const a1sys_hp_parents[] = {
752 	"clk26m",
753 	"apll1_d4"
754 };
755 
756 static const char * const a2sys_parents[] = {
757 	"clk26m",
758 	"apll2_d4"
759 };
760 
761 static const char * const a3sys_parents[] = {
762 	"clk26m",
763 	"apll3_d4",
764 	"apll4_d4",
765 	"apll5_d4",
766 	"hdmirx_apll_d3",
767 	"hdmirx_apll_d4",
768 	"hdmirx_apll_d6"
769 };
770 
771 static const char * const spinfi_b_parents[] = {
772 	"clk26m",
773 	"univpll_d6_d8",
774 	"univpll_d5_d8",
775 	"mainpll_d4_d8",
776 	"mainpll_d7_d4",
777 	"mainpll_d6_d4",
778 	"univpll_d6_d4",
779 	"univpll_d5_d4"
780 };
781 
782 static const char * const nfi1x_parents[] = {
783 	"clk26m",
784 	"univpll_d5_d4",
785 	"mainpll_d7_d4",
786 	"mainpll_d6_d4",
787 	"univpll_d6_d4",
788 	"mainpll_d4_d4",
789 	"mainpll_d7_d2",
790 	"mainpll_d6_d2"
791 };
792 
793 static const char * const ecc_parents[] = {
794 	"clk26m",
795 	"mainpll_d4_d4",
796 	"mainpll_d5_d2",
797 	"mainpll_d4_d2",
798 	"mainpll_d6",
799 	"univpll_d6"
800 };
801 
802 static const char * const audio_local_bus_parents[] = {
803 	"clk26m",
804 	"clk26m_d2",
805 	"mainpll_d4_d4",
806 	"mainpll_d7_d2",
807 	"mainpll_d4_d2",
808 	"mainpll_d5_d2",
809 	"mainpll_d6_d2",
810 	"mainpll_d7",
811 	"univpll_d6",
812 	"ulposc1",
813 	"ulposc1_d4",
814 	"ulposc1_d2"
815 };
816 
817 static const char * const spinor_parents[] = {
818 	"clk26m",
819 	"clk26m_d2",
820 	"mainpll_d7_d8",
821 	"univpll_d6_d8"
822 };
823 
824 static const char * const dvio_dgi_ref_parents[] = {
825 	"clk26m",
826 	"in_dgi",
827 	"in_dgi_d2",
828 	"in_dgi_d4",
829 	"in_dgi_d6",
830 	"in_dgi_d8",
831 	"mmpll_d4_d4"
832 };
833 
834 static const char * const ulposc_parents[] = {
835 	"ulposc1",
836 	"ethpll_d2",
837 	"mainpll_d4_d2",
838 	"ethpll_d10"
839 };
840 
841 static const char * const ulposc_core_parents[] = {
842 	"ulposc2",
843 	"univpll_d7",
844 	"mainpll_d6",
845 	"ethpll_d10"
846 };
847 
848 static const char * const srck_parents[] = {
849 	"ulposc1_d10",
850 	"clk26m"
851 };
852 
853 static const char * const mfg_fast_parents[] = {
854 	"top_mfg_core_tmp",
855 	"mfgpll"
856 };
857 
858 static const struct mtk_mux top_mtk_muxes[] = {
859 	/*
860 	 * CLK_CFG_0
861 	 * top_axi and top_bus_aximem are bus clocks, should not be closed by Linux.
862 	 * top_spm and top_scp are main clocks in always-on co-processor.
863 	 */
864 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi",
865 		axi_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x04, 0,
866 		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
867 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm",
868 		spm_parents, 0x020, 0x024, 0x028, 8, 2, 15, 0x04, 1,
869 		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
870 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp",
871 		scp_parents, 0x020, 0x024, 0x028, 16, 3, 23, 0x04, 2,
872 		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
873 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM, "top_bus_aximem",
874 		bus_aximem_parents, 0x020, 0x024, 0x028, 24, 3, 31, 0x04, 3,
875 		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
876 	/* CLK_CFG_1 */
877 	MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
878 		vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4),
879 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr",
880 		ethdr_parents, 0x02C, 0x030, 0x034, 8, 4, 15, 0x04, 5),
881 	MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
882 		ipe_parents, 0x02C, 0x030, 0x034, 16, 4, 23, 0x04, 6),
883 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
884 		cam_parents, 0x02C, 0x030, 0x034, 24, 4, 31, 0x04, 7),
885 	/* CLK_CFG_2 */
886 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
887 		ccu_parents, 0x038, 0x03C, 0x040, 0, 4, 7, 0x04, 8),
888 	MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
889 		img_parents, 0x038, 0x03C, 0x040, 8, 4, 15, 0x04, 9),
890 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
891 		camtm_parents, 0x038, 0x03C, 0x040, 16, 2, 23, 0x04, 10),
892 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
893 		dsp_parents, 0x038, 0x03C, 0x040, 24, 3, 31, 0x04, 11),
894 	/* CLK_CFG_3 */
895 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "top_dsp1",
896 		dsp1_parents, 0x044, 0x048, 0x04C, 0, 3, 7, 0x04, 12),
897 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "top_dsp2",
898 		dsp1_parents, 0x044, 0x048, 0x04C, 8, 3, 15, 0x04, 13),
899 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "top_dsp3",
900 		dsp1_parents, 0x044, 0x048, 0x04C, 16, 3, 23, 0x04, 14),
901 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4, "top_dsp4",
902 		dsp2_parents, 0x044, 0x048, 0x04C, 24, 3, 31, 0x04, 15),
903 	/* CLK_CFG_4 */
904 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5, "top_dsp5",
905 		dsp2_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x04, 16),
906 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6, "top_dsp6",
907 		dsp2_parents, 0x050, 0x054, 0x058, 8, 3, 15, 0x04, 17),
908 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7, "top_dsp7",
909 		dsp_parents, 0x050, 0x054, 0x058, 16, 3, 23, 0x04, 18),
910 	MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "top_ipu_if",
911 		ipu_if_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x04, 19),
912 	/* CLK_CFG_5 */
913 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_CORE_TMP, "top_mfg_core_tmp",
914 		mfg_parents, 0x05C, 0x060, 0x064, 0, 2, 7, 0x04, 20),
915 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
916 		camtg_parents, 0x05C, 0x060, 0x064, 8, 3, 15, 0x04, 21),
917 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
918 		camtg_parents, 0x05C, 0x060, 0x064, 16, 3, 23, 0x04, 22),
919 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
920 		camtg_parents, 0x05C, 0x060, 0x064, 24, 3, 31, 0x04, 23),
921 	/* CLK_CFG_6 */
922 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "top_camtg4",
923 		camtg_parents, 0x068, 0x06C, 0x070, 0, 3, 7, 0x04, 24),
924 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "top_camtg5",
925 		camtg_parents, 0x068, 0x06C, 0x070, 8, 3, 15, 0x04, 25),
926 	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
927 		uart_parents, 0x068, 0x06C, 0x070, 16, 1, 23, 0x04, 26),
928 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
929 		spi_parents, 0x068, 0x06C, 0x070, 24, 3, 31, 0x04, 27),
930 	/* CLK_CFG_7 */
931 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIS, "top_spis",
932 		spis_parents, 0x074, 0x078, 0x07C, 0, 3, 7, 0x04, 28),
933 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HCLK, "top_msdc50_0_hclk",
934 		msdc50_0_h_parents, 0x074, 0x078, 0x07C, 8, 2, 15, 0x04, 29, 0),
935 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0, "top_msdc50_0",
936 		msdc50_0_parents, 0x074, 0x078, 0x07C, 16, 3, 23, 0x04, 30, 0),
937 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1, "top_msdc30_1",
938 		msdc30_parents, 0x074, 0x078, 0x07C, 24, 3, 31, 0x04, 31, 0),
939 	/* CLK_CFG_8 */
940 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2, "top_msdc30_2",
941 		msdc30_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x08, 0, 0),
942 	MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
943 		intdir_parents, 0x080, 0x084, 0x088, 8, 2, 15, 0x08, 1),
944 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
945 		aud_intbus_parents, 0x080, 0x084, 0x088, 16, 2, 23, 0x08, 2),
946 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
947 		audio_h_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x08, 3),
948 	/*
949 	 * CLK_CFG_9
950 	 * top_pwrmcu is main clock in other co-processor, should not be
951 	 * handled by Linux.
952 	 */
953 	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
954 		pwrap_ulposc_parents, 0x08C, 0x090, 0x094, 0, 3, 7, 0x08, 4),
955 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb",
956 		atb_parents, 0x08C, 0x090, 0x094, 8, 2, 15, 0x08, 5),
957 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRMCU, "top_pwrmcu",
958 		pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6,
959 		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
960 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp",
961 		dp_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),
962 	/* CLK_CFG_10 */
963 	MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp",
964 		dp_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8),
965 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
966 		dp_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9),
967 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",
968 		disp_pwm_parents, 0x098, 0x09C, 0x0A0, 16, 3, 23, 0x08, 10),
969 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM1, "top_disp_pwm1",
970 		disp_pwm_parents, 0x098, 0x09C, 0x0A0, 24, 3, 31, 0x08, 11),
971 	/* CLK_CFG_11 */
972 	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb_top",
973 		usb_parents, 0x0A4, 0x0A8, 0x0AC, 0, 2, 7, 0x08, 12),
974 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
975 		usb_parents, 0x0A4, 0x0A8, 0x0AC, 8, 2, 15, 0x08, 13),
976 	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_1P, "top_usb_top_1p",
977 		usb_parents, 0x0A4, 0x0A8, 0x0AC, 16, 2, 23, 0x08, 14),
978 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_1P, "top_ssusb_xhci_1p",
979 		usb_parents, 0x0A4, 0x0A8, 0x0AC, 24, 2, 31, 0x08, 15),
980 	/* CLK_CFG_12 */
981 	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_2P, "top_usb_top_2p",
982 		usb_parents, 0x0B0, 0x0B4, 0x0B8, 0, 2, 7, 0x08, 16),
983 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P, "top_ssusb_xhci_2p",
984 		usb_parents, 0x0B0, 0x0B4, 0x0B8, 8, 2, 15, 0x08, 17),
985 	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_3P, "top_usb_top_3p",
986 		usb_parents, 0x0B0, 0x0B4, 0x0B8, 16, 2, 23, 0x08, 18),
987 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P, "top_ssusb_xhci_3p",
988 		usb_parents, 0x0B0, 0x0B4, 0x0B8, 24, 2, 31, 0x08, 19),
989 	/* CLK_CFG_13 */
990 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
991 		i2c_parents, 0x0BC, 0x0C0, 0x0C4, 0, 2, 7, 0x08, 20),
992 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
993 		seninf_parents, 0x0BC, 0x0C0, 0x0C4, 8, 3, 15, 0x08, 21),
994 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
995 		seninf_parents, 0x0BC, 0x0C0, 0x0C4, 16, 3, 23, 0x08, 22),
996 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "top_seninf2",
997 		seninf_parents, 0x0BC, 0x0C0, 0x0C4, 24, 3, 31, 0x08, 23),
998 	/* CLK_CFG_14 */
999 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3, "top_seninf3",
1000 		seninf_parents, 0x0C8, 0x0CC, 0x0D0, 0, 3, 7, 0x08, 24),
1001 	MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU, "top_gcpu",
1002 		gcpu_parents, 0x0C8, 0x0CC, 0x0D0, 8, 3, 15, 0x08, 25),
1003 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "top_dxcc",
1004 		dxcc_parents, 0x0C8, 0x0CC, 0x0D0, 16, 2, 23, 0x08, 26),
1005 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN, "top_dpmaif_main",
1006 		dpmaif_parents, 0x0C8, 0x0CC, 0x0D0, 24, 3, 31, 0x08, 27),
1007 	/* CLK_CFG_15 */
1008 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE, "top_aes_ufsfde",
1009 		aes_fde_parents, 0x0D4, 0x0D8, 0x0DC, 0, 3, 7, 0x08, 28),
1010 	MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS, "top_ufs",
1011 		ufs_parents, 0x0D4, 0x0D8, 0x0DC, 8, 3, 15, 0x08, 29),
1012 	MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_TICK1US, "top_ufs_tick1us",
1013 		ufs_tick1us_parents, 0x0D4, 0x0D8, 0x0DC, 16, 1, 23, 0x08, 30),
1014 	MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_MP_SAP_CFG, "top_ufs_mp_sap_cfg",
1015 		ufs_mp_sap_parents, 0x0D4, 0x0D8, 0x0DC, 24, 1, 31, 0x08, 31),
1016 	/*
1017 	 * CLK_CFG_16
1018 	 * top_mcupm is main clock in other co-processor, should not be
1019 	 * handled by Linux.
1020 	 */
1021 	MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
1022 		venc_parents, 0x0E0, 0x0E4, 0x0E8, 0, 4, 7, 0x0C, 0),
1023 	MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
1024 		vdec_parents, 0x0E0, 0x0E4, 0x0E8, 8, 4, 15, 0x0C, 1),
1025 	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
1026 		pwm_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1, 23, 0x0C, 2),
1027 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm",
1028 		mcupm_parents, 0x0E0, 0x0E4, 0x0E8, 24, 2, 31, 0x0C, 3,
1029 		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1030 	/*
1031 	 * CLK_CFG_17
1032 	 * top_dvfsrc is for internal DVFS usage, should not be handled by Linux.
1033 	 */
1034 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST, "top_spmi_p_mst",
1035 		spmi_parents, 0x0EC, 0x0F0, 0x0F4, 0, 4, 7, 0x0C, 4),
1036 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst",
1037 		spmi_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4, 15, 0x0C, 5),
1038 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc",
1039 		dvfsrc_parents, 0x0EC, 0x0F0, 0x0F4, 16, 2, 23, 0x0C, 6,
1040 		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1041 	MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl",
1042 		tl_parents, 0x0EC, 0x0F0, 0x0F4, 24, 2, 31, 0x0C, 7),
1043 	/* CLK_CFG_18 */
1044 	MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_P1, "top_tl_p1",
1045 		tl_parents, 0x0F8, 0x0FC, 0x0100, 0, 2, 7, 0x0C, 8),
1046 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
1047 		aes_fde_parents, 0x0F8, 0x0FC, 0x0100, 8, 3, 15, 0x0C, 9),
1048 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
1049 		dsi_occ_parents, 0x0F8, 0x0FC, 0x0100, 16, 2, 23, 0x0C, 10),
1050 	MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE_VPP, "top_wpe_vpp",
1051 		wpe_vpp_parents, 0x0F8, 0x0FC, 0x0100, 24, 4, 31, 0x0C, 11),
1052 	/* CLK_CFG_19 */
1053 	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP, "top_hdcp",
1054 		hdcp_parents, 0x0104, 0x0108, 0x010C, 0, 2, 7, 0x0C, 12),
1055 	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_24M, "top_hdcp_24m",
1056 		hdcp_24m_parents, 0x0104, 0x0108, 0x010C, 8, 2, 15, 0x0C, 13),
1057 	MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_DACR_REF_CLK, "top_hd20_dacr_ref_clk",
1058 		hd20_dacr_ref_parents, 0x0104, 0x0108, 0x010C, 16, 2, 23, 0x0C, 14),
1059 	MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_HDCP_CCLK, "top_hd20_hdcp_cclk",
1060 		hd20_hdcp_c_parents, 0x0104, 0x0108, 0x010C, 24, 2, 31, 0x0C, 15),
1061 	/* CLK_CFG_20 */
1062 	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_XTAL, "top_hdmi_xtal",
1063 		hdmi_xtal_parents, 0x0110, 0x0114, 0x0118, 0, 1, 7, 0x0C, 16),
1064 	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_APB, "top_hdmi_apb",
1065 		hdmi_apb_parents, 0x0110, 0x0114, 0x0118, 8, 2, 15, 0x0C, 17),
1066 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M, "top_snps_eth_250m",
1067 		snps_eth_250m_parents, 0x0110, 0x0114, 0x0118, 16, 1, 23, 0x0C, 18),
1068 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP, "top_snps_eth_62p4m_ptp",
1069 		snps_eth_62p4m_ptp_parents, 0x0110, 0x0114, 0x0118, 24, 2, 31, 0x0C, 19),
1070 	/* CLK_CFG_21 */
1071 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii",
1072 		snps_eth_50m_rmii_parents, 0x011C, 0x0120, 0x0124, 0, 1, 7, 0x0C, 20),
1073 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DGI_OUT, "top_dgi_out",
1074 		dgi_out_parents, 0x011C, 0x0120, 0x0124, 8, 3, 15, 0x0C, 21),
1075 	MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA0, "top_nna0",
1076 		nna_parents, 0x011C, 0x0120, 0x0124, 16, 4, 23, 0x0C, 22),
1077 	MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA1, "top_nna1",
1078 		nna_parents, 0x011C, 0x0120, 0x0124, 24, 4, 31, 0x0C, 23),
1079 	/* CLK_CFG_22 */
1080 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "top_adsp",
1081 		adsp_parents, 0x0128, 0x012C, 0x0130, 0, 4, 7, 0x0C, 24),
1082 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H, "top_asm_h",
1083 		asm_parents, 0x0128, 0x012C, 0x0130, 8, 2, 15, 0x0C, 25),
1084 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_M, "top_asm_m",
1085 		asm_parents, 0x0128, 0x012C, 0x0130, 16, 2, 23, 0x0C, 26),
1086 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_L, "top_asm_l",
1087 		asm_parents, 0x0128, 0x012C, 0x0130, 24, 2, 31, 0x0C, 27),
1088 	/* CLK_CFG_23 */
1089 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1",
1090 		apll1_parents, 0x0134, 0x0138, 0x013C, 0, 1, 7, 0x0C, 28),
1091 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
1092 		apll2_parents, 0x0134, 0x0138, 0x013C, 8, 1, 15, 0x0C, 29),
1093 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL3, "top_apll3",
1094 		apll3_parents, 0x0134, 0x0138, 0x013C, 16, 1, 23, 0x0C, 30),
1095 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL4, "top_apll4",
1096 		apll4_parents, 0x0134, 0x0138, 0x013C, 24, 1, 31, 0x0C, 31),
1097 	/*
1098 	 * CLK_CFG_24
1099 	 * i2so4_mck is not used in MT8195.
1100 	 */
1101 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5, "top_apll5",
1102 		apll5_parents, 0x0140, 0x0144, 0x0148, 0, 1, 7, 0x010, 0),
1103 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1_MCK, "top_i2so1_mck",
1104 		i2s_parents, 0x0140, 0x0144, 0x0148, 8, 3, 15, 0x010, 1),
1105 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2_MCK, "top_i2so2_mck",
1106 		i2s_parents, 0x0140, 0x0144, 0x0148, 16, 3, 23, 0x010, 2),
1107 	/*
1108 	 * CLK_CFG_25
1109 	 * i2so5_mck and i2si4_mck are not used in MT8195.
1110 	 */
1111 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1_MCK, "top_i2si1_mck",
1112 		i2s_parents, 0x014C, 0x0150, 0x0154, 8, 3, 15, 0x010, 5),
1113 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2_MCK, "top_i2si2_mck",
1114 		i2s_parents, 0x014C, 0x0150, 0x0154, 16, 3, 23, 0x010, 6),
1115 	/*
1116 	 * CLK_CFG_26
1117 	 * i2si5_mck is not used in MT8195.
1118 	 */
1119 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX_MCK, "top_dptx_mck",
1120 		i2s_parents, 0x0158, 0x015C, 0x0160, 8, 3, 15, 0x010, 9),
1121 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC_CLK, "top_aud_iec_clk",
1122 		i2s_parents, 0x0158, 0x015C, 0x0160, 16, 3, 23, 0x010, 10),
1123 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP, "top_a1sys_hp",
1124 		a1sys_hp_parents, 0x0158, 0x015C, 0x0160, 24, 1, 31, 0x010, 11),
1125 	/* CLK_CFG_27 */
1126 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS_HF, "top_a2sys_hf",
1127 		a2sys_parents, 0x0164, 0x0168, 0x016C, 0, 1, 7, 0x010, 12),
1128 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS_HF, "top_a3sys_hf",
1129 		a3sys_parents, 0x0164, 0x0168, 0x016C, 8, 3, 15, 0x010, 13),
1130 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS_HF, "top_a4sys_hf",
1131 		a3sys_parents, 0x0164, 0x0168, 0x016C, 16, 3, 23, 0x010, 14),
1132 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_BCLK, "top_spinfi_bclk",
1133 		spinfi_b_parents, 0x0164, 0x0168, 0x016C, 24, 3, 31, 0x010, 15),
1134 	/* CLK_CFG_28 */
1135 	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X, "top_nfi1x",
1136 		nfi1x_parents, 0x0170, 0x0174, 0x0178, 0, 3, 7, 0x010, 16),
1137 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC, "top_ecc",
1138 		ecc_parents, 0x0170, 0x0174, 0x0178, 8, 3, 15, 0x010, 17),
1139 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS, "top_audio_local_bus",
1140 		audio_local_bus_parents, 0x0170, 0x0174, 0x0178, 16, 4, 23, 0x010, 18),
1141 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
1142 		spinor_parents, 0x0170, 0x0174, 0x0178, 24, 2, 31, 0x010, 19),
1143 	/*
1144 	 * CLK_CFG_29
1145 	 * top_ulposc/top_ulposc_core/top_srck are clock source of always on co-processor,
1146 	 * should not be closed by Linux.
1147 	 */
1148 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DVIO_DGI_REF, "top_dvio_dgi_ref",
1149 		dvio_dgi_ref_parents, 0x017C, 0x0180, 0x0184, 0, 3, 7, 0x010, 20),
1150 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc",
1151 		ulposc_parents, 0x017C, 0x0180, 0x0184, 8, 2, 15, 0x010, 21,
1152 		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1153 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC_CORE, "top_ulposc_core",
1154 		ulposc_core_parents, 0x017C, 0x0180, 0x0184, 16, 2, 23, 0x010, 22,
1155 		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1156 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck",
1157 		srck_parents, 0x017C, 0x0180, 0x0184, 24, 1, 31, 0x010, 23,
1158 		CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
1159 	/*
1160 	 * the clocks in CLK_CFG_30 ~ 37 are backup clock source, no need to handled
1161 	 * by Linux.
1162 	 */
1163 };
1164 
1165 static const struct mtk_composite top_adj_divs[] = {
1166 	DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "top_i2si1_mck", 0x0320, 0, 0x0328, 8, 0),
1167 	DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "top_i2si2_mck", 0x0320, 1, 0x0328, 8, 8),
1168 	DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "top_i2so1_mck", 0x0320, 2, 0x0328, 8, 16),
1169 	DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "top_i2so2_mck", 0x0320, 3, 0x0328, 8, 24),
1170 	DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "top_aud_iec_clk", 0x0320, 4, 0x0334, 8, 0),
1171 	/* apll12_div5 ~ 8 are not used in MT8195. */
1172 	DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "top_dptx_mck", 0x0320, 9, 0x0338, 8, 8),
1173 };
1174 
1175 static const struct mtk_gate_regs top0_cg_regs = {
1176 	.set_ofs = 0x238,
1177 	.clr_ofs = 0x238,
1178 	.sta_ofs = 0x238,
1179 };
1180 
1181 static const struct mtk_gate_regs top1_cg_regs = {
1182 	.set_ofs = 0x250,
1183 	.clr_ofs = 0x250,
1184 	.sta_ofs = 0x250,
1185 };
1186 
1187 #define GATE_TOP0_FLAGS(_id, _name, _parent, _shift, _flag)		\
1188 	GATE_MTK_FLAGS(_id, _name, _parent, &top0_cg_regs, _shift,	\
1189 		&mtk_clk_gate_ops_no_setclr_inv, _flag)
1190 
1191 #define GATE_TOP0(_id, _name, _parent, _shift)			\
1192 	GATE_TOP0_FLAGS(_id, _name, _parent, _shift, 0)
1193 
1194 #define GATE_TOP1(_id, _name, _parent, _shift)			\
1195 	GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
1196 
1197 static const struct mtk_gate top_clks[] = {
1198 	/* TOP0 */
1199 	GATE_TOP0(CLK_TOP_CFG_VPP0, "cfg_vpp0", "top_vpp", 0),
1200 	GATE_TOP0(CLK_TOP_CFG_VPP1, "cfg_vpp1", "top_vpp", 1),
1201 	GATE_TOP0(CLK_TOP_CFG_VDO0, "cfg_vdo0", "top_vpp", 2),
1202 	GATE_TOP0(CLK_TOP_CFG_VDO1, "cfg_vdo1", "top_vpp", 3),
1203 	GATE_TOP0(CLK_TOP_CFG_UNIPLL_SES, "cfg_unipll_ses", "univpll_d2", 4),
1204 	GATE_TOP0(CLK_TOP_CFG_26M_VPP0, "cfg_26m_vpp0", "clk26m", 5),
1205 	GATE_TOP0(CLK_TOP_CFG_26M_VPP1, "cfg_26m_vpp1", "clk26m", 6),
1206 	GATE_TOP0(CLK_TOP_CFG_26M_AUD, "cfg_26m_aud", "clk26m", 9),
1207 	/*
1208 	 * cfg_axi_east, cfg_axi_east_north, cfg_axi_north and cfg_axi_south
1209 	 * are peripheral bus clock branches.
1210 	 */
1211 	GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST, "cfg_axi_east", "top_axi", 10, CLK_IS_CRITICAL),
1212 	GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST_NORTH, "cfg_axi_east_north", "top_axi", 11,
1213 		CLK_IS_CRITICAL),
1214 	GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_NORTH, "cfg_axi_north", "top_axi", 12, CLK_IS_CRITICAL),
1215 	GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_SOUTH, "cfg_axi_south", "top_axi", 13, CLK_IS_CRITICAL),
1216 	GATE_TOP0(CLK_TOP_CFG_EXT_TEST, "cfg_ext_test", "msdcpll_d2", 15),
1217 	/* TOP1 */
1218 	GATE_TOP1(CLK_TOP_SSUSB_REF, "ssusb_ref", "clk26m", 0),
1219 	GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 1),
1220 	GATE_TOP1(CLK_TOP_SSUSB_P1_REF, "ssusb_p1_ref", "clk26m", 2),
1221 	GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, "ssusb_phy_p1_ref", "clk26m", 3),
1222 	GATE_TOP1(CLK_TOP_SSUSB_P2_REF, "ssusb_p2_ref", "clk26m", 4),
1223 	GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, "ssusb_phy_p2_ref", "clk26m", 5),
1224 	GATE_TOP1(CLK_TOP_SSUSB_P3_REF, "ssusb_p3_ref", "clk26m", 6),
1225 	GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, "ssusb_phy_p3_ref", "clk26m", 7),
1226 };
1227 
1228 static const struct of_device_id of_match_clk_mt8195_topck[] = {
1229 	{ .compatible = "mediatek,mt8195-topckgen", },
1230 	{}
1231 };
1232 MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_topck);
1233 
1234 /* Register mux notifier for MFG mux */
1235 static int clk_mt8195_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
1236 {
1237 	struct mtk_mux_nb *mfg_mux_nb;
1238 
1239 	mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
1240 	if (!mfg_mux_nb)
1241 		return -ENOMEM;
1242 
1243 	mfg_mux_nb->ops = &clk_mux_ops;
1244 	mfg_mux_nb->bypass_index = 0; /* Bypass to TOP_MFG_CORE_TMP */
1245 
1246 	return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
1247 }
1248 
1249 static int clk_mt8195_topck_probe(struct platform_device *pdev)
1250 {
1251 	struct clk_hw_onecell_data *top_clk_data;
1252 	struct device_node *node = pdev->dev.of_node;
1253 	struct clk_hw *hw;
1254 	int r;
1255 	void __iomem *base;
1256 
1257 	top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1258 	if (!top_clk_data)
1259 		return -ENOMEM;
1260 
1261 	base = devm_platform_ioremap_resource(pdev, 0);
1262 	if (IS_ERR(base)) {
1263 		r = PTR_ERR(base);
1264 		goto free_top_data;
1265 	}
1266 
1267 	r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1268 					top_clk_data);
1269 	if (r)
1270 		goto free_top_data;
1271 
1272 	r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1273 	if (r)
1274 		goto unregister_fixed_clks;
1275 
1276 	r = mtk_clk_register_muxes(&pdev->dev, top_mtk_muxes,
1277 				   ARRAY_SIZE(top_mtk_muxes), node,
1278 				   &mt8195_clk_lock, top_clk_data);
1279 	if (r)
1280 		goto unregister_factors;
1281 
1282 	hw = devm_clk_hw_register_mux(&pdev->dev, "mfg_ck_fast_ref", mfg_fast_parents,
1283 				      ARRAY_SIZE(mfg_fast_parents), CLK_SET_RATE_PARENT,
1284 				      (base + 0x250), 8, 1, 0, &mt8195_clk_lock);
1285 	if (IS_ERR(hw)) {
1286 		r = PTR_ERR(hw);
1287 		goto unregister_muxes;
1288 	}
1289 	top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF] = hw;
1290 
1291 	r = clk_mt8195_reg_mfg_mux_notifier(&pdev->dev,
1292 					    top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF]->clk);
1293 	if (r)
1294 		goto unregister_muxes;
1295 
1296 	r = mtk_clk_register_composites(&pdev->dev, top_adj_divs,
1297 					ARRAY_SIZE(top_adj_divs), base,
1298 					&mt8195_clk_lock, top_clk_data);
1299 	if (r)
1300 		goto unregister_muxes;
1301 
1302 	r = mtk_clk_register_gates(&pdev->dev, node, top_clks,
1303 				   ARRAY_SIZE(top_clks), top_clk_data);
1304 	if (r)
1305 		goto unregister_composite_divs;
1306 
1307 	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
1308 	if (r)
1309 		goto unregister_gates;
1310 
1311 	platform_set_drvdata(pdev, top_clk_data);
1312 
1313 	return r;
1314 
1315 unregister_gates:
1316 	mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
1317 unregister_composite_divs:
1318 	mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
1319 unregister_muxes:
1320 	mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
1321 unregister_factors:
1322 	mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1323 unregister_fixed_clks:
1324 	mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
1325 free_top_data:
1326 	mtk_free_clk_data(top_clk_data);
1327 	return r;
1328 }
1329 
1330 static void clk_mt8195_topck_remove(struct platform_device *pdev)
1331 {
1332 	struct clk_hw_onecell_data *top_clk_data = platform_get_drvdata(pdev);
1333 	struct device_node *node = pdev->dev.of_node;
1334 
1335 	of_clk_del_provider(node);
1336 	mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
1337 	mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
1338 	mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
1339 	mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1340 	mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
1341 	mtk_free_clk_data(top_clk_data);
1342 }
1343 
1344 static struct platform_driver clk_mt8195_topck_drv = {
1345 	.probe = clk_mt8195_topck_probe,
1346 	.remove_new = clk_mt8195_topck_remove,
1347 	.driver = {
1348 		.name = "clk-mt8195-topck",
1349 		.of_match_table = of_match_clk_mt8195_topck,
1350 	},
1351 };
1352 module_platform_driver(clk_mt8195_topck_drv);
1353 MODULE_LICENSE("GPL");
1354