1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Copyright (c) 2021 MediaTek Inc.
4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
5 
6 #include "clk-gate.h"
7 #include "clk-mtk.h"
8 #include "clk-mux.h"
9 
10 #include <dt-bindings/clock/mt8195-clk.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 
14 static DEFINE_SPINLOCK(mt8195_clk_lock);
15 
16 static const struct mtk_fixed_clk top_fixed_clks[] = {
17 	FIXED_CLK(CLK_TOP_IN_DGI, "in_dgi", NULL, 165000000),
18 	FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc1", NULL, 248000000),
19 	FIXED_CLK(CLK_TOP_ULPOSC2, "ulposc2", NULL, 326000000),
20 	FIXED_CLK(CLK_TOP_MEM_466M, "mem_466m", NULL, 533000000),
21 	FIXED_CLK(CLK_TOP_MPHONE_SLAVE_B, "mphone_slave_b", NULL, 49152000),
22 	FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL, 250000000),
23 	FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL, "ufs_rx_symbol", NULL, 166000000),
24 	FIXED_CLK(CLK_TOP_UFS_TX_SYMBOL, "ufs_tx_symbol", NULL, 166000000),
25 	FIXED_CLK(CLK_TOP_SSUSB_U3PHY_P1_P_P0, "ssusb_u3phy_p1_p_p0", NULL, 131000000),
26 	FIXED_CLK(CLK_TOP_UFS_RX_SYMBOL1, "ufs_rx_symbol1", NULL, 166000000),
27 	FIXED_CLK(CLK_TOP_FPC, "fpc", NULL, 50000000),
28 	FIXED_CLK(CLK_TOP_HDMIRX_P, "hdmirx_p", NULL, 594000000),
29 };
30 
31 static const struct mtk_fixed_factor top_divs[] = {
32 	FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
33 	FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1, 52),
34 	FACTOR(CLK_TOP_IN_DGI_D2, "in_dgi_d2", "in_dgi", 1, 2),
35 	FACTOR(CLK_TOP_IN_DGI_D4, "in_dgi_d4", "in_dgi", 1, 4),
36 	FACTOR(CLK_TOP_IN_DGI_D6, "in_dgi_d6", "in_dgi", 1, 6),
37 	FACTOR(CLK_TOP_IN_DGI_D8, "in_dgi_d8", "in_dgi", 1, 8),
38 	FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
39 	FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
40 	FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2),
41 	FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4),
42 	FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8),
43 	FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
44 	FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
45 	FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
46 	FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8),
47 	FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
48 	FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2),
49 	FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4),
50 	FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8),
51 	FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
52 	FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
53 	FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
54 	FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8),
55 	FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9),
56 	FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
57 	FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
58 	FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
59 	FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2),
60 	FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4),
61 	FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8),
62 	FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
63 	FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
64 	FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
65 	FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
66 	FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
67 	FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2),
68 	FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4),
69 	FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8),
70 	FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16),
71 	FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
72 	FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
73 	FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
74 	FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
75 	FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
76 	FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
77 	FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3),
78 	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
79 	FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3),
80 	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
81 	FACTOR(CLK_TOP_APLL3_D4, "apll3_d4", "apll3", 1, 4),
82 	FACTOR(CLK_TOP_APLL4_D4, "apll4_d4", "apll4", 1, 4),
83 	FACTOR(CLK_TOP_APLL5_D4, "apll5_d4", "apll5", 1, 4),
84 	FACTOR(CLK_TOP_HDMIRX_APLL_D3, "hdmirx_apll_d3", "hdmirx_apll", 1, 3),
85 	FACTOR(CLK_TOP_HDMIRX_APLL_D4, "hdmirx_apll_d4", "hdmirx_apll", 1, 4),
86 	FACTOR(CLK_TOP_HDMIRX_APLL_D6, "hdmirx_apll_d6", "hdmirx_apll", 1, 6),
87 	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
88 	FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
89 	FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
90 	FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
91 	FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
92 	FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
93 	FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
94 	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
95 	FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
96 	FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9),
97 	FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2),
98 	FACTOR(CLK_TOP_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4),
99 	FACTOR(CLK_TOP_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8),
100 	FACTOR(CLK_TOP_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 1, 16),
101 	FACTOR(CLK_TOP_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2),
102 	FACTOR(CLK_TOP_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4),
103 	FACTOR(CLK_TOP_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8),
104 	FACTOR(CLK_TOP_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 1, 16),
105 	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
106 	FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
107 	FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
108 	FACTOR(CLK_TOP_ETHPLL_D2, "ethpll_d2", "ethpll", 1, 2),
109 	FACTOR(CLK_TOP_ETHPLL_D8, "ethpll_d8", "ethpll", 1, 8),
110 	FACTOR(CLK_TOP_ETHPLL_D10, "ethpll_d10", "ethpll", 1, 10),
111 	FACTOR(CLK_TOP_DGIPLL_D2, "dgipll_d2", "dgipll", 1, 2),
112 	FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1", 1, 2),
113 	FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1", 1, 4),
114 	FACTOR(CLK_TOP_ULPOSC1_D7, "ulposc1_d7", "ulposc1", 1, 7),
115 	FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1", 1, 8),
116 	FACTOR(CLK_TOP_ULPOSC1_D10, "ulposc1_d10", "ulposc1", 1, 10),
117 	FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1", 1, 16),
118 	FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll", 1, 2),
119 	FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
120 	FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll", 1, 8),
121 };
122 
123 static const char * const axi_parents[] = {
124 	"clk26m",
125 	"mainpll_d4_d4",
126 	"mainpll_d7_d2",
127 	"mainpll_d4_d2",
128 	"mainpll_d5_d2",
129 	"mainpll_d6_d2",
130 	"ulposc1_d4"
131 };
132 
133 static const char * const spm_parents[] = {
134 	"clk26m",
135 	"ulposc1_d10",
136 	"mainpll_d7_d4",
137 	"clk32k"
138 };
139 
140 static const char * const scp_parents[] = {
141 	"clk26m",
142 	"univpll_d4",
143 	"mainpll_d6",
144 	"univpll_d6",
145 	"univpll_d4_d2",
146 	"mainpll_d4_d2",
147 	"mainpll_d4",
148 	"mainpll_d6_d2"
149 };
150 
151 static const char * const bus_aximem_parents[] = {
152 	"clk26m",
153 	"mainpll_d7_d2",
154 	"mainpll_d4_d2",
155 	"mainpll_d5_d2",
156 	"mainpll_d6"
157 };
158 
159 static const char * const vpp_parents[] = {
160 	"clk26m",
161 	"univpll_d6_d2",
162 	"mainpll_d5_d2",
163 	"mmpll_d6_d2",
164 	"univpll_d5_d2",
165 	"univpll_d4_d2",
166 	"mmpll_d4_d2",
167 	"mmpll_d7",
168 	"univpll_d6",
169 	"mainpll_d4",
170 	"mmpll_d5",
171 	"tvdpll1",
172 	"tvdpll2",
173 	"univpll_d4",
174 	"mmpll_d4"
175 };
176 
177 static const char * const ethdr_parents[] = {
178 	"clk26m",
179 	"univpll_d6_d2",
180 	"mainpll_d5_d2",
181 	"mmpll_d6_d2",
182 	"univpll_d5_d2",
183 	"univpll_d4_d2",
184 	"mmpll_d4_d2",
185 	"mmpll_d7",
186 	"univpll_d6",
187 	"mainpll_d4",
188 	"mmpll_d5_d4",
189 	"tvdpll1",
190 	"tvdpll2",
191 	"univpll_d4",
192 	"mmpll_d4"
193 };
194 
195 static const char * const ipe_parents[] = {
196 	"clk26m",
197 	"imgpll",
198 	"mainpll_d4",
199 	"mmpll_d6",
200 	"univpll_d6",
201 	"mainpll_d6",
202 	"mmpll_d4_d2",
203 	"univpll_d4_d2",
204 	"mainpll_d4_d2",
205 	"mmpll_d6_d2",
206 	"univpll_d5_d2"
207 };
208 
209 static const char * const cam_parents[] = {
210 	"clk26m",
211 	"mainpll_d4",
212 	"mmpll_d4",
213 	"univpll_d4",
214 	"univpll_d5",
215 	"univpll_d6",
216 	"mmpll_d7",
217 	"univpll_d4_d2",
218 	"mainpll_d4_d2",
219 	"imgpll"
220 };
221 
222 static const char * const ccu_parents[] = {
223 	"clk26m",
224 	"univpll_d6",
225 	"mainpll_d4_d2",
226 	"mainpll_d4",
227 	"univpll_d5",
228 	"mainpll_d6",
229 	"mmpll_d6",
230 	"mmpll_d7",
231 	"univpll_d4_d2",
232 	"univpll_d7"
233 };
234 
235 static const char * const img_parents[] = {
236 	"clk26m",
237 	"imgpll",
238 	"univpll_d4",
239 	"mainpll_d4",
240 	"univpll_d5",
241 	"mmpll_d6",
242 	"univpll_d6",
243 	"mainpll_d6",
244 	"mmpll_d4_d2",
245 	"univpll_d4_d2",
246 	"mainpll_d4_d2",
247 	"univpll_d5_d2"
248 };
249 
250 static const char * const camtm_parents[] = {
251 	"clk26m",
252 	"univpll_d4_d4",
253 	"univpll_d6_d2",
254 	"univpll_d6_d4"
255 };
256 
257 static const char * const dsp_parents[] = {
258 	"clk26m",
259 	"univpll_d6_d2",
260 	"univpll_d4_d2",
261 	"univpll_d5",
262 	"univpll_d4",
263 	"mmpll_d4",
264 	"mainpll_d3",
265 	"univpll_d3"
266 };
267 
268 static const char * const dsp1_parents[] = {
269 	"clk26m",
270 	"univpll_d6_d2",
271 	"mainpll_d4_d2",
272 	"univpll_d5",
273 	"mmpll_d5",
274 	"univpll_d4",
275 	"mainpll_d3",
276 	"univpll_d3"
277 };
278 
279 static const char * const dsp2_parents[] = {
280 	"clk26m",
281 	"univpll_d6_d2",
282 	"univpll_d4_d2",
283 	"mainpll_d4",
284 	"univpll_d4",
285 	"mmpll_d4",
286 	"mainpll_d3",
287 	"univpll_d3"
288 };
289 
290 static const char * const ipu_if_parents[] = {
291 	"clk26m",
292 	"univpll_d6_d2",
293 	"univpll_d5_d2",
294 	"mainpll_d4_d2",
295 	"mainpll_d6",
296 	"univpll_d5",
297 	"univpll_d4",
298 	"mmpll_d4"
299 };
300 
301 static const char * const mfg_parents[] = {
302 	"clk26m",
303 	"mainpll_d5_d2",
304 	"univpll_d6",
305 	"univpll_d7"
306 };
307 
308 static const char * const camtg_parents[] = {
309 	"clk26m",
310 	"univpll_192m_d8",
311 	"univpll_d6_d8",
312 	"univpll_192m_d4",
313 	"univpll_d6_d16",
314 	"clk26m_d2",
315 	"univpll_192m_d16",
316 	"univpll_192m_d32"
317 };
318 
319 static const char * const uart_parents[] = {
320 	"clk26m",
321 	"univpll_d6_d8"
322 };
323 
324 static const char * const spi_parents[] = {
325 	"clk26m",
326 	"mainpll_d5_d4",
327 	"mainpll_d6_d4",
328 	"msdcpll_d4",
329 	"univpll_d6_d2",
330 	"mainpll_d6_d2",
331 	"mainpll_d4_d4",
332 	"univpll_d5_d4"
333 };
334 
335 static const char * const spis_parents[] = {
336 	"clk26m",
337 	"univpll_d6",
338 	"mainpll_d6",
339 	"univpll_d4_d2",
340 	"univpll_d6_d2",
341 	"univpll_d4_d4",
342 	"univpll_d6_d4",
343 	"mainpll_d7_d4"
344 };
345 
346 static const char * const msdc50_0_h_parents[] = {
347 	"clk26m",
348 	"mainpll_d4_d2",
349 	"mainpll_d6_d2"
350 };
351 
352 static const char * const msdc50_0_parents[] = {
353 	"clk26m",
354 	"msdcpll",
355 	"msdcpll_d2",
356 	"univpll_d4_d4",
357 	"mainpll_d6_d2",
358 	"univpll_d4_d2"
359 };
360 
361 static const char * const msdc30_parents[] = {
362 	"clk26m",
363 	"univpll_d6_d2",
364 	"mainpll_d6_d2",
365 	"mainpll_d7_d2",
366 	"msdcpll_d2"
367 };
368 
369 static const char * const intdir_parents[] = {
370 	"clk26m",
371 	"univpll_d6",
372 	"mainpll_d4",
373 	"univpll_d4"
374 };
375 
376 static const char * const aud_intbus_parents[] = {
377 	"clk26m",
378 	"mainpll_d4_d4",
379 	"mainpll_d7_d4"
380 };
381 
382 static const char * const audio_h_parents[] = {
383 	"clk26m",
384 	"univpll_d7",
385 	"apll1",
386 	"apll2"
387 };
388 
389 static const char * const pwrap_ulposc_parents[] = {
390 	"ulposc1_d10",
391 	"clk26m",
392 	"ulposc1_d4",
393 	"ulposc1_d7",
394 	"ulposc1_d8",
395 	"ulposc1_d16",
396 	"mainpll_d4_d8",
397 	"univpll_d5_d8"
398 };
399 
400 static const char * const atb_parents[] = {
401 	"clk26m",
402 	"mainpll_d4_d2",
403 	"mainpll_d5_d2"
404 };
405 
406 static const char * const pwrmcu_parents[] = {
407 	"clk26m",
408 	"mainpll_d7_d2",
409 	"mainpll_d6_d2",
410 	"mainpll_d5_d2",
411 	"mainpll_d9",
412 	"mainpll_d4_d2"
413 };
414 
415 static const char * const dp_parents[] = {
416 	"clk26m",
417 	"tvdpll1_d2",
418 	"tvdpll2_d2",
419 	"tvdpll1_d4",
420 	"tvdpll2_d4",
421 	"tvdpll1_d8",
422 	"tvdpll2_d8",
423 	"tvdpll1_d16",
424 	"tvdpll2_d16"
425 };
426 
427 static const char * const disp_pwm_parents[] = {
428 	"clk26m",
429 	"univpll_d6_d4",
430 	"ulposc1_d2",
431 	"ulposc1_d4",
432 	"ulposc1_d16"
433 };
434 
435 static const char * const usb_parents[] = {
436 	"clk26m",
437 	"univpll_d5_d4",
438 	"univpll_d6_d4",
439 	"univpll_d5_d2"
440 };
441 
442 static const char * const i2c_parents[] = {
443 	"clk26m",
444 	"mainpll_d4_d8",
445 	"univpll_d5_d4"
446 };
447 
448 static const char * const seninf_parents[] = {
449 	"clk26m",
450 	"univpll_d4_d4",
451 	"univpll_d6_d2",
452 	"univpll_d4_d2",
453 	"univpll_d7",
454 	"univpll_d6",
455 	"mmpll_d6",
456 	"univpll_d5"
457 };
458 
459 static const char * const gcpu_parents[] = {
460 	"clk26m",
461 	"mainpll_d6",
462 	"univpll_d4_d2",
463 	"mmpll_d5_d2",
464 	"univpll_d5_d2"
465 };
466 
467 static const char * const dxcc_parents[] = {
468 	"clk26m",
469 	"mainpll_d4_d2",
470 	"mainpll_d4_d4",
471 	"mainpll_d4_d8"
472 };
473 
474 static const char * const dpmaif_parents[] = {
475 	"clk26m",
476 	"univpll_d4_d4",
477 	"mainpll_d6",
478 	"mainpll_d4_d2",
479 	"univpll_d4_d2"
480 };
481 
482 static const char * const aes_fde_parents[] = {
483 	"clk26m",
484 	"mainpll_d4_d2",
485 	"mainpll_d6",
486 	"mainpll_d4_d4",
487 	"univpll_d4_d2",
488 	"univpll_d6"
489 };
490 
491 static const char * const ufs_parents[] = {
492 	"clk26m",
493 	"mainpll_d4_d4",
494 	"mainpll_d4_d8",
495 	"univpll_d4_d4",
496 	"mainpll_d6_d2",
497 	"univpll_d6_d2",
498 	"msdcpll_d2"
499 };
500 
501 static const char * const ufs_tick1us_parents[] = {
502 	"clk26m_d52",
503 	"clk26m"
504 };
505 
506 static const char * const ufs_mp_sap_parents[] = {
507 	"clk26m",
508 	"msdcpll_d16"
509 };
510 
511 static const char * const venc_parents[] = {
512 	"clk26m",
513 	"mmpll_d4_d2",
514 	"mainpll_d6",
515 	"univpll_d4_d2",
516 	"mainpll_d4_d2",
517 	"univpll_d6",
518 	"mmpll_d6",
519 	"mainpll_d5_d2",
520 	"mainpll_d6_d2",
521 	"mmpll_d9",
522 	"univpll_d4_d4",
523 	"mainpll_d4",
524 	"univpll_d4",
525 	"univpll_d5",
526 	"univpll_d5_d2",
527 	"mainpll_d5"
528 };
529 
530 static const char * const vdec_parents[] = {
531 	"clk26m",
532 	"mainpll_d5_d2",
533 	"mmpll_d6_d2",
534 	"univpll_d4_d2",
535 	"mmpll_d4_d2",
536 	"mainpll_d5",
537 	"mmpll_d6",
538 	"mmpll_d5",
539 	"vdecpll",
540 	"univpll_d4",
541 	"mmpll_d4",
542 	"univpll_d6_d2",
543 	"mmpll_d9",
544 	"univpll_d6",
545 	"univpll_d5",
546 	"mainpll_d4"
547 };
548 
549 static const char * const pwm_parents[] = {
550 	"clk26m",
551 	"univpll_d4_d8"
552 };
553 
554 static const char * const mcupm_parents[] = {
555 	"clk26m",
556 	"mainpll_d6_d2",
557 	"mainpll_d7_d4",
558 };
559 
560 static const char * const spmi_parents[] = {
561 	"clk26m",
562 	"clk26m_d2",
563 	"ulposc1_d8",
564 	"ulposc1_d10",
565 	"ulposc1_d16",
566 	"ulposc1_d7",
567 	"clk32k",
568 	"mainpll_d7_d8",
569 	"mainpll_d6_d8",
570 	"mainpll_d5_d8"
571 };
572 
573 static const char * const dvfsrc_parents[] = {
574 	"clk26m",
575 	"ulposc1_d10",
576 	"univpll_d6_d8",
577 	"msdcpll_d16"
578 };
579 
580 static const char * const tl_parents[] = {
581 	"clk26m",
582 	"univpll_d5_d4",
583 	"mainpll_d4_d4"
584 };
585 
586 static const char * const dsi_occ_parents[] = {
587 	"clk26m",
588 	"mainpll_d6_d2",
589 	"univpll_d5_d2",
590 	"univpll_d4_d2"
591 };
592 
593 static const char * const wpe_vpp_parents[] = {
594 	"clk26m",
595 	"mainpll_d5_d2",
596 	"mmpll_d6_d2",
597 	"univpll_d5_d2",
598 	"mainpll_d4_d2",
599 	"univpll_d4_d2",
600 	"mmpll_d4_d2",
601 	"mainpll_d6",
602 	"mmpll_d7",
603 	"univpll_d6",
604 	"mainpll_d5",
605 	"univpll_d5",
606 	"mainpll_d4",
607 	"tvdpll1",
608 	"univpll_d4"
609 };
610 
611 static const char * const hdcp_parents[] = {
612 	"clk26m",
613 	"univpll_d4_d8",
614 	"mainpll_d5_d8",
615 	"univpll_d6_d4"
616 };
617 
618 static const char * const hdcp_24m_parents[] = {
619 	"clk26m",
620 	"univpll_192m_d4",
621 	"univpll_192m_d8",
622 	"univpll_d6_d8"
623 };
624 
625 static const char * const hd20_dacr_ref_parents[] = {
626 	"clk26m",
627 	"univpll_d4_d2",
628 	"univpll_d4_d4",
629 	"univpll_d4_d8"
630 };
631 
632 static const char * const hd20_hdcp_c_parents[] = {
633 	"clk26m",
634 	"msdcpll_d4",
635 	"univpll_d4_d8",
636 	"univpll_d6_d8"
637 };
638 
639 static const char * const hdmi_xtal_parents[] = {
640 	"clk26m",
641 	"clk26m_d2"
642 };
643 
644 static const char * const hdmi_apb_parents[] = {
645 	"clk26m",
646 	"univpll_d6_d4",
647 	"msdcpll_d2"
648 };
649 
650 static const char * const snps_eth_250m_parents[] = {
651 	"clk26m",
652 	"ethpll_d2"
653 };
654 
655 static const char * const snps_eth_62p4m_ptp_parents[] = {
656 	"apll2_d3",
657 	"apll1_d3",
658 	"clk26m",
659 	"ethpll_d8"
660 };
661 
662 static const char * const snps_eth_50m_rmii_parents[] = {
663 	"clk26m",
664 	"ethpll_d10"
665 };
666 
667 static const char * const dgi_out_parents[] = {
668 	"clk26m",
669 	"dgipll",
670 	"dgipll_d2",
671 	"in_dgi",
672 	"in_dgi_d2",
673 	"mmpll_d4_d4"
674 };
675 
676 static const char * const nna_parents[] = {
677 	"clk26m",
678 	"nnapll",
679 	"univpll_d4",
680 	"mainpll_d4",
681 	"univpll_d5",
682 	"mmpll_d6",
683 	"univpll_d6",
684 	"mainpll_d6",
685 	"mmpll_d4_d2",
686 	"univpll_d4_d2",
687 	"mainpll_d4_d2",
688 	"mmpll_d6_d2"
689 };
690 
691 static const char * const adsp_parents[] = {
692 	"clk26m",
693 	"clk26m_d2",
694 	"mainpll_d6",
695 	"mainpll_d5_d2",
696 	"univpll_d4_d4",
697 	"univpll_d4",
698 	"univpll_d6",
699 	"ulposc1",
700 	"adsppll",
701 	"adsppll_d2",
702 	"adsppll_d4",
703 	"adsppll_d8"
704 };
705 
706 static const char * const asm_parents[] = {
707 	"clk26m",
708 	"univpll_d6_d4",
709 	"univpll_d6_d2",
710 	"mainpll_d5_d2"
711 };
712 
713 static const char * const apll1_parents[] = {
714 	"clk26m",
715 	"apll1_d4"
716 };
717 
718 static const char * const apll2_parents[] = {
719 	"clk26m",
720 	"apll2_d4"
721 };
722 
723 static const char * const apll3_parents[] = {
724 	"clk26m",
725 	"apll3_d4"
726 };
727 
728 static const char * const apll4_parents[] = {
729 	"clk26m",
730 	"apll4_d4"
731 };
732 
733 static const char * const apll5_parents[] = {
734 	"clk26m",
735 	"apll5_d4"
736 };
737 
738 static const char * const i2s_parents[] = {
739 	"clk26m",
740 	"apll1",
741 	"apll2",
742 	"apll3",
743 	"apll4",
744 	"apll5",
745 	"hdmirx_apll"
746 };
747 
748 static const char * const a1sys_hp_parents[] = {
749 	"clk26m",
750 	"apll1_d4"
751 };
752 
753 static const char * const a2sys_parents[] = {
754 	"clk26m",
755 	"apll2_d4"
756 };
757 
758 static const char * const a3sys_parents[] = {
759 	"clk26m",
760 	"apll3_d4",
761 	"apll4_d4",
762 	"apll5_d4",
763 	"hdmirx_apll_d3",
764 	"hdmirx_apll_d4",
765 	"hdmirx_apll_d6"
766 };
767 
768 static const char * const spinfi_b_parents[] = {
769 	"clk26m",
770 	"univpll_d6_d8",
771 	"univpll_d5_d8",
772 	"mainpll_d4_d8",
773 	"mainpll_d7_d4",
774 	"mainpll_d6_d4",
775 	"univpll_d6_d4",
776 	"univpll_d5_d4"
777 };
778 
779 static const char * const nfi1x_parents[] = {
780 	"clk26m",
781 	"univpll_d5_d4",
782 	"mainpll_d7_d4",
783 	"mainpll_d6_d4",
784 	"univpll_d6_d4",
785 	"mainpll_d4_d4",
786 	"mainpll_d7_d2",
787 	"mainpll_d6_d2"
788 };
789 
790 static const char * const ecc_parents[] = {
791 	"clk26m",
792 	"mainpll_d4_d4",
793 	"mainpll_d5_d2",
794 	"mainpll_d4_d2",
795 	"mainpll_d6",
796 	"univpll_d6"
797 };
798 
799 static const char * const audio_local_bus_parents[] = {
800 	"clk26m",
801 	"clk26m_d2",
802 	"mainpll_d4_d4",
803 	"mainpll_d7_d2",
804 	"mainpll_d4_d2",
805 	"mainpll_d5_d2",
806 	"mainpll_d6_d2",
807 	"mainpll_d7",
808 	"univpll_d6",
809 	"ulposc1",
810 	"ulposc1_d4",
811 	"ulposc1_d2"
812 };
813 
814 static const char * const spinor_parents[] = {
815 	"clk26m",
816 	"clk26m_d2",
817 	"mainpll_d7_d8",
818 	"univpll_d6_d8"
819 };
820 
821 static const char * const dvio_dgi_ref_parents[] = {
822 	"clk26m",
823 	"in_dgi",
824 	"in_dgi_d2",
825 	"in_dgi_d4",
826 	"in_dgi_d6",
827 	"in_dgi_d8",
828 	"mmpll_d4_d4"
829 };
830 
831 static const char * const ulposc_parents[] = {
832 	"ulposc1",
833 	"ethpll_d2",
834 	"mainpll_d4_d2",
835 	"ethpll_d10"
836 };
837 
838 static const char * const ulposc_core_parents[] = {
839 	"ulposc2",
840 	"univpll_d7",
841 	"mainpll_d6",
842 	"ethpll_d10"
843 };
844 
845 static const char * const srck_parents[] = {
846 	"ulposc1_d10",
847 	"clk26m"
848 };
849 
850 static const char * const mfg_fast_parents[] = {
851 	"top_mfg_core_tmp",
852 	"mfgpll"
853 };
854 
855 static const struct mtk_mux top_mtk_muxes[] = {
856 	/*
857 	 * CLK_CFG_0
858 	 * top_axi and top_bus_aximem are bus clocks, should not be closed by Linux.
859 	 * top_spm and top_scp are main clocks in always-on co-processor.
860 	 */
861 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi",
862 		axi_parents, 0x020, 0x024, 0x028, 0, 3, 7, 0x04, 0, CLK_IS_CRITICAL),
863 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm",
864 		spm_parents, 0x020, 0x024, 0x028, 8, 2, 15, 0x04, 1, CLK_IS_CRITICAL),
865 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp",
866 		scp_parents, 0x020, 0x024, 0x028, 16, 3, 23, 0x04, 2, CLK_IS_CRITICAL),
867 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM, "top_bus_aximem",
868 		bus_aximem_parents, 0x020, 0x024, 0x028, 24, 3, 31, 0x04, 3, CLK_IS_CRITICAL),
869 	/* CLK_CFG_1 */
870 	MUX_GATE_CLR_SET_UPD(CLK_TOP_VPP, "top_vpp",
871 		vpp_parents, 0x02C, 0x030, 0x034, 0, 4, 7, 0x04, 4),
872 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ETHDR, "top_ethdr",
873 		ethdr_parents, 0x02C, 0x030, 0x034, 8, 4, 15, 0x04, 5),
874 	MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
875 		ipe_parents, 0x02C, 0x030, 0x034, 16, 4, 23, 0x04, 6),
876 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
877 		cam_parents, 0x02C, 0x030, 0x034, 24, 4, 31, 0x04, 7),
878 	/* CLK_CFG_2 */
879 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "top_ccu",
880 		ccu_parents, 0x038, 0x03C, 0x040, 0, 4, 7, 0x04, 8),
881 	MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "top_img",
882 		img_parents, 0x038, 0x03C, 0x040, 8, 4, 15, 0x04, 9),
883 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
884 		camtm_parents, 0x038, 0x03C, 0x040, 16, 2, 23, 0x04, 10),
885 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "top_dsp",
886 		dsp_parents, 0x038, 0x03C, 0x040, 24, 3, 31, 0x04, 11),
887 	/* CLK_CFG_3 */
888 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "top_dsp1",
889 		dsp1_parents, 0x044, 0x048, 0x04C, 0, 3, 7, 0x04, 12),
890 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "top_dsp2",
891 		dsp1_parents, 0x044, 0x048, 0x04C, 8, 3, 15, 0x04, 13),
892 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "top_dsp3",
893 		dsp1_parents, 0x044, 0x048, 0x04C, 16, 3, 23, 0x04, 14),
894 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP4, "top_dsp4",
895 		dsp2_parents, 0x044, 0x048, 0x04C, 24, 3, 31, 0x04, 15),
896 	/* CLK_CFG_4 */
897 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5, "top_dsp5",
898 		dsp2_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x04, 16),
899 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP6, "top_dsp6",
900 		dsp2_parents, 0x050, 0x054, 0x058, 8, 3, 15, 0x04, 17),
901 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7, "top_dsp7",
902 		dsp_parents, 0x050, 0x054, 0x058, 16, 3, 23, 0x04, 18),
903 	MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "top_ipu_if",
904 		ipu_if_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x04, 19),
905 	/* CLK_CFG_5 */
906 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_CORE_TMP, "top_mfg_core_tmp",
907 		mfg_parents, 0x05C, 0x060, 0x064, 0, 2, 7, 0x04, 20),
908 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
909 		camtg_parents, 0x05C, 0x060, 0x064, 8, 3, 15, 0x04, 21),
910 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
911 		camtg_parents, 0x05C, 0x060, 0x064, 16, 3, 23, 0x04, 22),
912 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
913 		camtg_parents, 0x05C, 0x060, 0x064, 24, 3, 31, 0x04, 23),
914 	/* CLK_CFG_6 */
915 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "top_camtg4",
916 		camtg_parents, 0x068, 0x06C, 0x070, 0, 3, 7, 0x04, 24),
917 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "top_camtg5",
918 		camtg_parents, 0x068, 0x06C, 0x070, 8, 3, 15, 0x04, 25),
919 	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
920 		uart_parents, 0x068, 0x06C, 0x070, 16, 1, 23, 0x04, 26),
921 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
922 		spi_parents, 0x068, 0x06C, 0x070, 24, 3, 31, 0x04, 27),
923 	/* CLK_CFG_7 */
924 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIS, "top_spis",
925 		spis_parents, 0x074, 0x078, 0x07C, 0, 3, 7, 0x04, 28),
926 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc50_0_hclk",
927 		msdc50_0_h_parents, 0x074, 0x078, 0x07C, 8, 2, 15, 0x04, 29),
928 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0",
929 		msdc50_0_parents, 0x074, 0x078, 0x07C, 16, 3, 23, 0x04, 30),
930 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1",
931 		msdc30_parents, 0x074, 0x078, 0x07C, 24, 3, 31, 0x04, 31),
932 	/* CLK_CFG_8 */
933 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2, "top_msdc30_2",
934 		msdc30_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x08, 0),
935 	MUX_GATE_CLR_SET_UPD(CLK_TOP_INTDIR, "top_intdir",
936 		intdir_parents, 0x080, 0x084, 0x088, 8, 2, 15, 0x08, 1),
937 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
938 		aud_intbus_parents, 0x080, 0x084, 0x088, 16, 2, 23, 0x08, 2),
939 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
940 		audio_h_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x08, 3),
941 	/*
942 	 * CLK_CFG_9
943 	 * top_pwrmcu is main clock in other co-processor, should not be
944 	 * handled by Linux.
945 	 */
946 	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
947 		pwrap_ulposc_parents, 0x08C, 0x090, 0x094, 0, 3, 7, 0x08, 4),
948 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "top_atb",
949 		atb_parents, 0x08C, 0x090, 0x094, 8, 2, 15, 0x08, 5),
950 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRMCU, "top_pwrmcu",
951 		pwrmcu_parents, 0x08C, 0x090, 0x094, 16, 3, 23, 0x08, 6, CLK_IS_CRITICAL),
952 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DP, "top_dp",
953 		dp_parents, 0x08C, 0x090, 0x094, 24, 4, 31, 0x08, 7),
954 	/* CLK_CFG_10 */
955 	MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP, "top_edp",
956 		dp_parents, 0x098, 0x09C, 0x0A0, 0, 4, 7, 0x08, 8),
957 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
958 		dp_parents, 0x098, 0x09C, 0x0A0, 8, 4, 15, 0x08, 9),
959 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM0, "top_disp_pwm0",
960 		disp_pwm_parents, 0x098, 0x09C, 0x0A0, 16, 3, 23, 0x08, 10),
961 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM1, "top_disp_pwm1",
962 		disp_pwm_parents, 0x098, 0x09C, 0x0A0, 24, 3, 31, 0x08, 11),
963 	/* CLK_CFG_11 */
964 	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb_top",
965 		usb_parents, 0x0A4, 0x0A8, 0x0AC, 0, 2, 7, 0x08, 12),
966 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
967 		usb_parents, 0x0A4, 0x0A8, 0x0AC, 8, 2, 15, 0x08, 13),
968 	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_1P, "top_usb_top_1p",
969 		usb_parents, 0x0A4, 0x0A8, 0x0AC, 16, 2, 23, 0x08, 14),
970 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_1P, "top_ssusb_xhci_1p",
971 		usb_parents, 0x0A4, 0x0A8, 0x0AC, 24, 2, 31, 0x08, 15),
972 	/* CLK_CFG_12 */
973 	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_2P, "top_usb_top_2p",
974 		usb_parents, 0x0B0, 0x0B4, 0x0B8, 0, 2, 7, 0x08, 16),
975 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_2P, "top_ssusb_xhci_2p",
976 		usb_parents, 0x0B0, 0x0B4, 0x0B8, 8, 2, 15, 0x08, 17),
977 	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_3P, "top_usb_top_3p",
978 		usb_parents, 0x0B0, 0x0B4, 0x0B8, 16, 2, 23, 0x08, 18),
979 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_3P, "top_ssusb_xhci_3p",
980 		usb_parents, 0x0B0, 0x0B4, 0x0B8, 24, 2, 31, 0x08, 19),
981 	/* CLK_CFG_13 */
982 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
983 		i2c_parents, 0x0BC, 0x0C0, 0x0C4, 0, 2, 7, 0x08, 20),
984 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
985 		seninf_parents, 0x0BC, 0x0C0, 0x0C4, 8, 3, 15, 0x08, 21),
986 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
987 		seninf_parents, 0x0BC, 0x0C0, 0x0C4, 16, 3, 23, 0x08, 22),
988 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "top_seninf2",
989 		seninf_parents, 0x0BC, 0x0C0, 0x0C4, 24, 3, 31, 0x08, 23),
990 	/* CLK_CFG_14 */
991 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3, "top_seninf3",
992 		seninf_parents, 0x0C8, 0x0CC, 0x0D0, 0, 3, 7, 0x08, 24),
993 	MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU, "top_gcpu",
994 		gcpu_parents, 0x0C8, 0x0CC, 0x0D0, 8, 3, 15, 0x08, 25),
995 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "top_dxcc",
996 		dxcc_parents, 0x0C8, 0x0CC, 0x0D0, 16, 2, 23, 0x08, 26),
997 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN, "top_dpmaif_main",
998 		dpmaif_parents, 0x0C8, 0x0CC, 0x0D0, 24, 3, 31, 0x08, 27),
999 	/* CLK_CFG_15 */
1000 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE, "top_aes_ufsfde",
1001 		aes_fde_parents, 0x0D4, 0x0D8, 0x0DC, 0, 3, 7, 0x08, 28),
1002 	MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS, "top_ufs",
1003 		ufs_parents, 0x0D4, 0x0D8, 0x0DC, 8, 3, 15, 0x08, 29),
1004 	MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_TICK1US, "top_ufs_tick1us",
1005 		ufs_tick1us_parents, 0x0D4, 0x0D8, 0x0DC, 16, 1, 23, 0x08, 30),
1006 	MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_MP_SAP_CFG, "top_ufs_mp_sap_cfg",
1007 		ufs_mp_sap_parents, 0x0D4, 0x0D8, 0x0DC, 24, 1, 31, 0x08, 31),
1008 	/*
1009 	 * CLK_CFG_16
1010 	 * top_mcupm is main clock in other co-processor, should not be
1011 	 * handled by Linux.
1012 	 */
1013 	MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
1014 		venc_parents, 0x0E0, 0x0E4, 0x0E8, 0, 4, 7, 0x0C, 0),
1015 	MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
1016 		vdec_parents, 0x0E0, 0x0E4, 0x0E8, 8, 4, 15, 0x0C, 1),
1017 	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
1018 		pwm_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1, 23, 0x0C, 2),
1019 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MCUPM, "top_mcupm",
1020 		mcupm_parents, 0x0E0, 0x0E4, 0x0E8, 24, 2, 31, 0x0C, 3, CLK_IS_CRITICAL),
1021 	/*
1022 	 * CLK_CFG_17
1023 	 * top_dvfsrc is for internal DVFS usage, should not be handled by Linux.
1024 	 */
1025 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_P_MST, "top_spmi_p_mst",
1026 		spmi_parents, 0x0EC, 0x0F0, 0x0F4, 0, 4, 7, 0x0C, 4),
1027 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_M_MST, "top_spmi_m_mst",
1028 		spmi_parents, 0x0EC, 0x0F0, 0x0F4, 8, 4, 15, 0x0C, 5),
1029 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc",
1030 		dvfsrc_parents, 0x0EC, 0x0F0, 0x0F4, 16, 2, 23, 0x0C, 6, CLK_IS_CRITICAL),
1031 	MUX_GATE_CLR_SET_UPD(CLK_TOP_TL, "top_tl",
1032 		tl_parents, 0x0EC, 0x0F0, 0x0F4, 24, 2, 31, 0x0C, 7),
1033 	/* CLK_CFG_18 */
1034 	MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_P1, "top_tl_p1",
1035 		tl_parents, 0x0F8, 0x0FC, 0x0100, 0, 2, 7, 0x0C, 8),
1036 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
1037 		aes_fde_parents, 0x0F8, 0x0FC, 0x0100, 8, 3, 15, 0x0C, 9),
1038 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
1039 		dsi_occ_parents, 0x0F8, 0x0FC, 0x0100, 16, 2, 23, 0x0C, 10),
1040 	MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE_VPP, "top_wpe_vpp",
1041 		wpe_vpp_parents, 0x0F8, 0x0FC, 0x0100, 24, 4, 31, 0x0C, 11),
1042 	/* CLK_CFG_19 */
1043 	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP, "top_hdcp",
1044 		hdcp_parents, 0x0104, 0x0108, 0x010C, 0, 2, 7, 0x0C, 12),
1045 	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDCP_24M, "top_hdcp_24m",
1046 		hdcp_24m_parents, 0x0104, 0x0108, 0x010C, 8, 2, 15, 0x0C, 13),
1047 	MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_DACR_REF_CLK, "top_hd20_dacr_ref_clk",
1048 		hd20_dacr_ref_parents, 0x0104, 0x0108, 0x010C, 16, 2, 23, 0x0C, 14),
1049 	MUX_GATE_CLR_SET_UPD(CLK_TOP_HD20_HDCP_CCLK, "top_hd20_hdcp_cclk",
1050 		hd20_hdcp_c_parents, 0x0104, 0x0108, 0x010C, 24, 2, 31, 0x0C, 15),
1051 	/* CLK_CFG_20 */
1052 	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_XTAL, "top_hdmi_xtal",
1053 		hdmi_xtal_parents, 0x0110, 0x0114, 0x0118, 0, 1, 7, 0x0C, 16),
1054 	MUX_GATE_CLR_SET_UPD(CLK_TOP_HDMI_APB, "top_hdmi_apb",
1055 		hdmi_apb_parents, 0x0110, 0x0114, 0x0118, 8, 2, 15, 0x0C, 17),
1056 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_250M, "top_snps_eth_250m",
1057 		snps_eth_250m_parents, 0x0110, 0x0114, 0x0118, 16, 1, 23, 0x0C, 18),
1058 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_62P4M_PTP, "top_snps_eth_62p4m_ptp",
1059 		snps_eth_62p4m_ptp_parents, 0x0110, 0x0114, 0x0118, 24, 2, 31, 0x0C, 19),
1060 	/* CLK_CFG_21 */
1061 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SNPS_ETH_50M_RMII, "snps_eth_50m_rmii",
1062 		snps_eth_50m_rmii_parents, 0x011C, 0x0120, 0x0124, 0, 1, 7, 0x0C, 20),
1063 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DGI_OUT, "top_dgi_out",
1064 		dgi_out_parents, 0x011C, 0x0120, 0x0124, 8, 3, 15, 0x0C, 21),
1065 	MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA0, "top_nna0",
1066 		nna_parents, 0x011C, 0x0120, 0x0124, 16, 4, 23, 0x0C, 22),
1067 	MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA1, "top_nna1",
1068 		nna_parents, 0x011C, 0x0120, 0x0124, 24, 4, 31, 0x0C, 23),
1069 	/* CLK_CFG_22 */
1070 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "top_adsp",
1071 		adsp_parents, 0x0128, 0x012C, 0x0130, 0, 4, 7, 0x0C, 24),
1072 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_H, "top_asm_h",
1073 		asm_parents, 0x0128, 0x012C, 0x0130, 8, 2, 15, 0x0C, 25),
1074 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_M, "top_asm_m",
1075 		asm_parents, 0x0128, 0x012C, 0x0130, 16, 2, 23, 0x0C, 26),
1076 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ASM_L, "top_asm_l",
1077 		asm_parents, 0x0128, 0x012C, 0x0130, 24, 2, 31, 0x0C, 27),
1078 	/* CLK_CFG_23 */
1079 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL1, "top_apll1",
1080 		apll1_parents, 0x0134, 0x0138, 0x013C, 0, 1, 7, 0x0C, 28),
1081 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL2, "top_apll2",
1082 		apll2_parents, 0x0134, 0x0138, 0x013C, 8, 1, 15, 0x0C, 29),
1083 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL3, "top_apll3",
1084 		apll3_parents, 0x0134, 0x0138, 0x013C, 16, 1, 23, 0x0C, 30),
1085 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL4, "top_apll4",
1086 		apll4_parents, 0x0134, 0x0138, 0x013C, 24, 1, 31, 0x0C, 31),
1087 	/*
1088 	 * CLK_CFG_24
1089 	 * i2so4_mck is not used in MT8195.
1090 	 */
1091 	MUX_GATE_CLR_SET_UPD(CLK_TOP_APLL5, "top_apll5",
1092 		apll5_parents, 0x0140, 0x0144, 0x0148, 0, 1, 7, 0x010, 0),
1093 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO1_MCK, "top_i2so1_mck",
1094 		i2s_parents, 0x0140, 0x0144, 0x0148, 8, 3, 15, 0x010, 1),
1095 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SO2_MCK, "top_i2so2_mck",
1096 		i2s_parents, 0x0140, 0x0144, 0x0148, 16, 3, 23, 0x010, 2),
1097 	/*
1098 	 * CLK_CFG_25
1099 	 * i2so5_mck and i2si4_mck are not used in MT8195.
1100 	 */
1101 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI1_MCK, "top_i2si1_mck",
1102 		i2s_parents, 0x014C, 0x0150, 0x0154, 8, 3, 15, 0x010, 5),
1103 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2SI2_MCK, "top_i2si2_mck",
1104 		i2s_parents, 0x014C, 0x0150, 0x0154, 16, 3, 23, 0x010, 6),
1105 	/*
1106 	 * CLK_CFG_26
1107 	 * i2si5_mck is not used in MT8195.
1108 	 */
1109 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPTX_MCK, "top_dptx_mck",
1110 		i2s_parents, 0x0158, 0x015C, 0x0160, 8, 3, 15, 0x010, 9),
1111 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_IEC_CLK, "top_aud_iec_clk",
1112 		i2s_parents, 0x0158, 0x015C, 0x0160, 16, 3, 23, 0x010, 10),
1113 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_HP, "top_a1sys_hp",
1114 		a1sys_hp_parents, 0x0158, 0x015C, 0x0160, 24, 1, 31, 0x010, 11),
1115 	/* CLK_CFG_27 */
1116 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A2SYS_HF, "top_a2sys_hf",
1117 		a2sys_parents, 0x0164, 0x0168, 0x016C, 0, 1, 7, 0x010, 12),
1118 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A3SYS_HF, "top_a3sys_hf",
1119 		a3sys_parents, 0x0164, 0x0168, 0x016C, 8, 3, 15, 0x010, 13),
1120 	MUX_GATE_CLR_SET_UPD(CLK_TOP_A4SYS_HF, "top_a4sys_hf",
1121 		a3sys_parents, 0x0164, 0x0168, 0x016C, 16, 3, 23, 0x010, 14),
1122 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_BCLK, "top_spinfi_bclk",
1123 		spinfi_b_parents, 0x0164, 0x0168, 0x016C, 24, 3, 31, 0x010, 15),
1124 	/* CLK_CFG_28 */
1125 	MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X, "top_nfi1x",
1126 		nfi1x_parents, 0x0170, 0x0174, 0x0178, 0, 3, 7, 0x010, 16),
1127 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC, "top_ecc",
1128 		ecc_parents, 0x0170, 0x0174, 0x0178, 8, 3, 15, 0x010, 17),
1129 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_LOCAL_BUS, "top_audio_local_bus",
1130 		audio_local_bus_parents, 0x0170, 0x0174, 0x0178, 16, 4, 23, 0x010, 18),
1131 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
1132 		spinor_parents, 0x0170, 0x0174, 0x0178, 24, 2, 31, 0x010, 19),
1133 	/*
1134 	 * CLK_CFG_29
1135 	 * top_ulposc/top_ulposc_core/top_srck are clock source of always on co-processor,
1136 	 * should not be closed by Linux.
1137 	 */
1138 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DVIO_DGI_REF, "top_dvio_dgi_ref",
1139 		dvio_dgi_ref_parents, 0x017C, 0x0180, 0x0184, 0, 3, 7, 0x010, 20),
1140 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC, "top_ulposc",
1141 		ulposc_parents, 0x017C, 0x0180, 0x0184, 8, 2, 15, 0x010, 21, CLK_IS_CRITICAL),
1142 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_ULPOSC_CORE, "top_ulposc_core",
1143 		ulposc_core_parents, 0x017C, 0x0180, 0x0184, 16, 2, 23, 0x010, 22, CLK_IS_CRITICAL),
1144 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck",
1145 		srck_parents, 0x017C, 0x0180, 0x0184, 24, 1, 31, 0x010, 23, CLK_IS_CRITICAL),
1146 	/*
1147 	 * the clocks in CLK_CFG_30 ~ 37 are backup clock source, no need to handled
1148 	 * by Linux.
1149 	 */
1150 };
1151 
1152 static struct mtk_composite top_muxes[] = {
1153 	/* CLK_MISC_CFG_3 */
1154 	MUX(CLK_TOP_MFG_CK_FAST_REF, "mfg_ck_fast_ref", mfg_fast_parents, 0x0250, 8, 1),
1155 };
1156 
1157 static const struct mtk_composite top_adj_divs[] = {
1158 	DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "top_i2si1_mck", 0x0320, 0, 0x0328, 8, 0),
1159 	DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "top_i2si2_mck", 0x0320, 1, 0x0328, 8, 8),
1160 	DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "top_i2so1_mck", 0x0320, 2, 0x0328, 8, 16),
1161 	DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "top_i2so2_mck", 0x0320, 3, 0x0328, 8, 24),
1162 	DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "top_aud_iec_clk", 0x0320, 4, 0x0334, 8, 0),
1163 	/* apll12_div5 ~ 8 are not used in MT8195. */
1164 	DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "top_dptx_mck", 0x0320, 9, 0x0338, 8, 8),
1165 };
1166 
1167 static const struct mtk_gate_regs top0_cg_regs = {
1168 	.set_ofs = 0x238,
1169 	.clr_ofs = 0x238,
1170 	.sta_ofs = 0x238,
1171 };
1172 
1173 static const struct mtk_gate_regs top1_cg_regs = {
1174 	.set_ofs = 0x250,
1175 	.clr_ofs = 0x250,
1176 	.sta_ofs = 0x250,
1177 };
1178 
1179 #define GATE_TOP0_FLAGS(_id, _name, _parent, _shift, _flag)		\
1180 	GATE_MTK_FLAGS(_id, _name, _parent, &top0_cg_regs, _shift,	\
1181 		&mtk_clk_gate_ops_no_setclr_inv, _flag)
1182 
1183 #define GATE_TOP0(_id, _name, _parent, _shift)			\
1184 	GATE_TOP0_FLAGS(_id, _name, _parent, _shift, 0)
1185 
1186 #define GATE_TOP1(_id, _name, _parent, _shift)			\
1187 	GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
1188 
1189 static const struct mtk_gate top_clks[] = {
1190 	/* TOP0 */
1191 	GATE_TOP0(CLK_TOP_CFG_VPP0, "cfg_vpp0", "top_vpp", 0),
1192 	GATE_TOP0(CLK_TOP_CFG_VPP1, "cfg_vpp1", "top_vpp", 1),
1193 	GATE_TOP0(CLK_TOP_CFG_VDO0, "cfg_vdo0", "top_vpp", 2),
1194 	GATE_TOP0(CLK_TOP_CFG_VDO1, "cfg_vdo1", "top_vpp", 3),
1195 	GATE_TOP0(CLK_TOP_CFG_UNIPLL_SES, "cfg_unipll_ses", "univpll_d2", 4),
1196 	GATE_TOP0(CLK_TOP_CFG_26M_VPP0, "cfg_26m_vpp0", "clk26m", 5),
1197 	GATE_TOP0(CLK_TOP_CFG_26M_VPP1, "cfg_26m_vpp1", "clk26m", 6),
1198 	GATE_TOP0(CLK_TOP_CFG_26M_AUD, "cfg_26m_aud", "clk26m", 9),
1199 	/*
1200 	 * cfg_axi_east, cfg_axi_east_north, cfg_axi_north and cfg_axi_south
1201 	 * are peripheral bus clock branches.
1202 	 */
1203 	GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST, "cfg_axi_east", "top_axi", 10, CLK_IS_CRITICAL),
1204 	GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_EAST_NORTH, "cfg_axi_east_north", "top_axi", 11,
1205 		CLK_IS_CRITICAL),
1206 	GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_NORTH, "cfg_axi_north", "top_axi", 12, CLK_IS_CRITICAL),
1207 	GATE_TOP0_FLAGS(CLK_TOP_CFG_AXI_SOUTH, "cfg_axi_south", "top_axi", 13, CLK_IS_CRITICAL),
1208 	GATE_TOP0(CLK_TOP_CFG_EXT_TEST, "cfg_ext_test", "msdcpll_d2", 15),
1209 	/* TOP1 */
1210 	GATE_TOP1(CLK_TOP_SSUSB_REF, "ssusb_ref", "clk26m", 0),
1211 	GATE_TOP1(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 1),
1212 	GATE_TOP1(CLK_TOP_SSUSB_P1_REF, "ssusb_p1_ref", "clk26m", 2),
1213 	GATE_TOP1(CLK_TOP_SSUSB_PHY_P1_REF, "ssusb_phy_p1_ref", "clk26m", 3),
1214 	GATE_TOP1(CLK_TOP_SSUSB_P2_REF, "ssusb_p2_ref", "clk26m", 4),
1215 	GATE_TOP1(CLK_TOP_SSUSB_PHY_P2_REF, "ssusb_phy_p2_ref", "clk26m", 5),
1216 	GATE_TOP1(CLK_TOP_SSUSB_P3_REF, "ssusb_p3_ref", "clk26m", 6),
1217 	GATE_TOP1(CLK_TOP_SSUSB_PHY_P3_REF, "ssusb_phy_p3_ref", "clk26m", 7),
1218 };
1219 
1220 static const struct of_device_id of_match_clk_mt8195_topck[] = {
1221 	{ .compatible = "mediatek,mt8195-topckgen", },
1222 	{}
1223 };
1224 
1225 static int clk_mt8195_topck_probe(struct platform_device *pdev)
1226 {
1227 	struct clk_onecell_data *top_clk_data;
1228 	struct device_node *node = pdev->dev.of_node;
1229 	int r;
1230 	void __iomem *base;
1231 
1232 	top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1233 	if (!top_clk_data)
1234 		return -ENOMEM;
1235 
1236 	base = devm_platform_ioremap_resource(pdev, 0);
1237 	if (IS_ERR(base)) {
1238 		r = PTR_ERR(base);
1239 		goto free_top_data;
1240 	}
1241 
1242 	mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1243 				    top_clk_data);
1244 	mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1245 	mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node,
1246 			       &mt8195_clk_lock, top_clk_data);
1247 	mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
1248 				    &mt8195_clk_lock, top_clk_data);
1249 	mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
1250 				    &mt8195_clk_lock, top_clk_data);
1251 	r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data);
1252 	if (r)
1253 		goto free_top_data;
1254 
1255 	r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
1256 	if (r)
1257 		goto free_top_data;
1258 
1259 	return r;
1260 
1261 free_top_data:
1262 	mtk_free_clk_data(top_clk_data);
1263 	return r;
1264 }
1265 
1266 static struct platform_driver clk_mt8195_topck_drv = {
1267 	.probe = clk_mt8195_topck_probe,
1268 	.driver = {
1269 		.name = "clk-mt8195-topck",
1270 		.of_match_table = of_match_clk_mt8195_topck,
1271 	},
1272 };
1273 builtin_platform_driver(clk_mt8195_topck_drv);
1274