1222e0fbcSChun-Jie Chen // SPDX-License-Identifier: GPL-2.0-only 2222e0fbcSChun-Jie Chen // 3222e0fbcSChun-Jie Chen // Copyright (c) 2021 MediaTek Inc. 4222e0fbcSChun-Jie Chen // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5222e0fbcSChun-Jie Chen 6222e0fbcSChun-Jie Chen #include "clk-gate.h" 7222e0fbcSChun-Jie Chen #include "clk-mtk.h" 8222e0fbcSChun-Jie Chen 9222e0fbcSChun-Jie Chen #include <dt-bindings/clock/mt8195-clk.h> 10222e0fbcSChun-Jie Chen #include <linux/clk-provider.h> 11222e0fbcSChun-Jie Chen #include <linux/platform_device.h> 12222e0fbcSChun-Jie Chen 13222e0fbcSChun-Jie Chen static const struct mtk_gate_regs imp_iic_wrap_cg_regs = { 14222e0fbcSChun-Jie Chen .set_ofs = 0xe08, 15222e0fbcSChun-Jie Chen .clr_ofs = 0xe04, 16222e0fbcSChun-Jie Chen .sta_ofs = 0xe00, 17222e0fbcSChun-Jie Chen }; 18222e0fbcSChun-Jie Chen 19222e0fbcSChun-Jie Chen #define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \ 20222e0fbcSChun-Jie Chen GATE_MTK_FLAGS(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, \ 21222e0fbcSChun-Jie Chen &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE) 22222e0fbcSChun-Jie Chen 23222e0fbcSChun-Jie Chen static const struct mtk_gate imp_iic_wrap_s_clks[] = { 24222e0fbcSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C5, "imp_iic_wrap_s_i2c5", "top_i2c", 0), 25222e0fbcSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C6, "imp_iic_wrap_s_i2c6", "top_i2c", 1), 26222e0fbcSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_S_I2C7, "imp_iic_wrap_s_i2c7", "top_i2c", 2), 27222e0fbcSChun-Jie Chen }; 28222e0fbcSChun-Jie Chen 29222e0fbcSChun-Jie Chen static const struct mtk_gate imp_iic_wrap_w_clks[] = { 30222e0fbcSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C0, "imp_iic_wrap_w_i2c0", "top_i2c", 0), 31222e0fbcSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C1, "imp_iic_wrap_w_i2c1", "top_i2c", 1), 32222e0fbcSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C2, "imp_iic_wrap_w_i2c2", "top_i2c", 2), 33222e0fbcSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C3, "imp_iic_wrap_w_i2c3", "top_i2c", 3), 34222e0fbcSChun-Jie Chen GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_W_I2C4, "imp_iic_wrap_w_i2c4", "top_i2c", 4), 35222e0fbcSChun-Jie Chen }; 36222e0fbcSChun-Jie Chen 37222e0fbcSChun-Jie Chen static const struct mtk_clk_desc imp_iic_wrap_s_desc = { 38222e0fbcSChun-Jie Chen .clks = imp_iic_wrap_s_clks, 39222e0fbcSChun-Jie Chen .num_clks = ARRAY_SIZE(imp_iic_wrap_s_clks), 40222e0fbcSChun-Jie Chen }; 41222e0fbcSChun-Jie Chen 42222e0fbcSChun-Jie Chen static const struct mtk_clk_desc imp_iic_wrap_w_desc = { 43222e0fbcSChun-Jie Chen .clks = imp_iic_wrap_w_clks, 44222e0fbcSChun-Jie Chen .num_clks = ARRAY_SIZE(imp_iic_wrap_w_clks), 45222e0fbcSChun-Jie Chen }; 46222e0fbcSChun-Jie Chen 47222e0fbcSChun-Jie Chen static const struct of_device_id of_match_clk_mt8195_imp_iic_wrap[] = { 48222e0fbcSChun-Jie Chen { 49222e0fbcSChun-Jie Chen .compatible = "mediatek,mt8195-imp_iic_wrap_s", 50222e0fbcSChun-Jie Chen .data = &imp_iic_wrap_s_desc, 51222e0fbcSChun-Jie Chen }, { 52222e0fbcSChun-Jie Chen .compatible = "mediatek,mt8195-imp_iic_wrap_w", 53222e0fbcSChun-Jie Chen .data = &imp_iic_wrap_w_desc, 54222e0fbcSChun-Jie Chen }, { 55222e0fbcSChun-Jie Chen /* sentinel */ 56222e0fbcSChun-Jie Chen } 57222e0fbcSChun-Jie Chen }; 5865c9ad77SAngeloGioacchino Del Regno MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_imp_iic_wrap); 59222e0fbcSChun-Jie Chen 60222e0fbcSChun-Jie Chen static struct platform_driver clk_mt8195_imp_iic_wrap_drv = { 61222e0fbcSChun-Jie Chen .probe = mtk_clk_simple_probe, 62*61ca6ee7SUwe Kleine-König .remove_new = mtk_clk_simple_remove, 63222e0fbcSChun-Jie Chen .driver = { 64222e0fbcSChun-Jie Chen .name = "clk-mt8195-imp_iic_wrap", 65222e0fbcSChun-Jie Chen .of_match_table = of_match_clk_mt8195_imp_iic_wrap, 66222e0fbcSChun-Jie Chen }, 67222e0fbcSChun-Jie Chen }; 68164d240dSAngeloGioacchino Del Regno module_platform_driver(clk_mt8195_imp_iic_wrap_drv); 69a451da86SAngeloGioacchino Del Regno MODULE_LICENSE("GPL"); 70