1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright (c) 2021 MediaTek Inc. 4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/mfd/syscon.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <linux/slab.h> 14 15 #include "clk-gate.h" 16 #include "clk-mtk.h" 17 #include "clk-mux.h" 18 #include "clk-pll.h" 19 20 #include <dt-bindings/clock/mt8192-clk.h> 21 22 static DEFINE_SPINLOCK(mt8192_clk_lock); 23 24 static const struct mtk_fixed_clk top_fixed_clks[] = { 25 FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 260000000), 26 }; 27 28 static const struct mtk_fixed_factor top_early_divs[] = { 29 FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2), 30 }; 31 32 static const struct mtk_fixed_factor top_divs[] = { 33 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3), 34 FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4), 35 FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2), 36 FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4), 37 FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8), 38 FACTOR(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16), 39 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5), 40 FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2), 41 FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4), 42 FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8), 43 FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6), 44 FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2), 45 FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4), 46 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7), 47 FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2), 48 FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4), 49 FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8), 50 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 51 FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4), 52 FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2), 53 FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4), 54 FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8), 55 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 56 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2), 57 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4), 58 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8), 59 FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6), 60 FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2), 61 FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4), 62 FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8), 63 FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16), 64 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 65 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 66 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2), 67 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4), 68 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8), 69 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), 70 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), 71 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), 72 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8), 73 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), 74 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2), 75 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), 76 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2), 77 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6), 78 FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2), 79 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), 80 FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9), 81 FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 2), 82 FACTOR(CLK_TOP_NPUPLL, "npupll_ck", "npupll", 1, 1), 83 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1), 84 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2), 85 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), 86 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8), 87 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16), 88 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 89 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 90 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), 91 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "ulposc", 1, 2), 92 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "ulposc", 1, 4), 93 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "ulposc", 1, 8), 94 FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10), 95 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16), 96 FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20), 97 FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1), 98 FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13), 99 FACTOR(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2), 100 FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4), 101 FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8), 102 FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16), 103 FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32), 104 }; 105 106 static const char * const axi_parents[] = { 107 "clk26m", 108 "mainpll_d4_d4", 109 "mainpll_d7_d2", 110 "mainpll_d4_d2", 111 "mainpll_d5_d2", 112 "mainpll_d6_d2", 113 "osc_d4" 114 }; 115 116 static const char * const spm_parents[] = { 117 "clk26m", 118 "osc_d10", 119 "mainpll_d7_d4", 120 "clk32k" 121 }; 122 123 static const char * const scp_parents[] = { 124 "clk26m", 125 "univpll_d5", 126 "mainpll_d6_d2", 127 "mainpll_d6", 128 "univpll_d6", 129 "mainpll_d4_d2", 130 "mainpll_d5_d2", 131 "univpll_d4_d2" 132 }; 133 134 static const char * const bus_aximem_parents[] = { 135 "clk26m", 136 "mainpll_d7_d2", 137 "mainpll_d4_d2", 138 "mainpll_d5_d2", 139 "mainpll_d6" 140 }; 141 142 static const char * const disp_parents[] = { 143 "clk26m", 144 "univpll_d6_d2", 145 "mainpll_d5_d2", 146 "mmpll_d6_d2", 147 "univpll_d5_d2", 148 "univpll_d4_d2", 149 "mmpll_d7", 150 "univpll_d6", 151 "mainpll_d4", 152 "mmpll_d5_d2" 153 }; 154 155 static const char * const mdp_parents[] = { 156 "clk26m", 157 "mainpll_d5_d2", 158 "mmpll_d6_d2", 159 "mainpll_d4_d2", 160 "mmpll_d4_d2", 161 "mainpll_d6", 162 "univpll_d6", 163 "mainpll_d4", 164 "tvdpll_ck", 165 "univpll_d4", 166 "mmpll_d5_d2" 167 }; 168 169 static const char * const img1_parents[] = { 170 "clk26m", 171 "univpll_d4", 172 "tvdpll_ck", 173 "mainpll_d4", 174 "univpll_d5", 175 "mmpll_d6", 176 "univpll_d6", 177 "mainpll_d6", 178 "mmpll_d4_d2", 179 "mainpll_d4_d2", 180 "mmpll_d6_d2", 181 "mmpll_d5_d2" 182 }; 183 184 static const char * const img2_parents[] = { 185 "clk26m", 186 "univpll_d4", 187 "tvdpll_ck", 188 "mainpll_d4", 189 "univpll_d5", 190 "mmpll_d6", 191 "univpll_d6", 192 "mainpll_d6", 193 "mmpll_d4_d2", 194 "mainpll_d4_d2", 195 "mmpll_d6_d2", 196 "mmpll_d5_d2" 197 }; 198 199 static const char * const ipe_parents[] = { 200 "clk26m", 201 "mainpll_d4", 202 "mmpll_d6", 203 "univpll_d6", 204 "mainpll_d6", 205 "univpll_d4_d2", 206 "mainpll_d4_d2", 207 "mmpll_d6_d2", 208 "mmpll_d5_d2" 209 }; 210 211 static const char * const dpe_parents[] = { 212 "clk26m", 213 "mainpll_d4", 214 "mmpll_d6", 215 "univpll_d6", 216 "mainpll_d6", 217 "univpll_d4_d2", 218 "univpll_d5_d2", 219 "mmpll_d6_d2" 220 }; 221 222 static const char * const cam_parents[] = { 223 "clk26m", 224 "mainpll_d4", 225 "mmpll_d6", 226 "univpll_d4", 227 "univpll_d5", 228 "univpll_d6", 229 "mmpll_d7", 230 "univpll_d4_d2", 231 "mainpll_d4_d2", 232 "univpll_d6_d2" 233 }; 234 235 static const char * const ccu_parents[] = { 236 "clk26m", 237 "mainpll_d4", 238 "mmpll_d6", 239 "mainpll_d6", 240 "mmpll_d7", 241 "univpll_d4_d2", 242 "mmpll_d6_d2", 243 "mmpll_d5_d2", 244 "univpll_d5", 245 "univpll_d6_d2" 246 }; 247 248 static const char * const dsp7_parents[] = { 249 "clk26m", 250 "mainpll_d4_d2", 251 "mainpll_d6", 252 "mmpll_d6", 253 "univpll_d5", 254 "mmpll_d5", 255 "univpll_d4", 256 "mmpll_d4" 257 }; 258 259 static const char * const mfg_ref_parents[] = { 260 "clk26m", 261 "clk26m", 262 "univpll_d6", 263 "mainpll_d5_d2" 264 }; 265 266 static const char * const mfg_pll_parents[] = { 267 "mfg_ref_sel", 268 "mfgpll" 269 }; 270 271 static const char * const camtg_parents[] = { 272 "clk26m", 273 "univpll_192m_d8", 274 "univpll_d6_d8", 275 "univpll_192m_d4", 276 "univpll_d6_d16", 277 "csw_f26m_d2", 278 "univpll_192m_d16", 279 "univpll_192m_d32" 280 }; 281 282 static const char * const camtg2_parents[] = { 283 "clk26m", 284 "univpll_192m_d8", 285 "univpll_d6_d8", 286 "univpll_192m_d4", 287 "univpll_d6_d16", 288 "csw_f26m_d2", 289 "univpll_192m_d16", 290 "univpll_192m_d32" 291 }; 292 293 static const char * const camtg3_parents[] = { 294 "clk26m", 295 "univpll_192m_d8", 296 "univpll_d6_d8", 297 "univpll_192m_d4", 298 "univpll_d6_d16", 299 "csw_f26m_d2", 300 "univpll_192m_d16", 301 "univpll_192m_d32" 302 }; 303 304 static const char * const camtg4_parents[] = { 305 "clk26m", 306 "univpll_192m_d8", 307 "univpll_d6_d8", 308 "univpll_192m_d4", 309 "univpll_d6_d16", 310 "csw_f26m_d2", 311 "univpll_192m_d16", 312 "univpll_192m_d32" 313 }; 314 315 static const char * const camtg5_parents[] = { 316 "clk26m", 317 "univpll_192m_d8", 318 "univpll_d6_d8", 319 "univpll_192m_d4", 320 "univpll_d6_d16", 321 "csw_f26m_d2", 322 "univpll_192m_d16", 323 "univpll_192m_d32" 324 }; 325 326 static const char * const camtg6_parents[] = { 327 "clk26m", 328 "univpll_192m_d8", 329 "univpll_d6_d8", 330 "univpll_192m_d4", 331 "univpll_d6_d16", 332 "csw_f26m_d2", 333 "univpll_192m_d16", 334 "univpll_192m_d32" 335 }; 336 337 static const char * const uart_parents[] = { 338 "clk26m", 339 "univpll_d6_d8" 340 }; 341 342 static const char * const spi_parents[] = { 343 "clk26m", 344 "mainpll_d5_d4", 345 "mainpll_d6_d4", 346 "msdcpll_d4" 347 }; 348 349 static const char * const msdc50_0_h_parents[] = { 350 "clk26m", 351 "mainpll_d4_d2", 352 "mainpll_d6_d2" 353 }; 354 355 static const char * const msdc50_0_parents[] = { 356 "clk26m", 357 "msdcpll_ck", 358 "msdcpll_d2", 359 "univpll_d4_d4", 360 "mainpll_d6_d2", 361 "univpll_d4_d2" 362 }; 363 364 static const char * const msdc30_1_parents[] = { 365 "clk26m", 366 "univpll_d6_d2", 367 "mainpll_d6_d2", 368 "mainpll_d7_d2", 369 "msdcpll_d2" 370 }; 371 372 static const char * const msdc30_2_parents[] = { 373 "clk26m", 374 "univpll_d6_d2", 375 "mainpll_d6_d2", 376 "mainpll_d7_d2", 377 "msdcpll_d2" 378 }; 379 380 static const char * const audio_parents[] = { 381 "clk26m", 382 "mainpll_d5_d8", 383 "mainpll_d7_d8", 384 "mainpll_d4_d16" 385 }; 386 387 static const char * const aud_intbus_parents[] = { 388 "clk26m", 389 "mainpll_d4_d4", 390 "mainpll_d7_d4" 391 }; 392 393 static const char * const pwrap_ulposc_parents[] = { 394 "osc_d10", 395 "clk26m", 396 "osc_d4", 397 "osc_d8", 398 "osc_d16" 399 }; 400 401 static const char * const atb_parents[] = { 402 "clk26m", 403 "mainpll_d4_d2", 404 "mainpll_d5_d2" 405 }; 406 407 static const char * const dpi_parents[] = { 408 "clk26m", 409 "tvdpll_d2", 410 "tvdpll_d4", 411 "tvdpll_d8", 412 "tvdpll_d16" 413 }; 414 415 static const char * const scam_parents[] = { 416 "clk26m", 417 "mainpll_d5_d4" 418 }; 419 420 static const char * const disp_pwm_parents[] = { 421 "clk26m", 422 "univpll_d6_d4", 423 "osc_d2", 424 "osc_d4", 425 "osc_d16" 426 }; 427 428 static const char * const usb_top_parents[] = { 429 "clk26m", 430 "univpll_d5_d4", 431 "univpll_d6_d4", 432 "univpll_d5_d2" 433 }; 434 435 static const char * const ssusb_xhci_parents[] = { 436 "clk26m", 437 "univpll_d5_d4", 438 "univpll_d6_d4", 439 "univpll_d5_d2" 440 }; 441 442 static const char * const i2c_parents[] = { 443 "clk26m", 444 "mainpll_d4_d8", 445 "univpll_d5_d4" 446 }; 447 448 static const char * const seninf_parents[] = { 449 "clk26m", 450 "univpll_d4_d4", 451 "univpll_d6_d2", 452 "univpll_d4_d2", 453 "univpll_d7", 454 "univpll_d6", 455 "mmpll_d6", 456 "univpll_d5" 457 }; 458 459 static const char * const seninf1_parents[] = { 460 "clk26m", 461 "univpll_d4_d4", 462 "univpll_d6_d2", 463 "univpll_d4_d2", 464 "univpll_d7", 465 "univpll_d6", 466 "mmpll_d6", 467 "univpll_d5" 468 }; 469 470 static const char * const seninf2_parents[] = { 471 "clk26m", 472 "univpll_d4_d4", 473 "univpll_d6_d2", 474 "univpll_d4_d2", 475 "univpll_d7", 476 "univpll_d6", 477 "mmpll_d6", 478 "univpll_d5" 479 }; 480 481 static const char * const seninf3_parents[] = { 482 "clk26m", 483 "univpll_d4_d4", 484 "univpll_d6_d2", 485 "univpll_d4_d2", 486 "univpll_d7", 487 "univpll_d6", 488 "mmpll_d6", 489 "univpll_d5" 490 }; 491 492 static const char * const tl_parents[] = { 493 "clk26m", 494 "univpll_192m_d2", 495 "mainpll_d6_d4" 496 }; 497 498 static const char * const dxcc_parents[] = { 499 "clk26m", 500 "mainpll_d4_d2", 501 "mainpll_d4_d4", 502 "mainpll_d4_d8" 503 }; 504 505 static const char * const aud_engen1_parents[] = { 506 "clk26m", 507 "apll1_d2", 508 "apll1_d4", 509 "apll1_d8" 510 }; 511 512 static const char * const aud_engen2_parents[] = { 513 "clk26m", 514 "apll2_d2", 515 "apll2_d4", 516 "apll2_d8" 517 }; 518 519 static const char * const aes_ufsfde_parents[] = { 520 "clk26m", 521 "mainpll_d4", 522 "mainpll_d4_d2", 523 "mainpll_d6", 524 "mainpll_d4_d4", 525 "univpll_d4_d2", 526 "univpll_d6" 527 }; 528 529 static const char * const ufs_parents[] = { 530 "clk26m", 531 "mainpll_d4_d4", 532 "mainpll_d4_d8", 533 "univpll_d4_d4", 534 "mainpll_d6_d2", 535 "mainpll_d5_d2", 536 "msdcpll_d2" 537 }; 538 539 static const char * const aud_1_parents[] = { 540 "clk26m", 541 "apll1_ck" 542 }; 543 544 static const char * const aud_2_parents[] = { 545 "clk26m", 546 "apll2_ck" 547 }; 548 549 static const char * const adsp_parents[] = { 550 "clk26m", 551 "mainpll_d6", 552 "mainpll_d5_d2", 553 "univpll_d4_d4", 554 "univpll_d4", 555 "univpll_d6", 556 "ulposc", 557 "adsppll_ck" 558 }; 559 560 static const char * const dpmaif_main_parents[] = { 561 "clk26m", 562 "univpll_d4_d4", 563 "mainpll_d6", 564 "mainpll_d4_d2", 565 "univpll_d4_d2" 566 }; 567 568 static const char * const venc_parents[] = { 569 "clk26m", 570 "mmpll_d7", 571 "mainpll_d6", 572 "univpll_d4_d2", 573 "mainpll_d4_d2", 574 "univpll_d6", 575 "mmpll_d6", 576 "mainpll_d5_d2", 577 "mainpll_d6_d2", 578 "mmpll_d9", 579 "univpll_d4_d4", 580 "mainpll_d4", 581 "univpll_d4", 582 "univpll_d5", 583 "univpll_d5_d2", 584 "mainpll_d5" 585 }; 586 587 static const char * const vdec_parents[] = { 588 "clk26m", 589 "univpll_192m_d2", 590 "univpll_d5_d4", 591 "mainpll_d5", 592 "mainpll_d5_d2", 593 "mmpll_d6_d2", 594 "univpll_d5_d2", 595 "mainpll_d4_d2", 596 "univpll_d4_d2", 597 "univpll_d7", 598 "mmpll_d7", 599 "mmpll_d6", 600 "univpll_d5", 601 "mainpll_d4", 602 "univpll_d4", 603 "univpll_d6" 604 }; 605 606 static const char * const camtm_parents[] = { 607 "clk26m", 608 "univpll_d7", 609 "univpll_d6_d2", 610 "univpll_d4_d2" 611 }; 612 613 static const char * const pwm_parents[] = { 614 "clk26m", 615 "univpll_d4_d8" 616 }; 617 618 static const char * const audio_h_parents[] = { 619 "clk26m", 620 "univpll_d7", 621 "apll1_ck", 622 "apll2_ck" 623 }; 624 625 static const char * const spmi_mst_parents[] = { 626 "clk26m", 627 "csw_f26m_d2", 628 "osc_d8", 629 "osc_d10", 630 "osc_d16", 631 "osc_d20", 632 "clk32k" 633 }; 634 635 static const char * const aes_msdcfde_parents[] = { 636 "clk26m", 637 "mainpll_d4_d2", 638 "mainpll_d6", 639 "mainpll_d4_d4", 640 "univpll_d4_d2", 641 "univpll_d6" 642 }; 643 644 static const char * const sflash_parents[] = { 645 "clk26m", 646 "mainpll_d7_d8", 647 "univpll_d6_d8", 648 "univpll_d5_d8" 649 }; 650 651 static const char * const apll_i2s0_m_parents[] = { 652 "aud_1_sel", 653 "aud_2_sel" 654 }; 655 656 static const char * const apll_i2s1_m_parents[] = { 657 "aud_1_sel", 658 "aud_2_sel" 659 }; 660 661 static const char * const apll_i2s2_m_parents[] = { 662 "aud_1_sel", 663 "aud_2_sel" 664 }; 665 666 static const char * const apll_i2s3_m_parents[] = { 667 "aud_1_sel", 668 "aud_2_sel" 669 }; 670 671 static const char * const apll_i2s4_m_parents[] = { 672 "aud_1_sel", 673 "aud_2_sel" 674 }; 675 676 static const char * const apll_i2s5_m_parents[] = { 677 "aud_1_sel", 678 "aud_2_sel" 679 }; 680 681 static const char * const apll_i2s6_m_parents[] = { 682 "aud_1_sel", 683 "aud_2_sel" 684 }; 685 686 static const char * const apll_i2s7_m_parents[] = { 687 "aud_1_sel", 688 "aud_2_sel" 689 }; 690 691 static const char * const apll_i2s8_m_parents[] = { 692 "aud_1_sel", 693 "aud_2_sel" 694 }; 695 696 static const char * const apll_i2s9_m_parents[] = { 697 "aud_1_sel", 698 "aud_2_sel" 699 }; 700 701 /* 702 * CRITICAL CLOCK: 703 * axi_sel is the main bus clock of whole SOC. 704 * spm_sel is the clock of the always-on co-processor. 705 * bus_aximem_sel is clock of the bus that access emi. 706 */ 707 static const struct mtk_mux top_mtk_muxes[] = { 708 /* CLK_CFG_0 */ 709 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", 710 axi_parents, 0x010, 0x014, 0x018, 0, 3, 7, 0x004, 0, 711 CLK_IS_CRITICAL), 712 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", 713 spm_parents, 0x010, 0x014, 0x018, 8, 2, 15, 0x004, 1, 714 CLK_IS_CRITICAL), 715 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", 716 scp_parents, 0x010, 0x014, 0x018, 16, 3, 23, 0x004, 2), 717 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel", 718 bus_aximem_parents, 0x010, 0x014, 0x018, 24, 3, 31, 0x004, 3, 719 CLK_IS_CRITICAL), 720 /* CLK_CFG_1 */ 721 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, "disp_sel", 722 disp_parents, 0x020, 0x024, 0x028, 0, 4, 7, 0x004, 4), 723 MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, "mdp_sel", 724 mdp_parents, 0x020, 0x024, 0x028, 8, 4, 15, 0x004, 5), 725 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel", 726 img1_parents, 0x020, 0x024, 0x028, 16, 4, 23, 0x004, 6), 727 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG2_SEL, "img2_sel", 728 img2_parents, 0x020, 0x024, 0x028, 24, 4, 31, 0x004, 7), 729 /* CLK_CFG_2 */ 730 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel", 731 ipe_parents, 0x030, 0x034, 0x038, 0, 4, 7, 0x004, 8), 732 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE_SEL, "dpe_sel", 733 dpe_parents, 0x030, 0x034, 0x038, 8, 3, 15, 0x004, 9), 734 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel", 735 cam_parents, 0x030, 0x034, 0x038, 16, 4, 23, 0x004, 10), 736 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel", 737 ccu_parents, 0x030, 0x034, 0x038, 24, 4, 31, 0x004, 11), 738 /* CLK_CFG_4 */ 739 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel", 740 dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16), 741 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel", 742 mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18), 743 MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel", 744 mfg_pll_parents, 0x050, 0x054, 0x058, 18, 1, -1, -1), 745 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", 746 camtg_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x004, 19), 747 /* CLK_CFG_5 */ 748 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel", 749 camtg2_parents, 0x060, 0x064, 0x068, 0, 3, 7, 0x004, 20), 750 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", 751 camtg3_parents, 0x060, 0x064, 0x068, 8, 3, 15, 0x004, 21), 752 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4_SEL, "camtg4_sel", 753 camtg4_parents, 0x060, 0x064, 0x068, 16, 3, 23, 0x004, 22), 754 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5_SEL, "camtg5_sel", 755 camtg5_parents, 0x060, 0x064, 0x068, 24, 3, 31, 0x004, 23), 756 /* CLK_CFG_6 */ 757 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6_SEL, "camtg6_sel", 758 camtg6_parents, 0x070, 0x074, 0x078, 0, 3, 7, 0x004, 24), 759 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", 760 uart_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25), 761 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", 762 spi_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x004, 26), 763 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", 764 msdc50_0_h_parents, 0x070, 0x074, 0x078, 24, 2, 31, 0x004, 27), 765 /* CLK_CFG_7 */ 766 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 767 msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28), 768 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 769 msdc30_1_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29), 770 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", 771 msdc30_2_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30), 772 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", 773 audio_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x008, 0), 774 /* CLK_CFG_8 */ 775 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", 776 aud_intbus_parents, 0x090, 0x094, 0x098, 0, 2, 7, 0x008, 1), 777 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL, "pwrap_ulposc_sel", 778 pwrap_ulposc_parents, 0x090, 0x094, 0x098, 8, 3, 15, 0x008, 2), 779 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", 780 atb_parents, 0x090, 0x094, 0x098, 16, 2, 23, 0x008, 3), 781 /* CLK_CFG_9 */ 782 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI_SEL, "dpi_sel", 783 dpi_parents, 0x0a0, 0x0a4, 0x0a8, 0, 3, 7, 0x008, 5), 784 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM_SEL, "scam_sel", 785 scam_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x008, 6), 786 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel", 787 disp_pwm_parents, 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, 0x008, 7), 788 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel", 789 usb_top_parents, 0x0a0, 0x0a4, 0x0a8, 24, 2, 31, 0x008, 8), 790 /* CLK_CFG_10 */ 791 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel", 792 ssusb_xhci_parents, 0x0b0, 0x0b4, 0x0b8, 0, 2, 7, 0x008, 9), 793 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", 794 i2c_parents, 0x0b0, 0x0b4, 0x0b8, 8, 2, 15, 0x008, 10), 795 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel", 796 seninf_parents, 0x0b0, 0x0b4, 0x0b8, 16, 3, 23, 0x008, 11), 797 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, "seninf1_sel", 798 seninf1_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x008, 12), 799 /* CLK_CFG_11 */ 800 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL, "seninf2_sel", 801 seninf2_parents, 0x0c0, 0x0c4, 0x0c8, 0, 3, 7, 0x008, 13), 802 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL, "seninf3_sel", 803 seninf3_parents, 0x0c0, 0x0c4, 0x0c8, 8, 3, 15, 0x008, 14), 804 MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_SEL, "tl_sel", 805 tl_parents, 0x0c0, 0x0c4, 0x0c8, 16, 2, 23, 0x008, 15), 806 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", 807 dxcc_parents, 0x0c0, 0x0c4, 0x0c8, 24, 2, 31, 0x008, 16), 808 /* CLK_CFG_12 */ 809 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", 810 aud_engen1_parents, 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x008, 17), 811 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", 812 aud_engen2_parents, 0x0d0, 0x0d4, 0x0d8, 8, 2, 15, 0x008, 18), 813 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, "aes_ufsfde_sel", 814 aes_ufsfde_parents, 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, 0x008, 19), 815 MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_SEL, "ufs_sel", 816 ufs_parents, 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, 0x008, 20), 817 /* CLK_CFG_13 */ 818 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", 819 aud_1_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, 0x008, 21), 820 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", 821 aud_2_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, 0x008, 22), 822 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_SEL, "adsp_sel", 823 adsp_parents, 0x0e0, 0x0e4, 0x0e8, 16, 3, 23, 0x008, 23), 824 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN_SEL, "dpmaif_main_sel", 825 dpmaif_main_parents, 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, 0x008, 24), 826 /* CLK_CFG_14 */ 827 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel", 828 venc_parents, 0x0f0, 0x0f4, 0x0f8, 0, 4, 7, 0x008, 25), 829 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel", 830 vdec_parents, 0x0f0, 0x0f4, 0x0f8, 8, 4, 15, 0x008, 26), 831 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", 832 camtm_parents, 0x0f0, 0x0f4, 0x0f8, 16, 2, 23, 0x008, 27), 833 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", 834 pwm_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, 31, 0x008, 28), 835 /* CLK_CFG_15 */ 836 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, "audio_h_sel", 837 audio_h_parents, 0x100, 0x104, 0x108, 0, 2, 7, 0x008, 29), 838 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST_SEL, "spmi_mst_sel", 839 spmi_mst_parents, 0x100, 0x104, 0x108, 8, 3, 15, 0x008, 30), 840 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel", 841 aes_msdcfde_parents, 0x100, 0x104, 0x108, 24, 3, 31, 0x00c, 1), 842 /* CLK_CFG_16 */ 843 MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel", 844 sflash_parents, 0x110, 0x114, 0x118, 8, 2, 15, 0x00c, 3), 845 }; 846 847 static struct mtk_composite top_muxes[] = { 848 /* CLK_AUDDIV_0 */ 849 MUX(CLK_TOP_APLL_I2S0_M_SEL, "apll_i2s0_m_sel", apll_i2s0_m_parents, 0x320, 16, 1), 850 MUX(CLK_TOP_APLL_I2S1_M_SEL, "apll_i2s1_m_sel", apll_i2s1_m_parents, 0x320, 17, 1), 851 MUX(CLK_TOP_APLL_I2S2_M_SEL, "apll_i2s2_m_sel", apll_i2s2_m_parents, 0x320, 18, 1), 852 MUX(CLK_TOP_APLL_I2S3_M_SEL, "apll_i2s3_m_sel", apll_i2s3_m_parents, 0x320, 19, 1), 853 MUX(CLK_TOP_APLL_I2S4_M_SEL, "apll_i2s4_m_sel", apll_i2s4_m_parents, 0x320, 20, 1), 854 MUX(CLK_TOP_APLL_I2S5_M_SEL, "apll_i2s5_m_sel", apll_i2s5_m_parents, 0x320, 21, 1), 855 MUX(CLK_TOP_APLL_I2S6_M_SEL, "apll_i2s6_m_sel", apll_i2s6_m_parents, 0x320, 22, 1), 856 MUX(CLK_TOP_APLL_I2S7_M_SEL, "apll_i2s7_m_sel", apll_i2s7_m_parents, 0x320, 23, 1), 857 MUX(CLK_TOP_APLL_I2S8_M_SEL, "apll_i2s8_m_sel", apll_i2s8_m_parents, 0x320, 24, 1), 858 MUX(CLK_TOP_APLL_I2S9_M_SEL, "apll_i2s9_m_sel", apll_i2s9_m_parents, 0x320, 25, 1), 859 }; 860 861 static const struct mtk_composite top_adj_divs[] = { 862 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_m_sel", 0x320, 0, 0x328, 8, 0), 863 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_m_sel", 0x320, 1, 0x328, 8, 8), 864 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_m_sel", 0x320, 2, 0x328, 8, 16), 865 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_m_sel", 0x320, 3, 0x328, 8, 24), 866 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_m_sel", 0x320, 4, 0x334, 8, 0), 867 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 5, 0x334, 8, 8), 868 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll_i2s5_m_sel", 0x320, 6, 0x334, 8, 16), 869 DIV_GATE(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll_i2s6_m_sel", 0x320, 7, 0x334, 8, 24), 870 DIV_GATE(CLK_TOP_APLL12_DIV7, "apll12_div7", "apll_i2s7_m_sel", 0x320, 8, 0x338, 8, 0), 871 DIV_GATE(CLK_TOP_APLL12_DIV8, "apll12_div8", "apll_i2s8_m_sel", 0x320, 9, 0x338, 8, 8), 872 DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "apll_i2s9_m_sel", 0x320, 10, 0x338, 8, 16), 873 }; 874 875 static const struct mtk_gate_regs apmixed_cg_regs = { 876 .set_ofs = 0x14, 877 .clr_ofs = 0x14, 878 .sta_ofs = 0x14, 879 }; 880 881 #define GATE_APMIXED(_id, _name, _parent, _shift) \ 882 GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 883 884 static const struct mtk_gate apmixed_clks[] = { 885 GATE_APMIXED(CLK_APMIXED_MIPID26M, "mipid26m", "clk26m", 16), 886 }; 887 888 static const struct mtk_gate_regs infra0_cg_regs = { 889 .set_ofs = 0x80, 890 .clr_ofs = 0x84, 891 .sta_ofs = 0x90, 892 }; 893 894 static const struct mtk_gate_regs infra1_cg_regs = { 895 .set_ofs = 0x88, 896 .clr_ofs = 0x8c, 897 .sta_ofs = 0x94, 898 }; 899 900 static const struct mtk_gate_regs infra2_cg_regs = { 901 .set_ofs = 0xa4, 902 .clr_ofs = 0xa8, 903 .sta_ofs = 0xac, 904 }; 905 906 static const struct mtk_gate_regs infra3_cg_regs = { 907 .set_ofs = 0xc0, 908 .clr_ofs = 0xc4, 909 .sta_ofs = 0xc8, 910 }; 911 912 static const struct mtk_gate_regs infra4_cg_regs = { 913 .set_ofs = 0xd0, 914 .clr_ofs = 0xd4, 915 .sta_ofs = 0xd8, 916 }; 917 918 static const struct mtk_gate_regs infra5_cg_regs = { 919 .set_ofs = 0xe0, 920 .clr_ofs = 0xe4, 921 .sta_ofs = 0xe8, 922 }; 923 924 #define GATE_INFRA0(_id, _name, _parent, _shift) \ 925 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 926 927 #define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flag) \ 928 GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \ 929 &mtk_clk_gate_ops_setclr, _flag) 930 931 #define GATE_INFRA1(_id, _name, _parent, _shift) \ 932 GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0) 933 934 #define GATE_INFRA2(_id, _name, _parent, _shift) \ 935 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 936 937 #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag) \ 938 GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, \ 939 &mtk_clk_gate_ops_setclr, _flag) 940 941 #define GATE_INFRA3(_id, _name, _parent, _shift) \ 942 GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0) 943 944 #define GATE_INFRA4(_id, _name, _parent, _shift) \ 945 GATE_MTK(_id, _name, _parent, &infra4_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 946 947 #define GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, _flag) \ 948 GATE_MTK_FLAGS(_id, _name, _parent, &infra5_cg_regs, _shift, \ 949 &mtk_clk_gate_ops_setclr, _flag) 950 951 #define GATE_INFRA5(_id, _name, _parent, _shift) \ 952 GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, 0) 953 954 /* 955 * CRITICAL CLOCK: 956 * infra_133m and infra_66m are main peripheral bus clocks of SOC. 957 * infra_device_apc and infra_device_apc_sync are for device access permission control module. 958 */ 959 static const struct mtk_gate infra_clks[] = { 960 /* INFRA0 */ 961 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "pwrap_ulposc_sel", 0), 962 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pwrap_ulposc_sel", 1), 963 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pwrap_ulposc_sel", 2), 964 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pwrap_ulposc_sel", 3), 965 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4), 966 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5), 967 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6), 968 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 8), 969 GATE_INFRA0(CLK_INFRA_GCE2, "infra_gce2", "axi_sel", 9), 970 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10), 971 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11), 972 GATE_INFRA0(CLK_INFRA_AP_DMA_PSEUDO, "infra_ap_dma_pseudo", "axi_sel", 12), 973 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13), 974 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14), 975 GATE_INFRA0(CLK_INFRA_PWM_H, "infra_pwm_h", "axi_sel", 15), 976 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "pwm_sel", 16), 977 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "pwm_sel", 17), 978 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "pwm_sel", 18), 979 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "pwm_sel", 19), 980 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21), 981 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22), 982 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), 983 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24), 984 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25), 985 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27), 986 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cq_dma_fpc", "axi_sel", 28), 987 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31), 988 /* INFRA1 */ 989 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1), 990 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_h_sel", 2), 991 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc50_0_h_sel", 4), 992 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc50_0_h_sel", 5), 993 GATE_INFRA1(CLK_INFRA_MSDC0_SRC, "infra_msdc0_src", "msdc50_0_sel", 6), 994 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8), 995 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9), 996 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10), 997 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11), 998 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12), 999 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13), 1000 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "clk26m", 14), 1001 GATE_INFRA1(CLK_INFRA_PCIE_TL_26M, "infra_pcie_tl_26m", "axi_sel", 15), 1002 GATE_INFRA1(CLK_INFRA_MSDC1_SRC, "infra_msdc1_src", "msdc30_1_sel", 16), 1003 GATE_INFRA1(CLK_INFRA_MSDC2_SRC, "infra_msdc2_src", "msdc30_2_sel", 17), 1004 GATE_INFRA1(CLK_INFRA_PCIE_TL_96M, "infra_pcie_tl_96m", "tl_sel", 18), 1005 GATE_INFRA1(CLK_INFRA_PCIE_PL_P_250M, "infra_pcie_pl_p_250m", "axi_sel", 19), 1006 GATE_INFRA1_FLAGS(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20, CLK_IS_CRITICAL), 1007 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23), 1008 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24), 1009 GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25), 1010 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26), 1011 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 27), 1012 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28), 1013 GATE_INFRA1(CLK_INFRA_DBG_TRACE, "infra_dbg_trace", "axi_sel", 29), 1014 GATE_INFRA1(CLK_INFRA_DEVMPU_B, "infra_devmpu_b", "axi_sel", 30), 1015 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31), 1016 /* INFRA2 */ 1017 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "clk26m", 0), 1018 GATE_INFRA2(CLK_INFRA_SSUSB, "infra_ssusb", "usb_top_sel", 1), 1019 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "axi_sel", 2), 1020 GATE_INFRA2(CLK_INFRA_CLDMA_B, "infra_cldma_b", "axi_sel", 3), 1021 GATE_INFRA2(CLK_INFRA_AUDIO_26M_B, "infra_audio_26m_b", "clk26m", 4), 1022 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share", "clk26m", 5), 1023 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6), 1024 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7), 1025 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9), 1026 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10), 1027 GATE_INFRA2(CLK_INFRA_UNIPRO_SYS, "infra_unipro_sys", "ufs_sel", 11), 1028 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "clk26m", 12), 1029 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_B, "infra_ufs_mp_sap_b", "clk26m", 13), 1030 GATE_INFRA2(CLK_INFRA_MD32_B, "infra_md32_b", "axi_sel", 14), 1031 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16), 1032 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18), 1033 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19), 1034 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20), 1035 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21), 1036 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22), 1037 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23), 1038 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24), 1039 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25), 1040 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26), 1041 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cq_dma", "axi_sel", 27), 1042 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "ufs_sel", 28), 1043 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "aes_ufsfde_sel", 29), 1044 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "ufs_sel", 30), 1045 GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci", "ssusb_xhci_sel", 31), 1046 /* INFRA3 */ 1047 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0), 1048 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1), 1049 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2), 1050 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5), 1051 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6), 1052 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_0_sel", 7), 1053 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_0_sel", 8), 1054 GATE_INFRA3(CLK_INFRA_CCIF5_AP, "infra_ccif5_ap", "axi_sel", 9), 1055 GATE_INFRA3(CLK_INFRA_CCIF5_MD, "infra_ccif5_md", "axi_sel", 10), 1056 GATE_INFRA3(CLK_INFRA_PCIE_TOP_H_133M, "infra_pcie_top_h_133m", "axi_sel", 11), 1057 GATE_INFRA3(CLK_INFRA_FLASHIF_TOP_H_133M, "infra_flashif_top_h_133m", "axi_sel", 14), 1058 GATE_INFRA3(CLK_INFRA_PCIE_PERI_26M, "infra_pcie_peri_26m", "axi_sel", 15), 1059 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16), 1060 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17), 1061 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18), 1062 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19), 1063 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "clk26m", 20), 1064 GATE_INFRA3(CLK_INFRA_AES, "infra_aes", "axi_sel", 21), 1065 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22), 1066 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23), 1067 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24), 1068 GATE_INFRA3_FLAGS(CLK_INFRA_DEVICE_APC_SYNC, "infra_device_apc_sync", "axi_sel", 25, 1069 CLK_IS_CRITICAL), 1070 GATE_INFRA3(CLK_INFRA_DPMAIF_MAIN, "infra_dpmaif_main", "dpmaif_main_sel", 26), 1071 GATE_INFRA3(CLK_INFRA_PCIE_TL_32K, "infra_pcie_tl_32k", "axi_sel", 27), 1072 GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap", "axi_sel", 28), 1073 GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md", "axi_sel", 29), 1074 GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6", "spi_sel", 30), 1075 GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7", "spi_sel", 31), 1076 /* INFRA4 */ 1077 GATE_INFRA4(CLK_INFRA_AP_DMA, "infra_ap_dma", "infra_ap_dma_pseudo", 31), 1078 /* INFRA5 */ 1079 GATE_INFRA5_FLAGS(CLK_INFRA_133M, "infra_133m", "axi_sel", 0, CLK_IS_CRITICAL), 1080 GATE_INFRA5_FLAGS(CLK_INFRA_66M, "infra_66m", "axi_sel", 1, CLK_IS_CRITICAL), 1081 GATE_INFRA5(CLK_INFRA_66M_PERI_BUS, "infra_66m_peri_bus", "axi_sel", 2), 1082 GATE_INFRA5(CLK_INFRA_FREE_DCM_133M, "infra_free_dcm_133m", "axi_sel", 3), 1083 GATE_INFRA5(CLK_INFRA_FREE_DCM_66M, "infra_free_dcm_66m", "axi_sel", 4), 1084 GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_133M, "infra_peri_bus_dcm_133m", "axi_sel", 5), 1085 GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_66M, "infra_peri_bus_dcm_66m", "axi_sel", 6), 1086 GATE_INFRA5(CLK_INFRA_FLASHIF_PERI_26M, "infra_flashif_peri_26m", "axi_sel", 30), 1087 GATE_INFRA5(CLK_INFRA_FLASHIF_SFLASH, "infra_flashif_fsflash", "axi_sel", 31), 1088 }; 1089 1090 static const struct mtk_gate_regs peri_cg_regs = { 1091 .set_ofs = 0x20c, 1092 .clr_ofs = 0x20c, 1093 .sta_ofs = 0x20c, 1094 }; 1095 1096 #define GATE_PERI(_id, _name, _parent, _shift) \ 1097 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 1098 1099 static const struct mtk_gate peri_clks[] = { 1100 GATE_PERI(CLK_PERI_PERIAXI, "peri_periaxi", "axi_sel", 31), 1101 }; 1102 1103 static const struct mtk_gate_regs top_cg_regs = { 1104 .set_ofs = 0x150, 1105 .clr_ofs = 0x150, 1106 .sta_ofs = 0x150, 1107 }; 1108 1109 #define GATE_TOP(_id, _name, _parent, _shift) \ 1110 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 1111 1112 static const struct mtk_gate top_clks[] = { 1113 GATE_TOP(CLK_TOP_SSUSB_TOP_REF, "ssusb_top_ref", "clk26m", 24), 1114 GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25), 1115 }; 1116 1117 #define MT8192_PLL_FMAX (3800UL * MHZ) 1118 #define MT8192_PLL_FMIN (1500UL * MHZ) 1119 #define MT8192_INTEGER_BITS 8 1120 1121 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1122 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 1123 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 1124 _pcw_reg, _pcw_shift, _pcw_chg_reg, \ 1125 _en_reg, _pll_en_bit) { \ 1126 .id = _id, \ 1127 .name = _name, \ 1128 .reg = _reg, \ 1129 .pwr_reg = _pwr_reg, \ 1130 .en_mask = _en_mask, \ 1131 .flags = _flags, \ 1132 .rst_bar_mask = _rst_bar_mask, \ 1133 .fmax = MT8192_PLL_FMAX, \ 1134 .fmin = MT8192_PLL_FMIN, \ 1135 .pcwbits = _pcwbits, \ 1136 .pcwibits = MT8192_INTEGER_BITS, \ 1137 .pd_reg = _pd_reg, \ 1138 .pd_shift = _pd_shift, \ 1139 .tuner_reg = _tuner_reg, \ 1140 .tuner_en_reg = _tuner_en_reg, \ 1141 .tuner_en_bit = _tuner_en_bit, \ 1142 .pcw_reg = _pcw_reg, \ 1143 .pcw_shift = _pcw_shift, \ 1144 .pcw_chg_reg = _pcw_chg_reg, \ 1145 .en_reg = _en_reg, \ 1146 .pll_en_bit = _pll_en_bit, \ 1147 } 1148 1149 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1150 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 1151 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 1152 _pcw_reg, _pcw_shift) \ 1153 PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1154 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 1155 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 1156 _pcw_reg, _pcw_shift, 0, 0, 0) 1157 1158 static const struct mtk_pll_data plls[] = { 1159 PLL_B(CLK_APMIXED_MAINPLL, "mainpll", 0x0340, 0x034c, 0xff000000, 1160 HAVE_RST_BAR, BIT(23), 22, 0x0344, 24, 0, 0, 0, 0x0344, 0), 1161 PLL_B(CLK_APMIXED_UNIVPLL, "univpll", 0x0308, 0x0314, 0xff000000, 1162 HAVE_RST_BAR, BIT(23), 22, 0x030c, 24, 0, 0, 0, 0x030c, 0), 1163 PLL(CLK_APMIXED_USBPLL, "usbpll", 0x03c4, 0x03cc, 0x00000000, 1164 0, 0, 22, 0x03c4, 24, 0, 0, 0, 0x03c4, 0, 0x03c4, 0x03cc, 2), 1165 PLL_B(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035c, 0x00000000, 1166 0, 0, 22, 0x0354, 24, 0, 0, 0, 0x0354, 0), 1167 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0360, 0x036c, 0xff000000, 1168 HAVE_RST_BAR, BIT(23), 22, 0x0364, 24, 0, 0, 0, 0x0364, 0), 1169 PLL_B(CLK_APMIXED_ADSPPLL, "adsppll", 0x0370, 0x037c, 0xff000000, 1170 HAVE_RST_BAR, BIT(23), 22, 0x0374, 24, 0, 0, 0, 0x0374, 0), 1171 PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0268, 0x0274, 0x00000000, 1172 0, 0, 22, 0x026c, 24, 0, 0, 0, 0x026c, 0), 1173 PLL_B(CLK_APMIXED_TVDPLL, "tvdpll", 0x0380, 0x038c, 0x00000000, 1174 0, 0, 22, 0x0384, 24, 0, 0, 0, 0x0384, 0), 1175 PLL_B(CLK_APMIXED_APLL1, "apll1", 0x0318, 0x0328, 0x00000000, 1176 0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0), 1177 PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000000, 1178 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0), 1179 }; 1180 1181 static struct clk_hw_onecell_data *top_clk_data; 1182 1183 static void clk_mt8192_top_init_early(struct device_node *node) 1184 { 1185 int i; 1186 1187 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 1188 if (!top_clk_data) 1189 return; 1190 1191 for (i = 0; i < CLK_TOP_NR_CLK; i++) 1192 top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); 1193 1194 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data); 1195 1196 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); 1197 } 1198 1199 CLK_OF_DECLARE_DRIVER(mt8192_topckgen, "mediatek,mt8192-topckgen", 1200 clk_mt8192_top_init_early); 1201 1202 static int clk_mt8192_top_probe(struct platform_device *pdev) 1203 { 1204 struct device_node *node = pdev->dev.of_node; 1205 int r; 1206 void __iomem *base; 1207 1208 base = devm_platform_ioremap_resource(pdev, 0); 1209 if (IS_ERR(base)) 1210 return PTR_ERR(base); 1211 1212 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data); 1213 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data); 1214 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); 1215 mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node, &mt8192_clk_lock, 1216 top_clk_data); 1217 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, &mt8192_clk_lock, 1218 top_clk_data); 1219 mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt8192_clk_lock, 1220 top_clk_data); 1221 r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data); 1222 if (r) 1223 return r; 1224 1225 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, 1226 top_clk_data); 1227 } 1228 1229 static int clk_mt8192_infra_probe(struct platform_device *pdev) 1230 { 1231 struct clk_hw_onecell_data *clk_data; 1232 struct device_node *node = pdev->dev.of_node; 1233 int r; 1234 1235 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 1236 if (!clk_data) 1237 return -ENOMEM; 1238 1239 r = mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data); 1240 if (r) 1241 goto free_clk_data; 1242 1243 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1244 if (r) 1245 goto free_clk_data; 1246 1247 return r; 1248 1249 free_clk_data: 1250 mtk_free_clk_data(clk_data); 1251 return r; 1252 } 1253 1254 static int clk_mt8192_peri_probe(struct platform_device *pdev) 1255 { 1256 struct clk_hw_onecell_data *clk_data; 1257 struct device_node *node = pdev->dev.of_node; 1258 int r; 1259 1260 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); 1261 if (!clk_data) 1262 return -ENOMEM; 1263 1264 r = mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), clk_data); 1265 if (r) 1266 goto free_clk_data; 1267 1268 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1269 if (r) 1270 goto free_clk_data; 1271 1272 return r; 1273 1274 free_clk_data: 1275 mtk_free_clk_data(clk_data); 1276 return r; 1277 } 1278 1279 static int clk_mt8192_apmixed_probe(struct platform_device *pdev) 1280 { 1281 struct clk_hw_onecell_data *clk_data; 1282 struct device_node *node = pdev->dev.of_node; 1283 int r; 1284 1285 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 1286 if (!clk_data) 1287 return -ENOMEM; 1288 1289 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 1290 r = mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); 1291 if (r) 1292 goto free_clk_data; 1293 1294 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1295 if (r) 1296 goto free_clk_data; 1297 1298 return r; 1299 1300 free_clk_data: 1301 mtk_free_clk_data(clk_data); 1302 return r; 1303 } 1304 1305 static const struct of_device_id of_match_clk_mt8192[] = { 1306 { 1307 .compatible = "mediatek,mt8192-apmixedsys", 1308 .data = clk_mt8192_apmixed_probe, 1309 }, { 1310 .compatible = "mediatek,mt8192-topckgen", 1311 .data = clk_mt8192_top_probe, 1312 }, { 1313 .compatible = "mediatek,mt8192-infracfg", 1314 .data = clk_mt8192_infra_probe, 1315 }, { 1316 .compatible = "mediatek,mt8192-pericfg", 1317 .data = clk_mt8192_peri_probe, 1318 }, { 1319 /* sentinel */ 1320 } 1321 }; 1322 1323 static int clk_mt8192_probe(struct platform_device *pdev) 1324 { 1325 int (*clk_probe)(struct platform_device *pdev); 1326 int r; 1327 1328 clk_probe = of_device_get_match_data(&pdev->dev); 1329 if (!clk_probe) 1330 return -EINVAL; 1331 1332 r = clk_probe(pdev); 1333 if (r) 1334 dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); 1335 1336 return r; 1337 } 1338 1339 static struct platform_driver clk_mt8192_drv = { 1340 .probe = clk_mt8192_probe, 1341 .driver = { 1342 .name = "clk-mt8192", 1343 .of_match_table = of_match_clk_mt8192, 1344 }, 1345 }; 1346 1347 static int __init clk_mt8192_init(void) 1348 { 1349 return platform_driver_register(&clk_mt8192_drv); 1350 } 1351 1352 arch_initcall(clk_mt8192_init); 1353