1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright (c) 2021 MediaTek Inc. 4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/mfd/syscon.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <linux/slab.h> 14 15 #include "clk-gate.h" 16 #include "clk-mtk.h" 17 #include "clk-mux.h" 18 #include "clk-pll.h" 19 20 #include <dt-bindings/clock/mt8192-clk.h> 21 #include <dt-bindings/reset/mt8192-resets.h> 22 23 static DEFINE_SPINLOCK(mt8192_clk_lock); 24 25 static const struct mtk_fixed_clk top_fixed_clks[] = { 26 FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 260000000), 27 }; 28 29 static const struct mtk_fixed_factor top_early_divs[] = { 30 FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2), 31 }; 32 33 static const struct mtk_fixed_factor top_divs[] = { 34 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3), 35 FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4), 36 FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2), 37 FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4), 38 FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8), 39 FACTOR(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16), 40 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5), 41 FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2), 42 FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4), 43 FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8), 44 FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6), 45 FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2), 46 FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4), 47 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7), 48 FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2), 49 FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4), 50 FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8), 51 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 52 FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4), 53 FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2), 54 FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4), 55 FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8), 56 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 57 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2), 58 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4), 59 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8), 60 FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6), 61 FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2), 62 FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4), 63 FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8), 64 FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16), 65 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 66 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 67 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2), 68 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4), 69 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8), 70 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), 71 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), 72 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), 73 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8), 74 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), 75 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2), 76 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), 77 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2), 78 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6), 79 FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2), 80 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), 81 FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9), 82 FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 2), 83 FACTOR(CLK_TOP_NPUPLL, "npupll_ck", "npupll", 1, 1), 84 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1), 85 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2), 86 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), 87 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8), 88 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16), 89 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 90 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 91 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), 92 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "ulposc", 1, 2), 93 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "ulposc", 1, 4), 94 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "ulposc", 1, 8), 95 FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10), 96 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16), 97 FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20), 98 FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1), 99 FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13), 100 FACTOR(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2), 101 FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4), 102 FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8), 103 FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16), 104 FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32), 105 }; 106 107 static const char * const axi_parents[] = { 108 "clk26m", 109 "mainpll_d4_d4", 110 "mainpll_d7_d2", 111 "mainpll_d4_d2", 112 "mainpll_d5_d2", 113 "mainpll_d6_d2", 114 "osc_d4" 115 }; 116 117 static const char * const spm_parents[] = { 118 "clk26m", 119 "osc_d10", 120 "mainpll_d7_d4", 121 "clk32k" 122 }; 123 124 static const char * const scp_parents[] = { 125 "clk26m", 126 "univpll_d5", 127 "mainpll_d6_d2", 128 "mainpll_d6", 129 "univpll_d6", 130 "mainpll_d4_d2", 131 "mainpll_d5_d2", 132 "univpll_d4_d2" 133 }; 134 135 static const char * const bus_aximem_parents[] = { 136 "clk26m", 137 "mainpll_d7_d2", 138 "mainpll_d4_d2", 139 "mainpll_d5_d2", 140 "mainpll_d6" 141 }; 142 143 static const char * const disp_parents[] = { 144 "clk26m", 145 "univpll_d6_d2", 146 "mainpll_d5_d2", 147 "mmpll_d6_d2", 148 "univpll_d5_d2", 149 "univpll_d4_d2", 150 "mmpll_d7", 151 "univpll_d6", 152 "mainpll_d4", 153 "mmpll_d5_d2" 154 }; 155 156 static const char * const mdp_parents[] = { 157 "clk26m", 158 "mainpll_d5_d2", 159 "mmpll_d6_d2", 160 "mainpll_d4_d2", 161 "mmpll_d4_d2", 162 "mainpll_d6", 163 "univpll_d6", 164 "mainpll_d4", 165 "tvdpll_ck", 166 "univpll_d4", 167 "mmpll_d5_d2" 168 }; 169 170 static const char * const img_parents[] = { 171 "clk26m", 172 "univpll_d4", 173 "tvdpll_ck", 174 "mainpll_d4", 175 "univpll_d5", 176 "mmpll_d6", 177 "univpll_d6", 178 "mainpll_d6", 179 "mmpll_d4_d2", 180 "mainpll_d4_d2", 181 "mmpll_d6_d2", 182 "mmpll_d5_d2" 183 }; 184 185 static const char * const ipe_parents[] = { 186 "clk26m", 187 "mainpll_d4", 188 "mmpll_d6", 189 "univpll_d6", 190 "mainpll_d6", 191 "univpll_d4_d2", 192 "mainpll_d4_d2", 193 "mmpll_d6_d2", 194 "mmpll_d5_d2" 195 }; 196 197 static const char * const dpe_parents[] = { 198 "clk26m", 199 "mainpll_d4", 200 "mmpll_d6", 201 "univpll_d6", 202 "mainpll_d6", 203 "univpll_d4_d2", 204 "univpll_d5_d2", 205 "mmpll_d6_d2" 206 }; 207 208 static const char * const cam_parents[] = { 209 "clk26m", 210 "mainpll_d4", 211 "mmpll_d6", 212 "univpll_d4", 213 "univpll_d5", 214 "univpll_d6", 215 "mmpll_d7", 216 "univpll_d4_d2", 217 "mainpll_d4_d2", 218 "univpll_d6_d2" 219 }; 220 221 static const char * const ccu_parents[] = { 222 "clk26m", 223 "mainpll_d4", 224 "mmpll_d6", 225 "mainpll_d6", 226 "mmpll_d7", 227 "univpll_d4_d2", 228 "mmpll_d6_d2", 229 "mmpll_d5_d2", 230 "univpll_d5", 231 "univpll_d6_d2" 232 }; 233 234 static const char * const dsp7_parents[] = { 235 "clk26m", 236 "mainpll_d4_d2", 237 "mainpll_d6", 238 "mmpll_d6", 239 "univpll_d5", 240 "mmpll_d5", 241 "univpll_d4", 242 "mmpll_d4" 243 }; 244 245 static const char * const mfg_ref_parents[] = { 246 "clk26m", 247 "clk26m", 248 "univpll_d6", 249 "mainpll_d5_d2" 250 }; 251 252 static const char * const mfg_pll_parents[] = { 253 "mfg_ref_sel", 254 "mfgpll" 255 }; 256 257 static const char * const camtg_parents[] = { 258 "clk26m", 259 "univpll_192m_d8", 260 "univpll_d6_d8", 261 "univpll_192m_d4", 262 "univpll_d6_d16", 263 "csw_f26m_d2", 264 "univpll_192m_d16", 265 "univpll_192m_d32" 266 }; 267 268 static const char * const uart_parents[] = { 269 "clk26m", 270 "univpll_d6_d8" 271 }; 272 273 static const char * const spi_parents[] = { 274 "clk26m", 275 "mainpll_d5_d4", 276 "mainpll_d6_d4", 277 "msdcpll_d4" 278 }; 279 280 static const char * const msdc50_0_h_parents[] = { 281 "clk26m", 282 "mainpll_d4_d2", 283 "mainpll_d6_d2" 284 }; 285 286 static const char * const msdc50_0_parents[] = { 287 "clk26m", 288 "msdcpll_ck", 289 "msdcpll_d2", 290 "univpll_d4_d4", 291 "mainpll_d6_d2", 292 "univpll_d4_d2" 293 }; 294 295 static const char * const msdc30_parents[] = { 296 "clk26m", 297 "univpll_d6_d2", 298 "mainpll_d6_d2", 299 "mainpll_d7_d2", 300 "msdcpll_d2" 301 }; 302 303 static const char * const audio_parents[] = { 304 "clk26m", 305 "mainpll_d5_d8", 306 "mainpll_d7_d8", 307 "mainpll_d4_d16" 308 }; 309 310 static const char * const aud_intbus_parents[] = { 311 "clk26m", 312 "mainpll_d4_d4", 313 "mainpll_d7_d4" 314 }; 315 316 static const char * const pwrap_ulposc_parents[] = { 317 "osc_d10", 318 "clk26m", 319 "osc_d4", 320 "osc_d8", 321 "osc_d16" 322 }; 323 324 static const char * const atb_parents[] = { 325 "clk26m", 326 "mainpll_d4_d2", 327 "mainpll_d5_d2" 328 }; 329 330 static const char * const dpi_parents[] = { 331 "clk26m", 332 "tvdpll_d2", 333 "tvdpll_d4", 334 "tvdpll_d8", 335 "tvdpll_d16" 336 }; 337 338 static const char * const scam_parents[] = { 339 "clk26m", 340 "mainpll_d5_d4" 341 }; 342 343 static const char * const disp_pwm_parents[] = { 344 "clk26m", 345 "univpll_d6_d4", 346 "osc_d2", 347 "osc_d4", 348 "osc_d16" 349 }; 350 351 static const char * const usb_top_parents[] = { 352 "clk26m", 353 "univpll_d5_d4", 354 "univpll_d6_d4", 355 "univpll_d5_d2" 356 }; 357 358 static const char * const ssusb_xhci_parents[] = { 359 "clk26m", 360 "univpll_d5_d4", 361 "univpll_d6_d4", 362 "univpll_d5_d2" 363 }; 364 365 static const char * const i2c_parents[] = { 366 "clk26m", 367 "mainpll_d4_d8", 368 "univpll_d5_d4" 369 }; 370 371 static const char * const seninf_parents[] = { 372 "clk26m", 373 "univpll_d4_d4", 374 "univpll_d6_d2", 375 "univpll_d4_d2", 376 "univpll_d7", 377 "univpll_d6", 378 "mmpll_d6", 379 "univpll_d5" 380 }; 381 382 static const char * const tl_parents[] = { 383 "clk26m", 384 "univpll_192m_d2", 385 "mainpll_d6_d4" 386 }; 387 388 static const char * const dxcc_parents[] = { 389 "clk26m", 390 "mainpll_d4_d2", 391 "mainpll_d4_d4", 392 "mainpll_d4_d8" 393 }; 394 395 static const char * const aud_engen1_parents[] = { 396 "clk26m", 397 "apll1_d2", 398 "apll1_d4", 399 "apll1_d8" 400 }; 401 402 static const char * const aud_engen2_parents[] = { 403 "clk26m", 404 "apll2_d2", 405 "apll2_d4", 406 "apll2_d8" 407 }; 408 409 static const char * const aes_ufsfde_parents[] = { 410 "clk26m", 411 "mainpll_d4", 412 "mainpll_d4_d2", 413 "mainpll_d6", 414 "mainpll_d4_d4", 415 "univpll_d4_d2", 416 "univpll_d6" 417 }; 418 419 static const char * const ufs_parents[] = { 420 "clk26m", 421 "mainpll_d4_d4", 422 "mainpll_d4_d8", 423 "univpll_d4_d4", 424 "mainpll_d6_d2", 425 "mainpll_d5_d2", 426 "msdcpll_d2" 427 }; 428 429 static const char * const aud_1_parents[] = { 430 "clk26m", 431 "apll1_ck" 432 }; 433 434 static const char * const aud_2_parents[] = { 435 "clk26m", 436 "apll2_ck" 437 }; 438 439 static const char * const adsp_parents[] = { 440 "clk26m", 441 "mainpll_d6", 442 "mainpll_d5_d2", 443 "univpll_d4_d4", 444 "univpll_d4", 445 "univpll_d6", 446 "ulposc", 447 "adsppll_ck" 448 }; 449 450 static const char * const dpmaif_main_parents[] = { 451 "clk26m", 452 "univpll_d4_d4", 453 "mainpll_d6", 454 "mainpll_d4_d2", 455 "univpll_d4_d2" 456 }; 457 458 static const char * const venc_parents[] = { 459 "clk26m", 460 "mmpll_d7", 461 "mainpll_d6", 462 "univpll_d4_d2", 463 "mainpll_d4_d2", 464 "univpll_d6", 465 "mmpll_d6", 466 "mainpll_d5_d2", 467 "mainpll_d6_d2", 468 "mmpll_d9", 469 "univpll_d4_d4", 470 "mainpll_d4", 471 "univpll_d4", 472 "univpll_d5", 473 "univpll_d5_d2", 474 "mainpll_d5" 475 }; 476 477 static const char * const vdec_parents[] = { 478 "clk26m", 479 "univpll_192m_d2", 480 "univpll_d5_d4", 481 "mainpll_d5", 482 "mainpll_d5_d2", 483 "mmpll_d6_d2", 484 "univpll_d5_d2", 485 "mainpll_d4_d2", 486 "univpll_d4_d2", 487 "univpll_d7", 488 "mmpll_d7", 489 "mmpll_d6", 490 "univpll_d5", 491 "mainpll_d4", 492 "univpll_d4", 493 "univpll_d6" 494 }; 495 496 static const char * const camtm_parents[] = { 497 "clk26m", 498 "univpll_d7", 499 "univpll_d6_d2", 500 "univpll_d4_d2" 501 }; 502 503 static const char * const pwm_parents[] = { 504 "clk26m", 505 "univpll_d4_d8" 506 }; 507 508 static const char * const audio_h_parents[] = { 509 "clk26m", 510 "univpll_d7", 511 "apll1_ck", 512 "apll2_ck" 513 }; 514 515 static const char * const spmi_mst_parents[] = { 516 "clk26m", 517 "csw_f26m_d2", 518 "osc_d8", 519 "osc_d10", 520 "osc_d16", 521 "osc_d20", 522 "clk32k" 523 }; 524 525 static const char * const aes_msdcfde_parents[] = { 526 "clk26m", 527 "mainpll_d4_d2", 528 "mainpll_d6", 529 "mainpll_d4_d4", 530 "univpll_d4_d2", 531 "univpll_d6" 532 }; 533 534 static const char * const sflash_parents[] = { 535 "clk26m", 536 "mainpll_d7_d8", 537 "univpll_d6_d8", 538 "univpll_d5_d8" 539 }; 540 541 static const char * const apll_i2s_m_parents[] = { 542 "aud_1_sel", 543 "aud_2_sel" 544 }; 545 546 /* 547 * CRITICAL CLOCK: 548 * axi_sel is the main bus clock of whole SOC. 549 * spm_sel is the clock of the always-on co-processor. 550 * bus_aximem_sel is clock of the bus that access emi. 551 */ 552 static const struct mtk_mux top_mtk_muxes[] = { 553 /* CLK_CFG_0 */ 554 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", 555 axi_parents, 0x010, 0x014, 0x018, 0, 3, 7, 0x004, 0, 556 CLK_IS_CRITICAL), 557 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", 558 spm_parents, 0x010, 0x014, 0x018, 8, 2, 15, 0x004, 1, 559 CLK_IS_CRITICAL), 560 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", 561 scp_parents, 0x010, 0x014, 0x018, 16, 3, 23, 0x004, 2), 562 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel", 563 bus_aximem_parents, 0x010, 0x014, 0x018, 24, 3, 31, 0x004, 3, 564 CLK_IS_CRITICAL), 565 /* CLK_CFG_1 */ 566 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, "disp_sel", 567 disp_parents, 0x020, 0x024, 0x028, 0, 4, 7, 0x004, 4), 568 MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, "mdp_sel", 569 mdp_parents, 0x020, 0x024, 0x028, 8, 4, 15, 0x004, 5), 570 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel", 571 img_parents, 0x020, 0x024, 0x028, 16, 4, 23, 0x004, 6), 572 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG2_SEL, "img2_sel", 573 img_parents, 0x020, 0x024, 0x028, 24, 4, 31, 0x004, 7), 574 /* CLK_CFG_2 */ 575 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel", 576 ipe_parents, 0x030, 0x034, 0x038, 0, 4, 7, 0x004, 8), 577 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE_SEL, "dpe_sel", 578 dpe_parents, 0x030, 0x034, 0x038, 8, 3, 15, 0x004, 9), 579 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel", 580 cam_parents, 0x030, 0x034, 0x038, 16, 4, 23, 0x004, 10), 581 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel", 582 ccu_parents, 0x030, 0x034, 0x038, 24, 4, 31, 0x004, 11), 583 /* CLK_CFG_4 */ 584 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel", 585 dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16), 586 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel", 587 mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18), 588 MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel", 589 mfg_pll_parents, 0x050, 0x054, 0x058, 18, 1, -1, -1), 590 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", 591 camtg_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x004, 19), 592 /* CLK_CFG_5 */ 593 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel", 594 camtg_parents, 0x060, 0x064, 0x068, 0, 3, 7, 0x004, 20), 595 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", 596 camtg_parents, 0x060, 0x064, 0x068, 8, 3, 15, 0x004, 21), 597 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4_SEL, "camtg4_sel", 598 camtg_parents, 0x060, 0x064, 0x068, 16, 3, 23, 0x004, 22), 599 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5_SEL, "camtg5_sel", 600 camtg_parents, 0x060, 0x064, 0x068, 24, 3, 31, 0x004, 23), 601 /* CLK_CFG_6 */ 602 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6_SEL, "camtg6_sel", 603 camtg_parents, 0x070, 0x074, 0x078, 0, 3, 7, 0x004, 24), 604 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", 605 uart_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25), 606 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", 607 spi_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x004, 26), 608 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", 609 msdc50_0_h_parents, 0x070, 0x074, 0x078, 24, 2, 31, 0x004, 27), 610 /* CLK_CFG_7 */ 611 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 612 msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28), 613 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 614 msdc30_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29), 615 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", 616 msdc30_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30), 617 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", 618 audio_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x008, 0), 619 /* CLK_CFG_8 */ 620 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", 621 aud_intbus_parents, 0x090, 0x094, 0x098, 0, 2, 7, 0x008, 1), 622 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL, "pwrap_ulposc_sel", 623 pwrap_ulposc_parents, 0x090, 0x094, 0x098, 8, 3, 15, 0x008, 2), 624 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", 625 atb_parents, 0x090, 0x094, 0x098, 16, 2, 23, 0x008, 3), 626 /* CLK_CFG_9 */ 627 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI_SEL, "dpi_sel", 628 dpi_parents, 0x0a0, 0x0a4, 0x0a8, 0, 3, 7, 0x008, 5), 629 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM_SEL, "scam_sel", 630 scam_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x008, 6), 631 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel", 632 disp_pwm_parents, 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, 0x008, 7), 633 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel", 634 usb_top_parents, 0x0a0, 0x0a4, 0x0a8, 24, 2, 31, 0x008, 8), 635 /* CLK_CFG_10 */ 636 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel", 637 ssusb_xhci_parents, 0x0b0, 0x0b4, 0x0b8, 0, 2, 7, 0x008, 9), 638 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", 639 i2c_parents, 0x0b0, 0x0b4, 0x0b8, 8, 2, 15, 0x008, 10), 640 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel", 641 seninf_parents, 0x0b0, 0x0b4, 0x0b8, 16, 3, 23, 0x008, 11), 642 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, "seninf1_sel", 643 seninf_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x008, 12), 644 /* CLK_CFG_11 */ 645 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL, "seninf2_sel", 646 seninf_parents, 0x0c0, 0x0c4, 0x0c8, 0, 3, 7, 0x008, 13), 647 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL, "seninf3_sel", 648 seninf_parents, 0x0c0, 0x0c4, 0x0c8, 8, 3, 15, 0x008, 14), 649 MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_SEL, "tl_sel", 650 tl_parents, 0x0c0, 0x0c4, 0x0c8, 16, 2, 23, 0x008, 15), 651 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", 652 dxcc_parents, 0x0c0, 0x0c4, 0x0c8, 24, 2, 31, 0x008, 16), 653 /* CLK_CFG_12 */ 654 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", 655 aud_engen1_parents, 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x008, 17), 656 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", 657 aud_engen2_parents, 0x0d0, 0x0d4, 0x0d8, 8, 2, 15, 0x008, 18), 658 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, "aes_ufsfde_sel", 659 aes_ufsfde_parents, 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, 0x008, 19), 660 MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_SEL, "ufs_sel", 661 ufs_parents, 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, 0x008, 20), 662 /* CLK_CFG_13 */ 663 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", 664 aud_1_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, 0x008, 21), 665 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", 666 aud_2_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, 0x008, 22), 667 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_SEL, "adsp_sel", 668 adsp_parents, 0x0e0, 0x0e4, 0x0e8, 16, 3, 23, 0x008, 23), 669 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN_SEL, "dpmaif_main_sel", 670 dpmaif_main_parents, 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, 0x008, 24), 671 /* CLK_CFG_14 */ 672 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel", 673 venc_parents, 0x0f0, 0x0f4, 0x0f8, 0, 4, 7, 0x008, 25), 674 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel", 675 vdec_parents, 0x0f0, 0x0f4, 0x0f8, 8, 4, 15, 0x008, 26), 676 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", 677 camtm_parents, 0x0f0, 0x0f4, 0x0f8, 16, 2, 23, 0x008, 27), 678 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", 679 pwm_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, 31, 0x008, 28), 680 /* CLK_CFG_15 */ 681 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, "audio_h_sel", 682 audio_h_parents, 0x100, 0x104, 0x108, 0, 2, 7, 0x008, 29), 683 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST_SEL, "spmi_mst_sel", 684 spmi_mst_parents, 0x100, 0x104, 0x108, 8, 3, 15, 0x008, 30), 685 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel", 686 aes_msdcfde_parents, 0x100, 0x104, 0x108, 24, 3, 31, 0x00c, 1), 687 /* CLK_CFG_16 */ 688 MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel", 689 sflash_parents, 0x110, 0x114, 0x118, 8, 2, 15, 0x00c, 3), 690 }; 691 692 static struct mtk_composite top_muxes[] = { 693 /* CLK_AUDDIV_0 */ 694 MUX(CLK_TOP_APLL_I2S0_M_SEL, "apll_i2s0_m_sel", apll_i2s_m_parents, 0x320, 16, 1), 695 MUX(CLK_TOP_APLL_I2S1_M_SEL, "apll_i2s1_m_sel", apll_i2s_m_parents, 0x320, 17, 1), 696 MUX(CLK_TOP_APLL_I2S2_M_SEL, "apll_i2s2_m_sel", apll_i2s_m_parents, 0x320, 18, 1), 697 MUX(CLK_TOP_APLL_I2S3_M_SEL, "apll_i2s3_m_sel", apll_i2s_m_parents, 0x320, 19, 1), 698 MUX(CLK_TOP_APLL_I2S4_M_SEL, "apll_i2s4_m_sel", apll_i2s_m_parents, 0x320, 20, 1), 699 MUX(CLK_TOP_APLL_I2S5_M_SEL, "apll_i2s5_m_sel", apll_i2s_m_parents, 0x320, 21, 1), 700 MUX(CLK_TOP_APLL_I2S6_M_SEL, "apll_i2s6_m_sel", apll_i2s_m_parents, 0x320, 22, 1), 701 MUX(CLK_TOP_APLL_I2S7_M_SEL, "apll_i2s7_m_sel", apll_i2s_m_parents, 0x320, 23, 1), 702 MUX(CLK_TOP_APLL_I2S8_M_SEL, "apll_i2s8_m_sel", apll_i2s_m_parents, 0x320, 24, 1), 703 MUX(CLK_TOP_APLL_I2S9_M_SEL, "apll_i2s9_m_sel", apll_i2s_m_parents, 0x320, 25, 1), 704 }; 705 706 static const struct mtk_composite top_adj_divs[] = { 707 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_m_sel", 0x320, 0, 0x328, 8, 0), 708 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_m_sel", 0x320, 1, 0x328, 8, 8), 709 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_m_sel", 0x320, 2, 0x328, 8, 16), 710 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_m_sel", 0x320, 3, 0x328, 8, 24), 711 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_m_sel", 0x320, 4, 0x334, 8, 0), 712 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 5, 0x334, 8, 8), 713 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll_i2s5_m_sel", 0x320, 6, 0x334, 8, 16), 714 DIV_GATE(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll_i2s6_m_sel", 0x320, 7, 0x334, 8, 24), 715 DIV_GATE(CLK_TOP_APLL12_DIV7, "apll12_div7", "apll_i2s7_m_sel", 0x320, 8, 0x338, 8, 0), 716 DIV_GATE(CLK_TOP_APLL12_DIV8, "apll12_div8", "apll_i2s8_m_sel", 0x320, 9, 0x338, 8, 8), 717 DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "apll_i2s9_m_sel", 0x320, 10, 0x338, 8, 16), 718 }; 719 720 static const struct mtk_gate_regs apmixed_cg_regs = { 721 .set_ofs = 0x14, 722 .clr_ofs = 0x14, 723 .sta_ofs = 0x14, 724 }; 725 726 #define GATE_APMIXED(_id, _name, _parent, _shift) \ 727 GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 728 729 static const struct mtk_gate apmixed_clks[] = { 730 GATE_APMIXED(CLK_APMIXED_MIPID26M, "mipid26m", "clk26m", 16), 731 }; 732 733 static const struct mtk_gate_regs infra0_cg_regs = { 734 .set_ofs = 0x80, 735 .clr_ofs = 0x84, 736 .sta_ofs = 0x90, 737 }; 738 739 static const struct mtk_gate_regs infra1_cg_regs = { 740 .set_ofs = 0x88, 741 .clr_ofs = 0x8c, 742 .sta_ofs = 0x94, 743 }; 744 745 static const struct mtk_gate_regs infra2_cg_regs = { 746 .set_ofs = 0xa4, 747 .clr_ofs = 0xa8, 748 .sta_ofs = 0xac, 749 }; 750 751 static const struct mtk_gate_regs infra3_cg_regs = { 752 .set_ofs = 0xc0, 753 .clr_ofs = 0xc4, 754 .sta_ofs = 0xc8, 755 }; 756 757 static const struct mtk_gate_regs infra4_cg_regs = { 758 .set_ofs = 0xd0, 759 .clr_ofs = 0xd4, 760 .sta_ofs = 0xd8, 761 }; 762 763 static const struct mtk_gate_regs infra5_cg_regs = { 764 .set_ofs = 0xe0, 765 .clr_ofs = 0xe4, 766 .sta_ofs = 0xe8, 767 }; 768 769 #define GATE_INFRA0(_id, _name, _parent, _shift) \ 770 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 771 772 #define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flag) \ 773 GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \ 774 &mtk_clk_gate_ops_setclr, _flag) 775 776 #define GATE_INFRA1(_id, _name, _parent, _shift) \ 777 GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0) 778 779 #define GATE_INFRA2(_id, _name, _parent, _shift) \ 780 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 781 782 #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag) \ 783 GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, \ 784 &mtk_clk_gate_ops_setclr, _flag) 785 786 #define GATE_INFRA3(_id, _name, _parent, _shift) \ 787 GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0) 788 789 #define GATE_INFRA4(_id, _name, _parent, _shift) \ 790 GATE_MTK(_id, _name, _parent, &infra4_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 791 792 #define GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, _flag) \ 793 GATE_MTK_FLAGS(_id, _name, _parent, &infra5_cg_regs, _shift, \ 794 &mtk_clk_gate_ops_setclr, _flag) 795 796 #define GATE_INFRA5(_id, _name, _parent, _shift) \ 797 GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, 0) 798 799 /* 800 * CRITICAL CLOCK: 801 * infra_133m and infra_66m are main peripheral bus clocks of SOC. 802 * infra_device_apc and infra_device_apc_sync are for device access permission control module. 803 */ 804 static const struct mtk_gate infra_clks[] = { 805 /* INFRA0 */ 806 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "pwrap_ulposc_sel", 0), 807 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pwrap_ulposc_sel", 1), 808 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pwrap_ulposc_sel", 2), 809 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pwrap_ulposc_sel", 3), 810 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4), 811 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5), 812 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6), 813 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 8), 814 GATE_INFRA0(CLK_INFRA_GCE2, "infra_gce2", "axi_sel", 9), 815 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10), 816 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11), 817 GATE_INFRA0(CLK_INFRA_AP_DMA_PSEUDO, "infra_ap_dma_pseudo", "axi_sel", 12), 818 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13), 819 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14), 820 GATE_INFRA0(CLK_INFRA_PWM_H, "infra_pwm_h", "axi_sel", 15), 821 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "pwm_sel", 16), 822 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "pwm_sel", 17), 823 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "pwm_sel", 18), 824 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "pwm_sel", 19), 825 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21), 826 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22), 827 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), 828 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24), 829 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25), 830 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27), 831 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cq_dma_fpc", "axi_sel", 28), 832 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31), 833 /* INFRA1 */ 834 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1), 835 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_h_sel", 2), 836 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc50_0_h_sel", 4), 837 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc50_0_h_sel", 5), 838 GATE_INFRA1(CLK_INFRA_MSDC0_SRC, "infra_msdc0_src", "msdc50_0_sel", 6), 839 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8), 840 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9), 841 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10), 842 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11), 843 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12), 844 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13), 845 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "clk26m", 14), 846 GATE_INFRA1(CLK_INFRA_PCIE_TL_26M, "infra_pcie_tl_26m", "axi_sel", 15), 847 GATE_INFRA1(CLK_INFRA_MSDC1_SRC, "infra_msdc1_src", "msdc30_1_sel", 16), 848 GATE_INFRA1(CLK_INFRA_MSDC2_SRC, "infra_msdc2_src", "msdc30_2_sel", 17), 849 GATE_INFRA1(CLK_INFRA_PCIE_TL_96M, "infra_pcie_tl_96m", "tl_sel", 18), 850 GATE_INFRA1(CLK_INFRA_PCIE_PL_P_250M, "infra_pcie_pl_p_250m", "axi_sel", 19), 851 GATE_INFRA1_FLAGS(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20, CLK_IS_CRITICAL), 852 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23), 853 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24), 854 GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25), 855 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26), 856 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 27), 857 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28), 858 GATE_INFRA1(CLK_INFRA_DBG_TRACE, "infra_dbg_trace", "axi_sel", 29), 859 GATE_INFRA1(CLK_INFRA_DEVMPU_B, "infra_devmpu_b", "axi_sel", 30), 860 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31), 861 /* INFRA2 */ 862 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "clk26m", 0), 863 GATE_INFRA2(CLK_INFRA_SSUSB, "infra_ssusb", "usb_top_sel", 1), 864 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "axi_sel", 2), 865 GATE_INFRA2(CLK_INFRA_CLDMA_B, "infra_cldma_b", "axi_sel", 3), 866 GATE_INFRA2(CLK_INFRA_AUDIO_26M_B, "infra_audio_26m_b", "clk26m", 4), 867 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share", "clk26m", 5), 868 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6), 869 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7), 870 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9), 871 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10), 872 GATE_INFRA2(CLK_INFRA_UNIPRO_SYS, "infra_unipro_sys", "ufs_sel", 11), 873 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "clk26m", 12), 874 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_B, "infra_ufs_mp_sap_b", "clk26m", 13), 875 GATE_INFRA2(CLK_INFRA_MD32_B, "infra_md32_b", "axi_sel", 14), 876 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16), 877 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18), 878 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19), 879 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20), 880 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21), 881 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22), 882 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23), 883 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24), 884 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25), 885 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26), 886 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cq_dma", "axi_sel", 27), 887 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "ufs_sel", 28), 888 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "aes_ufsfde_sel", 29), 889 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "ufs_sel", 30), 890 GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci", "ssusb_xhci_sel", 31), 891 /* INFRA3 */ 892 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0), 893 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1), 894 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2), 895 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5), 896 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6), 897 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_0_sel", 7), 898 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_0_sel", 8), 899 GATE_INFRA3(CLK_INFRA_CCIF5_AP, "infra_ccif5_ap", "axi_sel", 9), 900 GATE_INFRA3(CLK_INFRA_CCIF5_MD, "infra_ccif5_md", "axi_sel", 10), 901 GATE_INFRA3(CLK_INFRA_PCIE_TOP_H_133M, "infra_pcie_top_h_133m", "axi_sel", 11), 902 GATE_INFRA3(CLK_INFRA_FLASHIF_TOP_H_133M, "infra_flashif_top_h_133m", "axi_sel", 14), 903 GATE_INFRA3(CLK_INFRA_PCIE_PERI_26M, "infra_pcie_peri_26m", "axi_sel", 15), 904 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16), 905 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17), 906 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18), 907 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19), 908 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "clk26m", 20), 909 GATE_INFRA3(CLK_INFRA_AES, "infra_aes", "axi_sel", 21), 910 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22), 911 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23), 912 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24), 913 GATE_INFRA3_FLAGS(CLK_INFRA_DEVICE_APC_SYNC, "infra_device_apc_sync", "axi_sel", 25, 914 CLK_IS_CRITICAL), 915 GATE_INFRA3(CLK_INFRA_DPMAIF_MAIN, "infra_dpmaif_main", "dpmaif_main_sel", 26), 916 GATE_INFRA3(CLK_INFRA_PCIE_TL_32K, "infra_pcie_tl_32k", "axi_sel", 27), 917 GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap", "axi_sel", 28), 918 GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md", "axi_sel", 29), 919 GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6", "spi_sel", 30), 920 GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7", "spi_sel", 31), 921 /* INFRA4 */ 922 GATE_INFRA4(CLK_INFRA_AP_DMA, "infra_ap_dma", "infra_ap_dma_pseudo", 31), 923 /* INFRA5 */ 924 GATE_INFRA5_FLAGS(CLK_INFRA_133M, "infra_133m", "axi_sel", 0, CLK_IS_CRITICAL), 925 GATE_INFRA5_FLAGS(CLK_INFRA_66M, "infra_66m", "axi_sel", 1, CLK_IS_CRITICAL), 926 GATE_INFRA5(CLK_INFRA_66M_PERI_BUS, "infra_66m_peri_bus", "axi_sel", 2), 927 GATE_INFRA5(CLK_INFRA_FREE_DCM_133M, "infra_free_dcm_133m", "axi_sel", 3), 928 GATE_INFRA5(CLK_INFRA_FREE_DCM_66M, "infra_free_dcm_66m", "axi_sel", 4), 929 GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_133M, "infra_peri_bus_dcm_133m", "axi_sel", 5), 930 GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_66M, "infra_peri_bus_dcm_66m", "axi_sel", 6), 931 GATE_INFRA5(CLK_INFRA_FLASHIF_PERI_26M, "infra_flashif_peri_26m", "axi_sel", 30), 932 GATE_INFRA5(CLK_INFRA_FLASHIF_SFLASH, "infra_flashif_fsflash", "axi_sel", 31), 933 }; 934 935 static const struct mtk_gate_regs peri_cg_regs = { 936 .set_ofs = 0x20c, 937 .clr_ofs = 0x20c, 938 .sta_ofs = 0x20c, 939 }; 940 941 #define GATE_PERI(_id, _name, _parent, _shift) \ 942 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 943 944 static const struct mtk_gate peri_clks[] = { 945 GATE_PERI(CLK_PERI_PERIAXI, "peri_periaxi", "axi_sel", 31), 946 }; 947 948 static const struct mtk_gate_regs top_cg_regs = { 949 .set_ofs = 0x150, 950 .clr_ofs = 0x150, 951 .sta_ofs = 0x150, 952 }; 953 954 #define GATE_TOP(_id, _name, _parent, _shift) \ 955 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 956 957 static const struct mtk_gate top_clks[] = { 958 GATE_TOP(CLK_TOP_SSUSB_TOP_REF, "ssusb_top_ref", "clk26m", 24), 959 GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25), 960 }; 961 962 static u16 infra_ao_rst_ofs[] = { 963 INFRA_RST0_SET_OFFSET, 964 INFRA_RST1_SET_OFFSET, 965 INFRA_RST2_SET_OFFSET, 966 INFRA_RST3_SET_OFFSET, 967 INFRA_RST4_SET_OFFSET, 968 }; 969 970 static u16 infra_ao_idx_map[] = { 971 [MT8192_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0, 972 [MT8192_INFRA_RST2_PEXTP_PHY_SWRST] = 2 * RST_NR_PER_BANK + 15, 973 [MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5, 974 [MT8192_INFRA_RST4_PCIE_TOP_SWRST] = 4 * RST_NR_PER_BANK + 1, 975 [MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 12, 976 }; 977 978 static const struct mtk_clk_rst_desc clk_rst_desc = { 979 .version = MTK_RST_SET_CLR, 980 .rst_bank_ofs = infra_ao_rst_ofs, 981 .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs), 982 .rst_idx_map = infra_ao_idx_map, 983 .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map), 984 }; 985 986 #define MT8192_PLL_FMAX (3800UL * MHZ) 987 #define MT8192_PLL_FMIN (1500UL * MHZ) 988 #define MT8192_INTEGER_BITS 8 989 990 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 991 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 992 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 993 _pcw_reg, _pcw_shift, _pcw_chg_reg, \ 994 _en_reg, _pll_en_bit) { \ 995 .id = _id, \ 996 .name = _name, \ 997 .reg = _reg, \ 998 .pwr_reg = _pwr_reg, \ 999 .en_mask = _en_mask, \ 1000 .flags = _flags, \ 1001 .rst_bar_mask = _rst_bar_mask, \ 1002 .fmax = MT8192_PLL_FMAX, \ 1003 .fmin = MT8192_PLL_FMIN, \ 1004 .pcwbits = _pcwbits, \ 1005 .pcwibits = MT8192_INTEGER_BITS, \ 1006 .pd_reg = _pd_reg, \ 1007 .pd_shift = _pd_shift, \ 1008 .tuner_reg = _tuner_reg, \ 1009 .tuner_en_reg = _tuner_en_reg, \ 1010 .tuner_en_bit = _tuner_en_bit, \ 1011 .pcw_reg = _pcw_reg, \ 1012 .pcw_shift = _pcw_shift, \ 1013 .pcw_chg_reg = _pcw_chg_reg, \ 1014 .en_reg = _en_reg, \ 1015 .pll_en_bit = _pll_en_bit, \ 1016 } 1017 1018 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1019 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 1020 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 1021 _pcw_reg, _pcw_shift) \ 1022 PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1023 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 1024 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 1025 _pcw_reg, _pcw_shift, 0, 0, 0) 1026 1027 static const struct mtk_pll_data plls[] = { 1028 PLL_B(CLK_APMIXED_MAINPLL, "mainpll", 0x0340, 0x034c, 0xff000000, 1029 HAVE_RST_BAR, BIT(23), 22, 0x0344, 24, 0, 0, 0, 0x0344, 0), 1030 PLL_B(CLK_APMIXED_UNIVPLL, "univpll", 0x0308, 0x0314, 0xff000000, 1031 HAVE_RST_BAR, BIT(23), 22, 0x030c, 24, 0, 0, 0, 0x030c, 0), 1032 PLL(CLK_APMIXED_USBPLL, "usbpll", 0x03c4, 0x03cc, 0x00000000, 1033 0, 0, 22, 0x03c4, 24, 0, 0, 0, 0x03c4, 0, 0x03c4, 0x03cc, 2), 1034 PLL_B(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035c, 0x00000000, 1035 0, 0, 22, 0x0354, 24, 0, 0, 0, 0x0354, 0), 1036 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0360, 0x036c, 0xff000000, 1037 HAVE_RST_BAR, BIT(23), 22, 0x0364, 24, 0, 0, 0, 0x0364, 0), 1038 PLL_B(CLK_APMIXED_ADSPPLL, "adsppll", 0x0370, 0x037c, 0xff000000, 1039 HAVE_RST_BAR, BIT(23), 22, 0x0374, 24, 0, 0, 0, 0x0374, 0), 1040 PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0268, 0x0274, 0x00000000, 1041 0, 0, 22, 0x026c, 24, 0, 0, 0, 0x026c, 0), 1042 PLL_B(CLK_APMIXED_TVDPLL, "tvdpll", 0x0380, 0x038c, 0x00000000, 1043 0, 0, 22, 0x0384, 24, 0, 0, 0, 0x0384, 0), 1044 PLL_B(CLK_APMIXED_APLL1, "apll1", 0x0318, 0x0328, 0x00000000, 1045 0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0), 1046 PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000000, 1047 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0), 1048 }; 1049 1050 static struct clk_hw_onecell_data *top_clk_data; 1051 1052 static void clk_mt8192_top_init_early(struct device_node *node) 1053 { 1054 int i; 1055 1056 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 1057 if (!top_clk_data) 1058 return; 1059 1060 for (i = 0; i < CLK_TOP_NR_CLK; i++) 1061 top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); 1062 1063 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data); 1064 1065 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); 1066 } 1067 1068 CLK_OF_DECLARE_DRIVER(mt8192_topckgen, "mediatek,mt8192-topckgen", 1069 clk_mt8192_top_init_early); 1070 1071 /* Register mux notifier for MFG mux */ 1072 static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) 1073 { 1074 struct mtk_mux_nb *mfg_mux_nb; 1075 int i; 1076 1077 mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL); 1078 if (!mfg_mux_nb) 1079 return -ENOMEM; 1080 1081 for (i = 0; i < ARRAY_SIZE(top_mtk_muxes); i++) 1082 if (top_mtk_muxes[i].id == CLK_TOP_MFG_PLL_SEL) 1083 break; 1084 if (i == ARRAY_SIZE(top_mtk_muxes)) 1085 return -EINVAL; 1086 1087 mfg_mux_nb->ops = top_mtk_muxes[i].ops; 1088 mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */ 1089 1090 return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); 1091 } 1092 1093 static int clk_mt8192_top_probe(struct platform_device *pdev) 1094 { 1095 struct device_node *node = pdev->dev.of_node; 1096 int r; 1097 void __iomem *base; 1098 1099 base = devm_platform_ioremap_resource(pdev, 0); 1100 if (IS_ERR(base)) 1101 return PTR_ERR(base); 1102 1103 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data); 1104 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data); 1105 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); 1106 mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node, &mt8192_clk_lock, 1107 top_clk_data); 1108 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, &mt8192_clk_lock, 1109 top_clk_data); 1110 mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt8192_clk_lock, 1111 top_clk_data); 1112 r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data); 1113 if (r) 1114 return r; 1115 1116 r = clk_mt8192_reg_mfg_mux_notifier(&pdev->dev, 1117 top_clk_data->hws[CLK_TOP_MFG_PLL_SEL]->clk); 1118 if (r) 1119 return r; 1120 1121 1122 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, 1123 top_clk_data); 1124 } 1125 1126 static int clk_mt8192_infra_probe(struct platform_device *pdev) 1127 { 1128 struct clk_hw_onecell_data *clk_data; 1129 struct device_node *node = pdev->dev.of_node; 1130 int r; 1131 1132 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 1133 if (!clk_data) 1134 return -ENOMEM; 1135 1136 r = mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data); 1137 if (r) 1138 goto free_clk_data; 1139 1140 r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); 1141 if (r) 1142 goto free_clk_data; 1143 1144 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1145 if (r) 1146 goto free_clk_data; 1147 1148 return r; 1149 1150 free_clk_data: 1151 mtk_free_clk_data(clk_data); 1152 return r; 1153 } 1154 1155 static int clk_mt8192_peri_probe(struct platform_device *pdev) 1156 { 1157 struct clk_hw_onecell_data *clk_data; 1158 struct device_node *node = pdev->dev.of_node; 1159 int r; 1160 1161 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); 1162 if (!clk_data) 1163 return -ENOMEM; 1164 1165 r = mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), clk_data); 1166 if (r) 1167 goto free_clk_data; 1168 1169 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1170 if (r) 1171 goto free_clk_data; 1172 1173 return r; 1174 1175 free_clk_data: 1176 mtk_free_clk_data(clk_data); 1177 return r; 1178 } 1179 1180 static int clk_mt8192_apmixed_probe(struct platform_device *pdev) 1181 { 1182 struct clk_hw_onecell_data *clk_data; 1183 struct device_node *node = pdev->dev.of_node; 1184 int r; 1185 1186 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 1187 if (!clk_data) 1188 return -ENOMEM; 1189 1190 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 1191 r = mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); 1192 if (r) 1193 goto free_clk_data; 1194 1195 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1196 if (r) 1197 goto free_clk_data; 1198 1199 return r; 1200 1201 free_clk_data: 1202 mtk_free_clk_data(clk_data); 1203 return r; 1204 } 1205 1206 static const struct of_device_id of_match_clk_mt8192[] = { 1207 { 1208 .compatible = "mediatek,mt8192-apmixedsys", 1209 .data = clk_mt8192_apmixed_probe, 1210 }, { 1211 .compatible = "mediatek,mt8192-topckgen", 1212 .data = clk_mt8192_top_probe, 1213 }, { 1214 .compatible = "mediatek,mt8192-infracfg", 1215 .data = clk_mt8192_infra_probe, 1216 }, { 1217 .compatible = "mediatek,mt8192-pericfg", 1218 .data = clk_mt8192_peri_probe, 1219 }, { 1220 /* sentinel */ 1221 } 1222 }; 1223 1224 static int clk_mt8192_probe(struct platform_device *pdev) 1225 { 1226 int (*clk_probe)(struct platform_device *pdev); 1227 int r; 1228 1229 clk_probe = of_device_get_match_data(&pdev->dev); 1230 if (!clk_probe) 1231 return -EINVAL; 1232 1233 r = clk_probe(pdev); 1234 if (r) 1235 dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); 1236 1237 return r; 1238 } 1239 1240 static struct platform_driver clk_mt8192_drv = { 1241 .probe = clk_mt8192_probe, 1242 .driver = { 1243 .name = "clk-mt8192", 1244 .of_match_table = of_match_clk_mt8192, 1245 }, 1246 }; 1247 1248 static int __init clk_mt8192_init(void) 1249 { 1250 return platform_driver_register(&clk_mt8192_drv); 1251 } 1252 1253 arch_initcall(clk_mt8192_init); 1254