1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright (c) 2021 MediaTek Inc. 4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/mfd/syscon.h> 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 #include <linux/of_device.h> 12 #include <linux/platform_device.h> 13 #include <linux/slab.h> 14 15 #include "clk-gate.h" 16 #include "clk-mtk.h" 17 #include "clk-mux.h" 18 #include "clk-pll.h" 19 20 #include <dt-bindings/clock/mt8192-clk.h> 21 #include <dt-bindings/reset/mt8192-resets.h> 22 23 static DEFINE_SPINLOCK(mt8192_clk_lock); 24 25 static const struct mtk_fixed_clk top_fixed_clks[] = { 26 FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 260000000), 27 }; 28 29 static const struct mtk_fixed_factor top_early_divs[] = { 30 FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2), 31 }; 32 33 static const struct mtk_fixed_factor top_divs[] = { 34 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3), 35 FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4), 36 FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2), 37 FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4), 38 FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8), 39 FACTOR(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16), 40 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5), 41 FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2), 42 FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4), 43 FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8), 44 FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6), 45 FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2), 46 FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4), 47 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7), 48 FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2), 49 FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4), 50 FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8), 51 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), 52 FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4), 53 FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2), 54 FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4), 55 FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8), 56 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), 57 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2), 58 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4), 59 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8), 60 FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6), 61 FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2), 62 FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4), 63 FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8), 64 FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16), 65 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), 66 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 67 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2), 68 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4), 69 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8), 70 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), 71 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), 72 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), 73 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8), 74 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), 75 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2), 76 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), 77 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2), 78 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6), 79 FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2), 80 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), 81 FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9), 82 FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 2), 83 FACTOR(CLK_TOP_NPUPLL, "npupll_ck", "npupll", 1, 1), 84 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1), 85 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2), 86 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4), 87 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8), 88 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16), 89 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 90 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2), 91 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4), 92 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "ulposc", 1, 2), 93 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "ulposc", 1, 4), 94 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "ulposc", 1, 8), 95 FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10), 96 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16), 97 FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20), 98 FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1), 99 FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13), 100 FACTOR(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2), 101 FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4), 102 FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8), 103 FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16), 104 FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32), 105 }; 106 107 static const char * const axi_parents[] = { 108 "clk26m", 109 "mainpll_d4_d4", 110 "mainpll_d7_d2", 111 "mainpll_d4_d2", 112 "mainpll_d5_d2", 113 "mainpll_d6_d2", 114 "osc_d4" 115 }; 116 117 static const char * const spm_parents[] = { 118 "clk26m", 119 "osc_d10", 120 "mainpll_d7_d4", 121 "clk32k" 122 }; 123 124 static const char * const scp_parents[] = { 125 "clk26m", 126 "univpll_d5", 127 "mainpll_d6_d2", 128 "mainpll_d6", 129 "univpll_d6", 130 "mainpll_d4_d2", 131 "mainpll_d5_d2", 132 "univpll_d4_d2" 133 }; 134 135 static const char * const bus_aximem_parents[] = { 136 "clk26m", 137 "mainpll_d7_d2", 138 "mainpll_d4_d2", 139 "mainpll_d5_d2", 140 "mainpll_d6" 141 }; 142 143 static const char * const disp_parents[] = { 144 "clk26m", 145 "univpll_d6_d2", 146 "mainpll_d5_d2", 147 "mmpll_d6_d2", 148 "univpll_d5_d2", 149 "univpll_d4_d2", 150 "mmpll_d7", 151 "univpll_d6", 152 "mainpll_d4", 153 "mmpll_d5_d2" 154 }; 155 156 static const char * const mdp_parents[] = { 157 "clk26m", 158 "mainpll_d5_d2", 159 "mmpll_d6_d2", 160 "mainpll_d4_d2", 161 "mmpll_d4_d2", 162 "mainpll_d6", 163 "univpll_d6", 164 "mainpll_d4", 165 "tvdpll_ck", 166 "univpll_d4", 167 "mmpll_d5_d2" 168 }; 169 170 static const char * const img1_parents[] = { 171 "clk26m", 172 "univpll_d4", 173 "tvdpll_ck", 174 "mainpll_d4", 175 "univpll_d5", 176 "mmpll_d6", 177 "univpll_d6", 178 "mainpll_d6", 179 "mmpll_d4_d2", 180 "mainpll_d4_d2", 181 "mmpll_d6_d2", 182 "mmpll_d5_d2" 183 }; 184 185 static const char * const img2_parents[] = { 186 "clk26m", 187 "univpll_d4", 188 "tvdpll_ck", 189 "mainpll_d4", 190 "univpll_d5", 191 "mmpll_d6", 192 "univpll_d6", 193 "mainpll_d6", 194 "mmpll_d4_d2", 195 "mainpll_d4_d2", 196 "mmpll_d6_d2", 197 "mmpll_d5_d2" 198 }; 199 200 static const char * const ipe_parents[] = { 201 "clk26m", 202 "mainpll_d4", 203 "mmpll_d6", 204 "univpll_d6", 205 "mainpll_d6", 206 "univpll_d4_d2", 207 "mainpll_d4_d2", 208 "mmpll_d6_d2", 209 "mmpll_d5_d2" 210 }; 211 212 static const char * const dpe_parents[] = { 213 "clk26m", 214 "mainpll_d4", 215 "mmpll_d6", 216 "univpll_d6", 217 "mainpll_d6", 218 "univpll_d4_d2", 219 "univpll_d5_d2", 220 "mmpll_d6_d2" 221 }; 222 223 static const char * const cam_parents[] = { 224 "clk26m", 225 "mainpll_d4", 226 "mmpll_d6", 227 "univpll_d4", 228 "univpll_d5", 229 "univpll_d6", 230 "mmpll_d7", 231 "univpll_d4_d2", 232 "mainpll_d4_d2", 233 "univpll_d6_d2" 234 }; 235 236 static const char * const ccu_parents[] = { 237 "clk26m", 238 "mainpll_d4", 239 "mmpll_d6", 240 "mainpll_d6", 241 "mmpll_d7", 242 "univpll_d4_d2", 243 "mmpll_d6_d2", 244 "mmpll_d5_d2", 245 "univpll_d5", 246 "univpll_d6_d2" 247 }; 248 249 static const char * const dsp7_parents[] = { 250 "clk26m", 251 "mainpll_d4_d2", 252 "mainpll_d6", 253 "mmpll_d6", 254 "univpll_d5", 255 "mmpll_d5", 256 "univpll_d4", 257 "mmpll_d4" 258 }; 259 260 static const char * const mfg_ref_parents[] = { 261 "clk26m", 262 "clk26m", 263 "univpll_d6", 264 "mainpll_d5_d2" 265 }; 266 267 static const char * const mfg_pll_parents[] = { 268 "mfg_ref_sel", 269 "mfgpll" 270 }; 271 272 static const char * const camtg_parents[] = { 273 "clk26m", 274 "univpll_192m_d8", 275 "univpll_d6_d8", 276 "univpll_192m_d4", 277 "univpll_d6_d16", 278 "csw_f26m_d2", 279 "univpll_192m_d16", 280 "univpll_192m_d32" 281 }; 282 283 static const char * const camtg2_parents[] = { 284 "clk26m", 285 "univpll_192m_d8", 286 "univpll_d6_d8", 287 "univpll_192m_d4", 288 "univpll_d6_d16", 289 "csw_f26m_d2", 290 "univpll_192m_d16", 291 "univpll_192m_d32" 292 }; 293 294 static const char * const camtg3_parents[] = { 295 "clk26m", 296 "univpll_192m_d8", 297 "univpll_d6_d8", 298 "univpll_192m_d4", 299 "univpll_d6_d16", 300 "csw_f26m_d2", 301 "univpll_192m_d16", 302 "univpll_192m_d32" 303 }; 304 305 static const char * const camtg4_parents[] = { 306 "clk26m", 307 "univpll_192m_d8", 308 "univpll_d6_d8", 309 "univpll_192m_d4", 310 "univpll_d6_d16", 311 "csw_f26m_d2", 312 "univpll_192m_d16", 313 "univpll_192m_d32" 314 }; 315 316 static const char * const camtg5_parents[] = { 317 "clk26m", 318 "univpll_192m_d8", 319 "univpll_d6_d8", 320 "univpll_192m_d4", 321 "univpll_d6_d16", 322 "csw_f26m_d2", 323 "univpll_192m_d16", 324 "univpll_192m_d32" 325 }; 326 327 static const char * const camtg6_parents[] = { 328 "clk26m", 329 "univpll_192m_d8", 330 "univpll_d6_d8", 331 "univpll_192m_d4", 332 "univpll_d6_d16", 333 "csw_f26m_d2", 334 "univpll_192m_d16", 335 "univpll_192m_d32" 336 }; 337 338 static const char * const uart_parents[] = { 339 "clk26m", 340 "univpll_d6_d8" 341 }; 342 343 static const char * const spi_parents[] = { 344 "clk26m", 345 "mainpll_d5_d4", 346 "mainpll_d6_d4", 347 "msdcpll_d4" 348 }; 349 350 static const char * const msdc50_0_h_parents[] = { 351 "clk26m", 352 "mainpll_d4_d2", 353 "mainpll_d6_d2" 354 }; 355 356 static const char * const msdc50_0_parents[] = { 357 "clk26m", 358 "msdcpll_ck", 359 "msdcpll_d2", 360 "univpll_d4_d4", 361 "mainpll_d6_d2", 362 "univpll_d4_d2" 363 }; 364 365 static const char * const msdc30_1_parents[] = { 366 "clk26m", 367 "univpll_d6_d2", 368 "mainpll_d6_d2", 369 "mainpll_d7_d2", 370 "msdcpll_d2" 371 }; 372 373 static const char * const msdc30_2_parents[] = { 374 "clk26m", 375 "univpll_d6_d2", 376 "mainpll_d6_d2", 377 "mainpll_d7_d2", 378 "msdcpll_d2" 379 }; 380 381 static const char * const audio_parents[] = { 382 "clk26m", 383 "mainpll_d5_d8", 384 "mainpll_d7_d8", 385 "mainpll_d4_d16" 386 }; 387 388 static const char * const aud_intbus_parents[] = { 389 "clk26m", 390 "mainpll_d4_d4", 391 "mainpll_d7_d4" 392 }; 393 394 static const char * const pwrap_ulposc_parents[] = { 395 "osc_d10", 396 "clk26m", 397 "osc_d4", 398 "osc_d8", 399 "osc_d16" 400 }; 401 402 static const char * const atb_parents[] = { 403 "clk26m", 404 "mainpll_d4_d2", 405 "mainpll_d5_d2" 406 }; 407 408 static const char * const dpi_parents[] = { 409 "clk26m", 410 "tvdpll_d2", 411 "tvdpll_d4", 412 "tvdpll_d8", 413 "tvdpll_d16" 414 }; 415 416 static const char * const scam_parents[] = { 417 "clk26m", 418 "mainpll_d5_d4" 419 }; 420 421 static const char * const disp_pwm_parents[] = { 422 "clk26m", 423 "univpll_d6_d4", 424 "osc_d2", 425 "osc_d4", 426 "osc_d16" 427 }; 428 429 static const char * const usb_top_parents[] = { 430 "clk26m", 431 "univpll_d5_d4", 432 "univpll_d6_d4", 433 "univpll_d5_d2" 434 }; 435 436 static const char * const ssusb_xhci_parents[] = { 437 "clk26m", 438 "univpll_d5_d4", 439 "univpll_d6_d4", 440 "univpll_d5_d2" 441 }; 442 443 static const char * const i2c_parents[] = { 444 "clk26m", 445 "mainpll_d4_d8", 446 "univpll_d5_d4" 447 }; 448 449 static const char * const seninf_parents[] = { 450 "clk26m", 451 "univpll_d4_d4", 452 "univpll_d6_d2", 453 "univpll_d4_d2", 454 "univpll_d7", 455 "univpll_d6", 456 "mmpll_d6", 457 "univpll_d5" 458 }; 459 460 static const char * const seninf1_parents[] = { 461 "clk26m", 462 "univpll_d4_d4", 463 "univpll_d6_d2", 464 "univpll_d4_d2", 465 "univpll_d7", 466 "univpll_d6", 467 "mmpll_d6", 468 "univpll_d5" 469 }; 470 471 static const char * const seninf2_parents[] = { 472 "clk26m", 473 "univpll_d4_d4", 474 "univpll_d6_d2", 475 "univpll_d4_d2", 476 "univpll_d7", 477 "univpll_d6", 478 "mmpll_d6", 479 "univpll_d5" 480 }; 481 482 static const char * const seninf3_parents[] = { 483 "clk26m", 484 "univpll_d4_d4", 485 "univpll_d6_d2", 486 "univpll_d4_d2", 487 "univpll_d7", 488 "univpll_d6", 489 "mmpll_d6", 490 "univpll_d5" 491 }; 492 493 static const char * const tl_parents[] = { 494 "clk26m", 495 "univpll_192m_d2", 496 "mainpll_d6_d4" 497 }; 498 499 static const char * const dxcc_parents[] = { 500 "clk26m", 501 "mainpll_d4_d2", 502 "mainpll_d4_d4", 503 "mainpll_d4_d8" 504 }; 505 506 static const char * const aud_engen1_parents[] = { 507 "clk26m", 508 "apll1_d2", 509 "apll1_d4", 510 "apll1_d8" 511 }; 512 513 static const char * const aud_engen2_parents[] = { 514 "clk26m", 515 "apll2_d2", 516 "apll2_d4", 517 "apll2_d8" 518 }; 519 520 static const char * const aes_ufsfde_parents[] = { 521 "clk26m", 522 "mainpll_d4", 523 "mainpll_d4_d2", 524 "mainpll_d6", 525 "mainpll_d4_d4", 526 "univpll_d4_d2", 527 "univpll_d6" 528 }; 529 530 static const char * const ufs_parents[] = { 531 "clk26m", 532 "mainpll_d4_d4", 533 "mainpll_d4_d8", 534 "univpll_d4_d4", 535 "mainpll_d6_d2", 536 "mainpll_d5_d2", 537 "msdcpll_d2" 538 }; 539 540 static const char * const aud_1_parents[] = { 541 "clk26m", 542 "apll1_ck" 543 }; 544 545 static const char * const aud_2_parents[] = { 546 "clk26m", 547 "apll2_ck" 548 }; 549 550 static const char * const adsp_parents[] = { 551 "clk26m", 552 "mainpll_d6", 553 "mainpll_d5_d2", 554 "univpll_d4_d4", 555 "univpll_d4", 556 "univpll_d6", 557 "ulposc", 558 "adsppll_ck" 559 }; 560 561 static const char * const dpmaif_main_parents[] = { 562 "clk26m", 563 "univpll_d4_d4", 564 "mainpll_d6", 565 "mainpll_d4_d2", 566 "univpll_d4_d2" 567 }; 568 569 static const char * const venc_parents[] = { 570 "clk26m", 571 "mmpll_d7", 572 "mainpll_d6", 573 "univpll_d4_d2", 574 "mainpll_d4_d2", 575 "univpll_d6", 576 "mmpll_d6", 577 "mainpll_d5_d2", 578 "mainpll_d6_d2", 579 "mmpll_d9", 580 "univpll_d4_d4", 581 "mainpll_d4", 582 "univpll_d4", 583 "univpll_d5", 584 "univpll_d5_d2", 585 "mainpll_d5" 586 }; 587 588 static const char * const vdec_parents[] = { 589 "clk26m", 590 "univpll_192m_d2", 591 "univpll_d5_d4", 592 "mainpll_d5", 593 "mainpll_d5_d2", 594 "mmpll_d6_d2", 595 "univpll_d5_d2", 596 "mainpll_d4_d2", 597 "univpll_d4_d2", 598 "univpll_d7", 599 "mmpll_d7", 600 "mmpll_d6", 601 "univpll_d5", 602 "mainpll_d4", 603 "univpll_d4", 604 "univpll_d6" 605 }; 606 607 static const char * const camtm_parents[] = { 608 "clk26m", 609 "univpll_d7", 610 "univpll_d6_d2", 611 "univpll_d4_d2" 612 }; 613 614 static const char * const pwm_parents[] = { 615 "clk26m", 616 "univpll_d4_d8" 617 }; 618 619 static const char * const audio_h_parents[] = { 620 "clk26m", 621 "univpll_d7", 622 "apll1_ck", 623 "apll2_ck" 624 }; 625 626 static const char * const spmi_mst_parents[] = { 627 "clk26m", 628 "csw_f26m_d2", 629 "osc_d8", 630 "osc_d10", 631 "osc_d16", 632 "osc_d20", 633 "clk32k" 634 }; 635 636 static const char * const aes_msdcfde_parents[] = { 637 "clk26m", 638 "mainpll_d4_d2", 639 "mainpll_d6", 640 "mainpll_d4_d4", 641 "univpll_d4_d2", 642 "univpll_d6" 643 }; 644 645 static const char * const sflash_parents[] = { 646 "clk26m", 647 "mainpll_d7_d8", 648 "univpll_d6_d8", 649 "univpll_d5_d8" 650 }; 651 652 static const char * const apll_i2s0_m_parents[] = { 653 "aud_1_sel", 654 "aud_2_sel" 655 }; 656 657 static const char * const apll_i2s1_m_parents[] = { 658 "aud_1_sel", 659 "aud_2_sel" 660 }; 661 662 static const char * const apll_i2s2_m_parents[] = { 663 "aud_1_sel", 664 "aud_2_sel" 665 }; 666 667 static const char * const apll_i2s3_m_parents[] = { 668 "aud_1_sel", 669 "aud_2_sel" 670 }; 671 672 static const char * const apll_i2s4_m_parents[] = { 673 "aud_1_sel", 674 "aud_2_sel" 675 }; 676 677 static const char * const apll_i2s5_m_parents[] = { 678 "aud_1_sel", 679 "aud_2_sel" 680 }; 681 682 static const char * const apll_i2s6_m_parents[] = { 683 "aud_1_sel", 684 "aud_2_sel" 685 }; 686 687 static const char * const apll_i2s7_m_parents[] = { 688 "aud_1_sel", 689 "aud_2_sel" 690 }; 691 692 static const char * const apll_i2s8_m_parents[] = { 693 "aud_1_sel", 694 "aud_2_sel" 695 }; 696 697 static const char * const apll_i2s9_m_parents[] = { 698 "aud_1_sel", 699 "aud_2_sel" 700 }; 701 702 /* 703 * CRITICAL CLOCK: 704 * axi_sel is the main bus clock of whole SOC. 705 * spm_sel is the clock of the always-on co-processor. 706 * bus_aximem_sel is clock of the bus that access emi. 707 */ 708 static const struct mtk_mux top_mtk_muxes[] = { 709 /* CLK_CFG_0 */ 710 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", 711 axi_parents, 0x010, 0x014, 0x018, 0, 3, 7, 0x004, 0, 712 CLK_IS_CRITICAL), 713 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", 714 spm_parents, 0x010, 0x014, 0x018, 8, 2, 15, 0x004, 1, 715 CLK_IS_CRITICAL), 716 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", 717 scp_parents, 0x010, 0x014, 0x018, 16, 3, 23, 0x004, 2), 718 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel", 719 bus_aximem_parents, 0x010, 0x014, 0x018, 24, 3, 31, 0x004, 3, 720 CLK_IS_CRITICAL), 721 /* CLK_CFG_1 */ 722 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, "disp_sel", 723 disp_parents, 0x020, 0x024, 0x028, 0, 4, 7, 0x004, 4), 724 MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, "mdp_sel", 725 mdp_parents, 0x020, 0x024, 0x028, 8, 4, 15, 0x004, 5), 726 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel", 727 img1_parents, 0x020, 0x024, 0x028, 16, 4, 23, 0x004, 6), 728 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG2_SEL, "img2_sel", 729 img2_parents, 0x020, 0x024, 0x028, 24, 4, 31, 0x004, 7), 730 /* CLK_CFG_2 */ 731 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel", 732 ipe_parents, 0x030, 0x034, 0x038, 0, 4, 7, 0x004, 8), 733 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE_SEL, "dpe_sel", 734 dpe_parents, 0x030, 0x034, 0x038, 8, 3, 15, 0x004, 9), 735 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel", 736 cam_parents, 0x030, 0x034, 0x038, 16, 4, 23, 0x004, 10), 737 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel", 738 ccu_parents, 0x030, 0x034, 0x038, 24, 4, 31, 0x004, 11), 739 /* CLK_CFG_4 */ 740 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel", 741 dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16), 742 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel", 743 mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18), 744 MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel", 745 mfg_pll_parents, 0x050, 0x054, 0x058, 18, 1, -1, -1), 746 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", 747 camtg_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x004, 19), 748 /* CLK_CFG_5 */ 749 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel", 750 camtg2_parents, 0x060, 0x064, 0x068, 0, 3, 7, 0x004, 20), 751 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", 752 camtg3_parents, 0x060, 0x064, 0x068, 8, 3, 15, 0x004, 21), 753 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4_SEL, "camtg4_sel", 754 camtg4_parents, 0x060, 0x064, 0x068, 16, 3, 23, 0x004, 22), 755 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5_SEL, "camtg5_sel", 756 camtg5_parents, 0x060, 0x064, 0x068, 24, 3, 31, 0x004, 23), 757 /* CLK_CFG_6 */ 758 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6_SEL, "camtg6_sel", 759 camtg6_parents, 0x070, 0x074, 0x078, 0, 3, 7, 0x004, 24), 760 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", 761 uart_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25), 762 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", 763 spi_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x004, 26), 764 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", 765 msdc50_0_h_parents, 0x070, 0x074, 0x078, 24, 2, 31, 0x004, 27), 766 /* CLK_CFG_7 */ 767 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", 768 msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28), 769 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", 770 msdc30_1_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29), 771 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", 772 msdc30_2_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30), 773 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", 774 audio_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x008, 0), 775 /* CLK_CFG_8 */ 776 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", 777 aud_intbus_parents, 0x090, 0x094, 0x098, 0, 2, 7, 0x008, 1), 778 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL, "pwrap_ulposc_sel", 779 pwrap_ulposc_parents, 0x090, 0x094, 0x098, 8, 3, 15, 0x008, 2), 780 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", 781 atb_parents, 0x090, 0x094, 0x098, 16, 2, 23, 0x008, 3), 782 /* CLK_CFG_9 */ 783 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI_SEL, "dpi_sel", 784 dpi_parents, 0x0a0, 0x0a4, 0x0a8, 0, 3, 7, 0x008, 5), 785 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM_SEL, "scam_sel", 786 scam_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x008, 6), 787 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel", 788 disp_pwm_parents, 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, 0x008, 7), 789 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel", 790 usb_top_parents, 0x0a0, 0x0a4, 0x0a8, 24, 2, 31, 0x008, 8), 791 /* CLK_CFG_10 */ 792 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel", 793 ssusb_xhci_parents, 0x0b0, 0x0b4, 0x0b8, 0, 2, 7, 0x008, 9), 794 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", 795 i2c_parents, 0x0b0, 0x0b4, 0x0b8, 8, 2, 15, 0x008, 10), 796 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel", 797 seninf_parents, 0x0b0, 0x0b4, 0x0b8, 16, 3, 23, 0x008, 11), 798 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, "seninf1_sel", 799 seninf1_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x008, 12), 800 /* CLK_CFG_11 */ 801 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL, "seninf2_sel", 802 seninf2_parents, 0x0c0, 0x0c4, 0x0c8, 0, 3, 7, 0x008, 13), 803 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL, "seninf3_sel", 804 seninf3_parents, 0x0c0, 0x0c4, 0x0c8, 8, 3, 15, 0x008, 14), 805 MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_SEL, "tl_sel", 806 tl_parents, 0x0c0, 0x0c4, 0x0c8, 16, 2, 23, 0x008, 15), 807 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", 808 dxcc_parents, 0x0c0, 0x0c4, 0x0c8, 24, 2, 31, 0x008, 16), 809 /* CLK_CFG_12 */ 810 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", 811 aud_engen1_parents, 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x008, 17), 812 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", 813 aud_engen2_parents, 0x0d0, 0x0d4, 0x0d8, 8, 2, 15, 0x008, 18), 814 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, "aes_ufsfde_sel", 815 aes_ufsfde_parents, 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, 0x008, 19), 816 MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_SEL, "ufs_sel", 817 ufs_parents, 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, 0x008, 20), 818 /* CLK_CFG_13 */ 819 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", 820 aud_1_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, 0x008, 21), 821 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", 822 aud_2_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, 0x008, 22), 823 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_SEL, "adsp_sel", 824 adsp_parents, 0x0e0, 0x0e4, 0x0e8, 16, 3, 23, 0x008, 23), 825 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN_SEL, "dpmaif_main_sel", 826 dpmaif_main_parents, 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, 0x008, 24), 827 /* CLK_CFG_14 */ 828 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel", 829 venc_parents, 0x0f0, 0x0f4, 0x0f8, 0, 4, 7, 0x008, 25), 830 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel", 831 vdec_parents, 0x0f0, 0x0f4, 0x0f8, 8, 4, 15, 0x008, 26), 832 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", 833 camtm_parents, 0x0f0, 0x0f4, 0x0f8, 16, 2, 23, 0x008, 27), 834 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", 835 pwm_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, 31, 0x008, 28), 836 /* CLK_CFG_15 */ 837 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, "audio_h_sel", 838 audio_h_parents, 0x100, 0x104, 0x108, 0, 2, 7, 0x008, 29), 839 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST_SEL, "spmi_mst_sel", 840 spmi_mst_parents, 0x100, 0x104, 0x108, 8, 3, 15, 0x008, 30), 841 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel", 842 aes_msdcfde_parents, 0x100, 0x104, 0x108, 24, 3, 31, 0x00c, 1), 843 /* CLK_CFG_16 */ 844 MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel", 845 sflash_parents, 0x110, 0x114, 0x118, 8, 2, 15, 0x00c, 3), 846 }; 847 848 static struct mtk_composite top_muxes[] = { 849 /* CLK_AUDDIV_0 */ 850 MUX(CLK_TOP_APLL_I2S0_M_SEL, "apll_i2s0_m_sel", apll_i2s0_m_parents, 0x320, 16, 1), 851 MUX(CLK_TOP_APLL_I2S1_M_SEL, "apll_i2s1_m_sel", apll_i2s1_m_parents, 0x320, 17, 1), 852 MUX(CLK_TOP_APLL_I2S2_M_SEL, "apll_i2s2_m_sel", apll_i2s2_m_parents, 0x320, 18, 1), 853 MUX(CLK_TOP_APLL_I2S3_M_SEL, "apll_i2s3_m_sel", apll_i2s3_m_parents, 0x320, 19, 1), 854 MUX(CLK_TOP_APLL_I2S4_M_SEL, "apll_i2s4_m_sel", apll_i2s4_m_parents, 0x320, 20, 1), 855 MUX(CLK_TOP_APLL_I2S5_M_SEL, "apll_i2s5_m_sel", apll_i2s5_m_parents, 0x320, 21, 1), 856 MUX(CLK_TOP_APLL_I2S6_M_SEL, "apll_i2s6_m_sel", apll_i2s6_m_parents, 0x320, 22, 1), 857 MUX(CLK_TOP_APLL_I2S7_M_SEL, "apll_i2s7_m_sel", apll_i2s7_m_parents, 0x320, 23, 1), 858 MUX(CLK_TOP_APLL_I2S8_M_SEL, "apll_i2s8_m_sel", apll_i2s8_m_parents, 0x320, 24, 1), 859 MUX(CLK_TOP_APLL_I2S9_M_SEL, "apll_i2s9_m_sel", apll_i2s9_m_parents, 0x320, 25, 1), 860 }; 861 862 static const struct mtk_composite top_adj_divs[] = { 863 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_m_sel", 0x320, 0, 0x328, 8, 0), 864 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_m_sel", 0x320, 1, 0x328, 8, 8), 865 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_m_sel", 0x320, 2, 0x328, 8, 16), 866 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_m_sel", 0x320, 3, 0x328, 8, 24), 867 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_m_sel", 0x320, 4, 0x334, 8, 0), 868 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 5, 0x334, 8, 8), 869 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll_i2s5_m_sel", 0x320, 6, 0x334, 8, 16), 870 DIV_GATE(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll_i2s6_m_sel", 0x320, 7, 0x334, 8, 24), 871 DIV_GATE(CLK_TOP_APLL12_DIV7, "apll12_div7", "apll_i2s7_m_sel", 0x320, 8, 0x338, 8, 0), 872 DIV_GATE(CLK_TOP_APLL12_DIV8, "apll12_div8", "apll_i2s8_m_sel", 0x320, 9, 0x338, 8, 8), 873 DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "apll_i2s9_m_sel", 0x320, 10, 0x338, 8, 16), 874 }; 875 876 static const struct mtk_gate_regs apmixed_cg_regs = { 877 .set_ofs = 0x14, 878 .clr_ofs = 0x14, 879 .sta_ofs = 0x14, 880 }; 881 882 #define GATE_APMIXED(_id, _name, _parent, _shift) \ 883 GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 884 885 static const struct mtk_gate apmixed_clks[] = { 886 GATE_APMIXED(CLK_APMIXED_MIPID26M, "mipid26m", "clk26m", 16), 887 }; 888 889 static const struct mtk_gate_regs infra0_cg_regs = { 890 .set_ofs = 0x80, 891 .clr_ofs = 0x84, 892 .sta_ofs = 0x90, 893 }; 894 895 static const struct mtk_gate_regs infra1_cg_regs = { 896 .set_ofs = 0x88, 897 .clr_ofs = 0x8c, 898 .sta_ofs = 0x94, 899 }; 900 901 static const struct mtk_gate_regs infra2_cg_regs = { 902 .set_ofs = 0xa4, 903 .clr_ofs = 0xa8, 904 .sta_ofs = 0xac, 905 }; 906 907 static const struct mtk_gate_regs infra3_cg_regs = { 908 .set_ofs = 0xc0, 909 .clr_ofs = 0xc4, 910 .sta_ofs = 0xc8, 911 }; 912 913 static const struct mtk_gate_regs infra4_cg_regs = { 914 .set_ofs = 0xd0, 915 .clr_ofs = 0xd4, 916 .sta_ofs = 0xd8, 917 }; 918 919 static const struct mtk_gate_regs infra5_cg_regs = { 920 .set_ofs = 0xe0, 921 .clr_ofs = 0xe4, 922 .sta_ofs = 0xe8, 923 }; 924 925 #define GATE_INFRA0(_id, _name, _parent, _shift) \ 926 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 927 928 #define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flag) \ 929 GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \ 930 &mtk_clk_gate_ops_setclr, _flag) 931 932 #define GATE_INFRA1(_id, _name, _parent, _shift) \ 933 GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0) 934 935 #define GATE_INFRA2(_id, _name, _parent, _shift) \ 936 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 937 938 #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag) \ 939 GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, \ 940 &mtk_clk_gate_ops_setclr, _flag) 941 942 #define GATE_INFRA3(_id, _name, _parent, _shift) \ 943 GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0) 944 945 #define GATE_INFRA4(_id, _name, _parent, _shift) \ 946 GATE_MTK(_id, _name, _parent, &infra4_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 947 948 #define GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, _flag) \ 949 GATE_MTK_FLAGS(_id, _name, _parent, &infra5_cg_regs, _shift, \ 950 &mtk_clk_gate_ops_setclr, _flag) 951 952 #define GATE_INFRA5(_id, _name, _parent, _shift) \ 953 GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, 0) 954 955 /* 956 * CRITICAL CLOCK: 957 * infra_133m and infra_66m are main peripheral bus clocks of SOC. 958 * infra_device_apc and infra_device_apc_sync are for device access permission control module. 959 */ 960 static const struct mtk_gate infra_clks[] = { 961 /* INFRA0 */ 962 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "pwrap_ulposc_sel", 0), 963 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pwrap_ulposc_sel", 1), 964 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pwrap_ulposc_sel", 2), 965 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pwrap_ulposc_sel", 3), 966 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4), 967 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5), 968 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6), 969 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 8), 970 GATE_INFRA0(CLK_INFRA_GCE2, "infra_gce2", "axi_sel", 9), 971 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10), 972 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11), 973 GATE_INFRA0(CLK_INFRA_AP_DMA_PSEUDO, "infra_ap_dma_pseudo", "axi_sel", 12), 974 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13), 975 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14), 976 GATE_INFRA0(CLK_INFRA_PWM_H, "infra_pwm_h", "axi_sel", 15), 977 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "pwm_sel", 16), 978 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "pwm_sel", 17), 979 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "pwm_sel", 18), 980 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "pwm_sel", 19), 981 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21), 982 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22), 983 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), 984 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24), 985 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25), 986 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27), 987 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cq_dma_fpc", "axi_sel", 28), 988 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31), 989 /* INFRA1 */ 990 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1), 991 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_h_sel", 2), 992 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc50_0_h_sel", 4), 993 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc50_0_h_sel", 5), 994 GATE_INFRA1(CLK_INFRA_MSDC0_SRC, "infra_msdc0_src", "msdc50_0_sel", 6), 995 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8), 996 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9), 997 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10), 998 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11), 999 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12), 1000 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13), 1001 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "clk26m", 14), 1002 GATE_INFRA1(CLK_INFRA_PCIE_TL_26M, "infra_pcie_tl_26m", "axi_sel", 15), 1003 GATE_INFRA1(CLK_INFRA_MSDC1_SRC, "infra_msdc1_src", "msdc30_1_sel", 16), 1004 GATE_INFRA1(CLK_INFRA_MSDC2_SRC, "infra_msdc2_src", "msdc30_2_sel", 17), 1005 GATE_INFRA1(CLK_INFRA_PCIE_TL_96M, "infra_pcie_tl_96m", "tl_sel", 18), 1006 GATE_INFRA1(CLK_INFRA_PCIE_PL_P_250M, "infra_pcie_pl_p_250m", "axi_sel", 19), 1007 GATE_INFRA1_FLAGS(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20, CLK_IS_CRITICAL), 1008 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23), 1009 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24), 1010 GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25), 1011 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26), 1012 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 27), 1013 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28), 1014 GATE_INFRA1(CLK_INFRA_DBG_TRACE, "infra_dbg_trace", "axi_sel", 29), 1015 GATE_INFRA1(CLK_INFRA_DEVMPU_B, "infra_devmpu_b", "axi_sel", 30), 1016 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31), 1017 /* INFRA2 */ 1018 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "clk26m", 0), 1019 GATE_INFRA2(CLK_INFRA_SSUSB, "infra_ssusb", "usb_top_sel", 1), 1020 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "axi_sel", 2), 1021 GATE_INFRA2(CLK_INFRA_CLDMA_B, "infra_cldma_b", "axi_sel", 3), 1022 GATE_INFRA2(CLK_INFRA_AUDIO_26M_B, "infra_audio_26m_b", "clk26m", 4), 1023 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share", "clk26m", 5), 1024 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6), 1025 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7), 1026 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9), 1027 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10), 1028 GATE_INFRA2(CLK_INFRA_UNIPRO_SYS, "infra_unipro_sys", "ufs_sel", 11), 1029 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "clk26m", 12), 1030 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_B, "infra_ufs_mp_sap_b", "clk26m", 13), 1031 GATE_INFRA2(CLK_INFRA_MD32_B, "infra_md32_b", "axi_sel", 14), 1032 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16), 1033 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18), 1034 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19), 1035 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20), 1036 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21), 1037 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22), 1038 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23), 1039 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24), 1040 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25), 1041 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26), 1042 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cq_dma", "axi_sel", 27), 1043 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "ufs_sel", 28), 1044 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "aes_ufsfde_sel", 29), 1045 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "ufs_sel", 30), 1046 GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci", "ssusb_xhci_sel", 31), 1047 /* INFRA3 */ 1048 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0), 1049 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1), 1050 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2), 1051 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5), 1052 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6), 1053 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_0_sel", 7), 1054 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_0_sel", 8), 1055 GATE_INFRA3(CLK_INFRA_CCIF5_AP, "infra_ccif5_ap", "axi_sel", 9), 1056 GATE_INFRA3(CLK_INFRA_CCIF5_MD, "infra_ccif5_md", "axi_sel", 10), 1057 GATE_INFRA3(CLK_INFRA_PCIE_TOP_H_133M, "infra_pcie_top_h_133m", "axi_sel", 11), 1058 GATE_INFRA3(CLK_INFRA_FLASHIF_TOP_H_133M, "infra_flashif_top_h_133m", "axi_sel", 14), 1059 GATE_INFRA3(CLK_INFRA_PCIE_PERI_26M, "infra_pcie_peri_26m", "axi_sel", 15), 1060 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16), 1061 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17), 1062 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18), 1063 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19), 1064 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "clk26m", 20), 1065 GATE_INFRA3(CLK_INFRA_AES, "infra_aes", "axi_sel", 21), 1066 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22), 1067 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23), 1068 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24), 1069 GATE_INFRA3_FLAGS(CLK_INFRA_DEVICE_APC_SYNC, "infra_device_apc_sync", "axi_sel", 25, 1070 CLK_IS_CRITICAL), 1071 GATE_INFRA3(CLK_INFRA_DPMAIF_MAIN, "infra_dpmaif_main", "dpmaif_main_sel", 26), 1072 GATE_INFRA3(CLK_INFRA_PCIE_TL_32K, "infra_pcie_tl_32k", "axi_sel", 27), 1073 GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap", "axi_sel", 28), 1074 GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md", "axi_sel", 29), 1075 GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6", "spi_sel", 30), 1076 GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7", "spi_sel", 31), 1077 /* INFRA4 */ 1078 GATE_INFRA4(CLK_INFRA_AP_DMA, "infra_ap_dma", "infra_ap_dma_pseudo", 31), 1079 /* INFRA5 */ 1080 GATE_INFRA5_FLAGS(CLK_INFRA_133M, "infra_133m", "axi_sel", 0, CLK_IS_CRITICAL), 1081 GATE_INFRA5_FLAGS(CLK_INFRA_66M, "infra_66m", "axi_sel", 1, CLK_IS_CRITICAL), 1082 GATE_INFRA5(CLK_INFRA_66M_PERI_BUS, "infra_66m_peri_bus", "axi_sel", 2), 1083 GATE_INFRA5(CLK_INFRA_FREE_DCM_133M, "infra_free_dcm_133m", "axi_sel", 3), 1084 GATE_INFRA5(CLK_INFRA_FREE_DCM_66M, "infra_free_dcm_66m", "axi_sel", 4), 1085 GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_133M, "infra_peri_bus_dcm_133m", "axi_sel", 5), 1086 GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_66M, "infra_peri_bus_dcm_66m", "axi_sel", 6), 1087 GATE_INFRA5(CLK_INFRA_FLASHIF_PERI_26M, "infra_flashif_peri_26m", "axi_sel", 30), 1088 GATE_INFRA5(CLK_INFRA_FLASHIF_SFLASH, "infra_flashif_fsflash", "axi_sel", 31), 1089 }; 1090 1091 static const struct mtk_gate_regs peri_cg_regs = { 1092 .set_ofs = 0x20c, 1093 .clr_ofs = 0x20c, 1094 .sta_ofs = 0x20c, 1095 }; 1096 1097 #define GATE_PERI(_id, _name, _parent, _shift) \ 1098 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 1099 1100 static const struct mtk_gate peri_clks[] = { 1101 GATE_PERI(CLK_PERI_PERIAXI, "peri_periaxi", "axi_sel", 31), 1102 }; 1103 1104 static const struct mtk_gate_regs top_cg_regs = { 1105 .set_ofs = 0x150, 1106 .clr_ofs = 0x150, 1107 .sta_ofs = 0x150, 1108 }; 1109 1110 #define GATE_TOP(_id, _name, _parent, _shift) \ 1111 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 1112 1113 static const struct mtk_gate top_clks[] = { 1114 GATE_TOP(CLK_TOP_SSUSB_TOP_REF, "ssusb_top_ref", "clk26m", 24), 1115 GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25), 1116 }; 1117 1118 static u16 infra_ao_rst_ofs[] = { 1119 INFRA_RST0_SET_OFFSET, 1120 INFRA_RST1_SET_OFFSET, 1121 INFRA_RST2_SET_OFFSET, 1122 INFRA_RST3_SET_OFFSET, 1123 INFRA_RST4_SET_OFFSET, 1124 }; 1125 1126 static u16 infra_ao_idx_map[] = { 1127 [MT8192_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0, 1128 [MT8192_INFRA_RST2_PEXTP_PHY_SWRST] = 2 * RST_NR_PER_BANK + 15, 1129 [MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5, 1130 [MT8192_INFRA_RST4_PCIE_TOP_SWRST] = 4 * RST_NR_PER_BANK + 1, 1131 [MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 12, 1132 }; 1133 1134 static const struct mtk_clk_rst_desc clk_rst_desc = { 1135 .version = MTK_RST_SET_CLR, 1136 .rst_bank_ofs = infra_ao_rst_ofs, 1137 .rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs), 1138 .rst_idx_map = infra_ao_idx_map, 1139 .rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map), 1140 }; 1141 1142 #define MT8192_PLL_FMAX (3800UL * MHZ) 1143 #define MT8192_PLL_FMIN (1500UL * MHZ) 1144 #define MT8192_INTEGER_BITS 8 1145 1146 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1147 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 1148 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 1149 _pcw_reg, _pcw_shift, _pcw_chg_reg, \ 1150 _en_reg, _pll_en_bit) { \ 1151 .id = _id, \ 1152 .name = _name, \ 1153 .reg = _reg, \ 1154 .pwr_reg = _pwr_reg, \ 1155 .en_mask = _en_mask, \ 1156 .flags = _flags, \ 1157 .rst_bar_mask = _rst_bar_mask, \ 1158 .fmax = MT8192_PLL_FMAX, \ 1159 .fmin = MT8192_PLL_FMIN, \ 1160 .pcwbits = _pcwbits, \ 1161 .pcwibits = MT8192_INTEGER_BITS, \ 1162 .pd_reg = _pd_reg, \ 1163 .pd_shift = _pd_shift, \ 1164 .tuner_reg = _tuner_reg, \ 1165 .tuner_en_reg = _tuner_en_reg, \ 1166 .tuner_en_bit = _tuner_en_bit, \ 1167 .pcw_reg = _pcw_reg, \ 1168 .pcw_shift = _pcw_shift, \ 1169 .pcw_chg_reg = _pcw_chg_reg, \ 1170 .en_reg = _en_reg, \ 1171 .pll_en_bit = _pll_en_bit, \ 1172 } 1173 1174 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1175 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 1176 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 1177 _pcw_reg, _pcw_shift) \ 1178 PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ 1179 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \ 1180 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ 1181 _pcw_reg, _pcw_shift, 0, 0, 0) 1182 1183 static const struct mtk_pll_data plls[] = { 1184 PLL_B(CLK_APMIXED_MAINPLL, "mainpll", 0x0340, 0x034c, 0xff000000, 1185 HAVE_RST_BAR, BIT(23), 22, 0x0344, 24, 0, 0, 0, 0x0344, 0), 1186 PLL_B(CLK_APMIXED_UNIVPLL, "univpll", 0x0308, 0x0314, 0xff000000, 1187 HAVE_RST_BAR, BIT(23), 22, 0x030c, 24, 0, 0, 0, 0x030c, 0), 1188 PLL(CLK_APMIXED_USBPLL, "usbpll", 0x03c4, 0x03cc, 0x00000000, 1189 0, 0, 22, 0x03c4, 24, 0, 0, 0, 0x03c4, 0, 0x03c4, 0x03cc, 2), 1190 PLL_B(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0350, 0x035c, 0x00000000, 1191 0, 0, 22, 0x0354, 24, 0, 0, 0, 0x0354, 0), 1192 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0360, 0x036c, 0xff000000, 1193 HAVE_RST_BAR, BIT(23), 22, 0x0364, 24, 0, 0, 0, 0x0364, 0), 1194 PLL_B(CLK_APMIXED_ADSPPLL, "adsppll", 0x0370, 0x037c, 0xff000000, 1195 HAVE_RST_BAR, BIT(23), 22, 0x0374, 24, 0, 0, 0, 0x0374, 0), 1196 PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0268, 0x0274, 0x00000000, 1197 0, 0, 22, 0x026c, 24, 0, 0, 0, 0x026c, 0), 1198 PLL_B(CLK_APMIXED_TVDPLL, "tvdpll", 0x0380, 0x038c, 0x00000000, 1199 0, 0, 22, 0x0384, 24, 0, 0, 0, 0x0384, 0), 1200 PLL_B(CLK_APMIXED_APLL1, "apll1", 0x0318, 0x0328, 0x00000000, 1201 0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0), 1202 PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x00000000, 1203 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0), 1204 }; 1205 1206 static struct clk_hw_onecell_data *top_clk_data; 1207 1208 static void clk_mt8192_top_init_early(struct device_node *node) 1209 { 1210 int i; 1211 1212 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); 1213 if (!top_clk_data) 1214 return; 1215 1216 for (i = 0; i < CLK_TOP_NR_CLK; i++) 1217 top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); 1218 1219 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data); 1220 1221 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); 1222 } 1223 1224 CLK_OF_DECLARE_DRIVER(mt8192_topckgen, "mediatek,mt8192-topckgen", 1225 clk_mt8192_top_init_early); 1226 1227 static int clk_mt8192_top_probe(struct platform_device *pdev) 1228 { 1229 struct device_node *node = pdev->dev.of_node; 1230 int r; 1231 void __iomem *base; 1232 1233 base = devm_platform_ioremap_resource(pdev, 0); 1234 if (IS_ERR(base)) 1235 return PTR_ERR(base); 1236 1237 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data); 1238 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data); 1239 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); 1240 mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node, &mt8192_clk_lock, 1241 top_clk_data); 1242 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, &mt8192_clk_lock, 1243 top_clk_data); 1244 mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt8192_clk_lock, 1245 top_clk_data); 1246 r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data); 1247 if (r) 1248 return r; 1249 1250 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, 1251 top_clk_data); 1252 } 1253 1254 static int clk_mt8192_infra_probe(struct platform_device *pdev) 1255 { 1256 struct clk_hw_onecell_data *clk_data; 1257 struct device_node *node = pdev->dev.of_node; 1258 int r; 1259 1260 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 1261 if (!clk_data) 1262 return -ENOMEM; 1263 1264 r = mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data); 1265 if (r) 1266 goto free_clk_data; 1267 1268 r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); 1269 if (r) 1270 goto free_clk_data; 1271 1272 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1273 if (r) 1274 goto free_clk_data; 1275 1276 return r; 1277 1278 free_clk_data: 1279 mtk_free_clk_data(clk_data); 1280 return r; 1281 } 1282 1283 static int clk_mt8192_peri_probe(struct platform_device *pdev) 1284 { 1285 struct clk_hw_onecell_data *clk_data; 1286 struct device_node *node = pdev->dev.of_node; 1287 int r; 1288 1289 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); 1290 if (!clk_data) 1291 return -ENOMEM; 1292 1293 r = mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), clk_data); 1294 if (r) 1295 goto free_clk_data; 1296 1297 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1298 if (r) 1299 goto free_clk_data; 1300 1301 return r; 1302 1303 free_clk_data: 1304 mtk_free_clk_data(clk_data); 1305 return r; 1306 } 1307 1308 static int clk_mt8192_apmixed_probe(struct platform_device *pdev) 1309 { 1310 struct clk_hw_onecell_data *clk_data; 1311 struct device_node *node = pdev->dev.of_node; 1312 int r; 1313 1314 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); 1315 if (!clk_data) 1316 return -ENOMEM; 1317 1318 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); 1319 r = mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); 1320 if (r) 1321 goto free_clk_data; 1322 1323 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); 1324 if (r) 1325 goto free_clk_data; 1326 1327 return r; 1328 1329 free_clk_data: 1330 mtk_free_clk_data(clk_data); 1331 return r; 1332 } 1333 1334 static const struct of_device_id of_match_clk_mt8192[] = { 1335 { 1336 .compatible = "mediatek,mt8192-apmixedsys", 1337 .data = clk_mt8192_apmixed_probe, 1338 }, { 1339 .compatible = "mediatek,mt8192-topckgen", 1340 .data = clk_mt8192_top_probe, 1341 }, { 1342 .compatible = "mediatek,mt8192-infracfg", 1343 .data = clk_mt8192_infra_probe, 1344 }, { 1345 .compatible = "mediatek,mt8192-pericfg", 1346 .data = clk_mt8192_peri_probe, 1347 }, { 1348 /* sentinel */ 1349 } 1350 }; 1351 1352 static int clk_mt8192_probe(struct platform_device *pdev) 1353 { 1354 int (*clk_probe)(struct platform_device *pdev); 1355 int r; 1356 1357 clk_probe = of_device_get_match_data(&pdev->dev); 1358 if (!clk_probe) 1359 return -EINVAL; 1360 1361 r = clk_probe(pdev); 1362 if (r) 1363 dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); 1364 1365 return r; 1366 } 1367 1368 static struct platform_driver clk_mt8192_drv = { 1369 .probe = clk_mt8192_probe, 1370 .driver = { 1371 .name = "clk-mt8192", 1372 .of_match_table = of_match_clk_mt8192, 1373 }, 1374 }; 1375 1376 static int __init clk_mt8192_init(void) 1377 { 1378 return platform_driver_register(&clk_mt8192_drv); 1379 } 1380 1381 arch_initcall(clk_mt8192_init); 1382