1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Copyright (c) 2021 MediaTek Inc.
4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
5 
6 #include <linux/clk.h>
7 #include <linux/delay.h>
8 #include <linux/mfd/syscon.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/slab.h>
14 
15 #include "clk-gate.h"
16 #include "clk-mtk.h"
17 #include "clk-mux.h"
18 
19 #include <dt-bindings/clock/mt8192-clk.h>
20 #include <dt-bindings/reset/mt8192-resets.h>
21 
22 static DEFINE_SPINLOCK(mt8192_clk_lock);
23 
24 static const struct mtk_fixed_clk top_fixed_clks[] = {
25 	FIXED_CLK(CLK_TOP_ULPOSC, "ulposc", NULL, 260000000),
26 };
27 
28 static const struct mtk_fixed_factor top_divs[] = {
29 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
30 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
31 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0),
32 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0),
33 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0),
34 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16, 0),
35 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
36 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
37 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
38 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0),
39 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6, 0),
40 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2, 0),
41 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4, 0),
42 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7, 0),
43 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2, 0),
44 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4, 0),
45 	FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8, 0),
46 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
47 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4, 0),
48 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2, 0),
49 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4, 0),
50 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8, 0),
51 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
52 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
53 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
54 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0),
55 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6, 0),
56 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2, 0),
57 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4, 0),
58 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8, 0),
59 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16, 0),
60 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
61 	FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
62 	FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
63 	FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
64 	FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
65 	FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
66 	FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
67 	FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
68 	FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
69 	FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
70 	FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
71 	FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
72 	FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
73 	FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
74 	FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll_d6", 1, 2),
75 	FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
76 	FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9),
77 	FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 2),
78 	FACTOR(CLK_TOP_NPUPLL, "npupll_ck", "npupll", 1, 1),
79 	FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
80 	FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
81 	FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
82 	FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
83 	FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
84 	FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
85 	FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
86 	FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
87 	FACTOR(CLK_TOP_OSC_D2, "osc_d2", "ulposc", 1, 2),
88 	FACTOR(CLK_TOP_OSC_D4, "osc_d4", "ulposc", 1, 4),
89 	FACTOR(CLK_TOP_OSC_D8, "osc_d8", "ulposc", 1, 8),
90 	FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10),
91 	FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16),
92 	FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20),
93 	FACTOR(CLK_TOP_CSW_F26M_D2, "csw_f26m_d2", "clk26m", 1, 2),
94 	FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1),
95 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13, 0),
96 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2, 0),
97 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4, 0),
98 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8, 0),
99 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16, 0),
100 	FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32, 0),
101 };
102 
103 static const char * const axi_parents[] = {
104 	"clk26m",
105 	"mainpll_d4_d4",
106 	"mainpll_d7_d2",
107 	"mainpll_d4_d2",
108 	"mainpll_d5_d2",
109 	"mainpll_d6_d2",
110 	"osc_d4"
111 };
112 
113 static const char * const spm_parents[] = {
114 	"clk26m",
115 	"osc_d10",
116 	"mainpll_d7_d4",
117 	"clk32k"
118 };
119 
120 static const char * const scp_parents[] = {
121 	"clk26m",
122 	"univpll_d5",
123 	"mainpll_d6_d2",
124 	"mainpll_d6",
125 	"univpll_d6",
126 	"mainpll_d4_d2",
127 	"mainpll_d5_d2",
128 	"univpll_d4_d2"
129 };
130 
131 static const char * const bus_aximem_parents[] = {
132 	"clk26m",
133 	"mainpll_d7_d2",
134 	"mainpll_d4_d2",
135 	"mainpll_d5_d2",
136 	"mainpll_d6"
137 };
138 
139 static const char * const disp_parents[] = {
140 	"clk26m",
141 	"univpll_d6_d2",
142 	"mainpll_d5_d2",
143 	"mmpll_d6_d2",
144 	"univpll_d5_d2",
145 	"univpll_d4_d2",
146 	"mmpll_d7",
147 	"univpll_d6",
148 	"mainpll_d4",
149 	"mmpll_d5_d2"
150 };
151 
152 static const char * const mdp_parents[] = {
153 	"clk26m",
154 	"mainpll_d5_d2",
155 	"mmpll_d6_d2",
156 	"mainpll_d4_d2",
157 	"mmpll_d4_d2",
158 	"mainpll_d6",
159 	"univpll_d6",
160 	"mainpll_d4",
161 	"tvdpll_ck",
162 	"univpll_d4",
163 	"mmpll_d5_d2"
164 };
165 
166 static const char * const img_parents[] = {
167 	"clk26m",
168 	"univpll_d4",
169 	"tvdpll_ck",
170 	"mainpll_d4",
171 	"univpll_d5",
172 	"mmpll_d6",
173 	"univpll_d6",
174 	"mainpll_d6",
175 	"mmpll_d4_d2",
176 	"mainpll_d4_d2",
177 	"mmpll_d6_d2",
178 	"mmpll_d5_d2"
179 };
180 
181 static const char * const ipe_parents[] = {
182 	"clk26m",
183 	"mainpll_d4",
184 	"mmpll_d6",
185 	"univpll_d6",
186 	"mainpll_d6",
187 	"univpll_d4_d2",
188 	"mainpll_d4_d2",
189 	"mmpll_d6_d2",
190 	"mmpll_d5_d2"
191 };
192 
193 static const char * const dpe_parents[] = {
194 	"clk26m",
195 	"mainpll_d4",
196 	"mmpll_d6",
197 	"univpll_d6",
198 	"mainpll_d6",
199 	"univpll_d4_d2",
200 	"univpll_d5_d2",
201 	"mmpll_d6_d2"
202 };
203 
204 static const char * const cam_parents[] = {
205 	"clk26m",
206 	"mainpll_d4",
207 	"mmpll_d6",
208 	"univpll_d4",
209 	"univpll_d5",
210 	"univpll_d6",
211 	"mmpll_d7",
212 	"univpll_d4_d2",
213 	"mainpll_d4_d2",
214 	"univpll_d6_d2"
215 };
216 
217 static const char * const ccu_parents[] = {
218 	"clk26m",
219 	"mainpll_d4",
220 	"mmpll_d6",
221 	"mainpll_d6",
222 	"mmpll_d7",
223 	"univpll_d4_d2",
224 	"mmpll_d6_d2",
225 	"mmpll_d5_d2",
226 	"univpll_d5",
227 	"univpll_d6_d2"
228 };
229 
230 static const char * const dsp7_parents[] = {
231 	"clk26m",
232 	"mainpll_d4_d2",
233 	"mainpll_d6",
234 	"mmpll_d6",
235 	"univpll_d5",
236 	"mmpll_d5",
237 	"univpll_d4",
238 	"mmpll_d4"
239 };
240 
241 static const char * const mfg_ref_parents[] = {
242 	"clk26m",
243 	"clk26m",
244 	"univpll_d6",
245 	"mainpll_d5_d2"
246 };
247 
248 static const char * const mfg_pll_parents[] = {
249 	"mfg_ref_sel",
250 	"mfgpll"
251 };
252 
253 static const char * const camtg_parents[] = {
254 	"clk26m",
255 	"univpll_192m_d8",
256 	"univpll_d6_d8",
257 	"univpll_192m_d4",
258 	"univpll_d6_d16",
259 	"csw_f26m_d2",
260 	"univpll_192m_d16",
261 	"univpll_192m_d32"
262 };
263 
264 static const char * const uart_parents[] = {
265 	"clk26m",
266 	"univpll_d6_d8"
267 };
268 
269 static const char * const spi_parents[] = {
270 	"clk26m",
271 	"mainpll_d5_d4",
272 	"mainpll_d6_d4",
273 	"msdcpll_d4"
274 };
275 
276 static const char * const msdc50_0_h_parents[] = {
277 	"clk26m",
278 	"mainpll_d4_d2",
279 	"mainpll_d6_d2"
280 };
281 
282 static const char * const msdc50_0_parents[] = {
283 	"clk26m",
284 	"msdcpll_ck",
285 	"msdcpll_d2",
286 	"univpll_d4_d4",
287 	"mainpll_d6_d2",
288 	"univpll_d4_d2"
289 };
290 
291 static const char * const msdc30_parents[] = {
292 	"clk26m",
293 	"univpll_d6_d2",
294 	"mainpll_d6_d2",
295 	"mainpll_d7_d2",
296 	"msdcpll_d2"
297 };
298 
299 static const char * const audio_parents[] = {
300 	"clk26m",
301 	"mainpll_d5_d8",
302 	"mainpll_d7_d8",
303 	"mainpll_d4_d16"
304 };
305 
306 static const char * const aud_intbus_parents[] = {
307 	"clk26m",
308 	"mainpll_d4_d4",
309 	"mainpll_d7_d4"
310 };
311 
312 static const char * const pwrap_ulposc_parents[] = {
313 	"osc_d10",
314 	"clk26m",
315 	"osc_d4",
316 	"osc_d8",
317 	"osc_d16"
318 };
319 
320 static const char * const atb_parents[] = {
321 	"clk26m",
322 	"mainpll_d4_d2",
323 	"mainpll_d5_d2"
324 };
325 
326 static const char * const dpi_parents[] = {
327 	"clk26m",
328 	"tvdpll_d2",
329 	"tvdpll_d4",
330 	"tvdpll_d8",
331 	"tvdpll_d16"
332 };
333 
334 static const char * const scam_parents[] = {
335 	"clk26m",
336 	"mainpll_d5_d4"
337 };
338 
339 static const char * const disp_pwm_parents[] = {
340 	"clk26m",
341 	"univpll_d6_d4",
342 	"osc_d2",
343 	"osc_d4",
344 	"osc_d16"
345 };
346 
347 static const char * const usb_top_parents[] = {
348 	"clk26m",
349 	"univpll_d5_d4",
350 	"univpll_d6_d4",
351 	"univpll_d5_d2"
352 };
353 
354 static const char * const ssusb_xhci_parents[] = {
355 	"clk26m",
356 	"univpll_d5_d4",
357 	"univpll_d6_d4",
358 	"univpll_d5_d2"
359 };
360 
361 static const char * const i2c_parents[] = {
362 	"clk26m",
363 	"mainpll_d4_d8",
364 	"univpll_d5_d4"
365 };
366 
367 static const char * const seninf_parents[] = {
368 	"clk26m",
369 	"univpll_d4_d4",
370 	"univpll_d6_d2",
371 	"univpll_d4_d2",
372 	"univpll_d7",
373 	"univpll_d6",
374 	"mmpll_d6",
375 	"univpll_d5"
376 };
377 
378 static const char * const tl_parents[] = {
379 	"clk26m",
380 	"univpll_192m_d2",
381 	"mainpll_d6_d4"
382 };
383 
384 static const char * const dxcc_parents[] = {
385 	"clk26m",
386 	"mainpll_d4_d2",
387 	"mainpll_d4_d4",
388 	"mainpll_d4_d8"
389 };
390 
391 static const char * const aud_engen1_parents[] = {
392 	"clk26m",
393 	"apll1_d2",
394 	"apll1_d4",
395 	"apll1_d8"
396 };
397 
398 static const char * const aud_engen2_parents[] = {
399 	"clk26m",
400 	"apll2_d2",
401 	"apll2_d4",
402 	"apll2_d8"
403 };
404 
405 static const char * const aes_ufsfde_parents[] = {
406 	"clk26m",
407 	"mainpll_d4",
408 	"mainpll_d4_d2",
409 	"mainpll_d6",
410 	"mainpll_d4_d4",
411 	"univpll_d4_d2",
412 	"univpll_d6"
413 };
414 
415 static const char * const ufs_parents[] = {
416 	"clk26m",
417 	"mainpll_d4_d4",
418 	"mainpll_d4_d8",
419 	"univpll_d4_d4",
420 	"mainpll_d6_d2",
421 	"mainpll_d5_d2",
422 	"msdcpll_d2"
423 };
424 
425 static const char * const aud_1_parents[] = {
426 	"clk26m",
427 	"apll1_ck"
428 };
429 
430 static const char * const aud_2_parents[] = {
431 	"clk26m",
432 	"apll2_ck"
433 };
434 
435 static const char * const adsp_parents[] = {
436 	"clk26m",
437 	"mainpll_d6",
438 	"mainpll_d5_d2",
439 	"univpll_d4_d4",
440 	"univpll_d4",
441 	"univpll_d6",
442 	"ulposc",
443 	"adsppll_ck"
444 };
445 
446 static const char * const dpmaif_main_parents[] = {
447 	"clk26m",
448 	"univpll_d4_d4",
449 	"mainpll_d6",
450 	"mainpll_d4_d2",
451 	"univpll_d4_d2"
452 };
453 
454 static const char * const venc_parents[] = {
455 	"clk26m",
456 	"mmpll_d7",
457 	"mainpll_d6",
458 	"univpll_d4_d2",
459 	"mainpll_d4_d2",
460 	"univpll_d6",
461 	"mmpll_d6",
462 	"mainpll_d5_d2",
463 	"mainpll_d6_d2",
464 	"mmpll_d9",
465 	"univpll_d4_d4",
466 	"mainpll_d4",
467 	"univpll_d4",
468 	"univpll_d5",
469 	"univpll_d5_d2",
470 	"mainpll_d5"
471 };
472 
473 static const char * const vdec_parents[] = {
474 	"clk26m",
475 	"univpll_192m_d2",
476 	"univpll_d5_d4",
477 	"mainpll_d5",
478 	"mainpll_d5_d2",
479 	"mmpll_d6_d2",
480 	"univpll_d5_d2",
481 	"mainpll_d4_d2",
482 	"univpll_d4_d2",
483 	"univpll_d7",
484 	"mmpll_d7",
485 	"mmpll_d6",
486 	"univpll_d5",
487 	"mainpll_d4",
488 	"univpll_d4",
489 	"univpll_d6"
490 };
491 
492 static const char * const camtm_parents[] = {
493 	"clk26m",
494 	"univpll_d7",
495 	"univpll_d6_d2",
496 	"univpll_d4_d2"
497 };
498 
499 static const char * const pwm_parents[] = {
500 	"clk26m",
501 	"univpll_d4_d8"
502 };
503 
504 static const char * const audio_h_parents[] = {
505 	"clk26m",
506 	"univpll_d7",
507 	"apll1_ck",
508 	"apll2_ck"
509 };
510 
511 static const char * const spmi_mst_parents[] = {
512 	"clk26m",
513 	"csw_f26m_d2",
514 	"osc_d8",
515 	"osc_d10",
516 	"osc_d16",
517 	"osc_d20",
518 	"clk32k"
519 };
520 
521 static const char * const aes_msdcfde_parents[] = {
522 	"clk26m",
523 	"mainpll_d4_d2",
524 	"mainpll_d6",
525 	"mainpll_d4_d4",
526 	"univpll_d4_d2",
527 	"univpll_d6"
528 };
529 
530 static const char * const sflash_parents[] = {
531 	"clk26m",
532 	"mainpll_d7_d8",
533 	"univpll_d6_d8",
534 	"univpll_d5_d8"
535 };
536 
537 static const char * const apll_i2s_m_parents[] = {
538 	"aud_1_sel",
539 	"aud_2_sel"
540 };
541 
542 /*
543  * CRITICAL CLOCK:
544  * axi_sel is the main bus clock of whole SOC.
545  * spm_sel is the clock of the always-on co-processor.
546  * bus_aximem_sel is clock of the bus that access emi.
547  */
548 static const struct mtk_mux top_mtk_muxes[] = {
549 	/* CLK_CFG_0 */
550 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel",
551 				   axi_parents, 0x010, 0x014, 0x018, 0, 3, 7, 0x004, 0,
552 				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
553 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel",
554 				   spm_parents, 0x010, 0x014, 0x018, 8, 2, 15, 0x004, 1,
555 				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
556 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel",
557 			     scp_parents, 0x010, 0x014, 0x018, 16, 3, 23, 0x004, 2),
558 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel",
559 				   bus_aximem_parents, 0x010, 0x014, 0x018, 24, 3, 31, 0x004, 3,
560 				   CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
561 	/* CLK_CFG_1 */
562 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL, "disp_sel",
563 			     disp_parents, 0x020, 0x024, 0x028, 0, 4, 7, 0x004, 4),
564 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL, "mdp_sel",
565 			     mdp_parents, 0x020, 0x024, 0x028, 8, 4, 15, 0x004, 5),
566 	MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel",
567 			     img_parents, 0x020, 0x024, 0x028, 16, 4, 23, 0x004, 6),
568 	MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG2_SEL, "img2_sel",
569 			     img_parents, 0x020, 0x024, 0x028, 24, 4, 31, 0x004, 7),
570 	/* CLK_CFG_2 */
571 	MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel",
572 			     ipe_parents, 0x030, 0x034, 0x038, 0, 4, 7, 0x004, 8),
573 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE_SEL, "dpe_sel",
574 			     dpe_parents, 0x030, 0x034, 0x038, 8, 3, 15, 0x004, 9),
575 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel",
576 			     cam_parents, 0x030, 0x034, 0x038, 16, 4, 23, 0x004, 10),
577 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel",
578 			     ccu_parents, 0x030, 0x034, 0x038, 24, 4, 31, 0x004, 11),
579 	/* CLK_CFG_4 */
580 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel",
581 			     dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16),
582 	MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel",
583 			     mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18),
584 	MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel",
585 			mfg_pll_parents, 0x050, 0x054, 0x058, 18, 1, -1, -1),
586 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
587 			     camtg_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x004, 19),
588 	/* CLK_CFG_5 */
589 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
590 			     camtg_parents, 0x060, 0x064, 0x068, 0, 3, 7, 0x004, 20),
591 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel",
592 			     camtg_parents, 0x060, 0x064, 0x068, 8, 3, 15, 0x004, 21),
593 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4_SEL, "camtg4_sel",
594 			     camtg_parents, 0x060, 0x064, 0x068, 16, 3, 23, 0x004, 22),
595 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5_SEL, "camtg5_sel",
596 			     camtg_parents, 0x060, 0x064, 0x068, 24, 3, 31, 0x004, 23),
597 	/* CLK_CFG_6 */
598 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6_SEL, "camtg6_sel",
599 			     camtg_parents, 0x070, 0x074, 0x078, 0, 3, 7, 0x004, 24),
600 	MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel",
601 			     uart_parents, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25),
602 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel",
603 			     spi_parents, 0x070, 0x074, 0x078, 16, 2, 23, 0x004, 26),
604 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel",
605 				   msdc50_0_h_parents, 0x070, 0x074, 0x078, 24, 2,
606 				   31, 0x004, 27, 0),
607 	/* CLK_CFG_7 */
608 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
609 				   msdc50_0_parents, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28, 0),
610 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
611 				   msdc30_parents, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29, 0),
612 	MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
613 				   msdc30_parents, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30, 0),
614 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel",
615 			     audio_parents, 0x080, 0x084, 0x088, 24, 2, 31, 0x008, 0),
616 	/* CLK_CFG_8 */
617 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
618 			     aud_intbus_parents, 0x090, 0x094, 0x098, 0, 2, 7, 0x008, 1),
619 	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL, "pwrap_ulposc_sel",
620 			     pwrap_ulposc_parents, 0x090, 0x094, 0x098, 8, 3, 15, 0x008, 2),
621 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel",
622 			     atb_parents, 0x090, 0x094, 0x098, 16, 2, 23, 0x008, 3),
623 	/* CLK_CFG_9 */
624 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI_SEL, "dpi_sel",
625 			     dpi_parents, 0x0a0, 0x0a4, 0x0a8, 0, 3, 7, 0x008, 5),
626 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM_SEL, "scam_sel",
627 			     scam_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x008, 6),
628 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
629 			     disp_pwm_parents, 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, 0x008, 7),
630 	MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel",
631 			     usb_top_parents, 0x0a0, 0x0a4, 0x0a8, 24, 2, 31, 0x008, 8),
632 	/* CLK_CFG_10 */
633 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel",
634 			     ssusb_xhci_parents, 0x0b0, 0x0b4, 0x0b8, 0, 2, 7, 0x008, 9),
635 	MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel",
636 			     i2c_parents, 0x0b0, 0x0b4, 0x0b8, 8, 2, 15, 0x008, 10),
637 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel",
638 			     seninf_parents, 0x0b0, 0x0b4, 0x0b8, 16, 3, 23, 0x008, 11),
639 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, "seninf1_sel",
640 			     seninf_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x008, 12),
641 	/* CLK_CFG_11 */
642 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL, "seninf2_sel",
643 			     seninf_parents, 0x0c0, 0x0c4, 0x0c8, 0, 3, 7, 0x008, 13),
644 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL, "seninf3_sel",
645 			     seninf_parents, 0x0c0, 0x0c4, 0x0c8, 8, 3, 15, 0x008, 14),
646 	MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_SEL, "tl_sel",
647 			     tl_parents, 0x0c0, 0x0c4, 0x0c8, 16, 2, 23, 0x008, 15),
648 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel",
649 			     dxcc_parents, 0x0c0, 0x0c4, 0x0c8, 24, 2, 31, 0x008, 16),
650 	/* CLK_CFG_12 */
651 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
652 			     aud_engen1_parents, 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x008, 17),
653 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel",
654 			     aud_engen2_parents, 0x0d0, 0x0d4, 0x0d8, 8, 2, 15, 0x008, 18),
655 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, "aes_ufsfde_sel",
656 			     aes_ufsfde_parents, 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, 0x008, 19),
657 	MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_SEL, "ufs_sel",
658 			     ufs_parents, 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, 0x008, 20),
659 	/* CLK_CFG_13 */
660 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel",
661 			     aud_1_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, 0x008, 21),
662 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel",
663 			     aud_2_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, 0x008, 22),
664 	MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_SEL, "adsp_sel",
665 			     adsp_parents, 0x0e0, 0x0e4, 0x0e8, 16, 3, 23, 0x008, 23),
666 	MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN_SEL, "dpmaif_main_sel",
667 			     dpmaif_main_parents, 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, 0x008, 24),
668 	/* CLK_CFG_14 */
669 	MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel",
670 			     venc_parents, 0x0f0, 0x0f4, 0x0f8, 0, 4, 7, 0x008, 25),
671 	MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel",
672 			     vdec_parents, 0x0f0, 0x0f4, 0x0f8, 8, 4, 15, 0x008, 26),
673 	MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel",
674 			     camtm_parents, 0x0f0, 0x0f4, 0x0f8, 16, 2, 23, 0x008, 27),
675 	MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel",
676 			     pwm_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, 31, 0x008, 28),
677 	/* CLK_CFG_15 */
678 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, "audio_h_sel",
679 			     audio_h_parents, 0x100, 0x104, 0x108, 0, 2, 7, 0x008, 29),
680 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST_SEL, "spmi_mst_sel",
681 			     spmi_mst_parents, 0x100, 0x104, 0x108, 8, 3, 15, 0x008, 30),
682 	MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel",
683 			     aes_msdcfde_parents, 0x100, 0x104, 0x108, 24, 3, 31, 0x00c, 1),
684 	/* CLK_CFG_16 */
685 	MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel",
686 			     sflash_parents, 0x110, 0x114, 0x118, 8, 2, 15, 0x00c, 3),
687 };
688 
689 static struct mtk_composite top_muxes[] = {
690 	/* CLK_AUDDIV_0 */
691 	MUX(CLK_TOP_APLL_I2S0_M_SEL, "apll_i2s0_m_sel", apll_i2s_m_parents, 0x320, 16, 1),
692 	MUX(CLK_TOP_APLL_I2S1_M_SEL, "apll_i2s1_m_sel", apll_i2s_m_parents, 0x320, 17, 1),
693 	MUX(CLK_TOP_APLL_I2S2_M_SEL, "apll_i2s2_m_sel", apll_i2s_m_parents, 0x320, 18, 1),
694 	MUX(CLK_TOP_APLL_I2S3_M_SEL, "apll_i2s3_m_sel", apll_i2s_m_parents, 0x320, 19, 1),
695 	MUX(CLK_TOP_APLL_I2S4_M_SEL, "apll_i2s4_m_sel", apll_i2s_m_parents, 0x320, 20, 1),
696 	MUX(CLK_TOP_APLL_I2S5_M_SEL, "apll_i2s5_m_sel", apll_i2s_m_parents, 0x320, 21, 1),
697 	MUX(CLK_TOP_APLL_I2S6_M_SEL, "apll_i2s6_m_sel", apll_i2s_m_parents, 0x320, 22, 1),
698 	MUX(CLK_TOP_APLL_I2S7_M_SEL, "apll_i2s7_m_sel", apll_i2s_m_parents, 0x320, 23, 1),
699 	MUX(CLK_TOP_APLL_I2S8_M_SEL, "apll_i2s8_m_sel", apll_i2s_m_parents, 0x320, 24, 1),
700 	MUX(CLK_TOP_APLL_I2S9_M_SEL, "apll_i2s9_m_sel", apll_i2s_m_parents, 0x320, 25, 1),
701 	/* APLL_DIV */
702 	DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_m_sel", 0x320, 0, 0x328, 8, 0),
703 	DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_m_sel", 0x320, 1, 0x328, 8, 8),
704 	DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_m_sel", 0x320, 2, 0x328, 8, 16),
705 	DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll_i2s3_m_sel", 0x320, 3, 0x328, 8, 24),
706 	DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll_i2s4_m_sel", 0x320, 4, 0x334, 8, 0),
707 	DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4", 0x320, 5, 0x334, 8, 8),
708 	DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll_i2s5_m_sel", 0x320, 6, 0x334, 8, 16),
709 	DIV_GATE(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll_i2s6_m_sel", 0x320, 7, 0x334, 8, 24),
710 	DIV_GATE(CLK_TOP_APLL12_DIV7, "apll12_div7", "apll_i2s7_m_sel", 0x320, 8, 0x338, 8, 0),
711 	DIV_GATE(CLK_TOP_APLL12_DIV8, "apll12_div8", "apll_i2s8_m_sel", 0x320, 9, 0x338, 8, 8),
712 	DIV_GATE(CLK_TOP_APLL12_DIV9, "apll12_div9", "apll_i2s9_m_sel", 0x320, 10, 0x338, 8, 16),
713 };
714 
715 static const struct mtk_gate_regs infra0_cg_regs = {
716 	.set_ofs = 0x80,
717 	.clr_ofs = 0x84,
718 	.sta_ofs = 0x90,
719 };
720 
721 static const struct mtk_gate_regs infra1_cg_regs = {
722 	.set_ofs = 0x88,
723 	.clr_ofs = 0x8c,
724 	.sta_ofs = 0x94,
725 };
726 
727 static const struct mtk_gate_regs infra2_cg_regs = {
728 	.set_ofs = 0xa4,
729 	.clr_ofs = 0xa8,
730 	.sta_ofs = 0xac,
731 };
732 
733 static const struct mtk_gate_regs infra3_cg_regs = {
734 	.set_ofs = 0xc0,
735 	.clr_ofs = 0xc4,
736 	.sta_ofs = 0xc8,
737 };
738 
739 static const struct mtk_gate_regs infra4_cg_regs = {
740 	.set_ofs = 0xd0,
741 	.clr_ofs = 0xd4,
742 	.sta_ofs = 0xd8,
743 };
744 
745 static const struct mtk_gate_regs infra5_cg_regs = {
746 	.set_ofs = 0xe0,
747 	.clr_ofs = 0xe4,
748 	.sta_ofs = 0xe8,
749 };
750 
751 #define GATE_INFRA0(_id, _name, _parent, _shift)	\
752 	GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
753 
754 #define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flag)		\
755 	GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift,	\
756 		&mtk_clk_gate_ops_setclr, _flag)
757 
758 #define GATE_INFRA1(_id, _name, _parent, _shift)	\
759 	GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
760 
761 #define GATE_INFRA2(_id, _name, _parent, _shift)	\
762 	GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
763 
764 #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag)		\
765 	GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift,	\
766 		&mtk_clk_gate_ops_setclr, _flag)
767 
768 #define GATE_INFRA3(_id, _name, _parent, _shift)	\
769 	GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
770 
771 #define GATE_INFRA4(_id, _name, _parent, _shift)	\
772 	GATE_MTK(_id, _name, _parent, &infra4_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
773 
774 #define GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, _flag)		\
775 	GATE_MTK_FLAGS(_id, _name, _parent, &infra5_cg_regs, _shift,	\
776 		&mtk_clk_gate_ops_setclr, _flag)
777 
778 #define GATE_INFRA5(_id, _name, _parent, _shift)	\
779 	GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, 0)
780 
781 /*
782  * CRITICAL CLOCK:
783  * infra_133m and infra_66m are main peripheral bus clocks of SOC.
784  * infra_device_apc and infra_device_apc_sync are for device access permission control module.
785  */
786 static const struct mtk_gate infra_clks[] = {
787 	/* INFRA0 */
788 	GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "pwrap_ulposc_sel", 0),
789 	GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pwrap_ulposc_sel", 1),
790 	GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md", "pwrap_ulposc_sel", 2),
791 	GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn", "pwrap_ulposc_sel", 3),
792 	GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scpsys", "scp_sel", 4),
793 	GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej", "axi_sel", 5),
794 	GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt", "axi_sel", 6),
795 	GATE_INFRA0(CLK_INFRA_GCE, "infra_gce", "axi_sel", 8),
796 	GATE_INFRA0(CLK_INFRA_GCE2, "infra_gce2", "axi_sel", 9),
797 	GATE_INFRA0(CLK_INFRA_THERM, "infra_therm", "axi_sel", 10),
798 	GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0", "i2c_sel", 11),
799 	GATE_INFRA0(CLK_INFRA_AP_DMA_PSEUDO, "infra_ap_dma_pseudo", "axi_sel", 12),
800 	GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2", "i2c_sel", 13),
801 	GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3", "i2c_sel", 14),
802 	GATE_INFRA0(CLK_INFRA_PWM_H, "infra_pwm_h", "axi_sel", 15),
803 	GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1", "pwm_sel", 16),
804 	GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2", "pwm_sel", 17),
805 	GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3", "pwm_sel", 18),
806 	GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4", "pwm_sel", 19),
807 	GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21),
808 	GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
809 	GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
810 	GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
811 	GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
812 	GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m", "axi_sel", 27),
813 	GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cq_dma_fpc", "axi_sel", 28),
814 	GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif", "axi_sel", 31),
815 	/* INFRA1 */
816 	GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 1),
817 	GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_h_sel", 2),
818 	GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc50_0_h_sel", 4),
819 	GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc50_0_h_sel", 5),
820 	GATE_INFRA1(CLK_INFRA_MSDC0_SRC, "infra_msdc0_src", "msdc50_0_sel", 6),
821 	GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8),
822 	GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9),
823 	GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10),
824 	GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11),
825 	GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap", "axi_sel", 12),
826 	GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md", "axi_sel", 13),
827 	GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md", "clk26m", 14),
828 	GATE_INFRA1(CLK_INFRA_PCIE_TL_26M, "infra_pcie_tl_26m", "axi_sel", 15),
829 	GATE_INFRA1(CLK_INFRA_MSDC1_SRC, "infra_msdc1_src", "msdc30_1_sel", 16),
830 	GATE_INFRA1(CLK_INFRA_MSDC2_SRC, "infra_msdc2_src", "msdc30_2_sel", 17),
831 	GATE_INFRA1(CLK_INFRA_PCIE_TL_96M, "infra_pcie_tl_96m", "tl_sel", 18),
832 	GATE_INFRA1(CLK_INFRA_PCIE_PL_P_250M, "infra_pcie_pl_p_250m", "axi_sel", 19),
833 	GATE_INFRA1_FLAGS(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20, CLK_IS_CRITICAL),
834 	GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
835 	GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys", "axi_sel", 24),
836 	GATE_INFRA1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
837 	GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
838 	GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core", "dxcc_sel", 27),
839 	GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao", "dxcc_sel", 28),
840 	GATE_INFRA1(CLK_INFRA_DBG_TRACE, "infra_dbg_trace", "axi_sel", 29),
841 	GATE_INFRA1(CLK_INFRA_DEVMPU_B, "infra_devmpu_b", "axi_sel", 30),
842 	GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31),
843 	/* INFRA2 */
844 	GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx", "clk26m", 0),
845 	GATE_INFRA2(CLK_INFRA_SSUSB, "infra_ssusb", "usb_top_sel", 1),
846 	GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "axi_sel", 2),
847 	GATE_INFRA2(CLK_INFRA_CLDMA_B, "infra_cldma_b", "axi_sel", 3),
848 	GATE_INFRA2(CLK_INFRA_AUDIO_26M_B, "infra_audio_26m_b", "clk26m", 4),
849 	GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_modem_temp_share", "clk26m", 5),
850 	GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 6),
851 	GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4", "i2c_sel", 7),
852 	GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2", "spi_sel", 9),
853 	GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3", "spi_sel", 10),
854 	GATE_INFRA2(CLK_INFRA_UNIPRO_SYS, "infra_unipro_sys", "ufs_sel", 11),
855 	GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick", "clk26m", 12),
856 	GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_B, "infra_ufs_mp_sap_b", "clk26m", 13),
857 	GATE_INFRA2(CLK_INFRA_MD32_B, "infra_md32_b", "axi_sel", 14),
858 	GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist", "axi_sel", 16),
859 	GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5", "i2c_sel", 18),
860 	GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter", "i2c_sel", 19),
861 	GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm", "i2c_sel", 20),
862 	GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter", "i2c_sel", 21),
863 	GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm", "i2c_sel", 22),
864 	GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter", "i2c_sel", 23),
865 	GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm", "i2c_sel", 24),
866 	GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4", "spi_sel", 25),
867 	GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5", "spi_sel", 26),
868 	GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cq_dma", "axi_sel", 27),
869 	GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs", "ufs_sel", 28),
870 	GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde", "aes_ufsfde_sel", 29),
871 	GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick", "ufs_sel", 30),
872 	GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci", "ssusb_xhci_sel", 31),
873 	/* INFRA3 */
874 	GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self", "msdc50_0_sel", 0),
875 	GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self", "msdc50_0_sel", 1),
876 	GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self", "msdc50_0_sel", 2),
877 	GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi", "axi_sel", 5),
878 	GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6", "i2c_sel", 6),
879 	GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0", "msdc50_0_sel", 7),
880 	GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0", "msdc50_0_sel", 8),
881 	GATE_INFRA3(CLK_INFRA_CCIF5_AP, "infra_ccif5_ap", "axi_sel", 9),
882 	GATE_INFRA3(CLK_INFRA_CCIF5_MD, "infra_ccif5_md", "axi_sel", 10),
883 	GATE_INFRA3(CLK_INFRA_PCIE_TOP_H_133M, "infra_pcie_top_h_133m", "axi_sel", 11),
884 	GATE_INFRA3(CLK_INFRA_FLASHIF_TOP_H_133M, "infra_flashif_top_h_133m", "axi_sel", 14),
885 	GATE_INFRA3(CLK_INFRA_PCIE_PERI_26M, "infra_pcie_peri_26m", "axi_sel", 15),
886 	GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap", "axi_sel", 16),
887 	GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md", "axi_sel", 17),
888 	GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap", "axi_sel", 18),
889 	GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md", "axi_sel", 19),
890 	GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m", "clk26m", 20),
891 	GATE_INFRA3(CLK_INFRA_AES, "infra_aes", "axi_sel", 21),
892 	GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7", "i2c_sel", 22),
893 	GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8", "i2c_sel", 23),
894 	GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc", "msdc50_0_sel", 24),
895 	GATE_INFRA3_FLAGS(CLK_INFRA_DEVICE_APC_SYNC, "infra_device_apc_sync", "axi_sel", 25,
896 			  CLK_IS_CRITICAL),
897 	GATE_INFRA3(CLK_INFRA_DPMAIF_MAIN, "infra_dpmaif_main", "dpmaif_main_sel", 26),
898 	GATE_INFRA3(CLK_INFRA_PCIE_TL_32K, "infra_pcie_tl_32k", "axi_sel", 27),
899 	GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap", "axi_sel", 28),
900 	GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md", "axi_sel", 29),
901 	GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6", "spi_sel", 30),
902 	GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7", "spi_sel", 31),
903 	/* INFRA4 */
904 	GATE_INFRA4(CLK_INFRA_AP_DMA, "infra_ap_dma", "infra_ap_dma_pseudo", 31),
905 	/* INFRA5 */
906 	GATE_INFRA5_FLAGS(CLK_INFRA_133M, "infra_133m", "axi_sel", 0, CLK_IS_CRITICAL),
907 	GATE_INFRA5_FLAGS(CLK_INFRA_66M, "infra_66m", "axi_sel", 1, CLK_IS_CRITICAL),
908 	GATE_INFRA5(CLK_INFRA_66M_PERI_BUS, "infra_66m_peri_bus", "axi_sel", 2),
909 	GATE_INFRA5(CLK_INFRA_FREE_DCM_133M, "infra_free_dcm_133m", "axi_sel", 3),
910 	GATE_INFRA5(CLK_INFRA_FREE_DCM_66M, "infra_free_dcm_66m", "axi_sel", 4),
911 	GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_133M, "infra_peri_bus_dcm_133m", "axi_sel", 5),
912 	GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_66M, "infra_peri_bus_dcm_66m", "axi_sel", 6),
913 	GATE_INFRA5(CLK_INFRA_FLASHIF_PERI_26M, "infra_flashif_peri_26m", "axi_sel", 30),
914 	GATE_INFRA5(CLK_INFRA_FLASHIF_SFLASH, "infra_flashif_fsflash", "axi_sel", 31),
915 };
916 
917 static const struct mtk_gate_regs peri_cg_regs = {
918 	.set_ofs = 0x20c,
919 	.clr_ofs = 0x20c,
920 	.sta_ofs = 0x20c,
921 };
922 
923 #define GATE_PERI(_id, _name, _parent, _shift)	\
924 	GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
925 
926 static const struct mtk_gate peri_clks[] = {
927 	GATE_PERI(CLK_PERI_PERIAXI, "peri_periaxi", "axi_sel", 31),
928 };
929 
930 static const struct mtk_gate_regs top_cg_regs = {
931 	.set_ofs = 0x150,
932 	.clr_ofs = 0x150,
933 	.sta_ofs = 0x150,
934 };
935 
936 #define GATE_TOP(_id, _name, _parent, _shift)	\
937 	GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
938 
939 static const struct mtk_gate top_clks[] = {
940 	GATE_TOP(CLK_TOP_SSUSB_TOP_REF, "ssusb_top_ref", "clk26m", 24),
941 	GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25),
942 };
943 
944 static u16 infra_ao_rst_ofs[] = {
945 	INFRA_RST0_SET_OFFSET,
946 	INFRA_RST1_SET_OFFSET,
947 	INFRA_RST2_SET_OFFSET,
948 	INFRA_RST3_SET_OFFSET,
949 	INFRA_RST4_SET_OFFSET,
950 };
951 
952 static u16 infra_ao_idx_map[] = {
953 	[MT8192_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
954 	[MT8192_INFRA_RST2_PEXTP_PHY_SWRST] = 2 * RST_NR_PER_BANK + 15,
955 	[MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
956 	[MT8192_INFRA_RST4_PCIE_TOP_SWRST] = 4 * RST_NR_PER_BANK + 1,
957 	[MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 12,
958 };
959 
960 static const struct mtk_clk_rst_desc clk_rst_desc = {
961 	.version = MTK_RST_SET_CLR,
962 	.rst_bank_ofs = infra_ao_rst_ofs,
963 	.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
964 	.rst_idx_map = infra_ao_idx_map,
965 	.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
966 };
967 
968 /* Register mux notifier for MFG mux */
969 static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
970 {
971 	struct mtk_mux_nb *mfg_mux_nb;
972 	int i;
973 
974 	mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
975 	if (!mfg_mux_nb)
976 		return -ENOMEM;
977 
978 	for (i = 0; i < ARRAY_SIZE(top_mtk_muxes); i++)
979 		if (top_mtk_muxes[i].id == CLK_TOP_MFG_PLL_SEL)
980 			break;
981 	if (i == ARRAY_SIZE(top_mtk_muxes))
982 		return -EINVAL;
983 
984 	mfg_mux_nb->ops = top_mtk_muxes[i].ops;
985 	mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */
986 
987 	return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
988 }
989 
990 static const struct mtk_clk_desc infra_desc = {
991 	.clks = infra_clks,
992 	.num_clks = ARRAY_SIZE(infra_clks),
993 	.rst_desc = &clk_rst_desc,
994 };
995 
996 static const struct mtk_clk_desc peri_desc = {
997 	.clks = peri_clks,
998 	.num_clks = ARRAY_SIZE(peri_clks),
999 };
1000 
1001 static const struct mtk_clk_desc topck_desc = {
1002 	.fixed_clks = top_fixed_clks,
1003 	.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
1004 	.factor_clks = top_divs,
1005 	.num_factor_clks = ARRAY_SIZE(top_divs),
1006 	.mux_clks = top_mtk_muxes,
1007 	.num_mux_clks = ARRAY_SIZE(top_mtk_muxes),
1008 	.composite_clks = top_muxes,
1009 	.num_composite_clks = ARRAY_SIZE(top_muxes),
1010 	.clks = top_clks,
1011 	.num_clks = ARRAY_SIZE(top_clks),
1012 	.clk_lock = &mt8192_clk_lock,
1013 	.clk_notifier_func = clk_mt8192_reg_mfg_mux_notifier,
1014 	.mfg_clk_idx = CLK_TOP_MFG_PLL_SEL,
1015 };
1016 
1017 static const struct of_device_id of_match_clk_mt8192[] = {
1018 	{ .compatible = "mediatek,mt8192-infracfg", .data = &infra_desc },
1019 	{ .compatible = "mediatek,mt8192-pericfg", .data = &peri_desc },
1020 	{ .compatible = "mediatek,mt8192-topckgen", .data = &topck_desc },
1021 	{ /* sentinel */ }
1022 };
1023 MODULE_DEVICE_TABLE(of, of_match_clk_mt8192);
1024 
1025 static struct platform_driver clk_mt8192_drv = {
1026 	.driver = {
1027 		.name = "clk-mt8192",
1028 		.of_match_table = of_match_clk_mt8192,
1029 	},
1030 	.probe = mtk_clk_simple_probe,
1031 	.remove_new = mtk_clk_simple_remove,
1032 };
1033 module_platform_driver(clk_mt8192_drv);
1034 MODULE_LICENSE("GPL");
1035